CN116053141A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN116053141A
CN116053141A CN202310114673.9A CN202310114673A CN116053141A CN 116053141 A CN116053141 A CN 116053141A CN 202310114673 A CN202310114673 A CN 202310114673A CN 116053141 A CN116053141 A CN 116053141A
Authority
CN
China
Prior art keywords
oxide dielectric
dielectric layer
groove
forming
gate oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310114673.9A
Other languages
Chinese (zh)
Inventor
王钦
祖健
唐峰辉
李海松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuxi Chipown Micro Electronics Ltd
Original Assignee
Wuxi Chipown Micro Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi Chipown Micro Electronics Ltd filed Critical Wuxi Chipown Micro Electronics Ltd
Priority to CN202310114673.9A priority Critical patent/CN116053141A/en
Publication of CN116053141A publication Critical patent/CN116053141A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a semiconductor substrate, wherein a first groove and a second groove are formed in the semiconductor substrate; forming a first gate oxide dielectric layer and a first initial gate electrode on the surface of the upper side wall of the first trench, forming a second gate oxide dielectric layer and a second gate electrode on the surface of the upper side wall of the second trench, removing a part of the first initial gate electrode, and removing the first gate oxide dielectric layer surrounding the removed part of the first initial gate electrode to expose the upper half part of the surface of the upper side wall of the first trench; and filling a gate electrode material in the first trench to form a first gate electrode. The invention can reduce the required quantity of the source electrode contact holes, effectively overcome the size limitation of the semiconductor device and reduce the production cost.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
A split gate (Shielded Gate Trench, SGT, also known as a shielded gate) field effect transistor (MOS) device is more advantageous for flexible applications of semiconductor integrated circuits than conventional MOS devices due to its lower gate-drain capacitance Cgd, lower on-resistance, and higher withstand voltage performance. Specifically, in the split gate field effect transistor, the shielding electrode is arranged below the gate electrode, so that the gate-drain capacitance can be greatly reduced, the electric field of the device is optimized, the breakdown voltage is improved, the drift region of the split gate field effect transistor also has higher impurity carrier concentration, and the on-resistance can be correspondingly reduced.
Further, for a semiconductor structure with a split gate field effect transistor, a rectifier, such as a super barrier rectifier (Supper Barrier Rectifier, SBR) device, is typically additionally provided in the semiconductor structure for realizing a fast switching thereof, increasing a reverse recovery speed thereof, and reducing power consumption when the transistor is turned off.
However, in the prior art, in order to realize the function of the SBR device, a source contact hole structure needs to be additionally formed on the surface of the gate electrode in the SBR device to short the remaining source terminals, so as to provide a reverse freewheeling capability. However, as device feature sizes shrink further, limiting device sizes limited by the maximum source contact hole density is difficult to shrink further.
There is a need for a method of forming a semiconductor structure that can effectively overcome the size limitations of semiconductor devices and reduce the manufacturing costs.
Disclosure of Invention
The invention solves the technical problem of providing a semiconductor structure and a forming method thereof, which can reduce the required quantity of source electrode contact hole structures, effectively overcome the size limitation of semiconductor devices and reduce the production cost.
In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, wherein a first groove and a second groove are formed in the semiconductor substrate; forming a field oxide dielectric layer on the surfaces of the bottom and the lower side wall of the first groove and the second groove, and forming a shielding electrode wrapped in the field oxide dielectric layer; forming a first gate oxide dielectric layer on the surface of the upper side wall of the first groove, and forming a second gate oxide dielectric layer on the surface of the upper side wall of the second groove, wherein the thickness of the first gate oxide dielectric layer is smaller than that of the second gate oxide dielectric layer; filling a gate electrode material on the surface of the field oxide dielectric layer in the first groove to form a first initial gate electrode, and forming a second gate electrode on the surface of the field oxide dielectric layer in the second groove; removing a portion of the first initial gate electrode and removing the first gate oxide dielectric layer surrounding the removed portion of the first initial gate electrode to expose an upper half of an upper sidewall surface of the first trench; and filling a gate electrode material in the first trench to form a first gate electrode.
Optionally, the method for forming the semiconductor structure further includes: forming a first well region and a first source region in the semiconductor substrate at the side of the first groove to form a super barrier rectifier SBR device; the first source region covers a part of the first well region, the first source region is electrically conducted with the first gate electrode, and the first well region and the first gate electrode are electrically isolated by the first gate oxide dielectric layer.
Optionally, the method for forming the semiconductor structure further includes: forming a source electrode contact hole structure in the semiconductor substrate at the side edge of the first groove; the first source region surrounds or semi-surrounds the source contact hole structure and is electrically communicated with the source contact hole structure; the first well region semi-surrounds the source electrode contact hole structure and is electrically conducted with the source electrode contact hole structure.
Optionally, the method for forming the semiconductor structure further includes: forming a first body region in the semiconductor substrate at the side edge of the first groove; wherein the first body region semi-surrounds the first well region, and the first source region covers a portion of the first body region.
Optionally, the method for forming the semiconductor structure further includes: forming one or more of the following in the semiconductor substrate at the side of the second trench to form a split gate field effect transistor SGT MOS device: a second body region, a second well region, and a second source region; the second source region covers a part of the second well region, the second source region and the second gate electrode are electrically isolated by the second gate oxide dielectric layer, the second well region and the second gate electrode are electrically isolated by the second gate oxide dielectric layer, the second body region semi-surrounds the second well region, and the second source region covers a part of the second body region.
Optionally, forming a field oxide dielectric layer on the bottom and lower sidewall surfaces of the first trench and the second trench, and forming a shielding electrode wrapped inside the field oxide dielectric layer, including: forming an initial field oxide dielectric film which covers the bottom and side wall surfaces of the first groove and the second groove and is provided with a cavity area; filling the shielding electrode in the cavity area; removing a portion of the shielding electrode, and removing an initial field oxide dielectric film surrounding the removed portion of the shielding electrode; depositing a field oxygen medium film, wherein the field oxygen medium film covers the rest initial field oxygen medium film and the shielding electrode; and removing a part of the field oxide dielectric film to obtain the field oxide dielectric layer.
Optionally, forming a first gate oxide dielectric layer on the surface of the upper sidewall of the first trench, and forming a second gate oxide dielectric layer on the surface of the upper sidewall of the second trench, including: forming a first initial gate oxide dielectric layer on the surface of the upper side wall of the first groove by adopting a first oxidation process, and forming a second initial gate oxide dielectric layer on the surface of the upper side wall of the second groove, wherein the thickness of the first initial gate oxide dielectric layer is consistent with that of the second initial gate oxide dielectric layer; removing the first initial gate oxide dielectric layer; and forming a first gate oxide dielectric layer on the surface of the side wall of the upper part of the first groove by adopting a second oxidation process, and performing secondary oxidation on the second initial gate oxide dielectric layer to obtain a second gate oxide dielectric layer.
In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a semiconductor substrate; a first trench and a second trench located in the semiconductor substrate; the field oxide dielectric layer is positioned at the bottom and the lower side wall surfaces of the first groove and the second groove; the first gate oxide dielectric layer is positioned on the surface of part of the upper side wall of the first groove; the second gate oxide dielectric layer is positioned on the surface of the upper side wall of the second groove, wherein the thickness of the first gate oxide dielectric layer is smaller than that of the second gate oxide dielectric layer; the first gate electrode is positioned on the surface of the field oxide dielectric layer in the first groove and is in contact with the upper half part of the surface of the upper side wall of the first groove; and the second gate electrode is positioned on the surface of the field oxide dielectric layer in the second groove.
Optionally, the semiconductor structure further includes: the first well region and the first source region are positioned in the semiconductor substrate at the side edge of the first groove to form a super barrier rectifier SBR device; the first source region covers a part of the first well region, the first source region is electrically conducted with the first gate electrode, and the first well region and the first gate electrode are electrically isolated by the first gate oxide dielectric layer.
Optionally, the semiconductor structure further includes: the source electrode contact hole structure is positioned in the semiconductor substrate at the side edge of the first groove; the first source region surrounds or semi-surrounds the source contact hole structure and is electrically communicated with the source contact hole structure; the first well region semi-surrounds the source electrode contact hole structure and is electrically conducted with the source electrode contact hole structure.
Optionally, the semiconductor structure further includes: the first body region is positioned in the semiconductor substrate at the side edge of the first groove; wherein the first body region semi-surrounds the first well region, and the first source region covers a portion of the first body region.
Optionally, the semiconductor structure further includes: one or more of a second body region, a second well region and a second source region are positioned in the semiconductor substrate at the side edge of the second groove to form a split gate field effect transistor SGT MOS device; the second source region covers a part of the second well region, the second source region and the second gate electrode are electrically isolated by the second gate oxide dielectric layer, the second well region and the second gate electrode are electrically isolated by the second gate oxide dielectric layer, the second body region semi-surrounds the second well region, and the second source region covers a part of the second body region.
Optionally, the SBR device and the SGT MOS device in the semiconductor structure are both located in a cell region.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, the first gate oxide dielectric layer and the first initial gate electrode are formed on the surface of the upper side wall of the first groove, the second gate oxide dielectric layer and the second gate electrode are formed on the surface of the upper side wall of the second groove, a part of the first initial gate electrode is removed, the first gate oxide dielectric layer surrounding the removed part of the first initial gate electrode is removed, so that the upper half part of the surface of the upper side wall of the first groove is exposed, then the gate electrode material is filled in the first groove to form the first gate electrode, the first gate oxide dielectric layer with smaller thickness can be formed in the first groove, and the first gate electrode which is in contact with the upper half part of the surface of the upper side wall of the first groove is formed, so that a device formed in the first groove can directly acquire the gate control voltage provided by the source electrode contact hole structure on the side edge of the groove without relying on an additional source electrode contact structure to provide the control voltage, and the control voltage can be realized in the first groove, compared with the prior art that the prior art, the prior art has the problem that the number of forming the gate electrode contact hole structure is reduced, and the current-carrying structure is reduced, and the number of the current-carrying structure is required, and the current-carrying device is reduced.
Further, forming a first well region and a first source region in the semiconductor substrate at the side of the first groove to form a super barrier rectifier SBR device; the first source region covers a part of the first well region, the first source region is electrically connected with the first gate electrode, and the first well region and the first gate electrode are electrically isolated by the first gate oxide dielectric layer, so that the SBR device can be turned on/off without providing gate control voltage depending on a source electrode contact hole structure, and leakage current is effectively reduced.
Further, by forming an initial field oxide dielectric film, filling the shielding electrode in the cavity area, removing a part of the shielding electrode, depositing a field oxide dielectric film, and removing a part of the field oxide dielectric film to obtain the field oxide dielectric layer, the field oxide dielectric layer wrapping the shielding electrode can be formed in the first groove and the second groove by adopting the same process, the process efficiency is effectively improved, and the process cost is reduced.
Further, a first initial gate oxide dielectric layer and a second initial gate oxide dielectric layer are formed by adopting a first oxidation process, and then the first initial gate oxide dielectric layer is removed; the second oxidation process is adopted to form a first gate oxide dielectric layer on the surface of the side wall of the upper part of the first groove, and the second initial gate oxide dielectric layer is subjected to secondary oxidation to obtain a second gate oxide dielectric layer, and by adopting the scheme of the embodiment of the invention, a thinner first gate oxide dielectric layer can be obtained through the oxidation process, and compared with other processes (such as a deposition process), a gate oxide dielectric layer with better quality can be formed, and devices (such as SBR devices) formed in the first groove can be oxidized to form a thinner gate oxide dielectric layer through the secondary oxidation after the first initial gate oxide dielectric layer is removed; and the second gate oxide dielectric layer formed by secondary oxidation also has better density and electric isolation characteristics.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor device of the prior art;
FIG. 2 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the invention;
fig. 3 to 13 are schematic cross-sectional views of a device corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention;
FIG. 14 is a schematic view of an operating scenario of an SBR device according to an embodiment of the present invention.
Reference numerals:
a semiconductor substrate 100; a source contact hole structure 151; SBR source contact hole structure 152; a metal layer 180; a semiconductor substrate 200; a first trench 211; a second trench 212; an initial field oxide dielectric film 221; a shield electrode 222; a field oxide dielectric film 223; a field oxide dielectric layer 220; a first initial gate oxide dielectric layer 231; a second initial gate oxide dielectric layer 232; a first mask layer 261; a first gate oxide dielectric layer 233; a second gate oxide dielectric layer 234; a first initial gate electrode 241; a second gate electrode 242; a second mask layer 262; a gate electrode material 243; a first gate electrode 240; source contact hole structure 251; a metal layer 280; a first source region 271; a first well region 272; a first body region 273; a second source region 274; a second well region 275; a second body region 276.
Detailed Description
In the prior art, SGT MOS devices are widely used in switching power supplies due to their excellent on-resistance and switching characteristics, and particularly in similar synchronous rectification applications, the dead zone of the MOS transistor before conduction is required to freewheel through the body diode, however the inherent forward voltage drop of the diode (0.7V at normal temperature) tends to increase the overall power consumption and limit the efficiency improvement.
To solve this problem, common solutions include the following three:
1. the schottky diode is integrated, however, the schottky diode is limited by the process to limit the high temperature characteristic and the poor reliability;
2. reducing body diode unbalanced carrier lifetime (electron irradiation, gold/platinum/palladium doping), however special processes are required, resulting in difficult universal application;
3. the SBR device is integrated, and the process compatibility of the SBR device and the MOS device is good, and the defect of a Schottky diode can be avoided through channel conduction, so that the method is more and more important.
It has been found that, in a specific embodiment of the prior art, in order to implement the function of the SBR device, a source contact hole structure needs to be additionally formed on the surface of the gate electrode in the SBR device to provide a gate control voltage, for example, the SBR device may be turned on when the gate control voltage is greater than or equal to a preset threshold voltage, and the SBR device may be turned off when the gate control voltage is less than the preset threshold voltage. In addition, source contact hole structures are also required to be formed in the semiconductor substrate at the side of the SBR device and the SGT MOS device to provide carrier flowing voltage, resulting in a larger number of source contact hole structures.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a semiconductor structure of the prior art.
As shown in the figure, in the prior art SGT MOS device integrated with the SBR device, the SBR device and the SGT MOS device can be formed in the semiconductor substrate 100 first, and as can be seen from the figure, the SBR device and the SGT MOS device have similar gate electrode structures and are isolated by a gate oxide dielectric layer.
In order to provide the gate control voltage, an SBR source contact hole structure 152 may be additionally formed on the surface of the gate electrode structure of the SBR device, and the gate control voltage may be provided via the metal layer 180, for example, the SBR device may be turned on when the gate control voltage is greater than or equal to a preset threshold voltage, and the SBR device may be turned off when the gate control voltage is less than the preset threshold voltage.
It is also desirable to form source contact hole structures 151 in the semiconductor substrate on the side of the SBR device and the SGT MOS device to provide carrier flow voltage via metal layer 180.
It has been found that in the prior art shown in fig. 1, the source contact hole structure 151 and the SBR source contact hole structure 152 are required at the same time, resulting in a large total required number of source contact hole structures 151, the size of the semiconductor device being limited and difficult to shrink, and the production cost increasing.
It should be noted that in another embodiment of the prior art, at the location of the SBR device, a larger source contact hole is formed using a cross-sectional dimension larger than the trench dimension of the SBR device, and then a conductive material is filled to provide a gate control voltage to the SBR device.
However, in this method, since the bottom of the larger source contact hole is formed in the semiconductor substrate, damage is generated to the semiconductor substrate material, and the cross-sectional size of the source contact hole is larger, occupies a larger space, is more difficult to reduce the size of the semiconductor device, and also is prone to short-circuit (short) problems.
In the embodiment of the invention, the first gate oxide dielectric layer and the first initial gate electrode are formed on the surface of the upper side wall of the first groove, the second gate oxide dielectric layer and the second gate electrode are formed on the surface of the upper side wall of the second groove, a part of the first initial gate electrode is removed, the first gate oxide dielectric layer surrounding the removed part of the first initial gate electrode is removed, so that the upper half part of the surface of the upper side wall of the first groove is exposed, then the gate electrode material is filled in the first groove to form the first gate electrode, the first gate oxide dielectric layer with smaller thickness can be formed in the first groove, and the first gate electrode which is in contact with the upper half part of the surface of the upper side wall of the first groove is formed, so that a device formed in the first groove can directly acquire the gate control voltage provided by the source electrode contact hole structure on the side edge of the groove without relying on an additional source electrode contact structure to provide the control voltage, and the control voltage can be realized in the first groove, compared with the prior art that the prior art, the prior art has the problem that the number of forming the gate electrode contact hole structure is reduced, and the current-carrying structure is reduced, and the number of the current-carrying structure is required, and the current-carrying device is reduced.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2, fig. 2 is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present invention. The method of forming the semiconductor structure may include steps S21 to S26:
step S21: providing a semiconductor substrate, wherein a first groove and a second groove are formed in the semiconductor substrate;
step S22: forming a field oxide dielectric layer on the surfaces of the bottom and the lower side wall of the first groove and the second groove, and forming a shielding electrode wrapped in the field oxide dielectric layer;
step S23: forming a first gate oxide dielectric layer on the surface of the upper side wall of the first groove, and forming a second gate oxide dielectric layer on the surface of the upper side wall of the second groove, wherein the thickness of the first gate oxide dielectric layer is smaller than that of the second gate oxide dielectric layer;
step S24: filling a gate electrode material on the surface of the field oxide dielectric layer in the first groove to form a first initial gate electrode, and forming a second gate electrode on the surface of the field oxide dielectric layer in the second groove;
Step S25: removing a portion of the first initial gate electrode and removing the first gate oxide dielectric layer surrounding the removed portion of the first initial gate electrode to expose an upper half of an upper sidewall surface of the first trench;
step S26: and filling a gate electrode material in the first trench to form a first gate electrode.
The respective steps described above are explained below with reference to fig. 3 to 13.
Fig. 3 to 13 are schematic cross-sectional views of a device corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 3, a semiconductor substrate 200 is provided, and a first trench 211 and a second trench 212 are formed in the semiconductor substrate 200.
The semiconductor substrate 200 may be a silicon substrate, or the material of the semiconductor substrate 200 may further include germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the semiconductor substrate 200 may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or a substrate with an epitaxial layer (Epi layer) grown thereon. Preferably, the semiconductor substrate 200 is a lightly doped semiconductor substrate.
Without limitation, the first type may be formed by applying a first type to an initial semiconductor substrate Ion implantation of the type to form the semiconductor substrate 200, e.g., implantation of N-type ions, formation of N-type shallow doping (N - ) A substrate.
The dimensions of the first trench 211 and the second trench 212 may be determined according to devices to be formed later, for example, the first trench 211 is used to form an SBR device, and the second trench 212 is used to form an SGT MOS device, and then the first trench 211 and the second trench 212 may be formed according to design dimensions.
Referring to fig. 4, an initial field oxide dielectric film 221 is formed, the initial field oxide dielectric film 221 covers the bottom and sidewall surfaces of the first and second trenches 211 and 212 and has a cavity region in which the shield electrode 222 is filled.
The material of the initial field oxide dielectric film 221 may be a dielectric material, for example, may be selected from: a stacked material of oxide and nitride, oxide, nitride, or other suitable dielectric material.
The material of the shielding electrode 222 may be a conductive material, such as a polysilicon (Poly) material or other suitable conductive material.
Further, a source connection structure may be formed to electrically lead out the shielding electrode 222.
Referring to fig. 5, a portion of the shielding electrode 222 is removed, and an initial field oxide dielectric film 221 surrounding the removed portion of the shielding electrode 222 is removed.
In a specific implementation, the shielding electrode 222 and the initial field oxide dielectric film 221 with the same thickness may be removed, for example, the same etching process may be used for removing.
Specifically, a dry etching manner may be adopted to remove a portion of the thickness of the shielding electrode 222 and a portion of the thickness of the initial field oxide dielectric film 221 from top to bottom.
Referring to fig. 6, a field oxide dielectric film 223 is deposited, the field oxide dielectric film 223 covers the remaining initial field oxide dielectric film 221 and the shielding electrode 222, and a portion of the field oxide dielectric film 223 is removed to obtain the field oxide dielectric layer 220. Specifically, the material of the field oxide dielectric thin film 223 may be identical to that of the initial field oxide dielectric thin film 221 to improve the insulation effect; the material of the field oxide dielectric film 223 may also be inconsistent with the material of the initial field oxide dielectric film 221 to enhance the stress effect.
In the embodiment of the present invention, the field oxide dielectric film 223 and the remaining initial field oxide dielectric film 221 are combined to form the field oxide dielectric layer 220, and the field oxide dielectric layer 220 wraps the shielding electrode 222, and the shielding electrode 222 is wrapped inside the field oxide dielectric layer 220.
It should be noted that by depositing the thicker field oxide dielectric film 223 and then removing a portion of the field oxide dielectric film 223, the upper sidewall surface of the first trench 211 may be maintained as the material of the semiconductor substrate 200 after the formation of the field oxide dielectric layer 220.
In the embodiment of the present invention, by forming the initial field oxide dielectric film 221, filling the shielding electrode 222 in the cavity area, removing a part of the shielding electrode 222, depositing the field oxide dielectric film 223, removing a part of the field oxide dielectric film 223 to obtain the field oxide dielectric layer 220, the field oxide dielectric layer 220 wrapping the shielding electrode 222 can be formed in the first trench 211 and the second trench 212 by adopting the same process, thereby effectively improving the process efficiency and reducing the process cost.
Referring to fig. 7, a first oxidation process is used to form a first initial gate oxide dielectric layer 231 on the upper sidewall surface of the first trench 211, and a second initial gate oxide dielectric layer 232 on the upper sidewall surface of the second trench 212, where the thickness of the first initial gate oxide dielectric layer 231 is consistent with the thickness of the second initial gate oxide dielectric layer 232.
The material of the first initial gate oxide dielectric layer 231 is oxide, for example, silicon oxide. By adopting the first oxidation process to oxidize the material of the semiconductor substrate 200 to form the first initial gate oxide dielectric layer 231, the thickness of the first initial gate oxide dielectric layer 231 can be effectively controlled, better insulation quality can be obtained, and the second initial gate oxide dielectric layer 232 can be obtained in the same way.
Referring to fig. 8, the first initial gate oxide dielectric layer 231 (refer to fig. 7) is removed.
Specifically, a patterned first mask layer 261 may be formed, where the first mask layer 261 covers the second initial gate oxide dielectric layer 232 and exposes the first initial gate oxide dielectric layer 231, and then the first initial gate oxide dielectric layer 231 is removed.
Referring to fig. 9, a second oxidation process is used to form a first gate oxide dielectric layer 233 on the upper sidewall surface of the first trench 211, and the second initial gate oxide dielectric layer 232 is subjected to a secondary oxidation to obtain a second gate oxide dielectric layer 234.
It should be noted that, in another specific implementation manner of the embodiment of the present application, the first gate oxide dielectric layer 233 and the second gate oxide dielectric layer 234 may be formed sequentially, and the forming sequence between the two may not be limited, for example, the second gate oxide dielectric layer 234 may be formed first, then the first gate oxide dielectric layer 233 may be formed, and then the second gate oxide dielectric layer 234 may be formed first.
The material of the first gate oxide dielectric layer 233 may be consistent with the first initial gate oxide dielectric layer 231, and may be an oxide, for example, silicon oxide. By oxidizing the material of the semiconductor substrate 200 to form the first gate oxide dielectric layer 233 by using the second oxidation process, the thickness of the first gate oxide dielectric layer 233 can be effectively controlled, and better insulation quality can be obtained.
It should be noted that, in the case where the thickness of the first gate oxide dielectric layer 233 is more finely required, the thickness may be properly controlled when the first initial gate oxide dielectric layer 231 and the second initial gate oxide dielectric layer 232 are formed by using the first oxidation process, for example, the preset thickness may be reduced based on the design thickness of the second initial gate oxide dielectric layer 232, so that the thickness of the second initial gate oxide dielectric layer 232 after the second oxidation meets the design requirement.
Under the condition of higher cost control requirement, the first initial gate oxide dielectric layer 231 and the second initial gate oxide dielectric layer 232 can be formed by adopting the design thickness of the second initial gate oxide dielectric layer 232 in the first oxidation process, and the thickness of the second initial gate oxide dielectric layer 232 is larger, so that the secondary increase thickness formed in the secondary oxidation process through the second oxidation process is smaller, and the thickness of the secondary oxidation increase can be not managed, controlled and monitored any more, thereby being beneficial to reducing the production cost.
In the embodiment of the present invention, a first oxidation process is adopted to form a first initial gate oxide dielectric layer 231 and a second initial gate oxide dielectric layer 232, and then the first initial gate oxide dielectric layer 231 is removed; a second oxidation process is further adopted to form a first gate oxide dielectric layer 233 on the surface of the upper side wall of the first trench 211, and secondary oxidation is performed on the second initial gate oxide dielectric layer 232 to obtain a second gate oxide dielectric layer 234, by adopting the scheme of the embodiment of the invention, a thinner first gate oxide dielectric layer 233 can be obtained through the oxidation process, and compared with other processes (such as a deposition process), a gate oxide dielectric layer 233 with better quality can be formed, and by adopting the secondary oxidation after the first initial gate oxide dielectric layer 231 is removed, the oxidation of devices (such as SBR devices) formed in the first trench 211 to form a thinner first gate oxide dielectric layer 233 can be realized; and the second gate oxide dielectric layer 234 formed by the secondary oxidation also has better density and electrical isolation characteristics.
Referring to fig. 10, a gate electrode material is filled in the first trench 211 on the surface of the field oxide dielectric layer 220 to form a first initial gate electrode 241, and a second gate electrode 242 is formed in the second trench 212 on the surface of the field oxide dielectric layer 220.
The gate electrode material may be a conductive material, for example, a polysilicon material or other suitable conductive material.
Referring to fig. 11, a portion of the first initial gate electrode 241 is removed, and the first gate oxide dielectric layer 233 surrounding the removed portion of the first initial gate electrode 241 is removed to expose an upper half portion (e.g., a portion outlined by a dotted line) of an upper sidewall surface of the first trench 211.
In a specific implementation, the first initial gate electrode 241 and the first gate oxide dielectric layer 233 with the same thickness may be removed, for example, the same etching process may be used for removing.
Specifically, a patterned second mask layer 262 may be formed, the second mask layer 262 covering the second gate electrode 242 and exposing the first initial gate electrode 241, and then the first initial gate electrode 241 is removed.
Specifically, a dry etching manner may be adopted to remove a portion of the thickness of the first initial gate electrode 241 and a portion of the thickness of the first gate oxide dielectric layer 233 from top to bottom.
Referring to fig. 12, a gate electrode material 243 is filled in the first trench 211 to form a first gate electrode 240.
It should be noted that the second mask layer 262 covering the second trench 212 and its internal structure may be left while the first trench 211 is processed, so as to effectively protect the completed device in the second trench 212.
Wherein the gate electrode material 243 may be consistent with the material forming the first initial gate electrode 241 to improve the conductive performance of the device; the gate electrode material 243 may also be inconsistent with the material forming the first initial gate electrode 241 to meet other performance requirements of the device while ensuring that the conductive properties of the device meet the requirements.
Referring to fig. 13, a first well region 272 and a first source region 271 may be formed in the semiconductor substrate 200 at the side of the first trench 211 to form a super barrier rectifier SBR device; wherein the first source region 271 covers a portion of the first well region 272, the first source region 271 is electrically connected to the first gate electrode 240, and the first well region 272 and the first gate electrode 240 are electrically isolated by the first gate oxide dielectric layer 233.
Without limitation, the N-type heavy doping may be formed by performing a first type ion implantation to form the first source region 271, such as implanting N-type ions (N + ) A first source region 271.
Without limitation, a P-type shallow doping (P may be formed by performing a second type ion implantation to form the first well region 272, such as implanting P-type ions - ) The first well region 272.
The method for forming the semiconductor structure can further comprise the following steps: forming a first body region 273 in the semiconductor substrate 200 at the side of the first trench 211; wherein the first body region 273 half surrounds the first well region 272, the first source region 271 covers a portion of the first body region 273.
Without limitation, a P-type heavy doping (P may be formed by performing a second type ion implantation to form the first body region 273, such as implanting P-type ions + ) The first well region 272.
In the embodiment of the present invention, the first well region 272 and the first source region 271 are formed to form the super barrier rectifier SBR device, the first source region 271 is electrically connected to the first gate electrode 240, and the first well region 272 and the first gate electrode 240 are electrically isolated by the first gate oxide dielectric layer 233, so that the SBR device can be turned on/off without providing a gate control voltage depending on a source contact hole structure, and meanwhile, leakage current between the first well region 272 and the first gate electrode 240 is effectively reduced, and device quality is improved.
It is noted that other suitable structures may be used to form the SBR device, such as adding or subtracting suitable doped regions.
The method for forming the semiconductor structure can further comprise the following steps: forming a source contact hole structure 251 in the semiconductor substrate 200 at the side of the first trench 211; wherein the first source region 271 surrounds or semi-surrounds the source contact hole structure 251 and is in electrical communication with the source contact hole structure 251; the first well region 272 semi-surrounds the source contact hole structure 251 and is electrically conductive to the source contact hole structure 251. Wherein the gate control voltage may be provided via the metal layer 280.
In the embodiment of the present invention, the device formed in the first trench 211 may not be isolated by the first gate oxide dielectric layer 233, but may directly obtain the gate control voltage provided by the source contact hole structure 251 located at the side edge of the first trench 211, so that the control (such as on/off) of the device formed in the first trench 211 may be achieved without relying on an additional source contact hole structure (such as the SBR source contact hole structure 252 shown in fig. 1) to provide the gate control voltage.
In addition, the method for forming the semiconductor structure further comprises the following steps: one or more of the following is formed in the semiconductor substrate 200 at the side of the second trench 212 to form an SGT MOS device: a second body region 276, a second well region 275, and a second source region 274; wherein the second source region 274 covers a portion of the second well region 275, the second source region 274 is electrically isolated from the second gate electrode 242 by the second gate oxide dielectric layer 234, the second well region 275 is electrically isolated from the second gate electrode 242 by the second gate oxide dielectric layer 234, the second body region 276 semi-surrounds the second well region 275, and the second source region 274 covers a portion of the second body region 276.
Without limitation, the second source region 274 may be formed by performing a first type ion implantation, such as implanting N-type ions, to form N-type heavily doped (N + ) A second source region 274; the second well region 275 may also be formed by performing a second type of ion implantation, such as implanting P-type ions, to form a P-type shallow doping (P - ) A second well region 275; the second body region 276 may also be formed by performing a second type of ion implantation, such as implanting P-type ions, to form a P-type heavily doped (P + ) A second body region 276.
It should be noted that other suitable structures may be used to form the SGT MOS device, such as adding or subtracting appropriate doped regions.
It will be appreciated that although the first body region 273 and the second body region 276 are used to represent body regions (body regions) in the SBR device and the SGT MOS device, respectively, in this application, the first body region 273 and the second body region 276 may be formed together using the same process in order to reduce the cost of the process and increase the production efficiency, and similarly, the first source region 271 and the second source region 274 may be formed together using the same process, and the first well region 272 and the second well region 275 may be formed together using the same process.
Referring to fig. 14, fig. 14 is a schematic view of an operating scenario of an SBR device according to an embodiment of the present invention.
As shown in fig. 14, since the first gate electrode 240 is in contact with the upper half portion (e.g., the region surrounded by the dotted line) of the upper sidewall surface of the first trench 211, the first gate electrode 240 is electrically connected to the first source region 271 and is electrically connected to the source contact hole structure 251, i.e., the first gate electrode 240, the first source region 271 and the source contact hole structure 251 have an equipotential therebetween.
In the embodiment of the invention, the SBR device can directly obtain the gate control voltage provided by the source contact hole structure 251 located at the side of the first trench 211 without being isolated by the first gate oxide dielectric layer 233, so that the gate control function of the SBR device can be implemented without providing the gate control voltage depending on an additional source contact hole structure.
Without limitation, when the gate control voltage is greater than or equal to a preset threshold voltage, carrier flow as shown by a dotted arrow can be realized, and the SBR device is turned on, for example, for positive carriers, the arrow direction may be upward, and for negative carriers, the arrow direction may be downward.
It can be understood that the voltage drop of the SBR device is smaller than that of the SGT MOS device, so that the reverse power consumption improving effect is more obvious, and the device performance is effectively improved.
In the embodiment of the invention, the first gate oxide dielectric layer 231 and the first initial gate electrode 241 are formed on the surface of the upper side wall of the first trench 211, the second gate oxide dielectric layer 232 and the second gate electrode 242 are formed on the surface of the upper side wall of the second trench 212, a part of the first initial gate electrode 241 is removed, the first gate oxide dielectric layer 233 surrounding the removed part of the first initial gate electrode 241 is removed, the upper half of the surface of the upper side wall of the first trench 241 is exposed, then the gate electrode material is filled in the first trench 241 to form the first gate electrode 240, the first gate oxide dielectric layer 231 with smaller thickness is formed in the first trench 241, and the first gate electrode 240 is in contact with the upper half of the surface of the upper side wall of the first trench 211, so that devices formed in the first trench 211 can be isolated without the first gate oxide dielectric layer 233, and source contact hole structures located on the sides of the first trench 211 can be directly obtained, compared with the prior art that the control hole structures of the first trench 251 are provided, the number of the control hole structures can be reduced, compared with the prior art, the number of the control hole structures can be provided, the number of the control hole structures can be reduced, the current requirements can be realized, and the number of the control hole structures can be reduced, compared with the requirements can be provided, and the control hole structures can be realized, the device.
In an embodiment of the present invention, a semiconductor structure is also disclosed, referring to fig. 13, which may include: a semiconductor substrate 200; a first trench 211 and a second trench 212 located in the semiconductor substrate 200; a field oxide dielectric layer 220 and a shielding electrode 222 wrapped inside the field oxide dielectric layer 220, wherein the field oxide dielectric layer 220 is positioned on the bottom and lower side wall surfaces of the first groove 211 and the second groove 212; a first gate oxide dielectric layer 233 located on a surface of a portion of the upper sidewall of the first trench 211; a second gate oxide dielectric layer 234 located on the upper sidewall surface of the second trench 212, wherein the thickness of the first gate oxide dielectric layer 233 is smaller than the thickness of the second gate oxide dielectric layer 234; a first gate electrode 240 located on the surface of the field oxide dielectric layer 220 in the first trench 211 and contacting the upper half of the upper sidewall surface of the first trench 211; and a second gate electrode 242 located on the surface of the field oxide dielectric layer 220 in the second trench 212.
Further, the semiconductor structure may further include: a first well region 272 and a first source region 271, which are located in the semiconductor substrate 200 at the side of the first trench 211, so as to form an SBR device; wherein the first source region 271 covers a portion of the first well region 272, the first source region 271 is electrically connected to the first gate electrode 240, and the first well region 272 and the first gate electrode 240 are electrically isolated by the first gate oxide dielectric layer 233.
Further, the semiconductor structure may further include: source contact hole structures 251 located in the semiconductor substrate 200 beside the first trenches 211; wherein the first source region 271 surrounds or semi-surrounds the source contact hole structure 251 and is in electrical communication with the source contact hole structure 251; the first well region 272 semi-surrounds the source contact hole structure 251 and is electrically conductive to the source contact hole structure 251.
Further, the semiconductor structure may further include: a first body 273 in the semiconductor substrate 200 beside the first trench 211; wherein the first body region 273 half surrounds the first well region 272, the first source region 271 covers a portion of the first body region 273.
Further, the semiconductor structure may further include: one or more of a second body region 276, a second well region 275, and a second source region 274 are located in the semiconductor substrate 200 at the sides of the second trench 212 to form an SGT MOS device; wherein the second source region 274 covers a portion of the second well region 275, the second source region 274 is electrically isolated from the second gate electrode 242 by the second gate oxide dielectric layer 234, the second well region 275 is electrically isolated from the second gate electrode 242 by the second gate oxide dielectric layer 234, the second body region 276 semi-surrounds the second well region 275, and the second source region 274 covers a portion of the second body region 276.
Further, the SBR device and the SGT MOS device in the semiconductor structure are both located in a Cell region (Cell).
In the embodiment of the invention, by arranging the SBR device and the SGT MOS device to be positioned in the cell area, the integration of the SBR device and the SGT MOS device under all cell sizes can be compatible, and the pressure resistance problem caused by different grooves (such as the first groove 211 and the second groove 212) can be solved.
For the principles, specific implementations and advantages of the semiconductor structure, reference should be made to the above description of the method for forming a semiconductor structure, which is not repeated herein.
It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In this context, the character "/" indicates that the front and rear associated objects are an "or" relationship.
The term "plurality" as used in the embodiments herein refers to two or more.
The first, second, etc. descriptions in the embodiments of the present application are only used for illustrating and distinguishing the description objects, and no order division is used, nor does it indicate that the number of the devices in the embodiments of the present application is particularly limited, and no limitation on the embodiments of the present application should be construed.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (13)

1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, wherein a first groove and a second groove are formed in the semiconductor substrate;
forming a field oxide dielectric layer on the surfaces of the bottom and the lower side wall of the first groove and the second groove, and forming a shielding electrode wrapped in the field oxide dielectric layer;
forming a first gate oxide dielectric layer on the surface of the upper side wall of the first groove, and forming a second gate oxide dielectric layer on the surface of the upper side wall of the second groove, wherein the thickness of the first gate oxide dielectric layer is smaller than that of the second gate oxide dielectric layer;
filling a gate electrode material on the surface of the field oxide dielectric layer in the first groove to form a first initial gate electrode, and forming a second gate electrode on the surface of the field oxide dielectric layer in the second groove;
removing a portion of the first initial gate electrode and removing the first gate oxide dielectric layer surrounding the removed portion of the first initial gate electrode to expose an upper half of an upper sidewall surface of the first trench;
And filling a gate electrode material in the first trench to form a first gate electrode.
2. The method of forming a semiconductor structure of claim 1, further comprising:
forming a first well region and a first source region in the semiconductor substrate at the side of the first groove to form a super barrier rectifier SBR device;
the first source region covers a part of the first well region, the first source region is electrically conducted with the first gate electrode, and the first well region and the first gate electrode are electrically isolated by the first gate oxide dielectric layer.
3. The method of forming a semiconductor structure of claim 2, further comprising:
forming a source electrode contact hole structure in the semiconductor substrate at the side edge of the first groove;
the first source region surrounds or semi-surrounds the source contact hole structure and is electrically communicated with the source contact hole structure;
the first well region semi-surrounds the source electrode contact hole structure and is electrically conducted with the source electrode contact hole structure.
4. The method of forming a semiconductor structure of claim 2, further comprising:
forming a first body region in the semiconductor substrate at the side edge of the first groove;
Wherein the first body region semi-surrounds the first well region, and the first source region covers a portion of the first body region.
5. The method of forming a semiconductor structure of claim 1, further comprising:
forming one or more of the following in the semiconductor substrate at the side of the second trench to form a split gate field effect transistor SGT MOS device: a second body region, a second well region, and a second source region;
the second source region covers a part of the second well region, the second source region and the second gate electrode are electrically isolated by the second gate oxide dielectric layer, the second well region and the second gate electrode are electrically isolated by the second gate oxide dielectric layer, the second body region semi-surrounds the second well region, and the second source region covers a part of the second body region.
6. The method of claim 1, wherein forming a field oxide dielectric layer on bottom and lower sidewall surfaces of the first trench and the second trench, and forming a shield electrode wrapped inside the field oxide dielectric layer, comprises:
forming an initial field oxide dielectric film which covers the bottom and side wall surfaces of the first groove and the second groove and is provided with a cavity area;
Filling the shielding electrode in the cavity area;
removing a portion of the shielding electrode, and removing an initial field oxide dielectric film surrounding the removed portion of the shielding electrode;
depositing a field oxygen medium film, wherein the field oxygen medium film covers the rest initial field oxygen medium film and the shielding electrode;
and removing a part of the field oxide dielectric film to obtain the field oxide dielectric layer.
7. The method of forming a semiconductor structure of claim 1, wherein forming a first gate oxide dielectric layer on an upper sidewall surface of the first trench and forming a second gate oxide dielectric layer on an upper sidewall surface of the second trench comprises:
forming a first initial gate oxide dielectric layer on the surface of the upper side wall of the first groove by adopting a first oxidation process, and forming a second initial gate oxide dielectric layer on the surface of the upper side wall of the second groove, wherein the thickness of the first initial gate oxide dielectric layer is consistent with that of the second initial gate oxide dielectric layer;
removing the first initial gate oxide dielectric layer;
and forming a first gate oxide dielectric layer on the surface of the side wall of the upper part of the first groove by adopting a second oxidation process, and performing secondary oxidation on the second initial gate oxide dielectric layer to obtain a second gate oxide dielectric layer.
8. A semiconductor structure, comprising:
a semiconductor substrate;
a first trench and a second trench located in the semiconductor substrate;
the field oxide dielectric layer is positioned at the bottom and the lower side wall surfaces of the first groove and the second groove;
the first gate oxide dielectric layer is positioned on the surface of part of the upper side wall of the first groove;
the second gate oxide dielectric layer is positioned on the surface of the upper side wall of the second groove, wherein the thickness of the first gate oxide dielectric layer is smaller than that of the second gate oxide dielectric layer;
the first gate electrode is positioned on the surface of the field oxide dielectric layer in the first groove and is in contact with the upper half part of the surface of the upper side wall of the first groove;
and the second gate electrode is positioned on the surface of the field oxide dielectric layer in the second groove.
9. The semiconductor structure of claim 8, further comprising:
the first well region and the first source region are positioned in the semiconductor substrate at the side edge of the first groove to form a super barrier rectifier SBR device;
the first source region covers a part of the first well region, the first source region is electrically conducted with the first gate electrode, and the first well region and the first gate electrode are electrically isolated by the first gate oxide dielectric layer.
10. The semiconductor structure of claim 9, further comprising:
the source electrode contact hole structure is positioned in the semiconductor substrate at the side edge of the first groove;
the first source region surrounds or semi-surrounds the source contact hole structure and is electrically communicated with the source contact hole structure;
the first well region semi-surrounds the source electrode contact hole structure and is electrically conducted with the source electrode contact hole structure.
11. The semiconductor structure of claim 9, further comprising:
the first body region is positioned in the semiconductor substrate at the side edge of the first groove;
wherein the first body region semi-surrounds the first well region, and the first source region covers a portion of the first body region.
12. The semiconductor structure of claim 8, further comprising:
one or more of a second body region, a second well region and a second source region are positioned in the semiconductor substrate at the side edge of the second groove to form a split gate field effect transistor SGT MOS device;
the second source region covers a part of the second well region, the second source region and the second gate electrode are electrically isolated by the second gate oxide dielectric layer, the second well region and the second gate electrode are electrically isolated by the second gate oxide dielectric layer, the second body region semi-surrounds the second well region, and the second source region covers a part of the second body region.
13. The semiconductor structure of claim 8, wherein the SBR device and the SGT MOS device in the semiconductor structure are both located in a cell region.
CN202310114673.9A 2023-02-14 2023-02-14 Semiconductor structure and forming method thereof Pending CN116053141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310114673.9A CN116053141A (en) 2023-02-14 2023-02-14 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310114673.9A CN116053141A (en) 2023-02-14 2023-02-14 Semiconductor structure and forming method thereof

Publications (1)

Publication Number Publication Date
CN116053141A true CN116053141A (en) 2023-05-02

Family

ID=86119971

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310114673.9A Pending CN116053141A (en) 2023-02-14 2023-02-14 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN116053141A (en)

Similar Documents

Publication Publication Date Title
US9245963B2 (en) Insulated gate semiconductor device structure
US10355125B2 (en) Electrode contact structure for semiconductor device
US8362548B2 (en) Contact structure for semiconductor device having trench shield electrode and method
US7915672B2 (en) Semiconductor device having trench shield electrode structure
TWI464885B (en) New approach to integrate schottky in mosfet
US9306018B2 (en) Trench shielding structure for semiconductor device and method
CN107564908B (en) Bidirectional switch with back-to-back field effect transistors
US10861965B2 (en) Power MOSFET with an integrated pseudo-Schottky diode in source contact trench
US20190386129A1 (en) Power device having super junction and schottky diode
US8921184B2 (en) Method of making an electrode contact structure and structure therefor
CN216624288U (en) Semiconductor structure
TW201939616A (en) Laterally diffused metal oxide semiconductor (LDMOS) transistor and manufacturing method thereof
CN103311271B (en) Charge compensation semiconductor device
CN111933716B (en) LDMOS transistor and manufacturing method thereof
US20220130981A1 (en) Ldmos transistor and manufacturing method thereof
KR102542415B1 (en) Semiconductor device and method for fabricating the same
CN114497201A (en) Field effect transistor of integrated body relay diode, preparation method thereof and power device
CN113206148A (en) Trench MOSFET and method of manufacturing the same
CN219419037U (en) Groove type silicon carbide MOSFET device
CN113644108A (en) Trench gate semiconductor device and preparation method thereof
CN116314302A (en) Manufacturing method of groove type silicon carbide MOSFET device
CN115547838A (en) Preparation method of metal oxide semiconductor device and device
CN113809148B (en) Power element and manufacturing method thereof
US11664434B2 (en) Semiconductor power devices having multiple gate trenches and methods of forming such devices
CN114068701B (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination