CN113690233A - Unidirectional ESD protection device capable of enhancing through-current capacity and manufacturing method thereof - Google Patents

Unidirectional ESD protection device capable of enhancing through-current capacity and manufacturing method thereof Download PDF

Info

Publication number
CN113690233A
CN113690233A CN202111105478.7A CN202111105478A CN113690233A CN 113690233 A CN113690233 A CN 113690233A CN 202111105478 A CN202111105478 A CN 202111105478A CN 113690233 A CN113690233 A CN 113690233A
Authority
CN
China
Prior art keywords
diffusion region
metal layer
layer
diffusion area
boron
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202111105478.7A
Other languages
Chinese (zh)
Other versions
CN113690233B (en
Inventor
宋文龙
杨珏琳
张鹏
许志峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Jilaixin Technology Co ltd
Jiangsu Jilai Microelectronics Co ltd
Original Assignee
Chengdu Jilaixin Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Jilaixin Technology Co ltd filed Critical Chengdu Jilaixin Technology Co ltd
Priority to CN202111105478.7A priority Critical patent/CN113690233B/en
Publication of CN113690233A publication Critical patent/CN113690233A/en
Application granted granted Critical
Publication of CN113690233B publication Critical patent/CN113690233B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thyristors (AREA)

Abstract

The invention discloses a unidirectional ESD protection device capable of enhancing the through-current capacity and a manufacturing method thereof, the device comprises a P-type single crystal material, an N + diffusion region, a P diffusion region, a surface passivation layer, a metal layer I and a metal layer II, wherein the concentration of the P diffusion region is gradually reduced from the N + diffusion region below the metal layer I to the N + diffusion region below the metal layer II, and in the design of a photoetching window of the P diffusion region, the size of the window can be named as follows in sequence: l1, L2, L3, L4, L5, the size of the window pitch in turn can be named: d1, D2, D3, D4, L5> L4> L3> L2> L1, D1> D2> D3> D4, so that a P diffusion region is obtained, the concentration of the P diffusion region is gradually reduced from the N + diffusion region (below the metal layer II) to the N + diffusion region (below the metal layer I), a built-in electric field from left to right is formed, and therefore higher current capacity can be obtained, and compared with a conventional structure, the current capacity of the invention can be improved by 20-40% through reasonably designing the photoetching window size of the P diffusion region.

Description

Unidirectional ESD protection device capable of enhancing through-current capacity and manufacturing method thereof
Technical Field
The invention relates to the field of electronic science and technology, in particular to a unidirectional ESD protection device capable of enhancing the current capacity and a manufacturing method thereof.
Background
Electrostatic discharge (ESD) phenomena are a significant cause of damage and even failure of integrated circuit products. Integrated circuit products are highly susceptible to ESD during their manufacture, fabrication, assembly, and operation, resulting in internal damage and reduced reliability. Therefore, the research on the high-performance and high-reliability ESD protection device plays a crucial role in improving the yield and reliability of the integrated circuit. In general, the design of ESD protection devices requires consideration of three issues: firstly, the ESD protection device can release large current; the other is that the ESD protection device has a specific trigger voltage and a low holding voltage. Third, the ESD protection device requires ultra-low parasitic capacitance.
Devices commonly used for ESD protection are diodes, BJTs (triodes), SCRs (silicon controlled rectifiers), etc. The BJT structure achieves a shallow flyback characteristic due to the introduction of the injection modulation effect. The SCR structure achieves deep retrace characteristics through the positive feedback mechanism of PNPN. Therefore, from the residual voltage parameter, the SCR structure is the lowest, the BJT structure is the next to the BJT structure, and the diode structure is the highest. Because the voltage of the SCR structure after deep retrace is only about 2V and is obviously lower than common power supply voltages such as 3.3V, 5V and the like, the SCR structure device is always in a latch-up effect and cannot be recovered to a blocking state after ESD pulse discharge, and the SCR structure device is limited in application. Therefore, in general, the BJT structure is a relatively reasonable choice, the residual voltage parameter is reduced, and the application scenario limitation is relatively small. For a unidirectional ESD protection device with a BJT structure, a structure is generally adopted in which an N + diffusion region 102, a P + diffusion region 103, a P diffusion region 104, and a surface passivation layer 105 are formed on a P-type single crystal material 101 to perform a dielectric isolation function, and a metal layer 107 and a metal layer 106 respectively represent two electrode ports of the unidirectional ESD protection device, i.e., an anode and a cathode, and have a low current capacity.
The prior art discloses a unidirectional ESD protection device with high current passing capability and a manufacturing method thereof (publication number CN 111599805A), the unidirectional ESD protection device comprises an N-type substrate material, an N-type epitaxial layer is extended on the front surface of the N-type substrate material, a P-type diffusion region with different depth PN junctions is arranged in the N-type epitaxial layer, an isolation dielectric layer is deposited on the N-type epitaxial layer, the front surface of the isolation dielectric layer and the outer front surface of the P-type diffusion region is sputtered or evaporated with a front surface metal region, and the back surface of the N-type substrate material is thinned and metallized to form a back surface metal region. The preparation method comprises the following steps: preparing an N-type substrate material, and growing an N-type epitaxial layer; growing a sacrificial oxide layer on the N-type epitaxial layer to obtain deep and shallow PN junctions with different heights; injecting boron into the front surface to form a P-type diffusion region; depositing an isolation medium layer on the front surface, and photoetching the front surface to form a contact hole area; sputtering or evaporating metal on the front surface; the front metal area and the back metal area are formed, and deep and shallow junctions with different junction depths are formed, so that higher current capacity is obtained, but the introduced conductance modulation effect is not strong, and the current capacity is to be optimized and enhanced.
Disclosure of Invention
The invention aims to provide a unidirectional ESD protection device capable of enhancing the current capacity under the conditions of unchanged chip area and unchanged chip processing procedures and a manufacturing method thereof.
The technical scheme adopted by the invention is as follows:
a unidirectional ESD protection device capable of enhancing through-current capacity comprises a P-type single crystal material, an N + diffusion region, a P diffusion region, a surface passivation layer, a metal layer I and a metal layer II, wherein the inner top of the P-type single crystal material is sequentially provided with the N + diffusion region, the P diffusion region, the N + diffusion region and the P + diffusion region, the top surface of the P-type single crystal material is provided with the metal layer I and the metal layer II, the surface passivation regions are respectively arranged at the edges of the metal layer I and the N + diffusion region and between the P diffusion region and the N + diffusion region, the surface passivation regions are respectively arranged at the edge of the metal layer II, and the concentration of the P diffusion region is gradually reduced from the N + diffusion region below the metal layer I to the N + diffusion region below the metal layer II.
A manufacturing method of a unidirectional ESD protection device capable of enhancing the current capacity comprises the following steps:
step 1: preparing a P-type single crystal material, wherein the crystal orientation is <100>, and the resistivity is 5-50 omega.cm;
step 2: growing a sacrificial oxide layer with a thickness of 680-1000A, performing front-side lithography to form an N + diffusion region pattern, performing front-side phosphorus implantation with a phosphorus implantation dose of 3E15-8E15cm-2The energy is 80-120 KeV;
and step 3: forming P + diffusion region pattern by front side photoetching, implanting boron into the front side, advancing boron to form N + diffusion region and P + diffusion region, wherein the boron implantation dosage is 1E15-3E15cm-2The energy is 30-80KeV, the boron propelling temperature is 1050-;
and 4, step 4: photoetching the front side to form a P diffusion area pattern and forming a P diffusion area photoetching pattern;
and 5: front boron implantation, boron drive-in to form P diffusion region, boron implantation dosage is 1E14-5E14cm-2The energy is 50-100KeV, the temperature of boron propulsion is 1000-;
step 6: the front side is deposited with an isolation medium layer, and the contact hole area formed by the front side through photoetching is as follows: at positions L1, L2, L3, L4, and L5, the corresponding contact hole spacing regions are: d1, D2, D3 and D4, wherein the areas are all isolation medium layers;
and 7: sputtering or evaporating metal and alloy on the front surface.
Further, the isolation dielectric layer in step 6 is tetraethoxysilane TEOS, the thickness is 5000-10000A, and a layer of TI/TIN is deposited after the contact hole is etched, so that the contact resistance is reduced, and the failure proportion of metal overheating can be effectively reduced.
Preferably, the isolation dielectric layer in step 6 is tetraethoxysilane TEOS with a thickness of 7000 a, and a layer of TI/TIN is deposited after the contact hole is etched.
Further, the metal sputtered or evaporated on the front surface in the step 7 is aluminum, aluminum copper or aluminum-silicon-copper, the thickness is 2-4um, the temperature of the alloy is 360-430 ℃, and the time is 25-45 min.
Preferably, the metal sputtered or evaporated from the front surface in step 7 is aluminum or aluminum copper or aluminum silicon copper, the thickness is 3um, the temperature of the alloy is 400 ℃, and the time is 35 min.
The invention has the advantages that: 1. the invention can obtain higher through-current capacity under the conditions of unchanged chip area and unchanged chip processing procedures;
2. in the photoetching process of the P diffusion region, photoetching windows with different sizes are designed, and the space between the windows with different sizes is reasonably optimized, so that the gradually-changed depth gradually reduced from the N + diffusion region (below the metal layer II) to the N + diffusion region (below the metal layer I) can be obtained after the P diffusion region is subjected to the diffusion process. In the design of the P-diffusion lithographic window, the size of the window can be named in turn: l1, L2, L3, L4, L5, the size of the window pitch in turn can be named: d1, D2, D3, D4, L5> L4> L3> L2> L1, D1> D2> D3> D4, so that a P diffusion region is obtained, the concentration of the P diffusion region is gradually reduced from the N + diffusion region (below the metal layer II) to the N + diffusion region (below the metal layer I), a built-in electric field from left to right is formed, and therefore higher current capacity can be obtained, and compared with a conventional structure, the current capacity of the invention can be improved by 20-40% through reasonably designing the photoetching window size of the P diffusion region.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
FIG. 1 is a cross-sectional structural view of the present invention;
FIG. 2 is a schematic diagram of the IV characteristics of the present invention;
FIG. 3 is a schematic process diagram of step 1 of the present invention;
FIG. 4 is a schematic process diagram of step 2 of the present invention;
FIG. 5 is a schematic process diagram of step 3 of the present invention;
FIG. 6 is a schematic process diagram of step 4 of the present invention;
FIG. 7 is a schematic process diagram of step 5 of the present invention.
Wherein: 101. a P-type single crystal material; 102. an N + diffusion region; 103. a P + diffusion region; 104. a P diffusion region; 105. a surface passivation layer; 106. a metal layer I; 107. a metal layer II; 108. sacrificing the oxide layer; 109. and isolating the dielectric layer.
Detailed Description
Example 1
As shown in fig. 1-7, a unidirectional ESD protection device capable of enhancing current capacity includes a P-type single crystal material 101, an N + diffusion region 102, a P + diffusion region 103, a P diffusion region 104, a surface passivation layer 105, a metal layer i 106, and a metal layer ii 107, wherein the top of the P-type single crystal material 101 is sequentially provided with the N + diffusion region 102, the P diffusion region 104, the N + diffusion region 102, and the P + diffusion region 103, the top of the P-type single crystal material 101 is provided with the metal layer i 106 and the metal layer ii 107, the surface passivation regions 105 are respectively provided between the edges of the metal layer i 106 and the N + diffusion region 102, and between the edges of the P diffusion region 104 and the N + diffusion region 102, between the N + diffusion region 102 and the P + diffusion region 103, and between the edges of the P + diffusion region 103, the concentration of the P diffusion region 104 is gradually reduced from the N + diffusion region 102 below the metal layer i 16 to the N + diffusion region 102 below the metal layer ii 107, and a built-in electric field from left to right is formed, so that higher through-current capacity can be obtained under the conditions of unchanged chip area and unchanged chip processing procedures, and through reasonably designing the size of a photoetching window of the P diffusion region, compared with the conventional structure, the through-current capacity of the invention can be improved by 20-40 percent.
When the metal layer II 107 is connected with a high potential and the metal layer I106 is connected with a low potential, the current sequentially passes through the P + diffusion region 103, the P-type single crystal material 101 and the N + diffusion region 102 (below the metal layer I106) to show the forward conduction characteristic of the diode, and when the metal layer I106 is connected with the high potential and the metal layer II 107 is connected with the low potential, the current sequentially passes through the N + diffusion region 102 (below the metal layer 106I), the P diffusion region 104 and the N + diffusion region 102 (below the metal layer II 107) to show the shallow flyback breakdown characteristic of the triode.
A manufacturing method of a unidirectional ESD protection device capable of enhancing the current capacity comprises the following steps:
step 1: preparing a P-type single crystal material 101, wherein the crystal orientation is <100>, and the resistivity is 5 omega-cm;
step 2: a sacrificial oxide layer 108 is grown, the thickness of the sacrificial oxide layer 108 is 680 a, a pattern of N + diffusion regions 102 is formed by front-side lithography,front side phosphorus implant with a dose of 3E15cm-2Energy is 80 KeV;
and step 3: forming P + diffusion region 103 pattern by front side lithography, implanting boron into front side, and advancing boron to form N + diffusion region 102 and P + diffusion region 103, wherein the boron implantation dosage is 1E15-3E15cm-2Forming a P + diffusion region 103 and an N + diffusion region 102 with energy of 30KeV, boron propelling temperature of 1050 ℃ and time of 60 min;
and 4, step 4: the front side is photoetched to form a P diffusion region 104 graph, the P diffusion region 104 photoetching graph is formed, photoetching windows with different sizes are designed in the photoetching process of the P diffusion region 104, and the space between the windows with different sizes is reasonably optimized, so that the gradually-changed depth gradually reduced from the N + diffusion region (below a metal layer II 107) to the N + diffusion region (below a metal layer I106) can be obtained after the P diffusion region 104 is subjected to the diffusion process, as shown in figure 6, in the design of the photoetching window of the P diffusion region 104, the size of the window can be named as follows in sequence: l1, L2, L3, L4, L5, the size of the window pitch in turn can be named: d1, D2, D3, D4, L5> L4> L3> L2> L1, D1> D2> D3> D4, thereby obtaining a P diffusion region 104 as shown in fig. 6;
and 5: front side boron implantation with a boron implant dose of 1E14cm, boron drive-in, forming P diffusion region 104-2The energy is 50KeV, the boron propelling temperature is 1000 ℃, the time is 30min, a P diffusion region 104 is formed, and the technological conditions of boron injection and boron propelling are selected and optimized according to the requirements of PN junction breakdown voltage;
step 6: as shown in fig. 6, the front side is deposited with an isolation dielectric layer, and the contact hole region formed by front side lithography is: at positions L1, L2, L3, L4, and L5, the corresponding contact hole spacing regions are: d1, D2, D3 and D4, wherein the isolation medium layer 109 is arranged in each region;
and 7: sputtering or evaporating metal and alloy on the front surface.
Further, the isolation dielectric layer in step 6 is tetraethoxysilane TEOS, the thickness is 5000-10000A, and a layer of TI/TIN is deposited after the contact hole is etched, so that the contact resistance is reduced, and the failure proportion of metal overheating can be effectively reduced.
Further, the metal sputtered or evaporated from the front surface in the step 7 is aluminum or aluminum copper or aluminum-silicon-copper, the thickness is 2um, the temperature of the alloy is 360 ℃, and the time is 25 min.
Example 2
As shown in fig. 1-7, a unidirectional ESD protection device capable of enhancing current capacity includes a P-type single crystal material 101, an N + diffusion region 102, a P + diffusion region 103, a P diffusion region 104, a surface passivation layer 105, a metal layer i 106, and a metal layer ii 107, wherein the top of the P-type single crystal material 101 is sequentially provided with the N + diffusion region 102, the P diffusion region 104, the N + diffusion region 102, and the P + diffusion region 103, the top of the P-type single crystal material 101 is provided with the metal layer i 106 and the metal layer ii 107, the surface passivation regions 105 are respectively provided between the edges of the metal layer i 106 and the N + diffusion region 102, and between the edges of the P diffusion region 104 and the N + diffusion region 102, between the N + diffusion region 102 and the P + diffusion region 103, and between the edges of the P + diffusion region 103, the concentration of the P diffusion region 104 is gradually reduced from the N + diffusion region 102 below the metal layer i 16 to the N + diffusion region 102 below the metal layer ii 107, and a built-in electric field from left to right is formed, so that higher through-current capacity can be obtained under the conditions of unchanged chip area and unchanged chip processing procedures, and through reasonably designing the size of a photoetching window of the P diffusion region, compared with the conventional structure, the through-current capacity of the invention can be improved by 20-40 percent.
When the metal layer II 107 is connected with a high potential and the metal layer I106 is connected with a low potential, the current sequentially passes through the P + diffusion region 103, the P-type single crystal material 101 and the N + diffusion region 102 (below the metal layer I106) to show the forward conduction characteristic of the diode, and when the metal layer I106 is connected with the high potential and the metal layer II 107 is connected with the low potential, the current sequentially passes through the N + diffusion region 102 (below the metal layer 106I), the P diffusion region 104 and the N + diffusion region 102 (below the metal layer II 107) to show the shallow flyback breakdown characteristic of the triode.
A manufacturing method of a unidirectional ESD protection device capable of enhancing the current capacity comprises the following steps:
step 1: preparing a P-type single crystal material 101, wherein the crystal orientation is <100>, and the resistivity is 50 omega-cm;
step 2: a sacrificial oxide layer 108 is grown, the sacrificial oxide layer 108 having a thickness of1000A, front side photo-etched N + diffusion region 102 pattern, front side phosphorus implant with a phosphorus implant dose of 8E15cm-2The energy is 120 KeV;
and step 3: forming P + diffusion region 103 pattern by front side lithography, implanting boron into front side, advancing boron to form N + diffusion region 102 and P + diffusion region 103, and implanting boron at a dose of 3E15cm-2Forming a P + diffusion region 103 and an N + diffusion region 102 with energy of 80KeV, boron propelling temperature of 1150 ℃ and time of 180 min;
and 4, step 4: the front side is photoetched to form a P diffusion region 104 graph, the P diffusion region 104 photoetching graph is formed, photoetching windows with different sizes are designed in the photoetching process of the P diffusion region 104, and the space between the windows with different sizes is reasonably optimized, so that the gradually-changed depth gradually reduced from the N + diffusion region (below a metal layer II 107) to the N + diffusion region (below a metal layer I106) can be obtained after the P diffusion region 104 is subjected to the diffusion process, as shown in figure 6, in the design of the photoetching window of the P diffusion region 104, the size of the window can be named as follows in sequence: l1, L2, L3, L4, L5, the size of the window pitch in turn can be named: d1, D2, D3, D4, L5> L4> L3> L2> L1, D1> D2> D3> D4, thereby obtaining a P diffusion region 104 as shown in fig. 6;
and 5: front side boron implantation with a boron implant dose of 5E14cm, boron drive-in, forming P diffusion region 104-2The energy is 100KeV, the boron propelling temperature is 1100 ℃, the time is 90min, a P diffusion region 104 is formed, and the technological conditions of boron injection and boron propelling are selected and optimized according to the requirements of PN junction breakdown voltage;
step 6: as shown in fig. 6, the front side is deposited with an isolation dielectric layer, and the contact hole region formed by front side lithography is: at positions L1, L2, L3, L4, and L5, the corresponding contact hole spacing regions are: d1, D2, D3 and D4, wherein the isolation medium layer 109 is arranged in each region;
and 7: sputtering or evaporating metal and alloy on the front surface.
Further, the isolation dielectric layer in the step 6 is tetraethoxysilane TEOS, the thickness of the isolation dielectric layer is 10000A, and a layer of TI/TIN is deposited after the contact hole is etched, so that the failure proportion of metal overheating can be effectively reduced while the contact resistance is reduced.
Further, the metal sputtered or evaporated from the front surface in the step 7 is aluminum or aluminum copper or aluminum silicon copper, the thickness is 4um, the temperature of the alloy is 430 ℃, and the time is 45 min.
Example 3
As shown in fig. 1-7, a unidirectional ESD protection device capable of enhancing current capacity includes a P-type single crystal material 101, an N + diffusion region 102, a P + diffusion region 103, a P diffusion region 104, a surface passivation layer 105, a metal layer i 106, and a metal layer ii 107, wherein the top of the P-type single crystal material 101 is sequentially provided with the N + diffusion region 102, the P diffusion region 104, the N + diffusion region 102, and the P + diffusion region 103, the top of the P-type single crystal material 101 is provided with the metal layer i 106 and the metal layer ii 107, the surface passivation regions 105 are respectively provided between the edges of the metal layer i 106 and the N + diffusion region 102, and between the edges of the P diffusion region 104 and the N + diffusion region 102, between the N + diffusion region 102 and the P + diffusion region 103, and between the edges of the P + diffusion region 103, the concentration of the P diffusion region 104 is gradually reduced from the N + diffusion region 102 below the metal layer i 16 to the N + diffusion region 102 below the metal layer ii 107, and a built-in electric field from left to right is formed, so that higher through-current capacity can be obtained under the conditions of unchanged chip area and unchanged chip processing procedures, and through reasonably designing the size of a photoetching window of the P diffusion region, compared with the conventional structure, the through-current capacity of the invention can be improved by 20-40 percent.
When the metal layer II 107 is connected with a high potential and the metal layer I106 is connected with a low potential, the current sequentially passes through the P + diffusion region 103, the P-type single crystal material 101 and the N + diffusion region 102 (below the metal layer I106) to show the forward conduction characteristic of the diode, and when the metal layer I106 is connected with the high potential and the metal layer II 107 is connected with the low potential, the current sequentially passes through the N + diffusion region 102 (below the metal layer 106I), the P diffusion region 104 and the N + diffusion region 102 (below the metal layer II 107) to show the shallow flyback breakdown characteristic of the triode.
A manufacturing method of a unidirectional ESD protection device capable of enhancing the current capacity comprises the following steps:
step 1: preparing a P-type single crystal material 101, wherein the crystal orientation is <100>, and the resistivity is 25 omega-cm;
step 2: growing a layer of sacrificial oxygenForming an N + diffusion region 102 pattern by front-side lithography on a sacrificial oxide layer 108 with a thickness of 840A, front-side phosphorus implantation with a phosphorus implantation dose of 6E15cm-2The energy is 100 KeV;
and step 3: forming P + diffusion region 103 pattern by front side lithography, implanting boron into front side, advancing boron to form N + diffusion region 102 and P + diffusion region 103, and implanting boron at a dose of 2E15cm-2Forming a P + diffusion region 103 and an N + diffusion region 102 at an energy of 55KeV and a boron propelling temperature of 1100 ℃ for 120 min;
and 4, step 4: the front side is photoetched to form a P diffusion region 104 graph, the P diffusion region 104 photoetching graph is formed, photoetching windows with different sizes are designed in the photoetching process of the P diffusion region 104, and the space between the windows with different sizes is reasonably optimized, so that the gradually-changed depth gradually reduced from the N + diffusion region (below a metal layer II 107) to the N + diffusion region (below a metal layer I106) can be obtained after the P diffusion region 104 is subjected to the diffusion process, as shown in figure 6, in the design of the photoetching window of the P diffusion region 104, the size of the window can be named as follows in sequence: l1, L2, L3, L4, L5, the size of the window pitch in turn can be named: d1, D2, D3, D4, L5> L4> L3> L2> L1, D1> D2> D3> D4, thereby obtaining a P diffusion region 104 as shown in fig. 6;
and 5: front side boron implantation with a boron implant dose of 3E14cm, boron drive-in, forming P diffusion region 104-2The energy is 70KeV, the boron propelling temperature is 1050 ℃, the time is 60min, a P diffusion region 104 is formed, and the technological conditions of boron injection and boron propelling are selected and optimized according to the requirements of PN junction breakdown voltage;
step 6: as shown in fig. 6, the front side is deposited with an isolation dielectric layer, and the contact hole region formed by front side lithography is: at positions L1, L2, L3, L4, and L5, the corresponding contact hole spacing regions are: d1, D2, D3 and D4, wherein the isolation medium layer 109 is arranged in each region;
and 7: sputtering or evaporating metal and alloy on the front surface.
Further, the isolation dielectric layer in step 6 is tetraethoxysilane TEOS, the thickness is 7000A, and after the contact hole is etched, a layer of TI/TIN is deposited, so that the failure proportion of metal overheating can be effectively reduced while the contact resistance is reduced.
Further, the metal sputtered or evaporated from the front surface in the step 7 is aluminum, aluminum copper or aluminum-silicon-copper, the thickness is 3um, the temperature of the alloy is 400 ℃, and the time is 35 min.
The above-mentioned embodiments are merely illustrative of the preferred embodiments of the present invention, and do not limit the scope of the present invention, and various modifications and improvements made to the technical solution of the present invention by those skilled in the art without departing from the spirit of the present invention should be included in the protection scope defined by the claims of the present invention.

Claims (6)

1. A unidirectional ESD protection device capable of enhancing through-current capacity comprises a P-type single crystal material, an N + diffusion region, a P diffusion region, a surface passivation layer, a metal layer I and a metal layer II, and is characterized in that: the inner top of the P-type single crystal material is sequentially provided with an N + diffusion area, a P diffusion area, an N + diffusion area and a P + diffusion area, the top surface of the P-type single crystal material is provided with a metal layer I and a metal layer II, surface passivation areas are respectively arranged between the edges of the metal layer I and the N + diffusion area and between the edges of the P diffusion area and the N + diffusion area, the surface passivation areas are respectively arranged on the edges of the metal layer II, the N + diffusion area and the P diffusion area, the N + diffusion area and the P + diffusion area are arranged below the metal layer I, and the concentration of the P diffusion area is gradually reduced from the N + diffusion area to the N + diffusion area below the metal layer II.
2. A method for manufacturing a unidirectional ESD protection device with enhanced current capacity according to claim 1, wherein: the method comprises the following steps:
step 1: preparing a P-type single crystal material, wherein the crystal orientation is <100>, and the resistivity is 5-50 omega.cm;
step 2: growing a sacrificial oxide layer on the front surface, wherein the thickness of the sacrificial oxide layer is 680-1000A, photoetching the front surface to form an N + diffusion region pattern, and implanting phosphorus into the front surface at a dose of 3E15-8E15cm-2The energy is 80-120 KeV;
and step 3: forming P + diffusion region pattern by front side photoetching, implanting boron into the front side, advancing boron to form N + diffusion region and P + diffusion region, wherein the boron implantation dosage is 1E15-3E15cm-2The energy is 30-80KeV, the boron propelling temperature is 1050-;
and 4, step 4: photoetching the front side to form a P diffusion area pattern and forming a P diffusion area photoetching pattern;
and 5: front boron implantation, boron drive-in to form P diffusion region, boron implantation dosage is 1E14-5E14cm-2The energy is 50-100KeV, the temperature of boron propulsion is 1000-;
step 6: the front side is deposited with an isolation medium layer, and the contact hole area formed by the front side through photoetching is as follows: at positions L1, L2, L3, L4, and L5, the corresponding contact hole spacing regions are: d1, D2, D3 and D4, wherein the areas are all isolation medium layers;
and 7: sputtering or evaporating metal and alloy on the front surface.
3. A method of fabricating a unidirectional ESD protection device according to claim 2, wherein: and 6, the isolation medium layer in the step 6 is tetraethoxysilane TEOS with the thickness of 5000-10000A, and a layer of TI/TIN is deposited after the contact hole is etched.
4. A method of fabricating a unidirectional ESD protection device according to claim 3, wherein: and 6, the isolation medium layer in the step 6 is tetraethoxysilane TEOS, the thickness is 7000A, and a layer of TI/TIN is deposited after the contact hole is etched.
5. A method of fabricating a unidirectional ESD protection device according to claim 2, wherein: the metal sputtered or evaporated on the front surface in the step 7 is aluminum, aluminum copper or aluminum-silicon-copper, the thickness is 2-4um, the temperature of the alloy is 360-430 ℃, and the time is 25-45 min.
6. The method of claim 5, wherein the method comprises: the metal sputtered or evaporated from the front surface in the step 7 is aluminum, aluminum copper or aluminum-silicon-copper, the thickness is 3um, the temperature of the alloy is 400 ℃, and the time is 35 min.
CN202111105478.7A 2021-09-22 2021-09-22 Unidirectional ESD protection device capable of enhancing current capacity and manufacturing method thereof Active CN113690233B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111105478.7A CN113690233B (en) 2021-09-22 2021-09-22 Unidirectional ESD protection device capable of enhancing current capacity and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111105478.7A CN113690233B (en) 2021-09-22 2021-09-22 Unidirectional ESD protection device capable of enhancing current capacity and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN113690233A true CN113690233A (en) 2021-11-23
CN113690233B CN113690233B (en) 2024-03-08

Family

ID=78586758

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111105478.7A Active CN113690233B (en) 2021-09-22 2021-09-22 Unidirectional ESD protection device capable of enhancing current capacity and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN113690233B (en)

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1124408A (en) * 1994-07-20 1996-06-12 电子科技大学 Surface withstand voltage zone for semiconductor device
US20020028522A1 (en) * 1998-09-02 2002-03-07 Porter Stephen R. Electrostatic discharge protection device having a graded junction and method for forming the same
US20100187566A1 (en) * 2009-01-23 2010-07-29 Vanguard International Semiconductor Corporation Insulated gate bipolar transistor (igbt) electrostatic discharge (esd) protection devices
US20100289032A1 (en) * 2009-05-12 2010-11-18 Qingchun Zhang Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same
US7964485B1 (en) * 2009-10-23 2011-06-21 National Semiconductor Corporation Method of forming a region of graded doping concentration in a semiconductor device and related apparatus
CN102122668A (en) * 2010-01-11 2011-07-13 世界先进积体电路股份有限公司 Semiconductor structure and manufacturing method thereof
CN103280460A (en) * 2013-05-22 2013-09-04 矽力杰半导体技术(杭州)有限公司 High-voltage PMOS (p-channel metal oxide semiconductor) transistor with injection molded superimposed drift region and manufacturing method thereof
US20140061788A1 (en) * 2012-08-31 2014-03-06 Nuvoton Technology Corporation Semiconductor device and method of fabricating the same
CN104659091A (en) * 2013-11-20 2015-05-27 上海华虹宏力半导体制造有限公司 Ldmos device and manufacturing method thereof
US20160149018A1 (en) * 2014-11-25 2016-05-26 Power Integrations, Inc. Laterally-graded doping of materials
CN210110783U (en) * 2019-09-16 2020-02-21 江苏丽隽功率半导体有限公司 Integrated high-performance LDMOS structure
CN111968916A (en) * 2020-08-12 2020-11-20 无锡先仁智芯微电子技术有限公司 Manufacturing method of LDMOS structure
CN112002755A (en) * 2020-08-20 2020-11-27 合肥工业大学 Novel LDMOS device structure and preparation method and performance thereof
CN113270481A (en) * 2021-05-19 2021-08-17 济南大学 Circular drift region semiconductor device with gradually-changed doping concentration and preparation method thereof

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1124408A (en) * 1994-07-20 1996-06-12 电子科技大学 Surface withstand voltage zone for semiconductor device
US20020028522A1 (en) * 1998-09-02 2002-03-07 Porter Stephen R. Electrostatic discharge protection device having a graded junction and method for forming the same
US20100187566A1 (en) * 2009-01-23 2010-07-29 Vanguard International Semiconductor Corporation Insulated gate bipolar transistor (igbt) electrostatic discharge (esd) protection devices
US20100289032A1 (en) * 2009-05-12 2010-11-18 Qingchun Zhang Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same
US7964485B1 (en) * 2009-10-23 2011-06-21 National Semiconductor Corporation Method of forming a region of graded doping concentration in a semiconductor device and related apparatus
CN102122668A (en) * 2010-01-11 2011-07-13 世界先进积体电路股份有限公司 Semiconductor structure and manufacturing method thereof
US8912599B2 (en) * 2012-08-31 2014-12-16 Nuvoton Technology Corporation Semiconductor device and method of fabricating the same
US20140061788A1 (en) * 2012-08-31 2014-03-06 Nuvoton Technology Corporation Semiconductor device and method of fabricating the same
CN103280460A (en) * 2013-05-22 2013-09-04 矽力杰半导体技术(杭州)有限公司 High-voltage PMOS (p-channel metal oxide semiconductor) transistor with injection molded superimposed drift region and manufacturing method thereof
CN104659091A (en) * 2013-11-20 2015-05-27 上海华虹宏力半导体制造有限公司 Ldmos device and manufacturing method thereof
US20160149018A1 (en) * 2014-11-25 2016-05-26 Power Integrations, Inc. Laterally-graded doping of materials
CN210110783U (en) * 2019-09-16 2020-02-21 江苏丽隽功率半导体有限公司 Integrated high-performance LDMOS structure
CN111968916A (en) * 2020-08-12 2020-11-20 无锡先仁智芯微电子技术有限公司 Manufacturing method of LDMOS structure
CN112002755A (en) * 2020-08-20 2020-11-27 合肥工业大学 Novel LDMOS device structure and preparation method and performance thereof
CN113270481A (en) * 2021-05-19 2021-08-17 济南大学 Circular drift region semiconductor device with gradually-changed doping concentration and preparation method thereof

Also Published As

Publication number Publication date
CN113690233B (en) 2024-03-08

Similar Documents

Publication Publication Date Title
US9520488B2 (en) Silicon-controlled rectifier electrostatic discharge protection device and method for forming the same
US9911728B2 (en) Transient voltage suppressor (TVS) with reduced breakdown voltage
JP3413250B2 (en) Semiconductor device and manufacturing method thereof
US9397010B2 (en) Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
US10128227B2 (en) ESD protection device and method for manufacturing the same
JP6237915B2 (en) Semiconductor device and manufacturing method of semiconductor device
TW200828569A (en) Latch-up free vertical TVS diode array structure using trench isolation
US9929137B2 (en) Method for manufacturing ESD protection device
TW201306254A (en) Methods for fabricating anode shorted field stop insulated gate bipolar transistor
JP2010050441A (en) Semiconductor device
JP2012186353A (en) Composite semiconductor device
CN104465791A (en) Structure of fast recovery diode and preparation method for back face of fast recovery diode
CN113690233A (en) Unidirectional ESD protection device capable of enhancing through-current capacity and manufacturing method thereof
CN111446239A (en) Low-capacitance low-clamping voltage transient voltage suppressor and manufacturing method thereof
CN111370407A (en) Low-voltage low-capacitance unidirectional ESD (electro-static discharge) protection device and manufacturing method thereof
CN114334953A (en) Low-capacitance unidirectional ESD protection device and manufacturing method thereof
US9960158B2 (en) Semiconductor device
JP4096722B2 (en) Manufacturing method of semiconductor device
CN106558624B (en) Fast recovery diode and manufacturing method thereof
CN216773247U (en) Low-capacitance unidirectional ESD (electro-static discharge) protection device
CN111415984A (en) Manufacturing method of reverse conducting IGBT device
CN111863941A (en) Anti-radiation VDMOS device and preparation method thereof
CN107346791B (en) Transient voltage suppression diode and preparation method thereof
CN113889466A (en) Unidirectional ESD protector capable of enhancing ESD anti-interference capability and manufacturing method
JP2020057746A (en) Semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20220808

Address after: 226200 1800 Mudanjiang West Road, Huilong Town, Qidong City, Nantong City, Jiangsu Province

Applicant after: Jiangsu Jilai Microelectronics Co.,Ltd.

Applicant after: Chengdu Jilaixin Technology Co.,Ltd.

Address before: 610096 No. 505, floor 5, building 6, No. 599, shijicheng South Road, Chengdu hi tech Zone, Chengdu pilot Free Trade Zone, Sichuan Province

Applicant before: Chengdu Jilaixin Technology Co.,Ltd.

GR01 Patent grant
GR01 Patent grant