CN104465791A - Structure of fast recovery diode and preparation method for back face of fast recovery diode - Google Patents

Structure of fast recovery diode and preparation method for back face of fast recovery diode Download PDF

Info

Publication number
CN104465791A
CN104465791A CN201310441203.XA CN201310441203A CN104465791A CN 104465791 A CN104465791 A CN 104465791A CN 201310441203 A CN201310441203 A CN 201310441203A CN 104465791 A CN104465791 A CN 104465791A
Authority
CN
China
Prior art keywords
groove
type
area
district
type area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310441203.XA
Other languages
Chinese (zh)
Other versions
CN104465791B (en
Inventor
苏冠创
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing Lisheng Semiconductor Technology Co ltd
Original Assignee
SHENZHEN LIZHEN SEMICONDUCTOR Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SHENZHEN LIZHEN SEMICONDUCTOR Co Ltd filed Critical SHENZHEN LIZHEN SEMICONDUCTOR Co Ltd
Priority to CN201310441203.XA priority Critical patent/CN104465791B/en
Publication of CN104465791A publication Critical patent/CN104465791A/en
Application granted granted Critical
Publication of CN104465791B publication Critical patent/CN104465791B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes

Abstract

The invention discloses a structure of a fast recovery diode and a preparation method for the back face of the fast recovery diode. A unit structure of an active region of a device is characterized by comprising at least one groove, a part of the region between the grooves is a p-type region, a part of the region between the grooves is an n-type region, a part of the surface between the grooves is the surface of the p-type region, a part of the region between the grooves is the thin-layer p+ region, the surface between the grooves is provided with a contact hole, the surface p-type region and the thin-layer p+ region are connected to a surface electrode through the contact hole, and the grooves are connected to the surface electrode. The preparation method for the back face comprises the steps that hydrogen ions are injected into the back face of a silicon wafer, then, back face metallization is carried out by means of a sputtering or deposition method, and then the injected hydrogen ions are activated in an annealing mode.

Description

A kind of structure of fast recovery diode and the preparation method at the back side
Technical field
The present invention relates to a kind of design and manufaction technique of semiconductor power device, more particularly relate to a kind of semiconductor power fast recovery diode (the being called for short FRD) design of device and the new method of back side processing technology.
Background technology
The commercialization of thyristor is realized in 1956 by GE (GE).Since then, thyristor becomes rapidly the essential core switch of field of power electronics.Much different device architectures is derived by thyristor structure.Device performance is become better and better, and power level is more and more higher.Early stage thyristor power, about a few hectowatt, to the initial stage eighties, is developed to MW class.But, its operating frequency of the structural limitations of thyristor itself.The operating frequency of thyristor, generally lower than 5KHz, which greatly limits its application.At the initial stage eighties, there is multiple high frequency gated power device, and obtained and develop rapidly.These devices comprise (i) power MOS pipe, (ii) IGBT (insulated gate bipolar transistor Insulated Gate BipolarTransistor), (iii) SIT, (iv) MCT (MOS controls thyristor MOS Controlled Thyristor) etc.
1980, RCA Corp. of the U.S. applied for first IGBT patent, and within 1985, Toshiba Corp has made first industrial IGBT.From device physically, it is non-transparent collector punch IGBT, referred to as punch IGBT (Punchthrough IGBT-is abbreviated as PT-IGBT).
The turn-off time of early stage PT-IGBT is relatively very long, about has several microsecond, in order to shorten the turn-off time, improve switching speed, after the nineties, generally all quote high energy particle irradiation technique (as electron irradiation, hydrogen ion or helium ion irradiation etc.) and reduce excess carrier lifetime in device.This method can improve the switching speed of PT-IGBT, but on state voltage can be made to reduce to negative temperature coefficient, and negative temperature coefficient is a performance deficiency of PT-IGBT.
In 1996, motorola inc delivered one section of article description about manufacturing the research of non-break-through IGBT, and stress the technique how manufacturing collector electrode in thin silicon wafer, the thinnest of FZ n-type silicon chip used about has 170um thick.In next year, Infineon company has also delivered the NPT-IGBT making 600V by the FZ n-type silicon chip that 100um is thick.About 99 years, the IGBT of industrial a new generation starts to go into operation, the IGBT of this new generation is a kind of high-speed switching devices, its voltage reduces to positive temperature coefficient, it does not need to shorten minority carrier life time in device with heavy metal or irradiation, and main technology is that ultra thin silicon wafers technique adds weak collector junction (or being called transparent collector junction).Infineon company is referred to as field cut-off IGBT, the following years, and the company of each main production IGBT all releases one after another similar product.From that time, IGBT obtains qualitative leap on electric property, develops rapidly and has dominated the market of medium power range.
Along with the development of power device IGBT technology, the switching speed of IGBT is more and more faster, in application system, the IGBT with high-speed switch need to ask adopt fast diode as fly-wheel diode.Switching device IGBT is each time from opening to turn off process, and fly-wheel diode can become cut-off state from conducting state.And this process entails diode has fast soft recovery characteristics.In application process, wish that the power consumption of system is little, the electromagnetic noise that reliability is high and less, this all has high requirements to IGBT and FRD, but, in a very long time, industry ignores the exploitation of fast diode, because the performance of FRD does not catch up with, become the usefulness of restriction whole system, the performance of carving right IGBT is fine, also cannot bring into play, and the effect of fast diode receives the attention of height.Fast recovery diode (be called for short FRD) be a kind ofly have that switching characteristic is good, reverse recovery time short feature semiconductor diode, be mainly used in the electronic circuits such as Switching Power Supply, PWM pulse width modulator, uninterrupted power supply (UPS), frequency conversion and speed regulation of AC motor device.Using as the fly-wheel diode of high frequency, big current, high-frequency rectification diode or damper diode, is extremely rising electric power, electronic semiconductor components.The internal structure of fast recovery diode is different from common PN junction diode, and it belongs to PIN junction type diode, namely in the middle of P-type silicon material and N-type silicon materials, adds base I, forms PIN structural.The thickness of base and doping content determine the reverse breakdown voltage value (withstand voltage) of FRD.
The technology that FRD is main and performance (i.e. electrical parameter) have (1) puncture voltage, and turn-off characteristic etc. is opened in (2) forward voltage drop and (3).Turn-on characteristics refers to the transient state peak forward voltage occurred when voltage becomes reverse from forward, and what turn-off characteristic was mainly paid close attention to is reverse recovery characteristic.Reverse recovery characteristic (with reference to figure 1): when voltage becomes reverse from forward, electric current does not become at once (-I 0), but in a period of time ts, reverse current is very large all the time, and diode does not turn off.After ts, reverse current just diminishes gradually, then through the tf time, the electric current of diode just becomes (-I 0), as shown in Figure 1.Ts is called the storage time, and tf is called fall time.Trr=ts+tf is called reverse recovery time, and s=tf/ts is called the soft factor, I rRMfor maximum reverse restoring current, above process is called reversely restoring process.
In general, forward voltage drop is conflicting with reverse recovery characteristic, namely improve forward voltage drop and just can injure reverse recovery characteristic, as added the hole-electron pair density of n-extension layer, forward voltage drop can improve, but stored maximum reverse restoring current when more electric charge can make shutoff increase and reverse recovery time elongated, thus shutoff power consumption is increased.
Sometimes FRD can be in avalanche breakdown Like state And and has suitable electric current to flow through device in the application, in this case, if the design of device knot groove is bad, device can be easy to be broken, analyze occur in active area and termination environment when finding a lot of by the place of breaking junction near.
Since two thousand, the technological development making IGBT by thin silicon wafer technique is rapid, and the silicon chip that process 50um is thick or thicker is very ripe.Along with the development that thin silicon wafer IGBT makes, naturally corresponding technology is also used to make the technique that FRD. FZ n-type silicon chip manufactures 400V to 1200V FRD, is mainly divided into two large divisions, i.e. preceding working procedure and later process.Preceding working procedure is mainly made the front structure of device on the surface of FZ n-type silicon chip.After preceding working procedure completes just FZ silicon chip wear down to desired thickness, be 1200V as withstand voltage, then desired thickness is about about 120um.Then later process is entered, need in later process overleaf implant n-type dopant as electron emitter, general injection phosphorus or arsenic, if fruit is only injected once, silicon chip back side can form a height knot, and this can make the soft factor hardening, larger electromagnetic noise or vibration can be produced during shutoff, this is unacceptable, and general solution injects Two N-shaped impurity overleaf, as following scheme:
Scheme one:
The back side of (i) FZ n-type silicon chip after completing wear down technique, by ion implantation, implant n-type dopant (phosphonium ion or arsenic ion) is to the different depth of required injection at twice, what relatively dark and concentration was lower is resilient coating, inject relatively shallow and concentration higher be emission layer, general resilient coating implantation dosage scope is 5 × 10 13/ cm 2to 5 × 10 14/ cm 2, Implantation Energy is 500KeV to 2MeV, and emission layer implantation dosage scope is 1 × 10 15/ cm 2to 1 × 10 16/ cm 2, Implantation Energy is 30KeV to 100KeV;
(ii) then carry out back face metalization with sputtering or deposition process, metal level can be aluminium/nickel/silver or titanium/nickel/silver or other;
(iii) to the phosphonium ion injected before or arsenic ion, annealing is all needed to activate, typical annealing conditions is 300 DEG C to 450 DEG C in temperature range, anneal 30 minutes to 100 minutes, annealing steps before formation backplate, or can carry out afterwards or in the middle of formation backplate step.
Scheme two:
In order to further increase the soft factor, with outside injection Two N-shaped doping, also can implanted with p-type dopant, without mask plate during implant n-type dopant, during implanted with p-type doping, need mask plate, through the effect of mask plate, make silicon chip back side have partial area to be injected by p-type dopant, have part not injected by p-type dopant, those territories, p type island region are separated as shown in Figure 2 by n-type area each other, this p-type area can form pn with the n-type area of surrounding it and tie, and general junction depth is no more than 0.5um.Implanted with p-type dopant is boron ion, and dosage range is 5 × 10 14/ cm 2to 5 × 10 15/ cm 2, Implantation Energy is 30KeV to 100KeV.
Summary of the invention
The present invention is that to have taken into account the design and use of device front portion simple effectively and the back side injection technology of lower cost, when anterior device layout makes device forward, too many hole can not be injected in Yang pole before FRD, during shutoff, charge carrier is easier flows away from surface, puncture Shi Huixian and occur in active area place equably, and active area place has enough contact window to absorb when puncturing to produce a large amount of charge carriers, make FRD be in avalanche breakdown Like state not easily to be broken, the back side is injected and only need be injected the N-shaped emission layer that just can form n shape resilient coating and high concentration by a n-type dopant, concrete method carried out therewith is described below:
Embodiment (1) is relevant back side injection technology, and method is as follows:
I the back side of () FZ n-type silicon chip after completing wear down technique, by ion implantation, hydrogen injecting ion, the injection direction of silicon chip relative ion is tilted to be less than 10 degree, and implantation dosage scope is 1 × 10 14/ cm 2to 1 × 10 16/ cm 2, Implantation Energy is 20KeV to 100V;
(ii) then carry out back face metalization with sputtering or deposition process, metal level can be aluminium/nickel/silver or titanium/nickel/silver or other;
(iii) to the hydrogen ion injected before, need annealing to activate, typical annealing conditions is 300 DEG C to 450 DEG C in temperature range, anneals 30 minutes to 100 minutes, annealing steps before formation backplate, or can carry out afterwards or in the middle of formation backplate step.
Embodiment (2) is relevant back side injection technology, and method is as follows:
I the back side of () FZ n-type silicon chip after completing wear down technique, by ion implantation, hydrogen injecting ion, the injection direction of silicon chip relative ion is tilted to be less than 10 degree, and implantation dosage scope is 1 × 10 14/ cm 2to 1 × 10 16/ cm 2, Implantation Energy is 20KeV to 100V;
(ii) at the back side of silicon chip, with ion implantation implanted with p-type dopant, the junction depth of the p-type dopant injected is less than 0.5um, dopant implant matter ionic species is boron ion, the injection precedence of the p-type dopant injected and n-type dopant described before can be random, and implantation dosage scope is 5 × 10 14/ cm 2to 5 × 10 15/ cm 2, Implantation Energy is 20KeV to 100V;
(iii) then carry out back face metalization with sputtering or deposition process, metal level can be aluminium/nickel/silver or titanium/nickel/silver or other;
(iv) to hydrogen injecting ion and boron ion before, all need annealing to activate, typical annealing conditions is 300 DEG C to 450 DEG C in temperature range, anneals 30 minutes to 100 minutes, annealing steps before formation backplate, or can carry out afterwards or in the middle of formation backplate step.
Embodiment (3): with reference to figure 3,
Device cell contains at least one groove, and the degree of depth is 0.8um to 6.0um, and width is 0.2um to 2.0um, cell size be greatly less 1.0um to 10um not etc.Trench wall has oxide layer and inserts electric conducting material as highly doped polysilicon, partial area is had to be p-type area between groove and groove, partial area is had to be n-type area, there is part on surface between groove and groove for the surface of p-type area, partial area is had to be thin layer p+ district, there is contact hole on surface between groove and groove, contact hole the p-type area on surface and thin layer p+ district be connected to surface electrode (with reference to 3 li, figure a), or the p-type area on surface, n-type area and thin layer p+ district are connected to table electrode (b with reference to 3 li, figure), the junction depth in thin layer p+ district is less than 0.5um, concentration is less than 1 × 10 20/ cm 3transparency electrode is formed with surface metal, electronics can arrive external metallization through thin layer p+ district, groove is also connected to table electrode, the back side of Fig. 3 is only filled with hydrogen ion, the back side of Fig. 4 and Fig. 5 is filled with hydrogen ion and p-type ion, and the structure of Fig. 6 and Fig. 7 also belongs to embodiment (3).
Embodiment (4): with reference to figure 8,
The cellular construction of device and roughly the same described in embodiment one, just between groove and groove, there is p-type area, n-type area is not had among p-type area, there is contact hole on surface between groove and groove, contact hole is connected to surface electrode the p-type area on surface and thin layer p+ district, groove is also connected to surface electrode, and the junction depth in thin layer p+ district is less than 0.5um, and concentration is less than 1 × 10 20/ cm 3, form transparency electrode with surface metal.
Embodiment (5): with reference to figure 9,
The cellular construction of device and roughly the same described in embodiment (3) or embodiment (4), the surface just between groove and groove does not singly have p-type area and thin layer p+ district to also have n+ district; Or have p type island region, n-type area, n+ district and thin layer p+ district, there is contact hole on surface between groove and groove, and contact hole is the p-type area on surface, and thin layer p+ district and n+ district are connected to surface electrode, groove is also connected to surface electrode, and the degree of depth in n+ district is less than 0.6um from surface, and concentration is less than 1 × 10 20/ cm 3, thin layer p+ district junction depth is less than 0.5um, and concentration is less than 1 × 10 20/ cm 3, thin layer p+ district and surface metal form transparency electrode.
Embodiment (6): with reference to figures 10 to Figure 15
The cellular construction of device and roughly the same before described in each embodiment, just under surface p-type district, have a n-type area, the concentration of this n-type area is about 1 × 10 15/ cm 3to 2 × 10 16/ cm 3be high than the concentration of original N-shaped FZ silicon chip, this n-type area is formed via the n-type dopant injecting channel bottom, or by the n-type dopant of surface imp lantation through diffuseing to form, Figure 10 to Figure 15 is the cross-sectional structure schematic diagram of some devices belonging to embodiment (6), and Figure 16 comprises the unit of device and the cross-sectional structure schematic diagram of terminal.
The scheme of the above each preparation method can be used for semiconductor power device as IGBT or MCT or GTO etc. or power MOS pipe.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein is only for instruction and explanation of the present invention, is not intended to limit the present invention.
The manufacturing process of a kind of semiconductor power device of the present invention can be divided into preceding working procedure and later process, preceding working procedure is manufactured on the front surface of FZ silicon chip the surface cell of device, its method prepared comprises the following steps: utilize trench mask to form p-type base in the surface imp lantation p-type dopant of FZ silicon chip, corrode afterwards and form groove to the surface of n-type area FZ silicon chip; Then to channel bottom implant n-type dopant, then implant n-type dopant forms n+ district, at FZ silicon chip surface interlayer dielectric, recycling contact hole mask, inter-level dielectric is corroded, in inter-level dielectric, form perforate, afterwards effects on surface implanted with p-type dopant, then metal plug filling is carried out to contact hole; Finally, at the surface deposition metal level of device, metal mask is utilized to carry out metal attack, form metal pedestal layer and line, later process the back side wear down of FZ n-type silicon chip to desired thickness, then hydrogen injecting ion and boron ion overleaf, then carries out back face metalization and annealing, adopts this preparation method can produce the structure of described a kind of semiconductor power device.
Preferred embodiment:
The present embodiment does not comprise relevant termination environment step.
As shown in figure 17, accumulation or hot growth pattern is adopted to form oxide layer 17 (thickness is 0.3um to 1.5um oxide hard light shield) at n-type area FZ silicon chip surface, accumulation one deck lithography coating 18 again in oxide layer, then form by trench mask the some parts that pattern exposes oxide layer, formed after the oxide layer that exposes of pattern carries out dry corrosion to trench mask, expose FZ silicon chip surface, then dispose lithography coating.
As shown in figure 18, then to silicon chip surface implanted with p-type dopant, (B11, dosage is 7e12/cm 2to 2e16/cm 2), then by High temperature diffusion process, temperature is 950 to 1200 DEG C, and the time is 10 minutes to 300 minutes, and make p-type dopant Tui Jin spread and form p-type area 4, the p-type area degree of depth is 2.0um to 5.5um.
As shown in figure 19, form groove 19 by etching, groove 19 (degree of depth is 0.8um to 6um, and width is 0.2um to 2.0um) extends in N-shaped FZ silicon chip.
As shown in figure 20, after formation of the groove, (time is 10 minutes to 100 minutes to carry out sacrificial oxidation to groove, temperature is 1000 DEG C to 1200 DEG C), to eliminate by the silicon layer that plasma destroys in grooving process, afterwards to channel bottom implant n-type dopant, assorted agent dose is 1x10 12to 1 × 10 14/ cm 2, by High temperature diffusion process, temperature is 950 to 1200 DEG C, and the time is 10 minutes to 100 minutes, makes n-type dopant diffuse to form n-type area 5 at channel bottom Tui Jin.
As shown in figure 21, then all oxide layers are disposed, and by the hot mode grown, the sidewall that expose at groove and the upper surface of bottom and N-shaped FZ silicon chip form layer of oxide layer (thickness is 0.01um to 0.4um), and the polysilicon 9 of depositing n-type high dopant in the trench, polysilicon doping concentration is R s=5 Ω/ to 100 Ω/ (sheet resistance), covers end face with filling groove, then carries out plane corrosion treatment to the polysilicon layer on FZ silicon chip surface.
As shown in figure 22, at the surperficial accumulation lithography coating of FZ silicon chip, utilize n+ mask to expose the surface of part FZ silicon chip, then to silicon chip surface implant n-type dopant, (P31 or As, dosage is 1e15/cm 2to 2e16/cm 2), then dispose lithography coating, by High temperature diffusion process, temperature is 950 to 1200 DEG C, and the time is 10 minutes to 100 minutes, makes n-type area Tui Jin be diffused into p-type base and forms n+ district 7 (the n+ district degree of depth is 0.2um to 0.6um).
As shown in figure 23, epitaxial loayer most surface first deposits undoped silicon dioxide layer (thickness is 0.1um to 0.5um), then deposit boro-phosphorus glass (thickness is 0.1um to 0.8um) and form inter-level dielectric 13, at inter-level dielectric surface accumulation lithography coating, contact hole mask is utilized to expose part inter-level dielectric, then dry corrosion is carried out to the part inter-level dielectric exposed, until expose the upper surface of FZ n-type silicon chip, multiple contact hole mask perforate is formed in inter-level dielectric, then lithography coating is disposed, then to silicon chip surface implanted with p-type dopant (B11, dosage is 1e15/cm 2to 1e16/cm 2), not by High temperature diffusion process, make surface metal in p-type dopant and contact hole groove form transparency electrode.
As shown in figure 24, one deck titanium/titanium nitride layer is deposited in the contact hole with inter-level dielectric upper surface, then carry out tungsten 15 to contact hole to fill to form metal plug, one deck aluminium alloy 16 (thickness is 0.8um to 10um) is deposited again on this device, then carry out metal etch by metal mask, form surface metal bed course and termination environment field plate.
As shown in figure 25, complete the back side of just wear down FZ n-type silicon chip after preceding working procedure to desired thickness, then hydrogen injecting ion and boron ion overleaf, then carry out back face metalization and annealing.
Last it is noted that these are only the preferred embodiments of the present invention, be not limited to the present invention, the present invention can be used for relating to manufacture trench semiconductor power discrete device (such as, insulated trench gate bipolar transistor (Trench IGBT) or diode), the present invention can be used for the trench semiconductor power discrete device preparing 400V to 6500V, embodiments of the invention are made an explanation with N-shaped device, the present invention also can be used for p-type device, although with reference to embodiment to invention has been detailed description, for a person skilled in the art, it still can be modified to the technical scheme described in previous embodiment, or equivalent replacement is carried out to wherein portion of techniques feature, but it is within the spirit and principles in the present invention all, any amendment of doing, equivalent replacement, improve, all should be included within protection scope of the present invention.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, together with embodiments of the present invention for explaining the present invention, is not construed as limiting the invention, in the accompanying drawings:
Fig. 1 is the reverse recovery characteristic schematic diagram of fast recovery diode when turning off;
Fig. 2 is the vertical view that back surface of the present invention has p+ type region and n+ type region;
Fig. 3 is the cross-sectional structure schematic diagram of the device of the embodiment of the present invention (3);
Fig. 4 is the another kind of cross-sectional structure schematic diagram of the device of the embodiment of the present invention (3);
Fig. 5 is the another kind of cross-sectional structure schematic diagram of the device of the embodiment of the present invention (3);
Fig. 6 is the another kind of cross-sectional structure schematic diagram of the device of the embodiment of the present invention (3);
Fig. 7 is the another kind of cross-sectional structure schematic diagram of the device of the embodiment of the present invention (3);
Fig. 8 is the cross-sectional structure schematic diagram of the device of the embodiment of the present invention (4);
Fig. 9 is the cross-sectional structure schematic diagram of the device of the embodiment of the present invention (5);
Figure 10 is the cross-sectional structure schematic diagram of the device of the embodiment of the present invention (6);
Figure 11 is the another kind of cross-sectional structure schematic diagram of the device of the embodiment of the present invention (6);
Figure 12 is the another kind of cross-sectional structure schematic diagram of the device of the embodiment of the present invention (6);
Figure 13 is the another kind of cross-sectional structure schematic diagram of the device of the embodiment of the present invention (6);
Figure 14 is the another kind of cross-sectional structure schematic diagram of the device of the embodiment of the present invention (6);
Figure 15 is the another kind of cross-sectional structure schematic diagram of the device of the embodiment of the present invention (6);
Figure 16 is the unit comprising device of the embodiment of the present invention (6) and the cross-sectional structure schematic diagram of terminal;
Figure 17 exposes oxide layer schematic diagram in the preferred embodiment of the present invention;
Figure 18 is the schematic diagram to silicon chip surface implanted with p-type dopant in the preferred embodiment of the present invention;
Figure 19 is groove schematic diagram in the preferred embodiment of the present invention;
Figure 20 is to channel bottom implant n-type dopant schematic diagram in the preferred embodiment of the present invention;
Figure 21 is to the schematic diagram carried out after surface plane process in the preferred embodiment of the present invention;
Figure 22 is the surface n+district's schematic diagram in the preferred embodiment of the present invention;
Figure 23 is the schematic diagram in the preferred embodiment of the present invention, silicon chip surface being injected to skin layer p+ dopant;
Figure 24 is the surfaces of aluminum alloy-layer electrode schematic diagram in the preferred embodiment of the present invention;
Figure 25 is the cross-sectional structure schematic diagram completing later process in the preferred embodiment of the present invention.
Reference symbol table:
1 p+ district, the back side
2 n buffering area, the back side and n+ districts
3 N-shaped bases
4 p-type bases
Bottom 5 p-type area or the n-type area of channel bottom (floating voltage)
6 p-type area (floating voltage)
7 surface n+district
8 surface p+district
Highly doped polysilicon in 9 grooves
10 contact hole grooves
The p-type high-doped zone of 11 contact hole channel bottoms
The contact hole of 12 planes
13 inter-level dielectrics
14 titaniums/titanium nitride layer
15 tungsten layers
16 aluminium alloy layers
17 oxide layers
18 lithography coatings
19 grooves
20 skin layer p+ districts

Claims (12)

1. the preparation method at the back side of fast recovery diode, is characterized in that, comprises the following steps:
I the back side of () FZn type silicon chip after completing wear down technique, by ion implantation, hydrogen injecting ion, the injection direction of silicon chip relative ion is tilted to be less than 10 degree, and implantation dosage scope is 1 × 10 14/ cm 3to 1 × 10 16/ cm 3, Implantation Energy is 20KeV to 100V;
(ii) then carry out back face metalization with sputtering or deposition process, metal level can be aluminium/nickel/silver or titanium/nickel/silver or other;
(iii) to the hydrogen ion injected before, need annealing to activate, typical annealing conditions is 300 DEG C to 450 DEG C in temperature range, anneals 30 minutes to 100 minutes, annealing steps before formation backplate, or can carry out afterwards or in the middle of formation backplate step.
2. the preparation method at the back side of fast recovery diode, is characterized in that, comprises the following steps:
I the back side of () FZ n-type silicon chip after completing wear down technique, by ion implantation, hydrogen injecting ion, the injection direction of silicon chip relative ion is tilted to be less than 10 degree, and implantation dosage scope is 1 × 10 14/ cm 3to 1 × 10 16/ cm 3, Implantation Energy is 20KeV to 100V;
(ii) at the back side of silicon chip, with ion implantation implanted with p-type dopant, the junction depth of the p-type dopant injected is less than 0.5um, dopant implant matter ionic species is boron ion, the injection precedence of the p-type dopant injected and n-type dopant described before can be random, and implantation dosage scope is 5 × 10 14/ cm 3to 5 × 10 15/ cm 3, Implantation Energy is 20KeV to 100V;
(iii) then carry out back face metalization with sputtering or deposition process, metal level can be aluminium/nickel/silver or titanium/nickel/silver or other;
(iv) to the hydrogen ion injected before and boron ion, annealing is all needed to activate, typical annealing conditions is 300 DEG C to 450 DEG C in temperature range, anneal 30 minutes to 100 minutes, annealing steps before formation backplate, or can carry out afterwards or in the middle of formation backplate step.
3. the structure of a fast recovery diode comprises with lower part:
(1) active area and termination environment;
(2) active area elementary cell includes:
(i) at least one groove, the degree of depth is 0.8um to 6.0um, and width is 0.2um to 2.0um, cell size be greatly less 1.0um to 10um not etc., trench wall is with oxide layer and insert electric conducting material as highly doped polysilicon;
(ii) there is partial area to be p-type area between groove and groove, have partial area to be n-type area;
(iii) there is part on the surface between groove and groove for the surface of p-type area, has part for thin layer p+ district;
(iv) there is contact hole on the surface between groove and groove, and contact hole is connected to surface electrode the p-type area on surface and thin layer p+ district, and the junction depth in thin layer p+ district is less than 0.5um, and concentration is less than 1 × 10 20/ cm 3, form transparency electrode with surface metal;
V () groove is also connected to surface electrode;
(vi) show electricity and have inter-level dielectric, surface metal and passivation layer etc.
4. the groove according to claim 3 in part (2) it (i), it is characterized in that there is a n-type area at channel bottom, the concentration of this n-type area is about 5 × 10 12/ cm 3to 1 × 10 14/ cm 3, this n-type area is high than the concentration of original N-shaped FZ silicon chip.
5. the surface according to claim 3 in part (2) it (iii) between groove and groove, it is characterized in that there is part on surface for the surface of p-type area, there is part for the surface in n+ type district, partial area is had to be thin layer p+ district, wherein p-type area, n+ type district and thin layer p+ district are touched Kong Lian by surface electrode.
6. the structure of a fast recovery diode comprises with lower part:
(1) active area and termination environment;
(2) active area elementary cell includes:
(i) at least one groove, the degree of depth is 0.8um to 6.0um, and width is 0.2um to 2.0um, cell size be greatly less 1.0um to 10um not etc., trench wall is with oxide layer and insert electric conducting material as highly doped polysilicon;
(ii) there is partial area to be p-type area between groove and groove, have partial area to be n-type area;
(iii) there is part on the surface between groove and groove for the surface of p-type area, has partial area to be n-type area, has partial area to be thin layer p+ district;
(iv) there is contact hole on the surface between groove and groove, and contact hole is the p-type area on surface, and n-type area and thin layer p+ district are connected to surface electrode, and the junction depth in thin layer p+ district is less than 0.5um, and concentration is less than 1 × 10 20/ cm 3, form transparency electrode with surface metal;
V () groove is also connected to surface electrode;
(vi) show electricity and have inter-level dielectric, surface metal and passivation layer etc.
7. the groove according to claim 6 in part (2) it (i), it is characterized in that there is a n-type area at channel bottom, the concentration of this n-type area is about 5 × 10 12/ cm 3to 1 × 10 14/ cm 3, this n-type area is high than the concentration of original N-shaped FZ silicon chip.
8. the surface according to claim 6 in part (2) it (iii) between groove and groove, it is characterized in that there is part on surface for the surface of p-type area, there is part for the surface of n-type area, there is part for the surface in n+ type district, partial area is had to be thin layer p+ district, wherein p-type area, n-type area, n+ type district and thin layer p+ district are touched hole and are connected to surface electrode.
9. the structure of a fast recovery diode comprises with lower part:
(1) active area and termination environment;
(2) active area elementary cell includes:
(i) at least one groove, the degree of depth is 0.8um to 6.0um, and width is 0.2um to 2.0um, cell size be greatly less 1.0um to 10um not etc., trench wall is with oxide layer and insert electric conducting material as highly doped polysilicon;
(ii) there is partial area to be p-type area between groove and groove, in p-type area, there is no n-type area;
(iii) there is part on the surface between groove and groove for the surface of p-type area, has partial area to be thin layer p+ district;
(iv) there is contact hole on the surface between groove and groove, and contact hole is connected to surface electrode the p-type area on surface and thin layer p+ district, and the junction depth in thin layer p+ district is less than 0.5um, and concentration is less than 1 × 10 20/ cm 3, form transparency electrode with surface metal;
V () groove is also connected to surface electrode;
(vi) show electricity and have inter-level dielectric, surface metal and passivation layer etc.
10. the groove according to claim 9 in part (2) it (i), it is characterized in that there is a n-type area at channel bottom, the concentration of this n-type area is about 5 × 10 12/ cm 3to 1 × 10 14/ cm 3, this n-type area is high than the concentration of original N-shaped FZ silicon chip.
11. according to claim 9 on the middle surface between groove and groove of part (2) it (iii), it is characterized in that there is part on surface for the surface of p-type area, n-type area is not had in p-type area, there is part on surface for n+ type district, surface has partial area to be thin layer p+ district, wherein p-type area, the surface in n+ type district and thin layer p+ district is touched hole and is connected to surface electrode.
12. according to claim 9 part (2) it (iv) in contact hole, it is characterized in that contact hole can be trench contact hole.
CN201310441203.XA 2013-09-22 2013-09-22 A kind of preparation method of the structure and the back side of fast recovery diode Expired - Fee Related CN104465791B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310441203.XA CN104465791B (en) 2013-09-22 2013-09-22 A kind of preparation method of the structure and the back side of fast recovery diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310441203.XA CN104465791B (en) 2013-09-22 2013-09-22 A kind of preparation method of the structure and the back side of fast recovery diode

Publications (2)

Publication Number Publication Date
CN104465791A true CN104465791A (en) 2015-03-25
CN104465791B CN104465791B (en) 2018-10-26

Family

ID=52911537

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310441203.XA Expired - Fee Related CN104465791B (en) 2013-09-22 2013-09-22 A kind of preparation method of the structure and the back side of fast recovery diode

Country Status (1)

Country Link
CN (1) CN104465791B (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106548938A (en) * 2015-09-23 2017-03-29 杭州士兰集成电路有限公司 Manufacturing method of semiconductor device
CN106653834A (en) * 2015-09-22 2017-05-10 苏州东微半导体有限公司 Method for manufacturing semiconductor power device
CN108624844A (en) * 2017-03-17 2018-10-09 株洲中车时代电气股份有限公司 A kind of wafer rear metallic film and preparation method thereof
CN115295414A (en) * 2022-10-08 2022-11-04 深圳芯能半导体技术有限公司 Silicon-based diode manufacturing method, silicon-based diode and diode device
CN115295613A (en) * 2022-10-08 2022-11-04 烟台台芯电子科技有限公司 Fast recovery diode structure and manufacturing method thereof
CN116435353A (en) * 2023-06-08 2023-07-14 广东巨风半导体有限公司 Reverse conducting insulated gate bipolar transistor structure and preparation method thereof
CN116454119A (en) * 2023-06-15 2023-07-18 广东巨风半导体有限公司 Fast recovery diode and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009141202A (en) * 2007-12-07 2009-06-25 Toyota Motor Corp Semiconductor device, and driving method of power supply device having the semiconductor device
CN101494223A (en) * 2008-01-23 2009-07-29 富士电机电子技术株式会社 Semiconductor device and method of producing the same
US20110233684A1 (en) * 2010-03-24 2011-09-29 Kabushiki Kaisha Toshiba Semiconductor device
JP2013008778A (en) * 2011-06-23 2013-01-10 Toyota Central R&D Labs Inc Diode
WO2013014943A2 (en) * 2011-07-27 2013-01-31 Kabushiki Kaisha Toyota Chuo Kenkyusho Diode, semiconductor device, and mosfet

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009141202A (en) * 2007-12-07 2009-06-25 Toyota Motor Corp Semiconductor device, and driving method of power supply device having the semiconductor device
CN101494223A (en) * 2008-01-23 2009-07-29 富士电机电子技术株式会社 Semiconductor device and method of producing the same
US20110233684A1 (en) * 2010-03-24 2011-09-29 Kabushiki Kaisha Toshiba Semiconductor device
JP2013008778A (en) * 2011-06-23 2013-01-10 Toyota Central R&D Labs Inc Diode
WO2013014943A2 (en) * 2011-07-27 2013-01-31 Kabushiki Kaisha Toyota Chuo Kenkyusho Diode, semiconductor device, and mosfet

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106653834A (en) * 2015-09-22 2017-05-10 苏州东微半导体有限公司 Method for manufacturing semiconductor power device
CN106548938A (en) * 2015-09-23 2017-03-29 杭州士兰集成电路有限公司 Manufacturing method of semiconductor device
CN108624844A (en) * 2017-03-17 2018-10-09 株洲中车时代电气股份有限公司 A kind of wafer rear metallic film and preparation method thereof
CN108624844B (en) * 2017-03-17 2019-11-12 株洲中车时代电气股份有限公司 A kind of backside of wafer metallic film and preparation method thereof
CN115295414A (en) * 2022-10-08 2022-11-04 深圳芯能半导体技术有限公司 Silicon-based diode manufacturing method, silicon-based diode and diode device
CN115295613A (en) * 2022-10-08 2022-11-04 烟台台芯电子科技有限公司 Fast recovery diode structure and manufacturing method thereof
CN115295414B (en) * 2022-10-08 2023-03-24 深圳芯能半导体技术有限公司 Silicon-based diode manufacturing method, silicon-based diode and diode device
CN116435353A (en) * 2023-06-08 2023-07-14 广东巨风半导体有限公司 Reverse conducting insulated gate bipolar transistor structure and preparation method thereof
CN116454119A (en) * 2023-06-15 2023-07-18 广东巨风半导体有限公司 Fast recovery diode and preparation method thereof

Also Published As

Publication number Publication date
CN104465791B (en) 2018-10-26

Similar Documents

Publication Publication Date Title
CN107799582B (en) Trench gate charge storage type insulated gate bipolar transistor and manufacturing method thereof
CN104465791A (en) Structure of fast recovery diode and preparation method for back face of fast recovery diode
CN103872144B (en) A kind of soft fast recovery diode and manufacture method thereof
CN106128946A (en) Semiconductor device and the manufacture method of semiconductor device
CN105679816B (en) A kind of trench gate charge storage type IGBT and its manufacturing method
JPH06169088A (en) Semiconductor device and its manufacture
CN102867846A (en) Semiconductor device
CN110504310B (en) RET IGBT with self-bias PMOS and manufacturing method thereof
CN113571415B (en) IGBT device and manufacturing method thereof
CN105679667A (en) Manufacturing method for terminal structure of trench IGBT device
CN103325679B (en) Method for manufacturing back of semiconductor power device
CN111244171A (en) Trench RC-IGBT device structure and manufacturing method thereof
JP4904625B2 (en) Semiconductor device
CN110429077B (en) Single-particle burnout resistant structure suitable for power semiconductor device
CN104167436A (en) Semiconductor power device structure
JP4096722B2 (en) Manufacturing method of semiconductor device
CN113851379A (en) IGBT device and manufacturing method thereof
CN207781616U (en) Power semiconductor
CN113851380B (en) IGBT device and manufacturing method thereof
CN113497158A (en) Fast recovery semiconductor device and manufacturing method thereof
CN104600125B (en) A kind of device architecture of fast recovery diode
CN211789025U (en) Trench RC-IGBT device structure
CN105489636B (en) A kind of backside structure of semiconductor power device
CN104465732A (en) Semiconductor power device structure
CN112951915B (en) Power device reinforcing structure capable of resisting single-particle burning and preparation method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
DD01 Delivery of document by public notice

Addressee: SHENZHEN LIZHEN SEMICONDUCTOR Co.,Ltd.

Document name: Notification of Patent Invention Entering into Substantive Examination Stage

TA01 Transfer of patent application right

Effective date of registration: 20170504

Address after: Gulou District of Nanjing City, Jiangsu province 210000 loop Longqiao No. 15-1

Applicant after: NANJING LISHENG SEMICONDUCTOR TECHNOLOGY Co.,Ltd.

Address before: 518057 new Guangdong city in Shenzhen Province, the central area of Baoan Lu Mei Ju D District Business Center building room 801-806

Applicant before: SHENZHEN LIZHEN SEMICONDUCTOR Co.,Ltd.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20181026

Termination date: 20210922

CF01 Termination of patent right due to non-payment of annual fee