CN104167436A - Semiconductor power device structure - Google Patents
Semiconductor power device structure Download PDFInfo
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- CN104167436A CN104167436A CN201310187825.4A CN201310187825A CN104167436A CN 104167436 A CN104167436 A CN 104167436A CN 201310187825 A CN201310187825 A CN 201310187825A CN 104167436 A CN104167436 A CN 104167436A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 238000002161 passivation Methods 0.000 claims abstract description 3
- 239000002019 doping agent Substances 0.000 claims description 22
- 238000009792 diffusion process Methods 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 9
- 239000007943 implant Substances 0.000 claims 1
- 239000011229 interlayer Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 29
- 229910052710 silicon Inorganic materials 0.000 description 29
- 239000010703 silicon Substances 0.000 description 29
- 238000010586 diagram Methods 0.000 description 24
- 238000000034 method Methods 0.000 description 12
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- 238000001459 lithography Methods 0.000 description 11
- 239000011248 coating agent Substances 0.000 description 10
- 108091006146 Channels Proteins 0.000 description 9
- 238000009825 accumulation Methods 0.000 description 7
- 238000005260 corrosion Methods 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 238000009826 distribution Methods 0.000 description 5
- 239000002800 charge carrier Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 230000007773 growth pattern Effects 0.000 description 2
- 230000009931 harmful effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
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- 229910001385 heavy metal Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Abstract
The invention discloses a semiconductor power device structure which is characterized in that units of an active region include at least one deep trench, at least one shallow trench, P-type base regions, N-type regions, N-type base regions, N+ emission regions, contact holes, an interlayer dielectric, a surface metal, a passivation layer and the like, and the bottom of the deep trench is provided with at least one doped region. In forward conduction, the doped regions at the bottom of the deep trench can help to increase the surface carrier concentration so as to improve the forward voltage drop without increasing the switch-off time.
Description
Technical field
The present invention relates to a kind of semiconductor power device technology field, specifically, relate to a kind of structure of groove-type power field-effect transistor IGBT device.
Background technology
1980, U.S. RCA Corp. applied for first IGBT patent, and within 1985, Toshiba Corp has made first industrial IGBT.The physical structure of device, it is non-transparent collector punch IGBT, referred to as punch IGBT (Punchthrough IGBT-is abbreviated as PT-IGBT).In 1996, motorola inc delivered one piece of article and has described about manufacturing the research of non-break-through IGBT, stresses how on thin silicon sheet, to manufacture the technique of collector electrode, and the thinnest of FZ N-type silicon chip used approximately has 170um thick.In next year, Infineon company has also delivered the NPT-IGBT that makes 600V with the thick FZ N-type silicon chip of 100um.About 99 years, the IGBT of industrial a new generation starts to go into operation, the IGBT of this new generation is a kind of high-speed switching devices, it does not need to shorten minority carrier life time in device with heavy metal or irradiation, the technology of main use is that ultra thin silicon wafers technique adds weak collector junction or is called transparent collector junction, Infineon company is referred to as a cut-off IGBT, the following years, each company that mainly produces IGBT similar product that all releases one after another.
The technology that IGBT is main and performance (being electrical parameter) have (1) puncture voltage, (2) forward voltage drop, (3) switching characteristic, (4) short circuit place of safety (SCSOA), (5) reverse bias place of safety (RBSOA) and (6) forward bias place of safety (FBSOA) etc.Forward voltage drop is conflicting with switching speed, can injure the performance of switching speed, as increased N just improved forward voltage drop
-the hole-electron pair density of extension layer, forward voltage drop can improve, and can make the turn-off time increase, thereby make turn-off speed variation but stored more electric charge.Target of the present invention is that contradiction between forward voltage drop and switching speed is down to is minimum, when reduced forward voltage drop, being down to minimum to the harmful effect of switching speed.
In order to reduce the turn-off time, indirectly increase frequency capability and reduce the turn-off time, not quite increase forward voltage drop simultaneously, designer need to optimize the CHARGE DISTRIBUTION of injection device inside, make when forward conduction, the distribution of IGBT device inside charge carrier as shown in Figure 1, wants high in emitter terminal carrier concentration, low in collector terminal carrier concentration.The structure of field cut-off IGBT can provide effective mechanism, makes when forward conduction, and the weak collector electrode carrier concentration in the back side is less, during shutoff, can effectively rapidly charge carrier in body be removed.
Thin silicon blade technolgy adds that the transparent collector junction in the back side can be used for concentration and the distribution of control device back electric charge effectively, relatively little to concentration and distribution influence near surperficial Partial charge, affect device near concentration and the distribution of surperficial Partial charge, the most effective and easy method is to use the cellular construction of device surface, the concentration that improves device surface part charge carrier can reduce forward voltage drop, (after 2010) have several new surface cell structures to be used to improve forward voltage drop recently, and they have following several scheme:
Scheme one:
As shown in Figure 2, it is compared with general conventional trench IGBT, and its channel bottom is large than groove top, and the distance between undercut wall can be less than 0.3 μ m.
Scheme two:
As shown in Figure 3, compare with general trench IGBT, its special feature is in Xia YouyiNXing district, P type base 5, Xia Youyi p type island region, N-type district 6, and this p type island region 6 is not connected to surperficial emission electrode.
Scheme three:
Use superfine basic structural unit, general trench IGBT cell size is greater than 3.0 μ m, and this superfine construction unit size can be less than 1.0 μ m.
Several schemes all can reach increase surface carrier concentration above, thereby improve forward voltage drop, do not increase again the turn-off time, but they have some shortcomings, the technique of scheme one and scheme two is prepared more complicated, is unfavorable for cost and manufacture, and scheme three can make gate capacitance increase, this can increase the power consumption of drive circuit, and their these shortcomings are to be improved.
Summary of the invention
The object of the invention is to propose a new device architecture makes the contradiction between forward voltage drop and switching speed be down to minimum, as while reducing forward voltage drop, being down to minimum to the harmful effect of switching speed, and technique prepares and fairly simplely can reduce gate capacitance again, the present invention has following different embodiment:
Embodiment (1): with reference to figure 4, the groove that device cell contains at least two kinds of different depths: they are deep trench and shallow trench.The width range of deep trench is 0.5 μ m to 3.0 μ m, and the degree of depth is 3 μ m to 10 μ m, and the width range of shallow trench is 0.3 μ m to 2.0 μ m, and the degree of depth is 0.8 to 4 μ m.Trench wall is with oxide layer and insert electric conducting material as highly doped polysilicon, in deep trench bottom, has a p type island region, and this p type island region concentration is 3e
14cm
-3to 5e
16cm
-3, compared with N-type base, be dense, the concentration range of N-type base is 3e
13cm
-3to 3e
14cm
-3, the p type island region of deep trench bottom is to form after High temperature diffusion by injecting P type dopant to deep trench bottom.The distance 19 of the external boundary of the p type island region at the bottom of the external boundary of the p type island region of each deep trench bottom and contiguous deep trench is less than 3.0 μ m, but is no less than 0.1 μ m, and the electric conducting material in deep trench is connected to surface emitting electrode.Between deep trench and deep trench, have P type base, have contact hole, contact hole can be comprised of contact hole groove, and P type base region surface is near shallow trench Chu You N+ district.There is contact hole that N+ emitter region and p type island region are connected to surface emitting electrode.Shallow trench between deep trench and deep trench is gate trench, the oxide layer of gate trench inwall is gate oxide, gate trench can pass surperficial N+ emitter region and P type base, extend to beneath place, N-type base, P type base, when the voltage of gate trench is during higher than threshold voltage, gate trench wall and P type base intersection can form electron channel the N-type base under surperficial N+ district and P type base is coupled together, when if now the emitter voltage of the collector electrode specific surface at the back side is bigger than about 0.6V, just device can conducting.
Other embodiment: with reference to figure 5 to 10, the present invention can have various embodiments, except above-described a kind of, other embodiment can form by the variation of some unit member in above the first embodiment, member wherein includes the doped region of (i) deep trench bottom, (ii) the P type base between deep trench and deep trench and (iii) shallow trench.The combination of different component can form different embodiment, now main member is changed and is described below:
The variation of deep trench member: (i) p type island region is arranged at deep trench bottom, and this p type island region concentration is 3e
14cm
-3to 5e
16cm
-3, compared with N-type base, be dense, the concentration range of N-type base is 3e
13cm
-3to 3e
14cm
-3, the p type island region of deep trench bottom is to form after High temperature diffusion by injecting P type dopant to deep trench bottom.The distance of the external boundary of the p type island region at the bottom of the external boundary of the p type island region of each deep trench bottom and contiguous deep trench is less than 3.0 μ m, but is no less than 0.1 μ m, and the electric conducting material in deep trench is connected to surface emitting electrode.(ii) You YiNXing district, deep trench bottom, ZheNXing district concentration is 3e
14cm
-3to 5e
16cm
-3compared with N-type base, be dense, NXing district, deep trench bottom forms after High temperature diffusion by injecting N-type dopant to deep trench bottom, the border in each deep trench DiNXing district is less than 2.0 μ m with the distance range on the border in contiguous deep trench DiNXing district, also can be less than 0 μ m, overlap, the electric conducting material in deep trench is connected to surface emitting electrode.(iii) deep trench You YiNXing district, bottom and p type island region, wherein, in p type island region NXing district, ZheNXing district and p type island region are all through High temperature diffusion, to form to deep trench bottom by injecting N-type doping and P type doping, after N-type district and p type island region form, the concentration in N-type district is 3e
14cm
-3to 5e
16cm
-3, the concentration of p type island region is 3e
14cm
-3to 5e
16cm
-3, the electric conducting material in deep trench is connected to surface emitting electrode.
The variation of P type base member: (i) the P type base between deep trench and deep trench is all connected to surface emitting electrode, (ii) between deep trench and deep trench, there is P type base, wherein there is part P type base region surface YouN+ district, these p type island regions are not connected to surface emitting electrode, (iii) between deep trench and deep trench, there is P type base, wherein there is part P type base region surface there is no N+ district, these p type island regions are not connected between surface emitting electrode (iv) deep trench and deep trench N-type base, wherein this part N-type extends to the N-type base under P type base from surface.Above-described (i) P type base member (ii) and (iii) can be divided into again Di YouNXing district, P type base or there is no N-type district.
The variation of shallow trench member: (i) have shallow trench between deep trench and deep trench, all shallow trenchs are gate trench, (ii) between deep trench and deep trench, there is shallow trench, wherein having part shallow trench is gate trench, having part is not gate trench, be not gate trench be all connected to surface emitting electrode.Above-described (i) and shallow trench (ii) can be divided into again (i) shallow trench bottom and not be injected into doping, (ii) shallow trench bottom has P type doping to inject and forms p type island region, (iii) shallow trench bottom has N-type doping to inject and forms N-type district, (iv) shallow trench bottom has N-type doping and P type doping to inject and forms N-type district and p type island region, wherein in p type island region NXing district.
Above-described various member can arbitrarily freely match mutually, forms different embodiment, and several various combinations wherein as shown in Fig. 5 to 10, have more combination, do not do redundancy introduction here.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein, only for description and interpretation the present invention, is not intended to limit the present invention.
The structure of a kind of semiconductor power device of the present invention, its method of preparing comprises the following steps: utilize deep trench mask to corrode the surface of FZ silicon chip and form at least two deep trench, then, N-type dopant and P type dopant are injected in deep trench bottom, in deep trench bottom, form N-type district and p type island region, then utilize shallow trench mask to corrode the surface of FZ silicon chip and form at least one shallow trench, then, P type dopant is injected in the surface of FZ silicon chip and form P type base, then inject N+ type dopant and form N+ district, at FZ silicon chip surface deposition inter-level dielectric, recycling contact hole mask, inter-level dielectric is corroded, in inter-level dielectric, form perforate, effects on surface corrodes and forms contact hole groove afterwards, and contact hole groove is carried out to metal plug filling, finally, at the surface deposition metal level of device, utilize metal mask to carry out metal attack, form metal bed course and line, adopt this preparation method can produce the structure of described a kind of semiconductor power device.
Preferred embodiment:
The present embodiment does not comprise relevant termination environment step.
As shown in figure 15, at silicon chip surface, adopt accumulation or hot growth pattern to form oxide layer 12 (thickness is 0.3um to 1.5um oxide hard light shield), accumulation one deck lithography coating 17 again in oxide layer, then by deep trench mask, form the some parts that pattern exposes oxide layer, the oxide layer that deep trench mask formation pattern is exposed is carried out after dry corrosion, expose FZ silicon chip surface, then dispose lithography coating.
As shown in figure 16, by etching, form deep trench 18, this deep trench 18 (degree of depth is 3.0um to 10um, and width is 0.5um to 3.0um) extends in N-type silicon chip.
As shown in figure 17, after forming groove, to groove sacrifice property, (time is 10 minutes to 100 minutes in oxidation, temperature is 1000 ℃ to 1200 ℃), to eliminate the silicon layer being destroyed by plasma in grooving process, then dispose sacrifice property oxide layer, still retention surface oxide layer greatly, and the mode of growing by heat, layer of oxide layer (thickness is 0.05um to 0.3um) is formed on the sidewall exposing at groove and bottom, afterwards channel bottom is injected to N-type dopant, assorted agent concentration is 1x10
12to 1 * 10
14/ cm
2, by High temperature diffusion, to process, temperature is 950 to 1200 ℃, the time is 10 minutes to 100 minutes, makes N-type dopant diffuse to form N-type district 5 at channel bottom Tui Jin.
As shown in figure 18, (B11, dosage is 1e14/cm then channel bottom to be injected to P type dopant
2to 1e14/cm
2), by High temperature diffusion, to process, temperature is 950 to 1200 ℃, the time is 10 minutes to 100 minutes, makes P type dopant diffuse to form p type island region 6 at channel bottom Tui Jin.
As shown in figure 19, then dispose all oxide layers, and the mode of growing by heat, the upper surface of the sidewall exposing at groove and bottom and FZ N-type silicon chip forms layer of oxide layer (thickness is 0.05um to 0.3um), and in groove, depositing the polysilicon 8 of N-type high dopant, polysilicon doping concentration is R
s=5 Ω/ to 100 Ω/ (sheet resistance), with filling groove and cover end face, then to carrying out plane corrosion treatment at the lip-deep polysilicon layer of epitaxial loayer, at silicon chip surface, adopt accumulation or hot growth pattern to form oxide layer 12 (thickness is 0.3um to 1.5um oxide hard light shield), accumulation one deck lithography coating 17 again in oxide layer, then by shallow trench mask, form the some parts that pattern exposes oxide layer, the oxide layer that shallow trench mask formation pattern is exposed is carried out after dry corrosion, expose FZ silicon chip surface, then dispose lithography coating.By etching, form shallow trench, (degree of depth is 0.8um to 4.0um to this shallow trench, width is 0.3um to 2.0um) extend in N-type silicon chip, after forming groove, to groove sacrifice property, (time is 10 minutes to 100 minutes in oxidation, temperature is 1000 ℃ to 1200 ℃), to eliminate the silicon layer being destroyed by plasma in grooving process, then dispose the oxide layer on all surface cellular construction, and the mode of growing by heat, the sidewall exposing at groove and bottom, form the thin grid oxic horizon (thickness is 0.05um to 0.2um) of one deck with the upper surface of FZ N-type silicon chip, in groove, deposit the polysilicon 8 of N-type high dopant, polysilicon doping concentration is R
s=5 Ω/ to 100 Ω/ (sheet resistance), with filling groove and cover end face, then to carrying out plane corrosion treatment at the lip-deep polysilicon layer of epitaxial loayer.
As shown in figure 20, at the surperficial accumulation lithography coating of FZ silicon chip, utilize P type base mask to expose the surface of part FZ silicon chip, (B11, dosage is 1e13/cm then silicon chip surface to be injected to P type dopant
2to 2e14/cm
2, then dispose lithography coating.
As shown in figure 21, by High temperature diffusion, process, temperature is 950 to 1200 ℃, and the time is 10 minutes to 100 minutes, makes p type island region Tui Jin be diffused into N-type FZ silicon chip and forms P type base 4.
As shown in figure 22, at the surperficial accumulation lithography coating of FZ silicon chip, utilize N+ mask to expose the surface of part FZ silicon chip, (P31 or As, dosage is 1e15/cm then silicon chip surface to be injected to N-type dopant
2to 2e16/cm
2), then dispose lithography coating.
As shown in figure 23, by High temperature diffusion, process, temperature is 950 to 1200 ℃, and the time is 10 minutes to 100 minutes, and ShiNXing district pushes away Jin and is diffused into formation N+ district 7 (the N+ district degree of depth is 0.2um to 1.0um, and the P type base degree of depth is 1.0um to 3.5um), P type base.
As shown in figure 24, in epitaxial loayer most surface, first deposit undoped silicon dioxide layer (thickness is 0.1um to 0.5um), then deposit boro-phosphorus glass (thickness is 0.1um to 0.8um) and form inter-level dielectric 10, at inter-level dielectric surface accumulation lithography coating, utilize contact hole mask to expose part inter-level dielectric, then the part inter-level dielectric exposing is carried out to dry corrosion, until expose the upper surface of FZ N-type silicon chip, in inter-level dielectric, form a plurality of contact hole mask perforates, then dispose lithography coating; Then the silicon chip surface that contains dopant is carried out to etch, (degree of depth is 0.4um to 1.5um to make contact hole groove, width is 0.2um to 1.0um) through N-type source region, enter into P type base, afterwards contact hole groove is injected to P type high dopant 9, assorted agent concentration is 10
14to 5 * 10
15/ cm
2, to reduce the contact resistance between P type base and metal plug, this increases the safe handling district of device effectively.
As shown in figure 25, at contact hole trenched side-wall, bottom and inter-level dielectric upper surface deposition one deck titanium/titanium nitride layer, then contact hole groove is carried out to tungsten 14 fills to form metal plug, at this, above device, deposit again one deck aluminium alloy 11 (thickness is 0.8um to 10um), then by metal mask, carry out metal etch, form emitter region metal bed course and gate metal bed course and termination environment field plate.
Finally it should be noted that: these are only the preferred embodiments of the present invention, be not limited to the present invention, the present invention (for example can be used for relating to manufacture trench semiconductor power discrete device, insulated trench gate bipolar transistor (Trench IGBT) or trench diode), the present invention can be used for preparing the trench semiconductor power discrete device of 400V to 6500V, embodiments of the invention are to make an explanation with N-type channel device, the present invention also can be used for P type channel device, although the present invention is had been described in detail with reference to embodiment, for a person skilled in the art, its technical scheme that still can record previous embodiment is modified, or part technical characterictic is wherein equal to replacement, but within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improve etc., within all should being included in protection scope of the present invention.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, for explaining the present invention, is not construed as limiting the invention together with embodiments of the present invention, in the accompanying drawings:
During Fig. 1 forward conduction, the optimization of IGBT device inside charge carrier distributes;
Fig. 2 is the schematic diagram of a kind of prior art (US Patent No. 20120056241) device architecture;
Fig. 3 is a kind of schematic diagram of prior art device architecture;
Fig. 4 is the device architecture schematic diagram of this embodiment (1);
Fig. 5 is the device architecture schematic diagram of one of them embodiment of the present invention;
Fig. 6 is the device architecture schematic diagram of one of them embodiment of the present invention;
Fig. 7 is the device architecture schematic diagram of one of them embodiment of the present invention;
Fig. 8 is the device architecture schematic diagram of one of them embodiment of the present invention;
Fig. 9 is the device architecture schematic diagram of one of them embodiment of the present invention;
Figure 10 is the device architecture schematic diagram of one of them embodiment of the present invention;
Figure 11 is the device cell domain and corresponding cross-sectional structure schematic diagram of one of them embodiment of the present invention;
Figure 12 is the schematic diagram that several cell layouts of one of them embodiment of the present invention link together;
Figure 13 is the device cell domain and corresponding cross-sectional structure schematic diagram of one of them embodiment of the present invention;
Figure 14 is the wherein schematic diagram of the device cell domain of several embodiment of the present invention;
Figure 15 exposes oxide layer schematic diagram in the preferred embodiment of the present invention;
Figure 16 is deep trench schematic diagram in the preferred embodiment of the present invention;
Figure 17 injects N-type dopant schematic diagram to channel bottom in the preferred embodiment of the present invention;
Figure 18 injects P type dopant schematic diagram to channel bottom in the preferred embodiment of the present invention;
Figure 19 is the schematic diagram of the preferred embodiment of the present invention after carrying out plane treatment;
Figure 20 is the injection P dopant schematic diagram in the preferred embodiment of the present invention;
Figure 21 is P type base schematic diagram in the preferred embodiment of the present invention;
Figure 22 is the injection N+ dopant schematic diagram in the preferred embodiment of the present invention;
Figure 23 is the N+ emitter area schematic diagram in the preferred embodiment of the present invention;
Figure 24 is the contact hole groove schematic diagram in the preferred embodiment of the present invention;
Figure 25 is the surfaces of aluminum alloy-layer emission electrode schematic diagram in the preferred embodiment of the present invention.
Reference symbol table:
1 P+ district, the back side
2 N buffering area, the back sides
3 N-type bases
4 P type bases
5 N-type districts (floating voltage)
6 p type island regions (floating voltage)
7 N+ emitter regions
Highly doped polysilicon in 8 grooves
The P type high-doped zone of 9 contact hole channel bottoms
10 inter-level dielectrics
11 aluminium alloy layers
12 oxide layers
13 passivation layers
14 tungsten layers
The highly doped polysilicon of 15 silicon faces
16 FZ substrates
16 P type guard rings
17 lithography coatings
18 grooves
The distance of the external boundary of p type island region at the bottom of the external boundary of p type island region and contiguous deep trench at the bottom of 19 deep trench
Claims (13)
1. the structure of a semiconductor power device comprises following part:
(1) active area and termination environment;
(2) active area elementary cell includes (i) at least one deep trench, (ii) at least one shallow trench, (iii) P type base, (iv) N-type district, (v) N+ emitter region, N-type base (vi), (vii) contact hole, (viii) inter-level dielectric, (ix) surface metal and (x) passivation layer etc.
2. the structure of a kind of semiconductor power device according to claim 1, is characterized in that, in part (2), active area elementary cell contains at least one deep trench, and the width range of deep trench is 0.5 μ m to 3.0 μ m, and the degree of depth is 3 μ m to 10 μ m.Deep trench inwall is with oxide layer and insert electric conducting material as highly doped polysilicon, in deep trench bottom, has a doped region at least, and the electric conducting material in deep trench is connected to surface emitting electrode.
3. in part (2), active area elementary cell includes at least one deep trench according to claim 2, it is characterized in that, in deep trench bottom, has doped region, p type island region, and this doped region concentration is 3e
14cm
-3to 5e
16cm
-3, compared with N-type base, be dense, the concentration range of N-type base is 3e
13cm
-3to 3e
14cm
-3, the distance (19) of the external boundary of the p type island region at the bottom of the external boundary of the p type island region of each deep trench bottom and contiguous deep trench is less than 3.0 μ m, but is no less than 0.1 μ m, and this P doped region is to form through High temperature diffusion by injecting P type doping to deep trench bottom.
4. in part (2), active area elementary cell includes at least one deep trench according to claim 2, it is characterized in that, in doped region, YouNXing district, deep trench bottom, this doped region concentration is 3e
14cm
-3to 5e
16cm
-3, compared with N-type base, be dense, the concentration range of N-type base is 3e
13cm
-3to 3e
14cm
-3the external boundary in each NXing district, deep trench bottom is less than 2.0 μ m with the distance (19) of the external boundary in contiguous deep trench DiNXing district, also can be less than 0 μ m, overlap, this N doped region is to form through High temperature diffusion by injecting N-type doping to deep trench bottom.
5. in part (2), active area elementary cell includes at least one deep trench according to claim 2, it is characterized in that, in deep trench You YiNXing district, bottom and p type island region, wherein in p type island region NXing district, ZheNXing district and p type island region are all to form through High temperature diffusion by injecting N-type doping and P type doping to deep trench bottom, after N-type district and p type island region form, the concentration in N-type district is 3e
14cm
-3to 5e
16cm
-3, the concentration of p type island region is 3e
14cm
-3to 5e
16cm
-3.
6. the structure of a kind of semiconductor power device according to claim 1, it is characterized in that, in part (2), active area elementary cell contains P type base, and P type base region surface is near shallow trench Chu You N+ district, and contact hole is connected to surface emitting electrode N+ emitter region and p type island region.
7. the structure of a kind of semiconductor power device according to claim 1, it is characterized in that, in part (2), active area elementary cell contains P type base, wherein there is part P type base region surface near shallow trench Chu Wei N+ district, there is contact hole that N+ emitter region and p type island region are connected to surface emitting electrode, wherein have part P type base region surface Ke You N+ district can there is no N+ district, this part p type island region is not connected to surface emitting electrode yet.
8. the structure of a kind of semiconductor power device according to claim 1, is characterized in that, in part (2), active area elementary cell contains P type base, and in Di YouNXing district, P type base, ZheNXing district concentration is 3e
14cm
-3to 5e
16cm
-3, compared with N-type base, be dense, the concentration range of N-type base is 3e
13cm
-3to 3e
14cm
-3.
9. the structure of a kind of semiconductor power device according to claim 1, is characterized in that, in part (2), active area elementary cell contains N-type base, wherein has part N-type base from surface, to extend to the N-type base under P type base.
10. the structure of a kind of semiconductor power device according to claim 1, it is characterized in that, in part (2), active area elementary cell is containing at least one shallow trench, all shallow trenchs are gate trench, the width range of this shallow trench is 0.3 μ m to 2.0 μ m, and the degree of depth is 0.8 to 4 μ m.Trench wall is with oxide layer and insert electric conducting material as highly doped polysilicon.
The structure of 11. a kind of semiconductor power devices according to claim 1, it is characterized in that, in part (2), active area elementary cell is containing at least one shallow trench, the width range of this shallow trench is 0.3 μ m to 2.0 μ m, the degree of depth is 0.8 to 4 μ m, wherein having part shallow trench is gate trench, having part shallow trench is not gate trench, trench wall is with oxide layer and insert electric conducting material as highly doped polysilicon, is not that the shallow trench of gate trench is all connected to surface emitting electrode.
12. according to described in claim 10 part (2) in active area elementary cell contain at least one shallow trench, it is characterized in that, in shallow trench bottom, there is a doped region, this doped region can be N-type doping, also can be P type doped region, this doped region is through High temperature diffusion, to be formed to shallow trench bottom by dopant implant matter, and its concentration is 3e
14cm
-3to 5e
16cm
-3.
13. according to described in claim 10 part (2) in active area elementary cell contain at least one shallow trench, it is characterized in that, in shallow trench You YiNXing district, bottom and p type island region, wherein in p type island region NXing district, ZheNXing district and p type island region are all to form through High temperature diffusion by injecting N-type doping and P type doping to shallow trench bottom, after N-type district and p type island region form, the concentration in N-type district is 3e
14cm
-3to 5e
16cm
-3, the concentration of p type island region is 3e
14cm
-3to 5e
16cm
-3.
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