CN214477468U - Cell structure of trench insulated gate bipolar transistor - Google Patents
Cell structure of trench insulated gate bipolar transistor Download PDFInfo
- Publication number
- CN214477468U CN214477468U CN202120331568.7U CN202120331568U CN214477468U CN 214477468 U CN214477468 U CN 214477468U CN 202120331568 U CN202120331568 U CN 202120331568U CN 214477468 U CN214477468 U CN 214477468U
- Authority
- CN
- China
- Prior art keywords
- polycrystalline silicon
- grooves
- emitter
- grid
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 122
- 210000004027 cell Anatomy 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 28
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims abstract description 15
- 210000003850 cellular structure Anatomy 0.000 claims abstract description 13
- 238000003860 storage Methods 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims description 37
- 238000000034 method Methods 0.000 description 11
- 230000007704 transition Effects 0.000 description 10
- 239000012535 impurity Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Images
Abstract
The utility model discloses a cell structure of a trench insulated gate bipolar transistor, which comprises a cell structure body, wherein the cell structure body mainly comprises an N-type drift region and a P + region arranged at the bottom of the N-type drift region, the upper surface of the N-type drift region is sequentially provided with an N-type charge storage layer and a P-type channel region, and an emitting electrode is formed on the P-type channel region; a plurality of polycrystalline silicon grooves are formed on the cellular structure body, and polycrystalline silicon and an oxide layer are arranged in the polycrystalline silicon grooves; the polycrystalline silicon grooves comprise at least two real grid polycrystalline silicon grooves arranged in the cellular structure body and a plurality of emitter polycrystalline silicon grooves arranged between the real grid polycrystalline silicon grooves, the real grid polycrystalline silicon grooves extend to the grid metal ring from the polycrystalline silicon grooves in corresponding positions and are connected with the grid metal layer through first contact holes, and the emitter polycrystalline silicon grooves are formed by connecting the polycrystalline silicon grooves reserved in the emitter region with the emitter metal layer through second contact holes.
Description
Technical Field
The utility model relates to a semiconductor device technical field, concretely relates to cell structure of trench insulated gate bipolar transistor.
Background
As one of the most outstanding inventions of semiconductor devices at the end of the 20 th century, IGBTs are widely used in the fields of industry, information, new energy, medicine, transportation, military, and aviation. The electric power development of the present society has been kept away from the IGBT device, and the optimization of the electric performance of the IGBT device is not slow at all.
At present, the phenomenon that peak current is too large exists in the process of opening the injection enhancement type trench gate IGBT, so that the reliability of devices is reduced in the using process, and even the normal use of other components in a circuit is influenced, thereby limiting the use field of the traditional trench type IGBT. Aiming at the problem, the most common method is to design the trench polysilicon gate of the cell structure into a structure containing a real gate and a virtual gate by adjusting the cell structure, so as to reduce the number of effective gates, and the method can effectively reduce the peak current of the device, protect the device from being damaged by self or other circuit components caused by current overshoot in the opening process, but the increase of polysilicon trenches has the defect that the area of a chip is increased, so that the cost of the chip is increased.
Disclosure of Invention
The to-be-solved technical problem of the utility model lies in, to the above-mentioned defect of prior art, provide one kind and can effectively improve slot IGBT's electrical property and life, greatly reduced chip cost's slot insulated gate bipolar transistor's cellular structure.
The utility model aims at providing a cell structure of a trench insulated gate bipolar transistor, which comprises a cell structure body, wherein the cell structure body mainly comprises an N-type drift region and a P + region arranged at the bottom of the N-type drift region, the upper surface of the N-type drift region is sequentially provided with an N-type charge storage layer and a P-type channel region, and an emitter is formed on the P-type channel region; a plurality of polysilicon trenches which penetrate through the P-type channel region and the N-type charge storage layer and extend into the N-type drift region are formed on the cellular structure body, and polysilicon and an oxide layer are arranged in the polysilicon trenches; the polycrystalline silicon grooves comprise at least two real grid polycrystalline silicon grooves arranged in the cellular structure body and a plurality of emitter polycrystalline silicon grooves arranged between the real grid polycrystalline silicon grooves, the real grid polycrystalline silicon grooves extend to the grid metal ring from the polycrystalline silicon grooves in corresponding positions and are connected with the grid metal layer through first contact holes, and the emitter polycrystalline silicon grooves are formed by connecting the polycrystalline silicon grooves reserved in the emitter region with the emitter metal layer through second contact holes.
Furthermore, the polysilicon trench also comprises at least one virtual gate polysilicon trench, and the virtual gate polysilicon trench extends to the gate metal ring and is formed by connecting the first contact hole and the gate metal layer.
Furthermore, N + active regions are formed in the P-type channel regions on two sides of the real gate polycrystalline silicon groove.
Furthermore, the depth and the width of the real gate polycrystalline silicon groove, the virtual gate polycrystalline silicon groove and the emitter polycrystalline silicon groove are the same, and the real gate polycrystalline silicon groove, the virtual gate polycrystalline silicon groove and the emitter polycrystalline silicon groove are arranged on the cellular structure body at equal intervals.
Furthermore, the distance between the real gate polycrystalline silicon groove, the virtual gate polycrystalline silicon groove and the emitter polycrystalline silicon groove is 1/3-3 times of the width of the grooves.
The utility model has the advantages of: the utility model adopts the cell structure with narrow spacing, and a plurality of polysilicon grooves are manufactured on the cell, the polysilicon grooves comprise a real grid, a virtual grid and an emitting electrode polysilicon groove, the shapes and the spacing of the polysilicon grooves of three types are the same, but both sides of the real grid polysilicon groove have N + active regions, the polysilicon groove connected with the grid electrode needs to be extended to the grid electrode metal layer in the design of the device transition region, and is connected with the grid electrode through a contact hole; and the polycrystalline silicon emitter groove still remains in the emitter active region and is connected with the emitter metal layer through the contact hole. The structure effectively reduces the instantaneous current of the device, improves the problem of large peak current in the opening process, and the grooves with the same appearance as the grooves of the polycrystalline silicon layer of the emitter are arranged between the grooves of the grid electrode, so that the working capacitance of the device can be effectively adjusted, and the electrical stability and the product reliability of the IGBT device can be improved.
Drawings
FIG. 1 is a side view of a first embodiment of the present invention;
FIG. 2 is a top plan view of FIG. 1;
FIG. 3 is a side view of a second embodiment of the present invention;
FIG. 4 is a top plan view of FIG. 3;
FIG. 5 is a side view of a third embodiment of the present invention;
FIG. 6 is a top plan view of FIG. 5;
fig. 7 is a side view of a fourth embodiment of the present invention;
fig. 8 is a top plan view of fig. 7.
Detailed Description
To make the objects, technical solutions and advantages of the present invention more clearly understood by those skilled in the art, the present invention will be further described with reference to the accompanying drawings and examples.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "inner", "outer", "lateral", "vertical", and the like are the directions or positional relationships shown in the drawings, and are only for convenience of description of the present invention, and do not indicate or imply that the device or element referred to must have a specific direction, and therefore, should not be construed as limiting the present invention.
As shown in fig. 1-8, the cell structure of the trench igbt according to the present invention includes a cell structure body, the cell structure body mainly includes an N-type drift region 8 and a P + region 9 disposed at the bottom of the N-type drift region 8, the upper surface of the N-type drift region 8 is sequentially provided with an N-type charge storage layer 6 and a P-type channel region 7, and the P-type channel region 7 is formed with an emitter 4; a plurality of polysilicon grooves 15 which penetrate through the P-type channel region 7 and the N-type charge storage layer 6 and extend into the N-type drift region 8 are formed on the cellular structure body, and polysilicon 16 and an oxide layer 17 are arranged in the polysilicon grooves 15; the polycrystalline silicon grooves comprise at least two real grid polycrystalline silicon grooves 1 arranged in the cellular structure body and a plurality of emitter polycrystalline silicon grooves 3 arranged between the real grid polycrystalline silicon grooves 1, the real grid polycrystalline silicon grooves 1 extend from the polycrystalline silicon grooves at corresponding positions to a grid metal ring and are connected with a grid metal layer 11 through first contact holes 12, and the emitter polycrystalline silicon grooves 3 are formed by connecting the polycrystalline silicon grooves reserved in an emitter region with an emitter metal layer 14 through second contact holes 13; and a collector 10 is arranged on one side of the P + region 9 far away from the N-type drift region 8.
Referring to fig. 1-2, the polysilicon trench further includes at least one dummy gate polysilicon trench 2, and the dummy gate polysilicon trench 2 is formed by extending the polysilicon trench in the middle position to the gate metal ring and connecting with the gate metal layer 11 through the first contact hole 12.
Referring to fig. 1-2, N + active regions 5 are formed in the P-type channel regions 7 on both sides of the true gate polysilicon trench. The depths and the widths of the real gate polycrystalline silicon groove 1, the virtual gate polycrystalline silicon groove 2 and the emitter polycrystalline silicon groove 3 are the same, and the real gate polycrystalline silicon groove 1, the virtual gate polycrystalline silicon groove 2 and the emitter polycrystalline silicon groove 3 are arranged on the cellular structure body at equal intervals. And the distance between the real gate polycrystalline silicon groove 1, the virtual gate polycrystalline silicon groove 2 and the emitter polycrystalline silicon groove 3 is 1/3-3 times of the width of the groove.
Fig. 1-4 are a cell structure diagram of a trench type IGBT device, and the graph in two dotted lines is a graph of a cell, and the front structure thereof is characterized in that: at least 4 grooves with the same shape and appearance are arranged on the P well on the front surface of each cell at equal intervals, polycrystalline silicon is filled in the grooves, and a plurality of groove polycrystalline silicon layers comprise two real gate polycrystalline silicon grooves 1, one or more virtual gate polycrystalline silicon grooves 2 and one or more emitter polycrystalline silicon grooves 3; the width of the mesa among the plurality of grooves is 1/3-3 times of the width of the groove. Insulating media cover trench sidewall and chip surface, open the contact hole and draw out on the mesa of P trap between real grid and the virtual grid and the emitter, other not described structure of this unit cell is identical with ordinary trench type IGBT device.
Fig. 2 and 4 are top views of transition region structures corresponding to the cell structures of fig. 1 and 3, where the pattern width between two dotted lines is one cell width. The method is characterized in that: in the transition region, the trench gate (including two real gate polysilicon trenches 1 and one or more dummy gate polysilicon trenches 2) extends to the gate metal layer region 11 and is connected by a first contact hole 12; the emitter polycrystalline silicon groove 3 is still remained in the emitter metal area and is connected with the emitter; the space between the polysilicon grooves is equal, and a second contact hole 13 is arranged between every two grooves in the transition region.
Fig. 5-8 are cell structure diagrams of a trench type IGBT device, where the graph in the two dotted lines is a graph of a cell, and the front structure thereof is characterized in that: at least four grooves with the same shape and appearance are arranged on the P well on the front surface of each cell at equal intervals, polycrystalline silicon is filled in the grooves, and the polycrystalline silicon layers of the grooves comprise one or more real gate polycrystalline silicon grooves 1 and one or more emitter polycrystalline silicon grooves 3; the width of the mesa between every two grooves is 1/3-3 times of the width of the grooves. Insulating media cover trench sidewall and chip surface, open the contact hole and draw out on the mesa of P trap between real grid and the virtual grid and the emitter, other not described structure of this unit cell is identical with ordinary trench type IGBT device.
Fig. 6 and 8 are top views of transition region structures corresponding to the cell structures of fig. 5 and 7, where the pattern width between two dotted lines is one cell width. The method is characterized in that: in the transition region, the real gate polysilicon trench 1 extends to the gate metal layer region 11 and is connected through a first contact hole 12; a plurality of emitter polycrystalline silicon grooves 3 are still remained in the emitter metal area and connected with the emitter; the space between the polysilicon grooves is equal, and a second contact hole 13 is arranged between every two grooves in the transition region.
The preparation method of cellular structure is compatible with usual slot IGBT device technology, but because the slot that appears in every cellular is more, the mesa is narrower, to this type of project organization, use fig. 1-8 as an example, at first define the active area on selected N type epitaxial silicon substrate or zone-melting piece substrate, grow annular field area oxide layer at chip terminal position, adopt silicon chip surface chemical polishing technology with bellied field area oxide layer planarization, and inject into the P + impurity of certain dosage and spread between field oxide ring and form dark P type ring, just so formed the terminal structure of annular field oxide structure. Taking an emitter active region inside the terminal structure and a transition region between the emitter and the terminal as examples to carry out the process manufacturing: a. injecting N-type impurities into the active region and diffusing to form an N-type charge storage region; b. photoetching to form a plurality of equidistant groove patterns, etching the silicon substrate by a dry method, forming grooves with the same shape and appearance, and etching the grooves in the transition region; c. growing a grid oxide layer on the side surface of the groove, and depositing in-situ doped polycrystalline silicon material to fill the groove; d. carrying out chemical mechanical polishing on the polycrystalline silicon layer on the surface of the chip, and removing the polycrystalline silicon layer on the surface of the chip; e. injecting P-type impurities and diffusing to form a P-type channel region with a certain depth; f. photoetching N-type active region windows on two sides of the true gate trench and injecting N-type impurities; g. depositing an insulating medium layer such as silicon oxide, silicon nitride or borosilicate glass and the like, and annealing and compacting; h. photoetching a contact hole, for example, opening the contact hole at the position of an active p-well with N-type impurity injection and injecting p-type impurity for activation to form an emitter; extending the polysilicon real gate and the virtual gate to the gate oxide layer, and connecting the groove and the gate metal layer through the opening to form the real gate and the virtual gate; i. the back of the chip is thinned to a specific thickness, and an IGBT collector region (namely an FS-IGBT with a field stop level) is formed by injecting N-type impurities and P-type impurities through low-temperature annealing or laser annealing; j. and depositing back metal by a sputtering or evaporation method to form a collector, and finishing the manufacturing process of the whole IGBT device.
The utility model adopts the cell structure with narrow spacing, and a plurality of polysilicon grooves are manufactured on the cell, the polysilicon grooves comprise a real grid, a virtual grid and an emitting electrode polysilicon groove, the shapes and the spacing of the polysilicon grooves of three types are the same, but both sides of the real grid polysilicon groove have N + active regions, the polysilicon groove connected with the grid electrode needs to be extended to the grid electrode metal layer in the design of the device transition region, and is connected with the grid electrode through a contact hole; and the polycrystalline silicon emitter groove still remains in the emitter active region and is connected with the emitter metal layer through the contact hole. The structure effectively reduces the instantaneous current of the device, improves the problem of large peak current in the opening process, and the grooves with the same appearance as the grooves of the polycrystalline silicon layer of the emitter are arranged between the grooves of the grid electrode, so that the working capacitance of the device can be effectively adjusted, and the electrical stability and the product reliability of the IGBT device can be improved.
The specific embodiments described herein are merely illustrative of the principles of the present invention and its efficacy, and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical idea of the present invention shall be covered by the claims of the present invention.
Claims (5)
1. The utility model provides a cell structure of trench insulated gate bipolar transistor, includes cell structure body, its characterized in that: the cell structure body mainly comprises an N-type drift region and a P + region arranged at the bottom of the N-type drift region, wherein an N-type charge storage layer and a P-type channel region are sequentially arranged on the upper surface of the N-type drift region, and an emitting electrode is formed on the P-type channel region; a plurality of polysilicon trenches which penetrate through the P-type channel region and the N-type charge storage layer and extend into the N-type drift region are formed on the cellular structure body, and polysilicon and an oxide layer are arranged in the polysilicon trenches; the polycrystalline silicon grooves comprise at least two real grid polycrystalline silicon grooves arranged in the cellular structure body and a plurality of emitter polycrystalline silicon grooves arranged between the real grid polycrystalline silicon grooves, the real grid polycrystalline silicon grooves extend to the grid metal ring from the polycrystalline silicon grooves in corresponding positions and are connected with the grid metal layer through first contact holes, and the emitter polycrystalline silicon grooves are formed by connecting the polycrystalline silicon grooves reserved in the emitter region with the emitter metal layer through second contact holes.
2. The cell structure of a trench insulated gate bipolar transistor according to claim 1, wherein: the polycrystalline silicon groove further comprises at least one virtual grid polycrystalline silicon groove, and the virtual grid polycrystalline silicon groove extends to the grid metal ring and is formed by connecting the first contact hole with the grid metal layer.
3. The cell structure of a trench insulated gate bipolar transistor according to claim 2, wherein: and N + active regions are formed in the P-type channel regions on two sides of the true gate polycrystalline silicon groove.
4. The cell structure of a trench insulated gate bipolar transistor according to claim 2 or 3, wherein: the depths and the widths of the real grid polycrystalline silicon groove, the virtual grid polycrystalline silicon groove and the emitter polycrystalline silicon groove are the same, and the real grid polycrystalline silicon groove, the virtual grid polycrystalline silicon groove and the emitter polycrystalline silicon groove are arranged on the cellular structure body at equal intervals.
5. The cell structure of a trench insulated gate bipolar transistor according to claim 4, wherein: and the distance between the real gate polycrystalline silicon groove, the virtual gate polycrystalline silicon groove and the emitter polycrystalline silicon groove is 1/3-3 times of the width of the groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120331568.7U CN214477468U (en) | 2021-02-05 | 2021-02-05 | Cell structure of trench insulated gate bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120331568.7U CN214477468U (en) | 2021-02-05 | 2021-02-05 | Cell structure of trench insulated gate bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214477468U true CN214477468U (en) | 2021-10-22 |
Family
ID=78137633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120331568.7U Active CN214477468U (en) | 2021-02-05 | 2021-02-05 | Cell structure of trench insulated gate bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN214477468U (en) |
-
2021
- 2021-02-05 CN CN202120331568.7U patent/CN214477468U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8227330B2 (en) | Junction barrier Schottky (JBS) with floating islands | |
| TWI399815B (en) | High voltage structure and methods for vertical power devices with improved manufacturability | |
| CN104221153B (en) | Semiconductor device | |
| US8058670B2 (en) | Insulated gate bipolar transistor (IGBT) with monolithic deep body clamp diode to prevent latch-up | |
| US9059147B1 (en) | Junction barrier schottky (JBS) with floating islands | |
| CN219513110U (en) | IGBT device | |
| CN111244171A (en) | Trench RC-IGBT device structure and manufacturing method thereof | |
| CN110429134B (en) | IGBT device with asymmetric primitive cells and preparation method | |
| EP2551910B1 (en) | Insulated gate semiconductor device with optimized breakdown voltage and manufacturing method thereof | |
| CN103199018B (en) | Manufacturing method of field blocking type semiconductor device and device structure | |
| CN113517331A (en) | SiC-based trench gate MOSFET structure with floating island coupling vertical field plate protection | |
| CN214477468U (en) | Cell structure of trench insulated gate bipolar transistor | |
| CN104103518A (en) | Method for manufacturing semiconductor power device | |
| CN104167436A (en) | Semiconductor power device structure | |
| CN107658343B (en) | Semiconductor structure for optimizing device characteristics and manufacturing method thereof | |
| US20220216331A1 (en) | Semiconductor device and method for designing thereof | |
| CN214542244U (en) | IGBT layout structure capable of improving voltage resistance | |
| US11804524B2 (en) | Semiconductor device and method for producing same | |
| CN115842049A (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| CN113345954A (en) | Full super junction MOSFET device structure and manufacturing method thereof | |
| CN209626219U (en) | A kind of semiconductor power device | |
| US4042949A (en) | Semiconductor devices | |
| CN102881595B (en) | A kind of manufacture method of super-junction high-voltage power device | |
| CN112018174A (en) | Semiconductor device, manufacturing method thereof and household appliance | |
| CN212365970U (en) | Trench RC-IGBT device structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: No.988, Kexing Road, Nanhu District, Jiaxing City, Zhejiang Province Patentee after: Star Semiconductor Co.,Ltd. Address before: No.988, Kexing Road, Nanhu District, Jiaxing City, Zhejiang Province Patentee before: STARPOWER SEMICONDUCTOR Ltd. |