CN214542244U - IGBT layout structure capable of improving voltage resistance - Google Patents
IGBT layout structure capable of improving voltage resistance Download PDFInfo
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- CN214542244U CN214542244U CN202120593051.5U CN202120593051U CN214542244U CN 214542244 U CN214542244 U CN 214542244U CN 202120593051 U CN202120593051 U CN 202120593051U CN 214542244 U CN214542244 U CN 214542244U
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- withstand voltage
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Abstract
The utility model relates to a semiconductor manufacturing field, especially an improve withstand voltage's IGBT territory structure, including being the first groove structure of interdigital form, its first groove is the effective slot that control current and grid pad are connected, and the second groove does not be with the closed structure of grid lug direct connection, and its second groove is located closed float empty area inside, and the closed float empty area that indicates is connected with first groove through the both ends slot of territory and is formed. Under the state that the introduction of second slot will block, the electric field of floating P type base region has shared and has weakened, and then under the equal biggest electric field peak value condition, this application structure can bear higher voltage, does not influence the effect that the floating space region strengthened the carrier simultaneously.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to an IGBT layout structure capable of improving withstand voltage through holes formed in a floating space area at intervals.
Background
In order to improve the carrier enhancement effect of the conventional IGBT structure, the width of the floating region (the region without the electron channel) of the device is often increased. The layout of the stripe-shaped groove is shown in FIG. 1, the cross-sectional view of the layout along the AA' line is shown in FIG. 3, and the cell structures are arranged in a transverse direction periodically. The part without the N-type heavily doped region between the trenches is a floating region, and the introduction of an excessively wide floating region can improve the carrier enhancement effect and reduce the conduction voltage drop but can cause the blocking voltage of the device to be greatly reduced.
Disclosure of Invention
In order to reserve the wide floating space area design in the prior art and solve the problem of device blocking voltage reduction, the application optimizes the potential distribution of the floating space area and provides an IGBT layout structure capable of improving voltage resistance on the premise of reserving a wide floating space area.
In order to achieve the technical effects, the technical scheme of the application is as follows:
the IGBT layout structure capable of improving the withstand voltage comprises a chip bottom plate, wherein a plurality of groups of first grooves which are transversely and periodically distributed are formed in the upper surface of the chip bottom plate, two first grooves are formed in each group, and the two first grooves are arranged side by side in an interdigital shape; set up some N type heavily doped region between the same group of first slot, be equipped with in the middle of the N type heavily doped region and connect the projecting pole contact hole, inject impurity such as boron through the contact hole and form P type heavily doped region, its characterized in that: the region without the N-type heavily doped region between the two adjacent groups of first grooves is a closed region, the closed region is formed by connecting the transverse grooves at two ends with the first grooves at two sides of the transverse grooves, the closed region is internally provided with two transverse grooves which are periodically arranged, each group of the two second grooves is two, and two ends of the two second grooves are connected with the transverse grooves.
Furthermore, the distance between two adjacent groups of first grooves is a, the distance between two first grooves in the same group is b, the distance between the second grooves in the same group is c, the value range of a is 5um-20um, the value range of b is 0.5um-10um, the value range of c is 1um-6um, and a: b is greater than 1.
Furthermore, a P-type base region, a chip bottom plate, an N-type heavily doped region and a P-type base region group insulated gate bipolar transistor are arranged among the grooves, and the back surface of the insulated gate bipolar transistor is of a non-through structure, a through structure or a field stop structure. And a P-type collector region is arranged on the back surface of the chip bottom plate, the P-type collector region is directly connected with a collector electrode C of the IGBT, and a gate electrode G is connected with the first groove and converged at the grid pad in a concentrated manner. The emitter electrode E is connected with the emitter contact hole.
Still further, first slot, second slot and horizontal groove structure constitute together by the gate oxide that thickness is 0.05um-0.20um and the polycrystalline silicon gate electrode of packing, the slot degree of depth is 3um-6um, the width is 1um-4 um.
Furthermore, a P-type base region enclosed by the first grooves and the transverse grooves of the adjacent groups is a floating space region; two ends of two second grooves arranged in the floating empty area are respectively connected with the transverse grooves, and the floating empty area is surrounded into a closed shape again.
And furthermore, emitter contact holes are formed in the two second grooves in the same group. The voltage resistance of the IGBT device can be improved.
And furthermore, the first groove is converged to a grid pad through a connecting line of the grid, and the connecting line of the grid and the grid pad are both made of semiconductor such as polysilicon and the like, and metal conductive materials such as aluminum or copper and the like.
The N-type heavily doped region and the emitter contact hole are both arranged in the region between the first grooves in the same group.
The application has the advantages that:
the utility model discloses under the prerequisite that does not increase the processing cost, can effectively improve the blocking voltage of the IGBT that has the floating space area, its principle lies in through the introduction of floating space area slot, under the state of will blocking, the electric field of floating P type base region has shared and has weakened, and then under the equal biggest electric field peak value condition, the higher voltage can be born to the invention structure, does not influence the effect that the floating space area strengthens the carrier simultaneously.
Drawings
Fig. 1 is a conventional stripe trench layout structure.
Fig. 2 is a schematic structural diagram of embodiment 3 of the present invention.
Fig. 3 is a schematic structural diagram of embodiment 4 of the present invention.
Fig. 4 is a schematic sectional view a-a' of a conventional striped trench layout structure.
Fig. 5 is a schematic cross-sectional view of B-B' of embodiment 3 of the present invention.
Fig. 6 is a schematic cross-sectional view of C-C' according to embodiment 4 of the present invention.
In the drawings: 00-chip bottom plate, 01-first groove, 02-second groove, 03-emitter contact hole, 04-N type heavily doped region, 05-P type heavily doped region, 06-P type base region, 07-P type collector region, 08-transverse groove, 09-grid pad, a-distance between adjacent groups of first grooves, b-distance between the same group of first grooves, and c-distance between the same group of second grooves.
Detailed Description
Example 1
As shown in fig. 2 and 5, the IGBT layout structure for improving withstand voltage includes a chip substrate 00, wherein multiple groups of first trenches 01 are arranged on the upper surface of the chip substrate 00 in a transverse periodic manner, two first trenches 01 are arranged in each group, and the two first trenches 01 are arranged side by side in an interdigital shape; an N-type heavily doped region 04 is formed between the same group of first grooves 01, a contact hole 03 for connecting an emitter is formed in the middle of the N-type heavily doped region 04, impurities such as boron are injected through the contact hole to form a P-type heavily doped region 05, the region between the two adjacent groups of first grooves 01, where the N-type heavily doped region 04 is not formed, is a floating region, the floating region is in a closed shape, the closed shape is formed by connecting transverse grooves 08 at two ends with the first grooves 01 located at two sides of the transverse grooves 08, transverse second grooves 02 which are periodically arranged are arranged in the floating region, two second grooves 02 in each group are arranged, and two ends of each second groove 02 are connected with the transverse grooves 08.
The utility model discloses under the prerequisite that does not increase the processing cost, can effectively improve the blocking voltage of the IGBT that has the float space area, its principle lies in through the introduction of float space area slot, under the state of will blocking, the electric field of float space P type base region 06 shares and weakens, and then under the equal biggest electric field peak value condition, the higher voltage can be born to the invention structure, does not influence the effect that the float space area strengthens the carrier simultaneously.
Example 2
As shown in fig. 2 and 5, the IGBT layout structure for improving withstand voltage includes a chip substrate 00, wherein multiple groups of first trenches 01 are arranged on the upper surface of the chip substrate 00 in a transverse periodic manner, two first trenches 01 are arranged in each group, and the two first trenches 01 are arranged side by side in an interdigital shape; an N-type heavily doped region 04 is formed between the same group of first grooves 01, a contact hole 03 for connecting an emitter is formed in the middle of the N-type heavily doped region 04, impurities such as boron are injected through the contact hole to form a P-type heavily doped region 05, the region between the two adjacent groups of first grooves 01, where the N-type heavily doped region 04 is not formed, is a floating region, the floating region is in a closed shape, the closed shape is formed by connecting transverse grooves 08 at two ends with the first grooves 01 located at two sides of the transverse grooves 08, transverse second grooves 02 which are periodically arranged are arranged in the floating region, two second grooves 02 in each group are arranged, and two ends of each second groove 02 are connected with the transverse grooves 08.
The distance between two adjacent groups of first grooves 01 is a, the distance between two first grooves 01 in the same group is b, the distance between the second grooves 02 in the same group is c, the value range of a is 5-20 um, the value range of b is 0.5-10 um, the value range of c is 1-6 um, and a: b is larger than 1.
A P-type base region 06, a chip bottom plate 00, an N-type heavily doped region 04 and the P-type base region 06 are arranged among the grooves, and the back face of the insulated gate bipolar transistor is of a non-through structure, a through structure or a field stop structure.
First slot 01, second slot 02 and horizontal slot 08 structure constitute together by the gate oxide that thickness is 0.05um-0.20um and the polycrystalline silicon gate electrode of packing, the slot degree of depth is 3um-6um, the width is 1um-4 um.
As shown in fig. 3 and 6, the P-type base region 06 surrounded by the first trench 01 and the lateral trench 08 of the adjacent group is a floating region; two ends of two second grooves 02 arranged in the floating space area are respectively connected with the transverse groove 08, and the floating space area is surrounded into a closed shape again. An emitter contact hole 03 is formed in the two second grooves 02 of the same group. The voltage resistance of the IGBT device can be improved.
The first trench 01 is converged to a gate pad09 through a connecting line of the gate, and the connecting line of the gate and the gate pad09 are both made of semiconductor such as polysilicon, or metal conductive materials such as aluminum or copper. The N-type heavily doped region 04 and the emitter contact hole 03 are both arranged in the region between the first grooves 01 of the same group.
Example 3
The utility model provides an improve withstand voltage's IGBT layout structure, first slot 01 and second slot 02 territory are the slot version, accomplish through photoetching once, N type heavy doping district 04 blocks through the photoresist, opens the window in first slot 01, pours into N type doping, N type doping can be phosphorus, arsenic, selenium or sulphur, P + contact hole version blocks through the photoresist, and photoetching etching medium layer forms, the dielectric layer can be SiO2, TEOS, BPSG etc..
The first grooves 01 are arranged in the transverse direction in a periodic mode, the area between every two adjacent groups of the first grooves 01 is a floating area, the floating area is in a closed shape, and the closed shape is formed by connecting the transverse grooves 08 at two ends with the first grooves 01.
The second grooves 02 are arranged in the transverse direction in a periodic mode, every two grooves form a group, the second grooves 02 are also connected with the transverse grooves 08 to form a closed shape, the second grooves are located in the floating space area, the distance c between the second grooves is obtained, and the blocking voltage of the IGBT can be improved in an adjustable mode by adjusting the size of c.
The same group of first grooves 01 are provided with emitter contact holes 03, and the manufacturing is completed after the process of the N-type heavily doped regions 04 which are transversely and periodically arranged.
The filling material in the groove is polysilicon or metal.
The first trench 01 is finally gathered to the gate pad 09.
The emitter contact hole 03 is formed by etching most of the insulating layer to be an oxide layer.
If the distance c of the second trench 02 is still large, a third trench may be added, which is similar to the second trench 02 in shape and addition. The structure of which corresponds to that shown in fig. 2 and 5.
Example 4
On the basis of embodiment 1, the emitter contact holes 03 may be distributed among the same group of first trenches 01, or may be distributed among the same group of second trenches 02, and the fabrication is completed after the process of forming the N-type heavily doped regions 04 which are periodically arranged in the transverse direction. The structure of which corresponds to that shown in fig. 3 and 6.
Claims (9)
1. The IGBT layout structure capable of improving withstand voltage comprises a chip bottom plate (00), wherein multiple groups of first grooves (01) which are transversely and periodically arranged are formed in the upper surface of the chip bottom plate (00), two first grooves (01) in each group are formed, and the two first grooves (01) are arranged side by side in an interdigital shape; set up some N type heavily doped region (04) between same group first slot (01), be equipped with in the middle of N type heavily doped region (04) and connect emitter contact hole (03), inject impurity through the contact hole and form P type heavily doped region (05), its characterized in that: the region, which is not provided with the N-type heavily doped region (04), between the two adjacent groups of first grooves (01) is a floating region, the floating region is in a closed shape, the closed shape is formed by connecting the transverse grooves (08) at the two ends with the first grooves (01) positioned at the two sides of the transverse grooves (08), the floating region is internally provided with two second grooves (02) which are transversely and periodically arranged, each group of second grooves (02) is two, and the two ends of the two second grooves (02) are connected with the transverse grooves (08).
2. The IGBT layout structure capable of improving the withstand voltage according to claim 1, is characterized in that: the distance between two adjacent groups of first grooves (01) is a, the distance between two first grooves (01) in the same group is b, the distance between the second grooves (02) in the same group is c, the value range of a is 5-20 um, the value range of b is 0.5-10 um, the value range of c is 1-6 um, and a: b is more than 1.
3. The IGBT layout structure capable of improving the withstand voltage according to claim 1, is characterized in that: a P-type base region (06), a chip bottom plate (00), an N-type heavily doped region (04) and the P-type base region (06) are arranged among the grooves, and the back surface of the insulated gate bipolar transistor is of a non-through structure, a through structure or a field stop structure.
4. The IGBT layout structure capable of improving the withstand voltage according to claim 1, is characterized in that: first slot (01), second slot (02) and horizontal slot (08) structure constitute together by the gate oxide that thickness is 0.05um-0.20um and the polycrystalline silicon gate electrode of packing, the slot degree of depth is 3um-6um, the width is 1um-4 um.
5. The IGBT layout structure capable of improving the withstand voltage according to claim 1, is characterized in that: a P-type base region (06) surrounded by the first grooves (01) and the transverse grooves (08) of the adjacent groups is a floating zone; two ends of two second grooves (02) arranged in the floating space area are respectively connected with the transverse groove (08), and the floating space area is surrounded into a closed shape again.
6. The IGBT layout structure capable of improving the withstand voltage according to claim 5, is characterized in that: and emitter contact holes (03) are arranged in the two second grooves (02) in the same group.
7. The IGBT layout structure capable of improving the withstand voltage according to claim 1, is characterized in that: the first groove (01) is converged to a grid pad (09) through a connecting line of a grid, and the connecting line of the grid and the grid pad (09) are made of semiconductors such as polycrystalline silicon and the like, aluminum or copper.
8. The IGBT layout structure capable of improving the withstand voltage according to any one of claims 1-6, wherein: the N-type heavily doped region (04) and the emitter contact hole (03) are arranged in the region between the first grooves (01) in the same group.
9. The IGBT layout structure capable of improving the withstand voltage according to claim 7, is characterized in that: the back of the chip bottom plate (00) is provided with a P-type collector region (07), the P-type collector region (07) is directly connected with a collector electrode C of the IGBT, and a gate electrode G is connected with the first groove (01) and converged at a grid pad (09) in a concentrated manner; the emitter electrode E is connected with the emitter contact hole (03).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120593051.5U CN214542244U (en) | 2021-03-24 | 2021-03-24 | IGBT layout structure capable of improving voltage resistance |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120593051.5U CN214542244U (en) | 2021-03-24 | 2021-03-24 | IGBT layout structure capable of improving voltage resistance |
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| CN214542244U true CN214542244U (en) | 2021-10-29 |
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| CN202120593051.5U Expired - Fee Related CN214542244U (en) | 2021-03-24 | 2021-03-24 | IGBT layout structure capable of improving voltage resistance |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115547963A (en) * | 2022-11-24 | 2022-12-30 | 深圳市威兆半导体股份有限公司 | Insulated gate bipolar transistor |
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- 2021-03-24 CN CN202120593051.5U patent/CN214542244U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115547963A (en) * | 2022-11-24 | 2022-12-30 | 深圳市威兆半导体股份有限公司 | Insulated gate bipolar transistor |
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