CN104078497B - A kind of structure of power field effect transistor device - Google Patents

A kind of structure of power field effect transistor device Download PDF

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Publication number
CN104078497B
CN104078497B CN201310104598.4A CN201310104598A CN104078497B CN 104078497 B CN104078497 B CN 104078497B CN 201310104598 A CN201310104598 A CN 201310104598A CN 104078497 B CN104078497 B CN 104078497B
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area
groove
region
polysilicon
strengthening part
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CN104078497A (en
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苏冠创
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NANJING LISHENG SEMICONDUCTOR TECHNOLOGY CO., LTD.
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Nanjing Lisheng Semiconductor Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices

Abstract

The invention discloses a kind of structures of power field effect transistor device, including following characteristics: the cellular construction of active area consists of two parts, and a portion is as general common trench IGBT cellular construction, referred to as regular section；Another part is to have a p type island region domain in silicon wafer, there is an area N+ on the surface of p type island region, it is groove around this region, trench wall has oxide layer, is filled with polysilicon in groove, this region is not connected to emission electrode directly, referred to as strengthening part, in order to improve short-circuit safety zone, the original N+ width of regular section is reduced 20% to 80%, and the original N+ area of strengthening part is also reduced 10% to 90%.

Description

A kind of structure of power field effect transistor device
Technical field
The present invention relates to a kind of semiconductor power device technology fields, specifically, are related to a kind of groove-type power field effect Answer the structure of transistor device.
Background technique
1980, RCA Corp., the U.S. applied for first IGBT patent, and Toshiba Corp is made that first within 1985 Industrial IGBT.From device physically for, it is non-transparent collector punch IGBT, referred to as punch IGBT (Punchthrough IGBT- is abbreviated as PT-IGBT).In 1996, motorola inc, which has delivered an article description, to be had The research for manufacturing non-break-through IGBT is closed, the technique for stressing how to manufacture collector in thin silicon wafer, FZ N-type silicon chip used is most Thin there are about 170um thickness.Next year, Infineon company have also delivered the NPT- that 600V is made with the FZ N-type silicon chip of 100um thickness IGBT.99 years or so, the IGBT of industrial a new generation started to go into operation, and the IGBT of this new generation is a kind of high-speed switching devices, It does not need to shorten minority carrier life time in device with heavy metal or irradiation, and technology mainly is ultra thin silicon wafers technique plus weak collection Electricity knot or be transparent collector junction, Infineon company is referred to as field cut-off IGBT, the following years, each main production IGBT Company all releases one after another similar product.
The main technology of IGBT and performance (i.e. electrical parameter) have (1) breakdown voltage, (2) forward voltage drop, (3) switch spy Property, (4) short circuit safety zone (SCSOA), (5) reverse-bias safe area (RBSOA) and (6) forward biased safe area (FBSOA) Deng.Forward voltage drop be it is conflicting with switching speed and short-circuit safety zone, that is, switch will have been injured by improving forward voltage drop The performance of speed and short-circuit safety zone, such as increases N-The hole-electron pair density of extension layer, forward voltage drop can improve, but store More charges can make that the turn-off time increases and short circuit current increases, so that turn-off speed and short-circuit safety zone be made to be deteriorated.This The target of invention is to minimize the contradiction between forward voltage drop and switching speed and short-circuit safety zone, such as reduces forward voltage drop When, the adverse effect to switching speed and short-circuit safety zone is minimized.
In order to reduce the turn-off time, increases frequency capability indirectly and reduce the turn-off time, while less increasing positive pressure Drop can be removed intracorporal charge is stored in as early as possible when designer needs to optimize charge Injection Level and shutdown.Field cut-off IGBT Backside structure the contradiction that effective MECHANISM SOLUTION determines forward voltage drop and turn-off time can be provided.The backside structure of field cut-off IGBT is main It is made of the buffer area N and P+ layer thin and that concentration is less high.The back side has the field cut-off IGBT of the buffer area N can be with punch IGBT equally uses the relatively thin expansion area N-, this is conducive to on-state voltage drop.With matching for the buffer area N and P+ layers of concentration and thickness The charge level of injection is controlled, keeps the charge of injection sufficiently high to such an extent that keep pressure drop low, while not being too high and to be significantly increased again Turn-off time.In useful mechanism, P+ layer thin and that concentration is not high is most critical.In turn off process, electronics can penetrate P + layer diffuses to passive electrode, this will be greatly reduced the turn-off time, more more effective and do not increase logical than with local minority carrier life time is reduced State pressure drop.
Forward voltage drop, turn-off time and these three electric parameters of short-circuit safety zone are the key technical indexes of IGBT.They It influences each other, exactly, forward voltage drop and turn-off time and short circuit safety zone contradiction each other.When improveing forward voltage drop, Two parameters of remaininging can be deteriorated.So it is incomplete that independent narration, which improves a certain parameter,.The quality of technology is to generate mutual Contradictory size.If taking punch IGBT compared with IGBT is ended in field, the contradiction that the latter generates in this respect is smaller.As just When being adjusted to same lower value to pressure drop, the turn-off time can be made shorter by use shut-off technology.
For example transparent collector junction of backside structure can be used to efficiently control the concentration and distribution of device back charge, to close The concentration of surface portion charge and distribution influence are relatively small, to influence concentration and distribution of the device close to surface portion charge, Most effective and easy way is the cellular construction using device surface, and the concentration for improving device surface Partial charge can be reduced Forward voltage drop, the existing scheme for improving forward voltage drop using surface cell structure have following several:
Scheme one:
As shown in Figure 1, the cellular construction of active area has two parts, a portion and general common trench IGBT list Meta structure is the same, and conventional structure part is called in this text；Is there is a region in another part in silicon wafer, around this area Domain is groove, and trench wall has oxide layer, is filled with polysilicon in groove, there is an oxide layer in region surface, is one in oxide layer Polysilicon layer, region are N-type region, and wherein without p type island region, this N-type region is not connected to emission electrode directly, this part It is called strengthening part in this text.
Scheme two:
As shown in Fig. 2, the cellular construction of active area has two parts, a portion and general common trench IGBT list Meta structure is the same, and another part is groove around this p type island region domain to there is a p type island region domain in silicon wafer, and trench wall has oxygen Change layer, is filled with polysilicon in groove, the p type island region in this unit is not connected directly to emission electrode.
Scheme three:
As shown in figure 3, strengthening part structure and scheme two are similar, only there is a N on p type island region+Area.
Scheme four:
As shown in figure 4, strengthening part structure and scheme three are similar, only in N+Mono- oxide layer of Qu Shangyou has in oxide layer One polysilicon layer, this polysilicon layer are connected with the polysilicon in groove.
Above several schemes are all with practical value, and different strengthening part structures, which is all up, in each scheme increases surface load Sub- concentration is flowed, so as to improve forward voltage drop, and does not increase the turn-off time, but they there are some disadvantages, can all gate capacitance be made to increase Greatly, this power consumption that will increase driving circuit, in addition, above each scheme does not all propose how to enhance short-circuit safety zone simultaneously, Do not have deliberately to set the position of breakdown voltage, their these disadvantages are to be improved.
Summary of the invention
It is an object of the invention to propose a new device architecture make forward voltage drop and switching speed and short circuit safety zone it Between contradiction minimize, when such as reducing forward voltage drop, the adverse effect to switching speed and short-circuit safety zone is minimized, Implementing the present invention has following several different schemes:
Scheme (1): referring to Fig. 5, and the left-hand side of Fig. 5 is the top view of device cell layout in active area, this unit point For two parts, from 1-1 ' to 2-2 ', the structure of part is the cellular construction of general common trench IGBT device, in this text Referred to as regular section is partially used as enhancing device surface carrier concentration from 2-2 ' to 3-3 ', this text is referred to as enhanced portion Point, the right-hand side of Fig. 5 is the sectional view of corresponding device, this class formation, which has been disclosed, to be discussed, but is only limited to be used as enhancing table Face carrier concentration, so as to improve positive pressure drop, how do not refer to enhances short-circuit safety zone.This scheme proposes how to improve just To when pressure drop, and short-circuit safety zone can be enhanced, method is the area ratio using correct regular section and strengthening part, to be increased Strong short circuit safety zone, strengthening part will account for the 25% to 60% of entire active region area, and active region area is regular section area The sum of with strengthening part area.
Scheme (2): referring to Fig. 6 A and 6B, this scheme is used as improving forward voltage drop and short-circuit safety zone simultaneously, and method is Reduce the N of regular section+Width reduces the width of regular section device channel, reduce the width of new channel after width It is the schematic diagram of domain that degree, which is the left side of 20% to 80%, Fig. 6 A and Fig. 6 B of original regular section device channel width, in figure Imaginary point is N+Exposure mask edition territory, it is opaque on the cartographic represenation of area mask plate that imaginary point surrounds, after lithography step, area that imaginary point surrounds It has photoresist on silicon chip surface to leave, in ion implanting, this photoresist can be ion barrier, with N shown in figure+ Domain can be N+Width reduces, to enhance short-circuit safety zone；The increasing that strengthening part can be discussed with any one in this text Strong structure improves forward voltage drop.
Scheme (3): refer to Fig. 7 A and 7B, the effect of this scheme and scheme (2) are similar, can also improve simultaneously forward voltage drop with Enhance short-circuit safety zone, method is the N for not only reducing regular section+Width also reduces the N of strengthening part+Area, strengthening part Reduce N+New N after area+Area is original strengthening part N+The 10% to 90% of area.
Scheme (4): referring to Fig. 8, this scheme be for optimizing strengthening part, make strengthening part can not only reduce forward voltage drop but also Less increase gate charge, in original groove domain, the groove (S) of both sides is connected to intermediate groove (M), device After causing, the polysilicon in polysilicon and intermediate groove (M) in both sides groove (S) is connected directly.This scheme is to penetrate Groove domain keeps apart the groove (S) of groove (M) and both sides among enhancement region, and device causes rear both sides groove (S) polysilicon in polysilicon and intermediate groove (M) in is not connected directly, and the polysilicon of both sides is used as gate electrode, in Between groove polysilicon can with electrical characteristic independently also can connect to emission electrode.
Scheme (5): referring to Fig. 9, is that scheme (2) and scheme (4) are combined.
Scheme (6): referring to Figure 10 A and Figure 10 B, is that scheme (3) and scheme (4) are combined.
Scheme (7): referring to Figure 11, through groove domain, increases the groove for enhancing region both sides a part of groove therein Width, increased width are 30% to 100% originally, this can be such that breakdown voltage first occurs in the enhancing wider groove in region both sides Near bottom.
Original strengthening part: being divided into several fritters with groove through channel domain with reference to Figure 12 by scheme (8), this The separation between groove and groove can be reduced, and relatively narrow groove can be used, this can make first to occur when breakdown normal Near channel bottom.
Scheme (9): referring to Figure 13, and enhancing some regions of region surface do not have N+, without N+Region on have polysilicon, this Polysilicon can be connected directly to emission electrode, can also independently float outstanding.
Scheme (10): refer to Figure 14, enhancing region in have an independent groove, the polysilicon and surface in this groove it is more Crystal silicon is connected, this polysilicon can be directly connected to emission electrode, can also independently float and hang, and the groove in enhancing region is not necessarily Be opened among region, can also open in the zone any one, surface does not have the region of polysilicon to have N+, this N+Region not by It is connected directly to emission electrode.
Scheme (11): referring to Figure 15, and it is field oxide that surface is at least a part of in enhancing region, in ion implanting When, this field oxide can be the base area P and N+Ion barrier, so, there is no p-type base area under field oxide, without N yet+ Area.
Various regular section structures and strengthening part structure described above can form device junction with mutually freely matching Structure, as shown in FIG. 16 and 17.:
Detailed description of the invention
Attached drawing is used to provide further understanding of the present invention, and is used to explain the present invention together with embodiments of the present invention, It is not construed as limiting the invention, in the accompanying drawings:
Fig. 1 is a kind of schematic diagram of the prior art (United States Patent (USP) US5329142) device architecture；
Fig. 2 is a kind of schematic diagram of the prior art (United States Patent (USP) US 6815769) device architecture；
Fig. 3 is a kind of schematic diagram of the prior art (United States Patent (USP) US5329142) device architecture；
Fig. 4 is a kind of schematic diagram of the prior art (United States Patent (USP) US US20100078674) device architecture；
Fig. 5 is the device architecture schematic diagram of the present invention program (1)；
Fig. 6 A and 6B are the device architecture schematic diagrames of the present invention program (2)；
Fig. 7 A and 7B are the device architecture schematic diagrames of the present invention program (3)；
Fig. 8 is the device architecture schematic diagram of the present invention program (4)；
Fig. 9 is the device architecture schematic diagram of the present invention program (5)；
Figure 10 A and 10B are the device architecture schematic diagrames of the present invention program (6)；
Figure 11 is the device architecture schematic diagram of the present invention program (7)；
Figure 12 is the device architecture schematic diagram of the present invention program (8)；
Figure 13 is the device architecture schematic diagram of the present invention program (9)；
Figure 14 is the device architecture schematic diagram of the present invention program (10)；
Figure 15 is the device architecture schematic diagram of the present invention program (11)；
Figure 16 is the schematic diagram that regular section and enhancing structure of the invention form device architecture with freely matching；
Figure 17 is the schematic diagram that regular section and enhancing structure of the invention form device architecture with freely matching；
Figure 18 is exposure oxide layer schematic diagram in the embodiment of the present invention；
Figure 19 is the schematic diagram that p-type protection ring is formed in the embodiment of the present invention；
Figure 20 is p-type base area schematic diagram in the embodiment of the present invention；
Figure 21 is groove schematic diagram in the embodiment of the present invention；
Figure 22 is schematic diagram of the embodiment of the present invention after carrying out plane treatment；
Figure 23 is the injection N type dopant schematic diagram in the embodiment of the present invention；
Figure 24 is the N-type emitter area schematic diagram in the embodiment of the present invention；
Figure 25 is the inter-level dielectric schematic diagram in the embodiment of the present invention；
Figure 26 is the contact hole groove schematic diagram in the embodiment of the present invention；
Figure 27 is in the embodiment of the present invention 1 aluminium alloy layer schematic diagram.
Reference symbol table:
1 P+ substrate
2 N buffer epitaxial layer
3 N- epitaxial layers
4 p-type base areas
5 N-type emitter areas
Highly doped polysilicon in 6 grooves
7 aluminium alloy layers
8 inter-level dielectrics
The p-type high-doped zone of 9 contact hole channel bottoms
10 oxide layers
11 passivation layers
12 tungsten layers
The highly doped polysilicon of 13 silicon faces
14 FZ substrates
15 p-type protection rings
16 lithography coatings
17 grooves
Specific embodiment
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, it should be understood that preferred reality described herein Apply example only for the purpose of illustrating and explaining the present invention and is not intended to limit the present invention.
A kind of structure of power field effect transistor device of the present invention, preparation method the following steps are included: P-type protection ring and p-type base area are formed on the surface of FZ silicon wafer first, trench mask is recycled to invade the surface of FZ silicon wafer It loses and forms multiple grooves；Then, the area N+ is formed to the surface injection N type dopant of FZ silicon wafer, it is then heavy in FZ silicon chip surface Interlevel dielectric recycles contact hole mask, erodes to inter-level dielectric, aperture is formed in inter-level dielectric, later to table Face erodes to form contact hole groove, and carries out metal plug filling to contact hole groove；Finally, being deposited on the surface of device Metal layer carries out metal attack using metal mask, forms metal pedestal layer and line, can produce institute using this preparation method A kind of structure for the power field effect transistor device stated.
Embodiment:
As shown in figure 18, first the upper surface of FZ silicon wafer using accumulation or thermal growth mode formed oxide layer 10 (with a thickness of Then 0.3um to 2.0um), one layer of lithography coating 16 of accumulation again in oxide layer form pattern by protection ring mask and expose The some parts of oxide layer, after forming the oxide layer progress dry corrosion that pattern exposes to protection ring mask, the table of exposure FZ silicon wafer Then lithography coating is disposed in face.
As shown in figure 19, to silicon chip surface injecting p-type dopant (B11, dosage 2e12/cm3To 2e14/cm3), injection P-type dopant by High temperature diffusion operation (time be 10 minutes to 1200 minutes, temperature be 950 DEG C to 1200 DEG C) be pushed into It is diffused into formation p-type protection ring 15 in FZ silicon wafer.
As shown in figure 20, in oxidation surface layer shallow lake lithography coating, portion of oxide layer is exposed using active area mask, so Etch is carried out to the portion of oxide layer exposed afterwards, until exposing the surface of FZ silicon wafer, then disposes lithography coating；Then To silicon chip surface injecting p-type dopant (B11, dosage 2e12/cm3To 2e14/cm3), the P-type dopant of injection passes through high temperature Diffusion operation (time is 10 minutes to 1000 minutes, and temperature is 950 DEG C to 1200 DEG C), which is pushed into be diffused into FZ silicon wafer, forms P Type base area 4.
As shown in figure 21, oxide layer 10 is formed (extremely with a thickness of 0.3um using accumulation or thermal growth mode in silicon chip surface 1.5um oxide hard light shield), then it is sudden and violent to form pattern by trench mask for one layer of lithography coating 16 of accumulation again in oxide layer The some parts for exposing oxide layer expose FZ silicon wafer after forming the oxide layer progress dry corrosion that pattern exposes to trench mask Then lithography coating is disposed on surface.Groove 17 is formed by etching, (depth is 0.8um to 7.5um, width to the groove 17 It is extended in N-type silicon chip for 0.6um to 2.2um).
As shown in figure 22, after formation of the groove, to groove carry out sacrifice oxidation (time be 10 minutes to 100 minutes, Temperature is 1000 DEG C to 1200 DEG C), to eliminate the silicon layer destroyed in grooving process by plasma, then dispose all oxidations Layer, and by thermally grown mode, the side wall and bottom that expose in groove and the upper surface of FZ N-type silicon chip form one layer thin Grid oxic horizon (with a thickness of 0.05um to 0.2um), the polysilicon 6 of deposited n-type high dopant in the trench, polysilicon doping Concentration is RS=5 Ω/ to 100 Ω/ (sheet resistance), to fill groove and cover top surface, then in epi-layer surface Polysilicon layer carries out plane corrosion treatment.
As shown in figure 23, in the surface accumulation lithography coating of FZ silicon wafer, the table of part FZ silicon wafer is exposed using N+ mask Then N type dopant (P31 or As, dosage 1e15/cm are injected to silicon chip surface in face3To 2e16/cm3), then dispose light Carve coating.
As shown in figure 24, it being handled by High temperature diffusion, temperature is 950 to 1200 DEG C, and the time is 10 minutes to 100 minutes, So that N-type region propulsion is diffused into the p-type base area formation area N+ 5, (area N+ depth 0.2um to 1.0um, p-type base area depth are 2.0um To 6.0um).
As shown in figure 25, undoped silicon dioxide layer is first deposited (extremely with a thickness of 0.1um in epitaxial layer most surface 0.5um), it then deposits boro-phosphorus glass and (forms inter-level dielectric 8 with a thickness of 0.1um to 0.8um).
As shown in figure 26, in inter-level dielectric surface accumulation lithography coating, part interlayer is exposed using contact hole mask and is situated between Then matter carries out dry corrosion to the part inter-level dielectric exposed, until the upper surface of FZ N-type silicon chip is exposed, in inter-level dielectric It is middle to form multiple contact hole mask apertures, then dispose lithography coating；Then the silicon chip surface containing dopant is soaked Erosion, making contact hole groove, (depth 0.4um to 1.5um, width pass through N-type source region for 0.12um to 1.6um) and enter p-type base Area, later to contact hole groove injecting p-type high dopant 9, miscellaneous dose of concentration is 1014To 5 × 1015/cm3, with reduce p-type base area with Contact resistance between metal plug, this effectively increases the safe handling area of device.
As shown in figure 27, one layer of titanium/titanium nitride is deposited in contact hole trenched side-wall, bottom and inter-level dielectric upper surface Layer then carries out the filling of tungsten 12 to contact hole groove to form metal plug, then deposits one layer of aluminum bronze in the upper surface of the device and close Gold 7 (with a thickness of 0.8um to 10um), then carries out metal etch by metal mask, forms emitter area metal pedestal layer 7 and grid Pole line and termination environment field plate.
Finally, it should be noted that these are only the preferred embodiment of the present invention, it is not intended to restrict the invention, this hair It is bright to can be used for being related to manufacturing groove semiconductor power discrete device (for example, trench insulated gate bipolar transistor (Trench IGBT) Or trench diode), the present invention can be used for preparing the trench semiconductor power discrete device of 400V to 1200V, reality of the invention Applying example is made an explanation with N-type passage device, and the present invention also can be used for p-type passage device, although referring to embodiment to the present invention It is described in detail, it for those skilled in the art, still can be to technology documented by previous embodiment Scheme is modified or equivalent replacement of some of the technical features, but it is all the spirit and principles in the present invention it Interior, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.

Claims (2)

1. a kind of structure of power field effect transistor device includes following part:
(1) active area and termination environment；
(2) basic unit is divided into two parts in active area: regular section and strengthening part；
(3) regular section structure is following any one:
* the first regular section includes p-type base area, N+Emitter area and trench-gate, p-type base area and N+Area is connected to hair Radio pole；
* second regular section includes p-type base area, N+Emitter area and trench-gate, part of N+Emitter area width is deleted Subtract, N+Emitter area width, that is, device channel width, the width for reducing new channel after width is original regular section The 20% to 80% of device channel width, p-type base area and N+Area is connected to emission electrode；
(4) strengthening part structure is following any one:
* the first strengthening part includes p-type base area, surface N+Area, what it is around close silicon chip surface enhancement region side is groove, The trench wall of enhancement region side has oxide layer, and polysilicon is filled out in centre, and the p-type base area and the area N+ enhanced in region does not all have It is connect with emitter, they are all electrology characteristic independence；
* second strengthening part includes p-type base area, surface N+Area, what it is around close silicon chip surface enhancement region side is groove, The trench wall of enhancement region side has oxide layer, and polysilicon is filled out in centre, enhances the p-type base area in region and N+Area does not all have It is connect with emitter, they are all electrology characteristic independence；The wherein N of strengthening part region surface+Area has part to be deleted, enhancing It is original strengthening part N that part, which reduces new N+ area after N+ area,+The 10% to 90% of area；
* the third strengthening part includes p-type base area, surface N+Area enhances the p-type base area in region and N+Area all not with transmitting Electrode is directly connected to, they are all electrology characteristic independence, main around four, the strengthening part region side by nearby Si surface Trench wall for groove, enhancement region side has oxide layer, and polysilicon is filled out in centre, wherein the groove (S) on both sides and routine Partial gate trench is parallel and is connected together, and separately has both sides (M) and the gate trench of regular section to be mutually perpendicular to, this two Polysilicon in side (M) groove is all respectively not attached to the polysilicon in other grooves, and the polysilicon in this both sides groove (M) is all Respective electrology characteristic independence is connected to emission electrode；
* the four kind of strengthening part includes p type island region, surface N+Area and groove around enhancement region side, wherein there is part of trench Width than the gate trench width of regular section be it is wide, the width of wider groove is 1.2 times to 2 times of gate trench width；
* the five kind of strengthening part is made of several small strengthening part regions, around the subregional groove of small enhanced portion and groove The distance between be less than regular section cell width, each zonule is not all connected directly with emission electrode；
* the six kind of strengthening part includes p-type base area, what it is around enhancement region side is groove, is grid oxygen on the surface of p type island region Change layer, wherein have polysilicon on some gate oxide, the part of the surface of polysilicon layer is not N+Area, on p-type base area Polysilicon is that electrology characteristic is independent or be connected to emission electrode, the N in enhancement region+Area is not connected to emission electrode；
* the seven kind of strengthening part includes p-type base area, what it is around enhancement region side is groove, is grid oxygen on the surface of p type island region Change layer, wherein has polysilicon on some gate oxide, there is an independent groove in p type island region, independent trench wall has Oxide layer fills out and is connected in the polysilicon in independent groove with the polysilicon on the surface of part p type island region, do not have on the surface of p type island region The part for having polysilicon layer is N+Area, the polysilicon on p-type base area are electrology characteristic independence or are connected to emission electrode, are enhanced N in area+Area is not attached to emission electrode；
* the eight kind of strengthening part includes n-type region, without p type island region and N+ type area, what it is around strengthening part side is Groove, trench wall are gate oxide, and centre is filled with polysilicon, are field oxide on N-type region field surface, enhance the N in region Type area is not connected directly to emission electrode.
2. a kind of structure of power field effect transistor device includes following part:
(1) active area and termination environment；
(2) basic unit can be divided into two parts in active area: regular section and strengthening part；
(3) regular section includes p-type base area, N+Emitter area and trench-gate, p-type base area and N+Area is connected to transmitting electricity Pole；
(4) strengthening part includes p-type base area, surface N+Area, what it is around close silicon chip surface enhancement region side is groove, enhancing The trench wall of area side has oxide layer, and polysilicon is filled out in centre, enhances the p-type base area in region and N+Area all not with hair Emitter-base bandgap grading connection, they are all electrology characteristic independence；
(5) strengthening part area accounts for the 25% to 60% of active region area, and active region area is equal to regular section area and enhancing The sum of area.
CN201310104598.4A 2013-03-28 2013-03-28 A kind of structure of power field effect transistor device Expired - Fee Related CN104078497B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1950947A (en) * 2004-05-12 2007-04-18 株式会社丰田中央研究所 Semiconductor device
US7638839B2 (en) * 2007-03-09 2009-12-29 Hitachi, Ltd. Power semiconductor device and power conversion device using the same
CN201608184U (en) * 2009-12-29 2010-10-13 无锡新洁能功率半导体有限公司 Groove type power MOS device with improved terminal protection structure
CN102246306A (en) * 2008-12-08 2011-11-16 飞兆半导体公司 Trench-based power semiconductor devices with increased breakdown voltage characteristics

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5634318B2 (en) * 2011-04-19 2014-12-03 三菱電機株式会社 Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1950947A (en) * 2004-05-12 2007-04-18 株式会社丰田中央研究所 Semiconductor device
US7638839B2 (en) * 2007-03-09 2009-12-29 Hitachi, Ltd. Power semiconductor device and power conversion device using the same
CN102246306A (en) * 2008-12-08 2011-11-16 飞兆半导体公司 Trench-based power semiconductor devices with increased breakdown voltage characteristics
CN201608184U (en) * 2009-12-29 2010-10-13 无锡新洁能功率半导体有限公司 Groove type power MOS device with improved terminal protection structure

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