CN113497158A - Fast recovery semiconductor device and manufacturing method thereof - Google Patents
Fast recovery semiconductor device and manufacturing method thereof Download PDFInfo
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- CN113497158A CN113497158A CN202010266554.1A CN202010266554A CN113497158A CN 113497158 A CN113497158 A CN 113497158A CN 202010266554 A CN202010266554 A CN 202010266554A CN 113497158 A CN113497158 A CN 113497158A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a fast recovery semiconductor device and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type drift region; forming an oxide layer on the drift region, wherein the oxide layer defines an active region and a terminal voltage-resistant structure region positioned on the periphery of the active region in the drift region; injecting second conductive type ions with the energy range of 100-150 KEV from the upper surface of the drift region to form a second conductive type well region in the drift region; performing junction pushing on the second conductive type well region to a specified depth; and forming a first conductive type stopping ring at one side of the edge of the terminal voltage-resistant structure region far away from the main-junction second conductive type enhancement region. The invention can simultaneously complete the injection of the second conductive type well region and the introduction of the defects of the first conductive type drift region by adopting the high-energy ion injection process, thereby reducing the minority carrier lifetime, improving the reverse recovery characteristic, improving the softness factor and reducing the production cost.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a fast recovery semiconductor device and a manufacturing method thereof.
Background
Fast Recovery Diodes (FRDs) have the characteristics of good switching characteristics, short reverse recovery time, large forward current, high reverse withstand voltage, and the like. As an important power semiconductor device, it is often used as a switch in an electronic circuit, and is also often connected in parallel with a MOSFET or an IGBT to function as a follow current or the like so as to function as a follow current or the like by a reactive current in a load. It is important to improve the switching characteristics of the FRD, the most critical of which is its reverse recovery characteristics.
It is necessary to reduce the minority carrier lifetime of the drift region in order to increase the reverse recovery speed of the diode. The current common methods are heavy metal diffusion (such as gold diffusion and platinum diffusion) or electron irradiation technology. The principle of the defects is that the defects are formed in a drift region of the diode, the minority carrier lifetime of the drift region is reduced, the reverse recovery time trr is further reduced, and the softness factor S is increased.
In a traditional FRD (fast recovery diode) preparation process, when a front structure of a semiconductor device is prepared, low-energy P-type ion boron is injected into an N-type epitaxial layer on an N-type silicon substrate to form a P well. In order to control the minority carrier lifetime of the FRD and reduce the reverse recovery time trr, an electron irradiation or heavy metal diffusion process is introduced to cause a certain defect in the drift region, thereby improving the reverse recovery characteristics thereof and increasing the softness factor, but this will cause an increase in process cost.
However, the cost of electron irradiation is high and the long-term reliability is poor, the gold diffusion leakage current is too large, and platinum diffusion has low leakage current, but the on-state voltage is high and the reliability is poor.
Disclosure of Invention
The invention provides a manufacturing method of a fast recovery semiconductor device, which solves the problem that the reverse recovery time of a fast recovery diode is not low enough and is not ideal, reduces the reverse recovery time trr, improves the softness factor S, and reduces the cost.
The invention provides a manufacturing method of a fast recovery semiconductor device, which comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type drift region;
forming an oxide layer on the drift region, and exposing part of the upper surface of the drift region in a patterning mode on the oxide layer so as to define an active region and a terminal voltage-resistant structure region located on the periphery of the active region in the drift region below the oxide layer;
injecting second conductive type ions in a designated energy range from the upper surface of the drift region to form a second conductive type well region in the drift region, wherein the second conductive type well region comprises at least one main junction second conductive type enhancement region formed in the active region and at least one second conductive type enhancement voltage-resistant ring formed in the terminal voltage-resistant structure region;
performing junction pushing on the second conductive type well region to a specified depth;
and forming a first conductive type stopping ring at one side of the edge of the terminal voltage-resistant structure region far away from the main-junction second conductive type enhancement region.
In an embodiment of the present invention, it is,
the injection specified energy range is 100 KEV-150 KEV.
In an embodiment of the present invention, it is,
forming an oxide layer on the drift region, and exposing part of the upper surface of the drift region in a patterning mode on the oxide layer so as to define an active region and a terminal voltage-resistant structure region located on the periphery of the active region in the drift region below the oxide layer; injecting second conductive type ions in a designated energy range from the upper surface of the drift region to form a second conductive type well region in the drift region, wherein the second conductive type well region comprises at least one main junction second conductive type enhancement region formed in the active region and at least one second conductive type enhancement voltage-resistant ring formed in the terminal voltage-resistant structure region, and the method comprises the following steps:
forming a first oxidation layer on the drift region, and patterning the first oxidation layer to expose an active region in the drift region and at least part of the upper surface of a terminal voltage-resistant structure region positioned at the periphery of the active region;
forming a second oxide layer on the patterned first oxide layer, the active region in the drift region and the exposed upper surface of the terminal voltage-withstanding structure region at the periphery of the active region, and patterning the second oxide layer to expose the upper surface of the active region in the drift region;
forming a third oxide layer on the patterned second oxide layer and the active region in the drift region;
and injecting second conductive type ions in a designated energy range from the upper surface of the third oxide layer, forming at least one main-junction second conductive type enhancement region in the active region of the drift region and forming at least one second conductive type enhancement voltage-withstanding ring in the terminal voltage-withstanding structure region of the drift region.
In an embodiment of the present invention, it is,
forming a third oxide layer on the patterned second oxide layer and the active region in the drift region, including:
and forming a third oxide layer with an initial thickness on the patterned second oxide layer and the main junction second conduction type enhancement region of the active region in the drift region, and then continuously growing to a specified thickness.
In an embodiment of the present invention, it is,
the material of the semiconductor substrate comprises silicon or silicon carbide;
the first, second and third oxide layers are made of silicon dioxide;
the second conductivity type ions include boron ions;
the first conductive type ions include phosphorus ions.
In an embodiment of the present invention, it is,
preparing a thickness range of the first oxide layer to be 1.0-1.5 μm;
the thickness range formed by preparing the second oxide layer is 1.0-4 mu m;
the initial thickness range formed by preparing the third oxide layer is 0.1-0.2 μm, and the designated thickness range is 0.5-1 μm;
carrying out the push junction of the main junction second conductive type enhancement region and at least one second conductive type enhancement voltage-withstanding ring to form a specified depth range of 6-9 μm;
the temperature range adopted by the knot pushing process is 750-1000 ℃, and the time range is 30-50 min.
In an embodiment of the present invention, it is,
further comprising the steps of:
depositing dielectric layers on the upper surface of the main junction second conductive type enhancement region, the upper surface of the second conductive type enhancement voltage-resisting ring, the upper surface of the first conductive type enhancement stop ring and the oxide layer to reach a specified thickness;
removing the oxide layer and the dielectric layer on the upper surface of the main junction second conduction type enhancement region to form a first contact hole, etching the contact hole in the second conduction type enhancement voltage-withstanding ring and the first conduction type enhancement stop ring region to form a second contact hole, and filling the first and second contact holes;
depositing a front metal layer on the fillers of the first contact hole and the second contact hole, wherein the metal layer exposes a part of the dielectric layer on the second conductive type enhanced voltage-resisting ring and the first conductive type enhanced stop ring;
forming a patterned passivation layer on the front metal layer and the dielectric layer which is not covered by the front metal layer, wherein the passivation layer exposes part of the upper surface of the front metal layer;
and preparing a back metal layer on the lower surface of the semiconductor substrate.
In an embodiment of the present invention, it is,
the dielectric layer comprises boron phosphorus silicon glass, and the specified thickness range of the formed dielectric layer is 0.6-0.7 mu m;
the contact hole filler comprises tungsten.
The passivation layer material comprises polyimide;
the front metal layer and the back metal layer are made of at least one of aluminum, titanium, nickel, silver or aluminum-copper alloy.
In an embodiment of the present invention, it is,
the semiconductor base comprises a wafer substrate of a first conduction type, or the semiconductor base comprises a substrate, and a first conduction type buffer layer and a first conduction type drift region which are sequentially formed on the substrate from bottom to top.
The present invention also provides a fast recovery semiconductor device, comprising:
a semiconductor substrate including a first conductive type drift region;
the oxide layer is positioned on the drift region of the first conduction type, the oxide layer exposes part of the upper surface of the drift region so as to define an active region and a terminal voltage-resistant structure region positioned on the periphery of the active region in the drift region, the active region of the drift region comprises at least one main-junction second conduction type enhancement region, and the terminal voltage-resistant structure region comprises at least one second conduction type enhancement voltage-resistant ring and a first conduction type stop ring positioned on one side, far away from the active region, of the second conduction type enhancement voltage-resistant ring;
the main junction second conduction type enhancement region and the second conduction type enhancement pressure ring are formed by injecting second conduction type ions in a specified energy range into the upper surface of the drift region and are connected to a specified depth in a pushing mode;
in an embodiment of the present invention, it is,
the injection specified energy range is 100 KEV-150 KEV.
In an embodiment of the present invention, it is,
a dielectric layer formed on the oxide layer;
the first contact hole penetrates through the oxide layer and the dielectric layer on the main junction second conduction type enhancement region, the second contact hole penetrates through the second conduction type enhancement voltage-withstanding ring, the oxide layer and the dielectric layer on the first conduction type enhancement stop ring region, and conductive fillers are filled in the first contact hole and the second contact hole;
the front metal layer is positioned on the fillers of the first contact hole and the second contact hole, and the metal layer exposes a part of the dielectric layer on the second conductive type enhanced voltage-resisting ring and the first conductive type enhanced stop ring;
the passivation layer is positioned on the front metal layer and the dielectric layer and exposes part of the upper surface of the front metal layer;
and the back metal layer is positioned on the lower surface of the semiconductor substrate.
One or more embodiments of the present invention may have the following advantages over the prior art:
1. according to the invention, through adopting the second conductive type ions with the energy range of 100-150 KEV to carry out the injection and annealing processes, more defects and impurity energy levels are introduced into silicon atoms, the impurity ions are activated, and partial lattice damage is eliminated, so that the injection of the second conductive type well region and the introduction of the defects of the first conductive type drift region can be simultaneously completed, the minority carrier lifetime is reduced, the reverse recovery characteristic is improved, and the softness factor is improved. Because high-energy ion injection is adopted, an electron irradiation or heavy metal diffusion process is not required to be introduced, the link of electron irradiation outside commission is reduced, and the production cost can be reduced.
2. The invention can reduce the junction-pushing temperature range and time parameter in the junction-pushing process because the energy of the second conductive type ion implantation is higher, and the junction depth after the high-energy ion implantation is larger than that of the low-energy ion implantation, thereby reducing the process cost.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic flow chart of a method for fabricating a fast recovery semiconductor device according to the present invention;
FIG. 2 is a schematic cross-sectional view of a fast recovery semiconductor device fabricated using the method of fabricating a fast recovery semiconductor device of the present invention;
fig. 3 shows a schematic cross-sectional view of a fast recovery semiconductor device structure after performing step 100;
FIG. 4 shows a schematic cross-sectional view of a fast recovery semiconductor device structure after performing step 300;
fig. 5.1 shows a schematic cross-sectional view of a fast recovery semiconductor device structure after step 210 is performed;
fig. 5.2 shows a schematic cross-sectional view of a fast recovery semiconductor device structure after step 220 is performed;
fig. 5.3 shows a schematic cross-sectional view of a fast recovery semiconductor device structure after step 230 is performed;
fig. 5.4 shows a schematic diagram of high-energy ion implantation in the fast recovery semiconductor device fabrication method of step 240;
FIG. 6 shows a schematic cross-sectional view of a fast recovery semiconductor device structure after performing step 400;
fig. 7 shows a schematic cross-sectional view of a fast recovery semiconductor device structure after performing step 500;
fig. 8 shows a schematic cross-sectional view of a fast recovery semiconductor device structure after performing step 600;
fig. 9 shows a schematic cross-sectional view of a fast recovery semiconductor device structure after performing step 800.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the following detailed description of the present invention with reference to the accompanying drawings is provided to fully understand and implement the technical effects of the present invention by solving the technical problems through technical means. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
First embodiment
FIG. 1 is a schematic flow chart of a method for fabricating a fast recovery semiconductor device according to the present invention;
FIG. 2 is a schematic cross-sectional view of a fast recovery semiconductor device fabricated using the method of fabricating a fast recovery semiconductor device of the present invention;
fig. 3, fig. 4, fig. 6 to fig. 9 are schematic cross-sectional views of the fast recovery semiconductor device structure after performing step 100, step 300, step 400, step 500, step 600 and step 800;
fig. 5.1 to 5.3 are schematic cross-sectional views of the fast recovery semiconductor device after step 210, step 220 and step 230 are performed;
fig. 5.4 shows a schematic diagram of the high-energy ion implantation in the fast recovery semiconductor device manufacturing method of step 240.
The structure of the fast recovery semiconductor device manufactured by the manufacturing method of the embodiment is shown in fig. 2, and the fast recovery semiconductor device of the embodiment includes: the semiconductor device comprises a substrate 1, a first conductive type buffer layer 2, a first conductive type drift region 3, an oxide layer 4, a main junction second conductive type enhancement region 501, a second conductive type enhancement voltage-proof ring 502, a first conductive type enhancement stop ring 6, a dielectric layer 7, a first contact hole 801, a second contact hole 802, a front metal layer 9, a passivation layer 10 and a back metal layer 11.
The semiconductor substrate includes a first conductive type wafer substrate manufactured by a zone-melting method, or a substrate, and a first conductive type buffer layer and a first conductive type drift region sequentially formed on the substrate from bottom to top, which are described in this embodiment by using a substrate 1 and a first conductive type buffer layer 2 and a first conductive type drift region 3 sequentially formed on the substrate 1 from bottom to top. The substrate material includes semiconductor elements such as silicon or silicon germanium in a single crystal, polycrystalline or amorphous structure, and also includes mixed semiconductor materials such as silicon carbide, alloy semiconductors, or combinations thereof, which are not limited herein. The substrate 1 in this embodiment is an already doped substrate, and the substrate 1 in this embodiment preferably adopts a silicon substrate, and may adopt an N-type or P-type silicon substrate, and in this embodiment, a doped N-type substrate is taken as an example for description. The material of the substrate 1, the first conductivity type buffer layer 2, and the first conductivity type drift region 3 includes silicon or silicon carbide, which is not limited.
In this embodiment, the N-type is a first conductivity type and the P-type is a second conductivity type.
As shown in fig. 1, the present embodiment provides a method for manufacturing a fast recovery semiconductor device, including the following steps:
Specifically, the semiconductor substrate of the present embodiment includes a substrate 1, and a first conductive type buffer layer 2 and a first conductive type drift region 3 sequentially grown on the substrate 1 from bottom to top, and a cross-sectional view of the fast recovery semiconductor device after the implementation is shown in fig. 3.
The material of the substrate 1, the first conductivity type buffer layer 2, and the first conductivity type drift region 3 in this embodiment includes silicon or silicon carbide, preferably silicon.
second conductive type ions with specified energy range are injected from the upper surface of the drift region 3 to form a second conductive type well region in the drift region 3, wherein the second conductive type well region comprises at least one main junction second conductive type enhancement region 501 formed in the active region and at least one second conductive type enhancement voltage-proof ring 502 formed in the terminal voltage-proof structure region.
The profile of the fast recovery semiconductor device after step 200 is shown in fig. 4, wherein the oxide layer 4 includes a first oxide layer 401, a second oxide layer 402, and a third oxide layer 403 after treatment.
In the traditional electron irradiation, a high-frequency and high-voltage electron accelerator is used for generating electrons with energy of 1-5 MeV to perform irradiation treatment on a semiconductor material, and a sample needs to be placed on a metal machine table provided with a circulating cooling device to perform cooling treatment on the sample. The ion implantation technology does not need an additional cooling device, so that the complexity of the technical equipment is reduced, and the cost is reduced. Because high-energy ion injection is adopted, an electron irradiation or heavy metal diffusion process is not required to be introduced, the link of electron irradiation outside commission is reduced, and the production cost can be reduced.
After the technology is adopted, the reverse recovery time can be reduced by 20% on the original basis, and the softness factor can be improved by 20% to the maximum extent.
Specifically, the method comprises the following steps:
step 210, growing a first oxide layer 401 on the drift region 3, wherein the thickness range of the first oxide layer 401 is 1.0 μm to 1.5 μm; the first oxide layer 401 is patterned and etched to expose the active region in the drift region 3 and at least a portion of the upper surface of the terminal voltage-withstanding structure region located at the periphery of the active region, and the cross-sectional view of the fast recovery semiconductor device after step 201 is implemented is shown in fig. 5.1.
The material of the first oxide layer comprises silicon dioxide or silicon nitride.
The terminal voltage-resistant structure of the embodiment adopts a field limiting ring and field plate structure, and can reduce the curvature radius of an electric field at the boundary of an active region of a device and improve the overall voltage-resistant strength of the device.
Step 220, forming a second oxide layer 402 on the etched first oxide layer 401, the active region in the drift region 3 and the exposed upper surface of the terminal voltage-withstanding structure region located at the periphery of the active region, patterning the second oxide layer 402 to expose the upper surface of the active region in the drift region 3, wherein the thickness range formed by the second oxide layer 402 is 1.0 μm to 4 μm.
Since the high energy ion energy adopted by the present embodiment is higher than that of the conventional ion, in order to protect the region where the defect is not required to be introduced, before the ion implantation process is performed, a second oxide layer 402 is further grown on the first oxide layer 401 and the reserved position for forming the second conductive type well region to serve as a barrier layer, and the material of the second oxide layer includes silicon dioxide or silicon nitride. Then, a layer of photoresist is coated on the second oxide layer 402, and a series of photolithography processes such as masking, exposure, and etching are performed to etch the second oxide layer so as to expose the upper surface of the active region in the drift region 3. The fast recovery semiconductor device structure after step 202 is implemented is shown in figure 5.2.
In step 230, a third oxide layer 403 is formed on the etched second oxide layer 402 and on the active region in the drift region 3.
Specifically, a third oxide layer 403 with a thickness ranging from 0.1 μm to 0.2 μm is formed on the etched second oxide layer 402 and on the main junction second conductivity type enhancement region of the active region in the drift region 3, and then the third oxide layer is grown to a specified thickness, the specified thickness range formed by the growth of the third oxide layer 403 is 0.5 μm to 1 μm, the material of the third oxide layer includes silicon dioxide or silicon nitride, and the third oxide layer is preferably silicon dioxide in this embodiment. The fast recovery semiconductor device structure after step 203 is implemented is shown in figure 5.3.
Step 240, second conductive type ions with the specified energy range of 100 to 150KEV are implanted from the upper surface of the third oxide layer 403, as shown in fig. 5.4, a main junction second conductive type enhancement region 501 is formed in the active region of the drift region 3, and at least one second conductive type enhancement voltage-withstanding ring 502 is formed in the termination voltage-withstanding structure region of the drift region, as shown in fig. 4.
Specifically, the second conductivity type ions include boron ions or phosphorus ions, and the present embodiment is preferably boron ions. When high-energy ion implantation is performed, the surface of the third oxide layer 403 is first amorphized, then high-energy ions are implanted into the surface of the drift region 3 to form a second conductive type well region, a main-junction second conductive type enhancement region 501 is formed in the active region of the drift region 3, at least one second conductive type enhancement voltage-withstanding ring 502 is formed in the terminal voltage-withstanding structure region of the drift region, and meanwhile, defects are introduced into the drift region 3 by the implantation of the high-energy ions.
Specifically, since the energy of the high-energy ions is higher than that of the conventional implanted ions, the junction depth of the second conductivity type well region after the high-energy ions are implanted is relatively deep, so the annealing temperature and time of the junction-pushing process of the embodiment are correspondingly reduced, the production cost of the process is reduced, and the specific annealing temperature and time should be adjusted and set according to actual process conditions and effects. The junction-pushing process of the embodiment adopts a temperature range of 750-1000 ℃, a time range of 30-50 min, and a specified depth range of 6-9 μm formed by the junction-pushing process of the main junction second conductive type enhancement region 501 and the at least one second conductive type enhancement pressure ring 502.
Specifically, the oxide layer is etched and thinned on the side of the edge of the terminal voltage-resistant structure region far away from the main-junction second-conduction-type enhancement region, and then first-conduction-type ions are implanted by adopting an aligned ion implantation process, so that a first-conduction-type stop ring 6 is formed, wherein the first-conduction-type ions preferentially adopt phosphorus ions.
a cross-section of a fast recovery semiconductor device structure after the implementation of step 700 is shown in fig. 9. The front metal layer includes at least one of aluminum, titanium, nickel, silver or aluminum copper alloy, and the embodiment is preferably aluminum.
Specifically, metal is deposited on the anode deposition surface, namely the filler of the first contact hole 801 in the active region and the filler of the second contact hole 802 in the terminal voltage-resistant structure region, and is led out to the surface of the chip, so that the electrodes can be led out to the pins of the finished package product by the subsequent lead bonding process of chip packaging.
In step 600, the filler of the first contact hole and the filler of the second contact hole can also be front metal layers, and the material of the filler of the contact hole and the material of the front metal layer are all the same, preferably aluminum.
Specifically, in order to reduce the bulk resistance of the device, the lower surface of the semiconductor substrate is firstly thinned to the actually required thickness, and then the back metal is deposited. In order to make the back collector of the chip have excellent conductivity and match with the subsequent process of packaging the chip, the metal types, the deposition sequence, the deposition thickness and the deposition process condition parameters in the process of preparing the back metal are optimized so as to meet the requirements.
The material of the back metal layer includes at least one of aluminum, titanium, nickel, silver or aluminum copper alloy, and the embodiment is preferably aluminum.
In view of the above, it is desirable to provide,
1. according to the invention, through adopting the second conductive type ions with the energy range of 100-150 KEV to carry out the injection and annealing processes, more defects and impurity energy levels are introduced into silicon atoms, the impurity ions are activated, and partial lattice damage is eliminated, so that the injection of the second conductive type well region and the introduction of the defects of the first conductive type drift region can be simultaneously completed, the minority carrier lifetime is reduced, the reverse recovery characteristic is improved, and the softness factor is improved. Because high-energy ion injection is adopted, an electron irradiation or heavy metal diffusion process is not required to be introduced, the link of electron irradiation outside commission is reduced, and the production cost can be reduced.
2. The invention has the advantages that because the energy of the second conductive type ion implantation is higher, the junction depth after the high-energy ion implantation is larger than that of the low-energy ion, and the junction pushing temperature range and time parameters in the junction pushing process can be reduced, so the process production cost is reduced.
Second embodiment
FIG. 2 is a schematic cross-sectional view of a fast recovery semiconductor device fabricated using the method of fabricating a fast recovery semiconductor device of the present invention;
the embodiment provides a fast recovery semiconductor device including:
a semiconductor substrate including a first conductive type drift region;
the oxide layer is positioned on the drift region of the first conduction type, the oxide layer exposes part of the upper surface of the drift region so as to define an active region and a terminal voltage-resistant structure region positioned on the periphery of the active region in the drift region, the active region of the drift region comprises at least one main-junction second conduction type enhancement region, and the terminal voltage-resistant structure region comprises at least one second conduction type enhancement voltage-resistant ring and a first conduction type stop ring positioned on one side, far away from the active region, of the second conduction type enhancement voltage-resistant ring;
the main junction second conduction type enhancement region and the second conduction type enhancement voltage-withstanding ring are formed by injecting second conduction type ions with the appointed energy range of 100-150 KEV into the upper surface of the drift region, and are connected to the appointed depth in a pushing mode.
A fast recovery semiconductor device, further comprising:
a dielectric layer formed on the oxide layer;
the first contact hole penetrates through the oxide layer and the dielectric layer on the main junction second conduction type enhancement region, the second contact hole penetrates through the second conduction type enhancement voltage-withstanding ring, the oxide layer and the dielectric layer on the first conduction type enhancement stop ring region, and conductive fillers are filled in the first contact hole and the second contact hole;
the front metal layer is positioned on the fillers of the first contact hole and the second contact hole, and the metal layer exposes partial dielectric layers on the second conductive type enhanced voltage-resistant ring and the first conductive type enhanced stop ring;
the passivation layer is positioned on the front metal layer and the dielectric layer and exposes part of the upper surface of the front metal layer;
and a back metal layer located on the lower surface of the semiconductor substrate.
In view of the above, it is desirable to provide,
1. in the embodiment, the fast recovery semiconductor device manufactured by adopting the second conductive type ions with the energy range of 100 to 150KEV to perform implantation and annealing is used for introducing more defects and impurity energy levels into silicon atoms, activating the impurity ions and eliminating partial lattice damage, so that the implantation of the second conductive type well region and the introduction of the defects of the first conductive type drift region can be completed simultaneously, the minority carrier lifetime is reduced, the reverse recovery characteristic is improved, and the softness factor is improved. Because high-energy ion injection is adopted, an electron irradiation or heavy metal diffusion process is not required to be introduced, the link of electron irradiation outside commission is reduced, and the production cost can be reduced.
2. The fast recovery semiconductor device of the embodiment has the advantages that the energy of the second conductive type ion implantation is high, the junction depth after the high-energy ion implantation is larger than that of the low-energy ion, and the junction pushing temperature range and time parameters in the junction pushing process can be reduced, so that the process production cost is reduced.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as disclosed, and that the scope of the invention is not to be limited to the particular embodiments disclosed herein but is to be accorded the full scope of the claims.
Claims (12)
1. A method for manufacturing a fast recovery semiconductor device is characterized by comprising the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type drift region;
forming an oxide layer on the drift region, and exposing part of the upper surface of the drift region in a patterning mode on the oxide layer so as to define an active region and a terminal voltage-resistant structure region located on the periphery of the active region in the drift region below the oxide layer;
injecting second conductive type ions in a designated energy range from the upper surface of the drift region to form a second conductive type well region in the drift region, wherein the second conductive type well region comprises at least one main junction second conductive type enhancement region formed in the active region and at least one second conductive type enhancement voltage-resistant ring formed in the terminal voltage-resistant structure region;
performing junction pushing on the second conductive type well region to a specified depth;
and forming a first conductive type stopping ring at one side of the edge of the terminal voltage-resistant structure region far away from the main-junction second conductive type enhancement region.
2. The method of fabricating a fast recovery semiconductor device as claimed in claim 1,
the injection specified energy range is 100 KEV-150 KEV.
3. The method of fabricating a fast recovery semiconductor device as claimed in claim 1,
forming an oxide layer on the drift region, and exposing part of the upper surface of the drift region in a patterning mode on the oxide layer so as to define an active region and a terminal voltage-resistant structure region located on the periphery of the active region in the drift region below the oxide layer; injecting second conductive type ions in a designated energy range from the upper surface of the drift region to form a second conductive type well region in the drift region, wherein the second conductive type well region comprises at least one main junction second conductive type enhancement region formed in the active region and at least one second conductive type enhancement voltage-resistant ring formed in the terminal voltage-resistant structure region, and the method comprises the following steps:
forming a first oxidation layer on the drift region, and patterning the first oxidation layer to expose an active region in the drift region and at least part of the upper surface of a terminal voltage-resistant structure region positioned at the periphery of the active region;
forming a second oxide layer on the patterned first oxide layer, the active region in the drift region and the exposed upper surface of the terminal voltage-withstanding structure region at the periphery of the active region, and patterning the second oxide layer to expose the upper surface of the active region in the drift region;
forming a third oxide layer on the patterned second oxide layer and the active region in the drift region;
and injecting second conductive type ions in a designated energy range from the upper surface of the third oxide layer, forming at least one main-junction second conductive type enhancement region in the active region of the drift region and forming at least one second conductive type enhancement voltage-withstanding ring in the terminal voltage-withstanding structure region of the drift region.
4. The method for manufacturing a fast recovery semiconductor device according to claim 3,
forming a third oxide layer on the patterned second oxide layer and the active region in the drift region, including:
and forming a third oxide layer with an initial thickness on the patterned second oxide layer and the main junction second conduction type enhancement region of the active region in the drift region, and then continuously growing to a specified thickness.
5. The method for manufacturing a fast recovery semiconductor device according to claim 4,
the material of the semiconductor substrate comprises silicon or silicon carbide;
the first, second and third oxide layers are made of silicon dioxide;
the second conductivity type ions include boron ions;
the first conductive type ions include phosphorus ions.
6. The method for manufacturing a fast recovery semiconductor device according to claim 5,
preparing a thickness range of the first oxide layer to be 1.0-1.5 μm;
the thickness range formed by preparing the second oxide layer is 1.0-4 mu m;
the initial thickness range formed by preparing the third oxide layer is 0.1-0.2 μm, and the designated thickness range is 0.5-1 μm;
carrying out the push junction of the main junction second conductive type enhancement region and at least one second conductive type enhancement voltage-withstanding ring to form a specified depth range of 6-9 μm;
the temperature range adopted by the knot pushing process is 750-1000 ℃, and the time range is 30-50 min.
7. The method of fabricating a fast recovery semiconductor device as claimed in claim 1,
further comprising the steps of:
depositing dielectric layers on the upper surface of the main junction second conductive type enhancement region, the upper surface of the second conductive type enhancement voltage-resisting ring, the upper surface of the first conductive type enhancement stop ring and the oxide layer to reach a specified thickness;
removing the oxide layer and the dielectric layer on the upper surface of the main junction second conduction type enhancement region to form a first contact hole, etching the contact hole in the second conduction type enhancement voltage-withstanding ring and the first conduction type enhancement stop ring region to form a second contact hole, and filling the first and second contact holes;
depositing a front metal layer on the fillers of the first contact hole and the second contact hole, wherein the metal layer exposes a part of the dielectric layer on the second conductive type enhanced voltage-resisting ring and the first conductive type enhanced stop ring;
forming a patterned passivation layer on the front metal layer and the dielectric layer which is not covered by the front metal layer, wherein the passivation layer exposes part of the upper surface of the front metal layer;
and preparing a back metal layer on the lower surface of the semiconductor substrate.
8. The method for manufacturing a fast recovery semiconductor device according to claim 7,
the dielectric layer comprises boron phosphorus silicon glass, and the specified thickness range of the formed dielectric layer is 0.6-0.7 mu m;
the contact hole filler comprises tungsten;
the passivation layer material comprises polyimide;
the front metal layer and the back metal layer are made of at least one of aluminum, titanium, nickel, silver or aluminum-copper alloy.
9. The method of fabricating a fast recovery semiconductor device as claimed in claim 1,
the semiconductor base comprises a wafer substrate of a first conduction type, or the semiconductor base comprises a substrate, and a first conduction type buffer layer and a first conduction type drift region which are sequentially formed on the substrate from bottom to top.
10. A fast recovery semiconductor device, comprising:
a semiconductor substrate including a first conductive type drift region;
the oxide layer is positioned on the drift region of the first conduction type, the oxide layer exposes part of the upper surface of the drift region so as to define an active region and a terminal voltage-resistant structure region positioned on the periphery of the active region in the drift region, the active region of the drift region comprises at least one main-junction second conduction type enhancement region, and the terminal voltage-resistant structure region comprises at least one second conduction type enhancement voltage-resistant ring and a first conduction type stop ring positioned on one side, far away from the active region, of the second conduction type enhancement voltage-resistant ring;
the main junction second conduction type enhancement region and the second conduction type enhancement pressure ring are formed by injecting second conduction type ions in a specified energy range into the upper surface of the drift region and are connected to a specified depth in a pushing mode.
11. The fast recovery semiconductor device of claim 10,
the injection specified energy range is 100 KEV-150 KEV.
12. The fast recovery semiconductor device of claim 11, further comprising:
a dielectric layer formed on the oxide layer;
the first contact hole penetrates through the oxide layer and the dielectric layer on the main junction second conduction type enhancement region, the second contact hole penetrates through the second conduction type enhancement voltage-withstanding ring, the oxide layer and the dielectric layer on the first conduction type enhancement stop ring region, and conductive fillers are filled in the first contact hole and the second contact hole;
the front metal layer is positioned on the fillers of the first contact hole and the second contact hole, and the metal layer exposes a part of the dielectric layer on the second conductive type enhanced voltage-resisting ring and the first conductive type enhanced stop ring;
the passivation layer is positioned on the front metal layer and the dielectric layer and exposes part of the upper surface of the front metal layer;
and the back metal layer is positioned on the lower surface of the semiconductor substrate.
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