CN112382568B - Manufacturing method of MOS control thyristor - Google Patents
Manufacturing method of MOS control thyristor Download PDFInfo
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- CN112382568B CN112382568B CN202011157039.6A CN202011157039A CN112382568B CN 112382568 B CN112382568 B CN 112382568B CN 202011157039 A CN202011157039 A CN 202011157039A CN 112382568 B CN112382568 B CN 112382568B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 23
- 239000011574 phosphorus Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 210000000746 body region Anatomy 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 230000007704 transition Effects 0.000 claims abstract description 5
- 238000002161 passivation Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 43
- 229910052710 silicon Inorganic materials 0.000 claims description 43
- 239000010703 silicon Substances 0.000 claims description 43
- 238000005468 ion implantation Methods 0.000 claims description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 238000001259 photo etching Methods 0.000 claims description 18
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 16
- 229910052796 boron Inorganic materials 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 12
- 230000000873 masking effect Effects 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 239000005360 phosphosilicate glass Substances 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 238000005275 alloying Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000012360 testing method Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000011104 metalized film Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 238000010992 reflux Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 description 14
- 230000000630 rising effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
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Abstract
The invention discloses a manufacturing method of a MOS control thyristor, which comprises the following steps: 1) Epitaxial formation of n on a substrate ‑ A drift region; 2) Forming an n region in the active region; 3) Forming a gate oxide layer; 4) Depositing a polysilicon layer and performing phosphorus doping; 5) Forming a p base region and a terminal p-type field limiting ring; 6) Formation of n + A cathode region; 7) Forming an n body region and a terminal n-type stop ring; 8) Formation of p ++ A source region; 9) Flattening the surface; 10 Forming a metallized cathode and gate; 11 Removing the substrate, using the substrate and n ‑ A transition region formed by convection diffusion between drift regions is used as n FS A layer; 12 Formation of p + An anode region; 13 Forming a multilayer metallized anode a;14 Forming a cathode and gate bonding area isolation pattern and a terminal passivation film; 15 Surface protection of the termination region is completed. The MOS control thyristor manufactured by the method can meet the requirements of the field of pulse power and solid-state circuit breakers.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and relates to a manufacturing method of a MOS control thyristor.
Background
The MOS Controlled Thyristor (MCT) is simpler to drive than a common thyristor controlled by current due to the voltage signal control. Although the traditional MCT can reduce the on-state voltage drop of the device, the concentration difference between the p-base region and the n-body region is smaller, and the channel concentration and the length are difficult to control during manufacturing, so that the channel penetration is easy to occur during blocking of the device, the threshold voltage is sensitive along with the change of the channel, the current rising rate during switching on is lower, the on-state voltage drop is high, and the wide application of the MCT in the fields of pulse power, solid-state circuit breakers and the like is limited.
Disclosure of Invention
The invention aims to provide a manufacturing method of a MOS control thyristor, which solves the problems that the channel doping concentration and the channel doping length of a device are difficult to accurately control and the application requirements in the field of pulse power and solid-state circuit breakers cannot be met in the prior art.
The technical scheme adopted by the invention is that the manufacturing method of the MOS control thyristor is implemented according to the following steps:
step 1: selecting a substrate, epitaxially forming n - A drift region;
step 2: performing dry-wet-dry oxidation on the silicon wafer treated in the step 1, forming a phosphorus ion implantation window on the upper surface through photoetching, performing phosphorus ion implantation, annealing and pushing, and forming an n region in an active region;
step 3: removing the oxide layer on the surface of the silicon wafer treated in the step 2, and carrying out dry oxygen oxidation again to form a gate oxide layer;
step 4: forming a polysilicon layer on the upper surface of the silicon wafer treated in the step 3 by adopting chemical vapor deposition, and carrying out phosphorus doping;
step 5: forming a boron ion implantation window on the upper surface of the silicon wafer treated in the step 4 through photoetching, then carrying out boron ion implantation under the masking of photoresist, annealing and high-temperature propulsion after photoresist removal to form a p-base region and a terminal p-type field limiting ring, and continuing propulsion of an n-region;
step 6: forming a phosphorus ion implantation window on the upper surface of the silicon wafer treated in the step 5 through photoetching, carrying out high-energy phosphorus ion implantation under the masking of photoresist, annealing and high-temperature propulsion to form an n+ cathode region, and continuing propulsion of an n region and a p base region;
step 7: forming a phosphorus ion implantation window of an n-body region on the upper surface of the silicon wafer treated in the step 6 through photoetching, then carrying out phosphorus ion implantation under the masking of photoresist, and annealing and advancing after photoresist removal to form an n-body region and a terminal n-type stop ring;
step 8: forming p on the upper surface of the silicon wafer processed in the step 7 through photoetching ++ The boron ion implantation window of the source region is then subjected to boron ion implantation under the masking of photoresist, and annealing is performed after photoresist removal to form p ++ A source region;
step 9: growing a phosphosilicate glass layer on the upper surface of the silicon wafer treated in the step 8 by utilizing low-pressure chemical vapor deposition, and refluxing at a high temperature to realize surface planarization;
step 10: photoetching the upper surface of the silicon wafer treated in the step 9 to form contact holes of a cathode and a grid electrode, depositing a metal aluminum layer, reversely etching, and alloying to form a metallized cathode and a metallized grid electrode;
step 11: thinning and etching the lower surface of the silicon wafer processed in the step 10, removing the original n substrate, and taking a transition region formed by convection diffusion between the substrate and the n-drift region as n FS A layer;
step 12: performing boron ion implantation on the lower surface of the silicon wafer treated in the step 11, and then performing rapid laser annealing to form a p+ anode region;
step 13: sputtering four layers of metallized films of aluminum, titanium, nickel and silver on the lower surface of the silicon wafer treated in the step 12 in sequence, and forming a multi-layer metallized anode A after alloying;
step 14: depositing silicon nitride on the upper surface of the silicon wafer treated in the step 13 by utilizing plasma enhanced chemical vapor deposition, and reversely etching to form a cathode and grid electrode bonding area isolation pattern and a terminal passivation film;
step 15: throwing a polyimide film on the upper surface of the silicon wafer treated in the step 14, reversely etching, and then curing to finish the surface protection of the terminal area; finally, dicing, testing and packaging are completed, and the finished product is obtained.
The invention has the beneficial effects that the manufacturing method of the MOS control thyristor is characterized in that n of the traditional MCT active region - An n region with higher concentration is introduced above the drift region through doping, so that the doping concentration and the length of a channel are convenient to adjust, the threshold voltage and the blocking voltage of a device are accurately controlled, the device has high current rising rate and low on-state voltage drop when being turned on, the process flow is completely compatible with the traditional MCT, the popularization and the utilization are convenient, and the application requirements of the fields of pulse power, solid-state circuit breakers and the like can be better met.
Drawings
Fig. 1 is a schematic cross-sectional view of a basic structure of a MOS-controlled thyristor obtained by the manufacturing method of the invention;
FIG. 2 is a graph of the forward blocking characteristics of the MOS-controlled thyristor of the present invention with a conventional MCT at zero gate voltage and negative gate voltage;
FIG. 3 is a graph showing the forward conduction characteristics of the MOS-controlled thyristor of the present invention versus a conventional MCT;
FIG. 4 is a graph showing the longitudinal carrier concentration profile versus a conventional MCT split along the center of the n-region during turn-on with the MOS-controlled thyristor of the present invention;
fig. 5 is a graph of on-current versus on-current in a pulsed power application of the MOS-controlled thyristor of the invention with a conventional MCT.
Detailed Description
The invention will be described in detail below with reference to the drawings and the detailed description.
Referring to fig. 1, the basic structure of the MOS controlled thyristor of the invention is that the entire device is represented by n - Drift region as voltage-resistant layer, n - A p base region is arranged in the center above the drift region, and n regions are arranged on two sides of the p base region; an n-type semiconductor device is arranged above the p-base region + Cathode region, n + The two sides of the cathode region are provided with n body regions, the n body regions and n + P is respectively arranged above the junction of the cathode region ++ A source region; two p ++ Aluminum layer and n on upper surface of source region + The aluminum layer on the upper surface of the cathode region is connected into a whole to form a cathode electrode K; two side n region, p base region, n body region and part p ++ The upper surface of the source region is commonly provided with a gate oxide layer (i.e. SiO 2 A material layer) on the upper surface of the gate oxide layer, a heavily doped polysilicon layer is provided as a gate electrode G; a phosphosilicate glass layer (namely, PSG material layer) is arranged between the cathode electrode K and the grid electrode G, and the PSG material layer is used for realizing isolation between the cathode electrode K and the grid electrode G; n is n - The lower surface of the drift region is provided with n FS Layer (i.e. n field stop layer), n FS The lower surface of the layer is provided with p + Anode region, p + The lower surface of the anode region is provided with a plurality of layers of metallized anodes A.
As can be seen from FIG. 1, the main structure of the MOS-controlled thyristor of the invention is composed of n + Cathode region, p-base region, n - Drift region, n FS Layer and p + A thyristor composed of anode regions; the heavily doped polysilicon layer forms PMOS and NMOS with the gate oxide layer, the n body region and the p base region under the heavily doped polysilicon layer, and the PMOS and NMOS are controlled by the same gate voltage. Wherein the p-base region and the n-bodyThe concentration difference of the regions has a great influence on the device characteristics. The concentration difference between the p-base region and the n-body region of the conventional MCT is small, typically 3×10 17 cm -3 ～5×10 17 cm -3 The channel concentration and the length are sensitive, so that channel penetration easily occurs when the device is blocked, the threshold voltage is not easy to control, the current rising rate is low when the device is opened, and the on-state voltage drop is high. The MOS control thyristor of the invention has the n region added, and the concentration of the n region has the value range of 8 multiplied by 10 15 cm -3 ～2×10 16 cm -3 Increasing the concentration tolerance range of the p base region and the n body region to 5×10 17 cm -3 ～9×10 17 cm -3 The length of the N channel is controlled in the range of 2-3 mu m, and the length of the P channel is controlled in the range of 0.6-0.8 mu m, so that the threshold voltage and the blocking voltage of the device can be accurately controlled, and meanwhile, the current rising rate is improved and the on-state voltage drop is reduced when the device is turned on.
The manufacturing method of the MOS control thyristor is specifically implemented according to the following steps:
step 1: selecting the original<100>Low-resistance n-type monocrystal as substrate and epitaxial formation of n - A drift region;
step 2: performing dry-wet-dry oxidation on the silicon wafer treated in the step 1, forming a phosphorus ion implantation window on the upper surface through photoetching, performing phosphorus ion implantation, annealing and pushing, and forming an n region in an active region;
step 3: removing the oxide layer on the surface of the silicon wafer treated in the step 2, and carrying out dry oxygen oxidation again to form a gate oxide layer;
step 4: forming a polysilicon layer on the upper surface of the silicon wafer treated in the step 3 by adopting chemical vapor deposition, and carrying out phosphorus doping;
step 5: forming a boron ion implantation window on the upper surface of the silicon wafer treated in the step 4 through photoetching, then carrying out boron ion implantation under the masking of photoresist, annealing and high-temperature propulsion after photoresist removal to form a p-base region and a terminal p-type field limiting ring, and continuing propulsion of an n-region;
step 6: forming a phosphorus ion implantation window on the upper surface of the silicon wafer treated in the step 5 through photoetching, carrying out high-energy phosphorus ion implantation under the masking of photoresist, annealing and high-temperature propulsion to form an n+ cathode region, and continuing propulsion of an n region and a p base region;
step 7: forming a phosphorus ion implantation window of an n-body region on the upper surface of the silicon wafer treated in the step 6 through photoetching, then carrying out phosphorus ion implantation under the masking of photoresist, and annealing and advancing after photoresist removal to form an n-body region and a terminal n-type stop ring;
step 8: forming p on the upper surface of the silicon wafer processed in the step 7 through photoetching ++ The boron ion implantation window of the source region is then subjected to boron ion implantation under the masking of photoresist, and annealing is performed after photoresist removal to form p ++ A source region;
step 9: growing a phosphosilicate glass layer on the upper surface of the silicon wafer treated in the step 8 by utilizing Low Pressure Chemical Vapor Deposition (LPCVD), and refluxing at a high temperature to realize surface planarization;
step 10: photoetching the upper surface of the silicon wafer treated in the step 9 to form contact holes of a cathode and a grid electrode, depositing a metal aluminum layer, reversely etching, and alloying to form a metallized cathode and a metallized grid electrode;
step 11: thinning and etching the lower surface of the silicon wafer processed in the step 10, removing the original n substrate, and taking a transition region formed by convection diffusion between the substrate and the n-drift region as n FS A layer;
step 12: performing boron ion implantation on the lower surface of the silicon wafer treated in the step 11, and then performing rapid laser annealing to form a p+ anode region;
step 13: sputtering four layers of metallized films of aluminum, titanium, nickel and silver on the lower surface of the silicon wafer treated in the step 12 in sequence, and forming a multi-layer metallized anode A after alloying;
step 14: depositing silicon nitride on the upper surface of the silicon wafer treated in the step 13 by utilizing Plasma Enhanced Chemical Vapor Deposition (PECVD), and carrying out back etching to form a cathode and gate bonding area isolation pattern and a terminal passivation film;
step 15: throwing a polyimide film on the upper surface of the silicon wafer treated in the step 14, reversely etching, and then curing to finish the surface protection of the terminal area; finally, dicing, testing and packaging are completed, and the finished product is obtained.
From the above, the manufacturing method of the MOS control thyristor has the following three characteristics: firstly, before front cell manufacturing, an n region is formed in an active region, so that the subsequent process is not influenced; second, in the case of cell formation, p-base region, n-body region and p ++ The source region can be realized through a self-alignment process, and the p base region is manufactured after the formation of the gate oxide, so that the influence of the segregation effect of impurity boron at the interface of the p base region and the oxide layer on an N channel in the high-temperature process of the growth of the gate oxide layer is effectively avoided; thirdly, the substrate is removed through thinning, and a transition area formed by convection diffusion between the epitaxial layer and the substrate in the high-temperature process of epitaxy is effectively utilized as n FS Layer, ensure n FS Quality and parameter requirements of the layer.
In particular, the method of the invention is suitable for blocking devices having voltages equal to or lower than 1400V. For the device with the blocking voltage larger than 1400V, the original high-resistance zone-melting mid-irradiation silicon single crystal polished wafer can be selected as n - Drift region, first in processed n - The lower surface of the drift region is formed into n by phosphorus ion implantation, annealing and high-temperature propulsion FS A layer, the upper surface is properly thinned according to the blocking voltage requirement, and then n is a sum of - The upper surface of the drift region is formed with cells, and the step 10 is omitted, and the other steps are the same.
And (3) experimental verification:
in order to evaluate the characteristics of the MOS control thyristor obtained by the manufacturing method, taking 1400V voltage class as an example, the forward blocking characteristic, the conduction characteristic and the opening characteristic in pulse power application of the MOS control thyristor are respectively simulated and verified by using professional simulation software, and the result is as follows:
1) Forward blocking characteristics
Referring to fig. 2, the forward blocking characteristic curves of the MOS controlled thyristor of the invention and a conventional MCT at zero gate voltage and negative gate voltage are shown. It can be seen that both have almost the same blocking characteristics, i.e. at the gate bias V G When zero, the forward blocking voltages are about 270V; at gate bias V G at-5V, the forward blocking voltages were all about 1710V. Therefore, the MOS-controlled thyristor obtained by the manufacturing method of the present invention is alsoIs capable of bearing higher blocking voltage under the negative grid voltage.
2) Conduction characteristics
Referring to fig. 3, the forward conduction characteristic of the MOS controlled thyristor of the invention versus the conventional MCT is shown. At 100A/cm 2 At anode current density, the on-state voltage drop of the traditional MCT is 1.15V, while the on-state voltage drop of the MOS control thyristor is only 0.95V, which is reduced by about 17%. It can be seen that the MOS controlled thyristor obtained with the manufacturing method of the invention has a lower on-state voltage drop.
Referring to fig. 4, there is a graph showing the longitudinal carrier concentration profile versus the conventional MCT split along the n-region center during turn-on for the MOS controlled thyristor of the invention. Therefore, the concentration of Fang Zailiu carriers under the grid electrode is far higher than that of the corresponding carriers in the traditional MCT when the MOS control thyristor is conducted. This shows that the method of the present invention can control the concentration and length of the channel and raise the carrier concentration in the cathode side of the device to reduce the on-state voltage drop.
3) Switching on characteristics
Referring to fig. 5, there is a graph of on-current versus pulse power application for a MOS controlled thyristor of the invention versus a conventional MCT. The test condition is the bus voltage U CC =800V, gate resistance R G =4.7Ω, gate voltage V GK = ±5V, inductance L S =8nh, capacitor c=0.2 μf, resistor r=0.01Ω. As can be seen, the peak current density at turn-on of conventional MCT is about 3055A/cm 2 The current rise rate was about 57 kA/. Mu.s; the peak current density of the MOS control thyristor is about 3325A/cm when being opened 2 The current rise rate was about 70 kA/. Mu.s. In comparison, the peak current density is increased by about 8.8%, and the current rise rate is increased by about 22.8%. It can be seen that the MOS controlled thyristor obtained by the method of the invention has higher peak current and current rise rate than the traditional MCT.
Claims (3)
1. A manufacturing method of MOS control thyristor is characterized in that the MOS control thyristor structure is that the whole device is formed by n parts - Drift region as voltage-resistant layer, n - The center above the drift region is provided withA p base region, wherein n regions are arranged at two sides of the p base region; an n-type semiconductor device is arranged above the p-base region + Cathode region, n + The two sides of the cathode region are provided with n body regions, the n body regions and n + P is respectively arranged above the junction of the cathode region ++ A source region; two p ++ Aluminum layer and n on upper surface of source region + The aluminum layer on the upper surface of the cathode region is connected into a whole to form a cathode electrode K; two side n region, p base region, n body region and part p ++ The upper surface of the source region is provided with a gate oxide layer, the upper surface of the gate oxide layer is provided with a heavily doped polysilicon layer, and the polysilicon layer is used as a grid G; a phosphosilicate glass layer is arranged between the cathode electrode K and the grid electrode G; n is n - The lower surface of the drift region is provided with n FS Layer, n FS The lower surface of the layer is provided with p + Anode region, p + The lower surface of the anode region is provided with a plurality of layers of metallized anodes A,
based on the structure, the method is implemented according to the following steps:
step 1: selecting the original<100>Low-resistance n-type monocrystal as substrate and epitaxial formation of n - A drift region;
step 2: performing dry-wet-dry oxidation on the silicon wafer treated in the step 1, forming a phosphorus ion implantation window on the upper surface through photoetching, performing phosphorus ion implantation, annealing and pushing, forming an n region in an active region, wherein the boundary of the n region is limited at the central position of the outermost cell in the active region;
step 3: removing the oxide layer on the surface of the silicon wafer treated in the step 2, and carrying out dry oxygen oxidation again to form a gate oxide layer;
step 4: forming a polysilicon layer on the upper surface of the silicon wafer treated in the step 3 by adopting chemical vapor deposition, and carrying out phosphorus doping;
step 5: forming a boron ion implantation window on the upper surface of the silicon wafer treated in the step 4 through photoetching, then carrying out boron ion implantation under the masking of photoresist, annealing and high-temperature propulsion after photoresist removal to form a p-base region and a terminal p-type field limiting ring, and continuing propulsion of an n-region;
step 6: forming a phosphorus ion implantation window on the upper surface of the silicon wafer treated in the step 5 through photoetching, carrying out high-energy phosphorus ion implantation under the masking of photoresist, annealing and high-temperature propulsion to form an n+ cathode region, and continuing propulsion of an n region and a p base region;
step 7: forming a phosphorus ion implantation window of an n-body region on the upper surface of the silicon wafer treated in the step 6 through photoetching, then carrying out phosphorus ion implantation under the masking of photoresist, and annealing and advancing after photoresist removal to form an n-body region and a terminal n-type stop ring;
step 8: forming p on the upper surface of the silicon wafer processed in the step 7 through photoetching ++ The boron ion implantation window of the source region is then subjected to boron ion implantation under the masking of photoresist, and annealing is performed after photoresist removal to form p ++ A source region;
step 9: growing a phosphosilicate glass layer on the upper surface of the silicon wafer treated in the step 8 by utilizing low-pressure chemical vapor deposition, and refluxing at a high temperature to realize surface planarization;
step 10: photoetching the upper surface of the silicon wafer treated in the step 9 to form contact holes of a cathode and a grid electrode, depositing a metal aluminum layer, reversely etching, and alloying to form a metallized cathode and a metallized grid electrode;
step 11: thinning and etching the lower surface of the silicon wafer processed in the step 10, removing the original n substrate, and taking a transition region formed by convection diffusion between the substrate and the n-drift region as n FS A layer;
step 12: performing boron ion implantation on the lower surface of the silicon wafer treated in the step 11, and then performing rapid laser annealing to form a p+ anode region;
step 13: sputtering four layers of metallized films of aluminum, titanium, nickel and silver on the lower surface of the silicon wafer treated in the step 12 in sequence, and forming a multi-layer metallized anode A after alloying;
step 14: depositing silicon nitride on the upper surface of the silicon wafer treated in the step 13 by utilizing plasma enhanced chemical vapor deposition, and reversely etching to form a cathode and grid electrode bonding area isolation pattern and a terminal passivation film;
step 15: throwing a polyimide film on the upper surface of the silicon wafer treated in the step 14, reversely etching, and then curing to finish the surface protection of the terminal area; finally, dicing, testing and packaging are completed, and the finished product is obtained.
2. The method of manufacturing a MOS controlled thyristor as recited in claim 1, wherein: the n region concentration is 8×10 15 cm -3 ～2×10 16 cm -3 。
3. The method of manufacturing a MOS controlled thyristor as recited in claim 1, wherein: the concentration difference range between the p base region and the n body region is 5 multiplied by 10 17 cm -3 ～9×10 17 cm -3 。
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| KR100900562B1 (en) * | 2003-03-24 | 2009-06-02 | 페어차일드코리아반도체 주식회사 | MOS-gated transistor having improved UIS capability |
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