CN112382568A - Manufacturing method of MOS control thyristor - Google Patents
Manufacturing method of MOS control thyristor Download PDFInfo
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- CN112382568A CN112382568A CN202011157039.6A CN202011157039A CN112382568A CN 112382568 A CN112382568 A CN 112382568A CN 202011157039 A CN202011157039 A CN 202011157039A CN 112382568 A CN112382568 A CN 112382568A
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- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 230000007704 transition Effects 0.000 claims abstract description 5
- 238000002161 passivation Methods 0.000 claims abstract description 4
- 238000003466 welding Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 43
- 229910052710 silicon Inorganic materials 0.000 claims description 43
- 239000010703 silicon Substances 0.000 claims description 43
- 238000005468 ion implantation Methods 0.000 claims description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 238000000137 annealing Methods 0.000 claims description 19
- 238000001259 photo etching Methods 0.000 claims description 18
- 229910052796 boron Inorganic materials 0.000 claims description 16
- 230000000873 masking effect Effects 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- -1 boron ions Chemical class 0.000 claims description 10
- 210000000746 body region Anatomy 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 238000005275 alloying Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 239000005360 phosphosilicate glass Substances 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000012360 testing method Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 claims description 3
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- 229910052751 metal Inorganic materials 0.000 claims description 3
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- 238000004806 packaging method and process Methods 0.000 claims description 3
- 238000010992 reflux Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 8
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
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Abstract
The invention discloses a manufacturing method of an MOS control thyristor, which comprises the following steps: 1) epitaxially forming n on a substrate‑A drift region; 2) forming an n region in the active region; 3) forming a gate oxide layer; 4) depositing a polysilicon layer and carrying out phosphorus doping; 5) forming a p-type base region and a terminal p-type field limiting ring; 6) form n+A cathode region; 7) forming an n-body region and a terminal n-type stop ring; 8) form p++A source region; 9) flattening the surface; 10) forming a metallized cathode and gate; 11) removing the substrate, using the substrate and n‑The transition region formed by convection diffusion between drift regions is used as nFSA layer; 12) form p+An anode region; 13) forming a multilayer metallized anode A; 14) forming a cathode and grid electrode pressure welding area isolation graph and a terminal passivation film; 15) surface protection of the termination region is accomplished. The MOS control thyristor manufactured by the method can be full ofSufficient pulse power and requirements in the field of solid state circuit breakers.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and relates to a manufacturing method of an MOS control thyristor.
Background
The MOS Control Thyristor (MCT) is controlled by a voltage signal, so that the driving is simpler than that of a common thyristor controlled by a current. Although the conventional MCT can reduce the on-state voltage drop of a device, the concentration difference between a p base region and an n body region is small, the concentration and the length of a channel are difficult to control during manufacturing, so that the device is easy to have channel penetration during blocking, the threshold voltage is sensitive to the change of the channel, the current rise rate is low during opening, the on-state voltage drop is high, and the wide application of the MCT in the fields of pulse power, solid-state circuit breakers and the like is limited.
Disclosure of Invention
The invention aims to provide a manufacturing method of an MOS control thyristor, which solves the problems that the doping concentration and the length of a channel of a device are difficult to accurately control and the application requirements in the field of pulse power and solid-state circuit breakers in the prior art can not be met.
The technical scheme adopted by the invention is that the manufacturing method of the MOS control thyristor is implemented according to the following steps:
step 1: selecting a substrate, epitaxially forming n-A drift region;
step 2: carrying out dry-wet-dry oxidation on the silicon wafer treated in the step (1), forming a phosphorus ion implantation window on the upper surface through photoetching, then carrying out phosphorus ion implantation, annealing and propelling, and forming an n region in the active region;
and step 3: removing the oxide layer on the surface of the silicon wafer treated in the step (2), and carrying out dry oxygen oxidation again to form a gate oxide layer;
and 4, step 4: forming a polycrystalline silicon layer on the upper surface of the silicon wafer treated in the step (3) by adopting chemical vapor deposition, and doping phosphorus;
and 5: forming a boron ion implantation window on the upper surface of the silicon wafer processed in the step 4 through photoetching, then performing boron ion implantation under the masking of photoresist, annealing and high-temperature propelling after photoresist removing to form a p-base region and a terminal p-type field limiting ring, and simultaneously continuing propelling the n region;
step 6: forming a phosphorus ion implantation window on the upper surface of the silicon wafer treated in the step 5 through photoetching, performing high-energy phosphorus ion implantation under the masking of photoresist, then annealing and high-temperature propelling to form an n + cathode region, and simultaneously continuing propelling the n region and the p base region;
and 7: forming a phosphorus ion implantation window of an n body area on the upper surface of the silicon wafer treated in the step 6 through photoetching, then performing phosphorus ion implantation under the masking of photoresist, and annealing and propelling after removing the photoresist to form the n body area and a terminal n-type stop ring;
and 8: forming p on the upper surface of the silicon wafer processed in the step 7 by photoetching++Injecting boron ions into the window of the source region, then injecting boron ions under the masking of the photoresist, and annealing after removing the photoresist to form p++A source region;
and step 9: growing a phosphosilicate glass layer on the upper surface of the silicon chip treated in the step 8 by using low-pressure chemical vapor deposition, and refluxing at high temperature to realize surface planarization;
step 10: photoetching the upper surface of the silicon wafer processed in the step 9 to form contact holes of a cathode and a grid, then depositing a metal aluminum layer, reversely etching, and then alloying to form a metalized cathode and a metalized grid;
step 11: thinning and corroding the lower surface of the silicon wafer treated in the step 10, removing the original n substrate, and taking a transition region formed by convection diffusion between the substrate and the n-drift region as nFSA layer;
step 12: implanting boron ions into the lower surface of the silicon wafer treated in the step 11, and then performing laser rapid annealing to form a p + anode region;
step 13: sputtering four layers of metallized films of aluminum, titanium, nickel and silver on the lower surface of the silicon wafer treated in the step 12 in sequence, and forming a multi-layer metallized anode A after alloying;
step 14: depositing silicon nitride on the upper surface of the silicon wafer treated in the step 13 by utilizing plasma enhanced chemical vapor deposition, and reversely etching to form a cathode and grid pressure welding area isolation pattern and a terminal passivation film;
step 15: throwing a polyimide film on the upper surface of the silicon chip treated in the step 14, reversely etching the polyimide film, and then carrying out curing treatment to finish surface protection of the terminal area; and finally scribing, testing and packaging are completed.
The MOS control crystal has the beneficial effect thatMethod for manufacturing gate tube in n of conventional MCT active region-An n region with higher concentration is introduced above the drift region through doping, so that the doping concentration and the length of a channel are convenient to adjust, the threshold voltage and the blocking voltage of the device can be accurately controlled, and the device has high current rise rate and low on-state voltage drop when being turned on.
Drawings
FIG. 1 is a schematic cross-sectional view of the basic structure of a MOS-controlled thyristor obtained by the manufacturing method of the present invention;
FIG. 2 is a forward blocking characteristic curve of a MOS controlled thyristor of the invention with a conventional MCT at zero and negative gate voltages;
FIG. 3 is a comparison of the forward conduction characteristics of the MOS controlled thyristor of the invention and a conventional MCT;
fig. 4 is a graph comparing the concentration distribution of longitudinal carriers of the MOS controlled thyristor of the invention and a conventional MCT, which are split along the center of the n region during conduction;
fig. 5 is a plot of on-current versus pulse power for a MOS-controlled thyristor of the present invention versus a conventional MCT.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
Referring to fig. 1, the basic structure of the MOS controlled thyristor of the present invention is that the whole device is divided into n-The drift region is used as a voltage-proof layer, n-A p base region is arranged in the center above the drift region, and n regions are arranged on two sides of the p base region; n is arranged above the p base region at the center+Cathode region, n+N body regions are arranged on two sides of the cathode region, and the n body regions and the n at two sides+A p is respectively arranged above the junction of the cathode regions++A source region; two p++Aluminum layer on upper surface of source region and n+The aluminum layers on the upper surface of the cathode region are connected into a whole to form a cathode electrode K; n region, p base region, n body region and partial p on two sides++The upper surface of the source region is provided with a gate oxide layer (SiO)2Material layer) on the gate oxide layerA heavily doped polysilicon layer is arranged on the surface of the substrate and is used as a grid G; a phosphorosilicate glass layer (namely a PSG material layer) is arranged between the cathode electrode K and the grid G, and the PSG material layer is used for realizing the isolation between the cathode electrode K and the grid G; n is-N is arranged on the lower surface of the drift regionFSLayer (i.e. n field stop layer), nFSThe lower surface of the layer is provided with p+Anode region, p+The lower surface of the anode region is provided with a plurality of layers of metallized anodes A.
As can be seen from FIG. 1, the main structure of the MOS controlled thyristor of the invention is formed by n+Cathode region, p-base region, n-Drift region, nFSLayer and p+A thyristor composed of an anode region; the heavily doped polysilicon layer, the gate oxide layer, the n body region and the p base region below the heavily doped polysilicon layer respectively form a PMOS and an NMOS which are controlled by the same grid voltage. Wherein the concentration difference between the p-base region and the n-body region has a great influence on the device characteristics. The concentration difference between the p-base region and the n-body region of the traditional MCT is small, and is generally 3 x 1017cm-3～5×1017cm-3The concentration and the length of the channel are sensitive, so that the channel punch-through is easy to occur when the device is blocked, the threshold voltage is not easy to control, and the current rise rate and the on-state voltage drop are low when the device is switched on. The MOS control thyristor of the invention has the n region with the concentration range of 8 multiplied by 10 due to the addition of the n region15cm-3～2×1016cm-3The concentration tolerance range of the p-base region and the n-body region is increased to 5 x 1017cm-3～9×1017cm-3The length of the N channel is controlled within the range of 2-3 mu m, and the length of the P channel is controlled within the range of 0.6-0.8 mu m, so that the threshold voltage and the blocking voltage of the device can be accurately controlled, and meanwhile, the current rise rate is improved and the on-state voltage drop is reduced during the turn-on.
The manufacturing method of the MOS control thyristor is specifically implemented according to the following steps:
step 1: selecting original<100>Epitaxially forming n on low-resistance n-type single crystal as substrate-A drift region;
step 2: carrying out dry-wet-dry oxidation on the silicon wafer treated in the step (1), forming a phosphorus ion implantation window on the upper surface through photoetching, then carrying out phosphorus ion implantation, annealing and propelling, and forming an n region in the active region;
and step 3: removing the oxide layer on the surface of the silicon wafer treated in the step (2), and carrying out dry oxygen oxidation again to form a gate oxide layer;
and 4, step 4: forming a polycrystalline silicon layer on the upper surface of the silicon wafer treated in the step (3) by adopting chemical vapor deposition, and doping phosphorus;
and 5: forming a boron ion implantation window on the upper surface of the silicon wafer processed in the step 4 through photoetching, then performing boron ion implantation under the masking of photoresist, annealing and high-temperature propelling after photoresist removing to form a p-base region and a terminal p-type field limiting ring, and simultaneously continuing propelling the n region;
step 6: forming a phosphorus ion implantation window on the upper surface of the silicon wafer treated in the step 5 through photoetching, performing high-energy phosphorus ion implantation under the masking of photoresist, then annealing and high-temperature propelling to form an n + cathode region, and simultaneously continuing propelling the n region and the p base region;
and 7: forming a phosphorus ion implantation window of an n body area on the upper surface of the silicon wafer treated in the step 6 through photoetching, then performing phosphorus ion implantation under the masking of photoresist, and annealing and propelling after removing the photoresist to form the n body area and a terminal n-type stop ring;
and 8: forming p on the upper surface of the silicon wafer processed in the step 7 by photoetching++Injecting boron ions into the window of the source region, then injecting boron ions under the masking of the photoresist, and annealing after removing the photoresist to form p++A source region;
and step 9: growing a phosphorosilicate glass layer on the upper surface of the silicon wafer treated in the step 8 by using low-pressure chemical vapor deposition (LPCVD), and refluxing at high temperature to realize surface planarization;
step 10: photoetching the upper surface of the silicon wafer processed in the step 9 to form contact holes of a cathode and a grid, then depositing a metal aluminum layer, reversely etching, and then alloying to form a metalized cathode and a metalized grid;
step 11: thinning and corroding the lower surface of the silicon wafer treated in the step 10, removing the original n substrate, and taking a transition region formed by convection diffusion between the substrate and the n-drift region as nFSA layer;
step 12: implanting boron ions into the lower surface of the silicon wafer treated in the step 11, and then performing laser rapid annealing to form a p + anode region;
step 13: sputtering four layers of metallized films of aluminum, titanium, nickel and silver on the lower surface of the silicon wafer treated in the step 12 in sequence, and forming a multi-layer metallized anode A after alloying;
step 14: depositing silicon nitride on the upper surface of the silicon wafer treated in the step 13 by utilizing Plasma Enhanced Chemical Vapor Deposition (PECVD), and reversely etching to form a cathode and grid pressure welding area isolation graph and a terminal passivation film;
step 15: throwing a polyimide film on the upper surface of the silicon chip treated in the step 14, reversely etching the polyimide film, and then carrying out curing treatment to finish surface protection of the terminal area; and finally scribing, testing and packaging are completed.
From the above, the manufacturing method of the MOS controlled thyristor of the present invention has the following three characteristics: firstly, before the front cell is manufactured, an n region is formed in an active region, and the subsequent process is not influenced; secondly, when the unit cell is formed, the p base region, the n body region and the p++The source region can be realized by a self-alignment process, the p base region is manufactured after the gate oxide is formed, and the influence of the segregation effect of impurity boron at the interface of the p base region and the oxide layer on the N channel in the high-temperature growth process of the gate oxide layer is effectively avoided; thirdly, the substrate is removed through thinning, and a transition region formed by convection diffusion between the epitaxial layer and the substrate in the epitaxial high-temperature process is effectively utilized as nFSLayer, ensure nFSQuality and parameter requirements of the layer.
In particular, the method of the present invention is suitable for devices having blocking voltages of 1400V or less. For the device with the blocking voltage larger than 1400V, the original high-resistance zone melting intermediate zone silicon single crystal polished wafer can be used as n-Drift region, first in processed n-Forming n on the lower surface of the drift region by implanting phosphorus ions and annealing and high-temperature propellingFSThe upper surface of the layer is thinned appropriately according to the blocking voltage requirement, and then n-The upper surface of the drift region is made into a cellular, and the above step 10 is omitted, and other steps are the same.
And (3) experimental verification:
in order to evaluate the characteristics of the MOS control thyristor obtained by the manufacturing method of the present invention, taking 1400V voltage level as an example, a professional simulation software is used to perform simulation verification on the forward blocking characteristic, the turn-on characteristic, and the turn-on characteristic in pulse power application, respectively, and the results are as follows:
1) forward blocking characteristics
Referring to fig. 2, the forward blocking characteristic curves of the MOS controlled thyristor of the present invention and the conventional MCT at zero gate voltage and negative gate voltage are shown. It can be seen that both have almost the same blocking characteristics, i.e., at gate bias VGWhen the voltage is zero, the forward blocking voltage is about 270V; at gate bias VGat-5V, the forward blocking voltages were all about 1710V. Therefore, the MOS control thyristor obtained by the manufacturing method of the invention can bear higher blocking voltage under the negative grid voltage.
2) Conduction characteristic
Referring to fig. 3, a forward conduction characteristic comparison curve of the MOS controlled thyristor of the present invention and a conventional MCT is shown. At 100A/cm2Under the current density of the anode, the on-state voltage drop of the traditional MCT is 1.15V, while the on-state voltage drop of the MOS control thyristor is only 0.95V, which is reduced by about 17 percent. Therefore, the MOS control thyristor obtained by the manufacturing method has lower on-state voltage drop.
Referring to fig. 4, a longitudinal carrier concentration distribution contrast curve of the MOS controlled thyristor of the present invention and a conventional MCT, which is split along the center of an n-region during turn-on. It can be seen that the carrier concentration under the gate when the MOS controlled thyristor of the invention is turned on is much higher than the corresponding carrier concentration in the conventional MCT. This shows that the method of the present invention can not only control the concentration and length of the channel, but also increase the carrier concentration on the cathode side when the device is turned on, thereby reducing the on-state voltage drop.
3) Opening characteristic
Referring to fig. 5, there is shown a plot of on-current versus pulse power for the MOS-controlled thyristor of the present invention versus a conventional MCT. The test condition is bus voltage UCC800V, gate resistance RG4.7 Ω, gate voltage V GK5V, electricityFeeling LSWhen the capacitance C is 8nH, the resistance R is 0.01 Ω, and the capacitance C is 0.2 μ F. It can be seen that the peak current density at the turn-on of a conventional MCT is about 3055A/cm2The current rise rate is about 57 kA/mu s; the peak current density of the MOS controlled thyristor in the invention is about 3325A/cm when being switched on2The current rise rate was about 70 kA/. mu.s. In comparison, the peak current density is improved by about 8.8%, and the current increase rate is improved by about 22.8%. It can be seen that the MOS control thyristor obtained by the method has higher peak current and current rise rate than the traditional MCT.
Claims (5)
1. A manufacturing method of a MOS control thyristor is characterized by comprising the following steps:
step 1: selecting a substrate, epitaxially forming n-A drift region;
step 2: carrying out dry-wet-dry oxidation on the silicon wafer treated in the step (1), forming a phosphorus ion implantation window on the upper surface through photoetching, then carrying out phosphorus ion implantation, annealing and propelling, and forming an n region in the active region;
and step 3: removing the oxide layer on the surface of the silicon wafer treated in the step (2), and carrying out dry oxygen oxidation again to form a gate oxide layer;
and 4, step 4: forming a polycrystalline silicon layer on the upper surface of the silicon wafer treated in the step (3) by adopting chemical vapor deposition, and doping phosphorus;
and 5: forming a boron ion implantation window on the upper surface of the silicon wafer processed in the step 4 through photoetching, then performing boron ion implantation under the masking of photoresist, annealing and high-temperature propelling after photoresist removing to form a p-base region and a terminal p-type field limiting ring, and simultaneously continuing propelling the n region;
step 6: forming a phosphorus ion implantation window on the upper surface of the silicon wafer treated in the step 5 through photoetching, performing high-energy phosphorus ion implantation under the masking of photoresist, then annealing and high-temperature propelling to form an n + cathode region, and simultaneously continuing propelling the n region and the p base region;
and 7: forming a phosphorus ion implantation window of an n body area on the upper surface of the silicon wafer treated in the step 6 through photoetching, then performing phosphorus ion implantation under the masking of photoresist, and annealing and propelling after removing the photoresist to form the n body area and a terminal n-type stop ring;
and 8: forming p on the upper surface of the silicon wafer processed in the step 7 by photoetching++Injecting boron ions into the window of the source region, then injecting boron ions under the masking of the photoresist, and annealing after removing the photoresist to form p++A source region;
and step 9: growing a phosphosilicate glass layer on the upper surface of the silicon chip treated in the step 8 by using low-pressure chemical vapor deposition, and refluxing at high temperature to realize surface planarization;
step 10: photoetching the upper surface of the silicon wafer processed in the step 9 to form contact holes of a cathode and a grid, then depositing a metal aluminum layer, reversely etching, and then alloying to form a metalized cathode and a metalized grid;
step 11: thinning and corroding the lower surface of the silicon wafer treated in the step 10, removing the original n substrate, and taking a transition region formed by convection diffusion between the substrate and the n-drift region as nFSA layer;
step 12: implanting boron ions into the lower surface of the silicon wafer treated in the step 11, and then performing laser rapid annealing to form a p + anode region;
step 13: sputtering four layers of metallized films of aluminum, titanium, nickel and silver on the lower surface of the silicon wafer treated in the step 12 in sequence, and forming a multi-layer metallized anode A after alloying;
step 14: depositing silicon nitride on the upper surface of the silicon wafer treated in the step 13 by utilizing plasma enhanced chemical vapor deposition, and reversely etching to form a cathode and grid pressure welding area isolation pattern and a terminal passivation film;
step 15: throwing a polyimide film on the upper surface of the silicon chip treated in the step 14, reversely etching the polyimide film, and then carrying out curing treatment to finish surface protection of the terminal area; and finally scribing, testing and packaging are completed.
2. The method of manufacturing a MOS controlled thyristor according to claim 1, wherein: the MOS control thyristor structure is that the whole device is controlled by n-The drift region is used as a voltage-proof layer, n-A p base region is arranged in the center above the drift region, and n regions are arranged on two sides of the p base region; in the p radicalN is arranged at the center above the region+Cathode region, n+N body regions are arranged on two sides of the cathode region, and the n body regions and the n at two sides+A p is respectively arranged above the junction of the cathode regions++A source region; two p++Aluminum layer on upper surface of source region and n+The aluminum layers on the upper surface of the cathode region are connected into a whole to form a cathode electrode K; n region, p base region, n body region and partial p on two sides++A layer of gate oxide layer is arranged on the upper surfaces of the source regions together, and a heavily doped polycrystalline silicon layer is arranged on the upper surface of the gate oxide layer and serves as a grid G; a phosphorosilicate glass layer is arranged between the cathode electrode K and the grid G; n is-N is arranged on the lower surface of the drift regionFSLayer nFSThe lower surface of the layer is provided with p+Anode region, p+The lower surface of the anode region is provided with a plurality of layers of metallized anodes A.
3. The method of manufacturing a MOS controlled thyristor according to claim 1, wherein: the value range of the n region concentration is 8 multiplied by 1015cm-3～2×1016cm-3。
4. The method of manufacturing a MOS controlled thyristor according to claim 1, wherein: the concentration difference range of the p-base region and the n-body region is 5 multiplied by 1017cm-3～9×1017cm-3。
5. The method of manufacturing a MOS controlled thyristor according to claim 1, wherein: the substrate is a low-resistance n-type single crystal with the resistance of <100 >.
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