CN1144975A - Grid-controlled transistor - Google Patents
Grid-controlled transistor Download PDFInfo
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- CN1144975A CN1144975A CN 96118670 CN96118670A CN1144975A CN 1144975 A CN1144975 A CN 1144975A CN 96118670 CN96118670 CN 96118670 CN 96118670 A CN96118670 A CN 96118670A CN 1144975 A CN1144975 A CN 1144975A
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Abstract
A grid-controlled thyristor features that depletion-type MOSFET is integrated on the surface of emitting area or the surface of emitting area and wide base area and the MOS channel area can make the emitting junction of thyristor short, so controlling its on-off. Its advantages include high cut current density, speed and reliability and monopolarity voltage control.
Description
The present invention relates to microelectric technique and electric and electronic technical field, particularly a kind of grid-controlled transistor power device of new principle structure.
Semiconductor device is through the development of many decades, progressively form two big fields, i.e. microelectronic component and power electronic device field, the former is a developing direction with the integrated circuit of process information, at present can be on a block semiconductor chip integrated more than one hundred million components and parts, promoted the develop rapidly of electronic technology; The latter is a direction with the processing power then, wishes that its power capacity is big, and high conversion speed is arranged, and this class power semiconductor is representative with high power transistor and thyristor (Thyristor) mainly.Yet the opening and closing of this class device all are to control with electric current at input, because the inherent characteristic of semiconductor device, determined to close to be in conducting state and to open this class device that is in cut-off state and needed bigger drive current, as close the reverse current that the thyristor input need add 1/4th output currents approximately, cause input power big, it is complicated that drive circuit becomes.The development of microelectric technique, the continuous maturation of microfabrication and metal-oxide semiconductor (MOS) (MOS) technology has developed voltage-controlled power semiconductor, makes device can control big power output under minimum input power.The seventies latter stage, invented vertical bilateral diffusion field-effect tranisistor (VDMOS) abroad, early eighties has been invented the thyristor (MCT) of igbt (IGBT) and MOS control again, in the middle of this three classes device, the former two's technology is mature on the whole, the latter is still among development, but the ability of processing power is maximum with MCT.MCT is the composite construction of metal oxide semiconductor field effect tube (MOSFET) and thyristor, and its input has a extensive future because voltage control and power output are big, is the research field of concern both at home and abroad and attention over year surplus in the of nearly ten.This device is the surperficial integrated enhancement mode MOS of common grid at thyristor, form inversion layer when just applying the narrow base region surface of (bearing) grid voltage device, channel current flows into wide base and triggers the thyristor conducting, it penetrates the inversion channel short circuit thyristor emitter junction that the surface, district forms to apply negative (just) grid voltage, and the many sons in narrow base flow to negative electrode orders about device shuts off.The ability of its controlled cut-off current depends on the resistance of this MOS inversion channel.Because its manufacturing technology is compatible with the MOS integrated circuit technology, has presented very big vitality, existing at present commodity in batches.After this reported multiple new structure devices around the research of device current turn-off capacity, formed such device of cluster, representational have a MOS depletion type thyristor (DMT), emitter turn-off thyristor (EST), the thyristor (BRT) of base resistance control and have the EST structures such as (ESTD) that knot is penetrated in the short circuit of MOS inversion layer.The MOS structure of their trigger device conductings is identical with the MCT structure with principle, and difference is being closed the MOS structure and the principle of device.DMT has adopted gate electrode vertically to go deep into the U type groove enhancement mode MOS structure of wide base, when applying grid voltage under the mos gate wide base exhaust, adjacent depletion layer vertically forces device shuts off with wide base pinch off.It adopts non-planar surface process to increase difficulty.EST is integrated enhancement mode MOS structure between the emitter-base bandgap grading of device and negative electrode, electric current flows into negative electrode through this enhancement mode MOS raceway groove during conducting, current path cut off and realizes closing when grid voltage dropped to the raceway groove disappearance, the Power Limitation of this MOS the operating current of device, and there is the parasitic thyristor that is not subjected to MOS control in the structure, influenced the ability of device cut-off current.BRT wide base region surface integrated enhancement mode MOS structure, rely on this MOS inversion channel that the many sons in narrow base are driven to negative electrode, control is closed, its essence and MCT to penetrate the knot short circuit similar.The limited ability of cut-off current is in the resistance of MOS inversion channel.ESTD can regard the composite construction of EST and BRT as, and it has kept the MOS structure that EST cuts off electric current, has increased the enhancement mode MOS structure with the BRT identical function, has improved the electric current closing force, has also kept their deficiency simultaneously.
The research and development emphasis of the thyristor class power device of MOS control at present is still at the controlled turn-off capacity of MOS structure to device current, i.e. the reliability of may command current density, turn-off speed and the shutoff of turn-offing etc.In addition, above-mentioned each structure devices all is to adopt opposite polarity two voltages to control its opening and closing respectively except that EST, and there is intrinsic deficiency in EST.
The objective of the invention is to propose such device of a kind of new principle structure, the ability of its cut-off current is superior, and the control opening and closing only need a unipolarity voltage, and promptly input applies the voltage signal break-over of device, voltage signal is reduced to a certain threshold value or zero, and device is then closed voluntarily.
Basic scheme of the present invention be thyristor in device surface design the enhancement mode MOS structure and the depletion type MOS structure of common grid.Enhancement mode MOS is integrated in the surface of the narrow base of thyristor, the conducting of this MOS control device.Depletion type MOS is integrated in the thyristor emitter region, and the raceway groove of this MOS has formed penetrating of thyristor and tied intrinsic short-circuit structure, the shutoff of control device.This structure devices operation principle can be sketched and be: when applying a certain polar voltages in the mos gate utmost point, the raceway groove pinch off of depletion type MOS, thyristor are penetrated the knot short circuit and are disappeared, and device is rendered as thyristor structure, and enhancement mode MOS forms inversion channel, and channel current orders about thyristor and opens.Be lower than a certain threshold value or zero when voltage drops to, enhancement mode MOS raceway groove disappears, and loses the condition that drives the thyristor conducting, and depletion type MOS is linked up recovery, and thyristor presents penetrates knot by the intrinsic structure of this raceway groove short circuit, orders about thyristor and closes.The ability of close current depends on that the short circuit device penetrates the depletion type MOS channel resistance of knot.
For further improving the ability of device cut-off current, in the wide integrated depletion type MOS structure of base region surface while of thyristor, its raceway groove has formed penetrating of thyristor equally and has tied the intrinsic short circuit, has effectively reduced and has penetrated the knot short-circuit resistance.
Because the ability of this structure devices cut-off current depends on the short-circuit resistance of penetrating knot, be the resistance of depletion type MOS raceway groove, reasonably its channel resistance of design is less than the inversion channel resistance of enhancement mode MOS, therefore, close current density height, speed is fast, and since thyristor penetrate the knot short circuit formed by the depletion type MOS raceway groove, the good reliability of close current, and realized the work of single polar voltages control device.
Below in conjunction with drawings and Examples device of the present invention is further described.
Fig. 1 is unit born of the same parents' longitudinal profile structural representation of first kind of embodiment of device of the present invention.
Fig. 2 is second kind of embodiment unit born of the same parents' longitudinal profile structural representation of device of the present invention.
Fig. 3 is unit born of the same parents' longitudinal profile structural representation of the third embodiment of device of the present invention.
Fig. 4 is the 4th kind of embodiment unit born of the same parents' longitudinal profile structural representation of device of the present invention.
Referring to Fig. 1, " 1 " shown in figure district uses P for p type island region
2Expression, " 2 " district is the gate electrode layer of MOSFET, and " 3 " district is insulating medium layer, and " 4 " district and " 5 " district are the external electrode metal layers.The P of bottom among the figure
+District and N
-District, P
1The PNP transistor arrangement that the district forms and the N (N of figure middle and upper part
+) district and P
1District, N
-The district forms that the NPN transistor structure is compound to have constituted PNPN type thyristor, wherein N
-District and P
1The district is respectively the wide base and the narrow base of thyristor, N (N
+) district is for its surface emitting district." A " " K " and " G " are respectively device anode, negative electrode and gate electrode.P in the surface emitting district
+District, P
2District and P
1Narrow base has constituted depletion type P ditch MOSFET, P with " 2 " district gate electrode
+District, P
2District and P
1The district is respectively its drain region, channel region and source region.The raceway groove P of this MOSFET as seen from Figure 1
2The district has formed the intrinsic short-circuit structure of thyristor emitter junction.This depletion type MOS raceway groove P
2District and drain electrode P
+The district is distributed in the surface with certain plane geometric shape (as the bridge shape), thus its at interval part be still N type emitter region, and this N type is penetrated district and N
-The district and between P
1The district has then constituted source region, drain region and the channel region of enhancement mode N ditch MOSFET respectively on the surface." 2 " district gate electrode shown in enhancement mode and the shared figure of depletion type MOS FET.
The operation principle of device embodiment of the present invention can be sketched and be: getting negative electrode K is reference potential, and anode A is put high potential, when applying positive electricity and be pressed on grid G, and P
2The district exhausts, surperficial P
+District and P
1Open circuit in the interval, depletion type P ditch MOSFET ends, and device is rendered as thyristor structure.Simultaneously, P
1The surface, district forms inversion-layer channel, and enhancement mode N ditch MOSFET opens, and its channel electrons stream is penetrated the district from the N type and flowed into N
-Wide base, trigger device enters conducting state.When gate voltage drops to a certain threshold value or zero, P
1District's surface inversion layer disappears, and enhancement mode N ditch MOSFET ends, the P of depletion type MOS FET
2Raceway groove recovers, and thyristor is penetrated knot and presented short circuit, P
1The hole is through this short circuit P in the narrow base
2Device shuts off is ordered about in the positive feedback of electric current in the device that the district has flowed into cathode breakdown.
As seen, device embodiment close current of the present invention shown in Figure 1 be relied on be integrated in the N type penetrate the district in depletion type P ditch MOSFET raceway groove short circuit device emitter junction, the ability of close current is by raceway groove P
2The decision of knot short-circuit resistance is promptly penetrated in the resistance decision in district, and this resistance is decided by P
2The Material Physics parameter and the geometrical structure parameter in district.
Referring to Fig. 2, this embodiment penetrates the knot short-circuit resistance for what reduce device, and the ability that further improves the device cut-off current proposes.Second kind of embodiment of device of the present invention shown in Figure 2 kept the structure of first kind of embodiment, in addition at the N of the adjacent first intercellular of device
-Wide base region surface is integrated depletion type P ditch MOSFET, " 6 " district is its channel region among Fig. 2, still uses P
2Expression, the P of both sides among the figure
+The district is its drain region, P
1Narrow base is its source region.The P in " 6 " district
2The P in district and " 1 " district
2Form simultaneously, and the P in " 6 " district
2The district also is arranged at the surface with certain plane geometric shape (as the bridge shape).The operation principle of present embodiment device is identical with the operation principle of first kind of embodiment device, but present embodiment is penetrated district and N at device
-Wide base table and two integrated respectively depletion type P ditch MOSFET are in parallel has effectively reduced the short-circuit resistance that device is penetrated knot, has improved the ability of device cut-off current.
Referring to Fig. 3, the third embodiment unit born of the same parents' longitudinal profile schematic diagram of device of the present invention is identical with the geometry of first kind of embodiment unit born of the same parents' longitudinal profile schematic diagram of device of the present invention shown in Figure 1, and difference is opposite at corresponding doping type." 1 " district uses N for N type district among the figure
2Expression, " 2 " district is the gate electrode layer of MOSFET, and " 3 " district is insulating medium layer, and " 4 " district and " 5 " district are the external electrode metal layers.The N of bottom among the figure
+District, P
-District and N
1The NPN transistor structure that the district forms and the P (P of figure middle and upper part
+) district and N
1District, P
-The PNP transistor arrangement that the district forms is compound to have constituted NPNP thyristor structure, wherein P (P
+) district be the surface emitting district of thyristor, P
-District and N
1The district is respectively the wide base of thyristor and anode, negative electrode and the gate electrode that narrow base, " A ", " K " and " G " are respectively device.N in the surface emitting district
+District, N
2District and N
1Narrow base has constituted drain region, channel region and the source region of depletion type N ditch MOSFET respectively.This MOSFET raceway groove N
2The district has formed thyristor and has penetrated knot intrinsic short-circuit structure.Its raceway groove N
2District and drain electrode N
+The district is distributed in certain plane geometric shape (as the bridge shape) and penetrates the surface, district, and compartment is still P type emitter region, and at device surface, this P type is penetrated district, P
-Wide base and middle N thereof
1Narrow base has constituted enhancement mode P ditch MOSFET.Enhancement mode and depletion type MOS FET be grid altogether.
The operation principle of the third embodiment of device of the present invention can be sketched and be: as the reference current potential, anode A is put negative potential with negative electrode K, when applying reverse voltage in grid G, and N
2The district exhausts, N
+District and N
1The district opens circuit, and depletion type N ditch MOSFET ends, and device architecture is rendered as thyristor.And while N
1The surface, district forms P type inversion channel, and enhancement mode P ditch MOSFET opens, and hole current flows into P from negative electrode through this MOSFET raceway groove
-Wide base, the trigger device conducting is when the absolute value of gate voltage is reduced to a certain threshold value or zero, N
1District's surface inversion layer disappears, and enhancement mode P ditch MOSFET ends, and depletion type N ditch MOSFET raceway groove recovers, and device is penetrated knot short circuit, N
1Electronics flows to negative electrode through this shorting region in the narrow base, orders about device shuts off.
Referring to Fig. 4, present embodiment has kept the structure of the third embodiment of device of the present invention, forms N but penetrate the surface, district at the device of the third embodiment
+District and N
2In the time of " 1 " district, at the P of adjacent first intercellular
-Wide base region surface has also formed the N as shown in Fig. 4 with certain plane geometric shape (as the bridge shape)
+District and N
2" 6 " district.N
2" 6 " district, N
+District and N
1Narrow base has constituted depletion type N ditch MOSFET, and it is in parallel that this depletion type MOS FET and device are penetrated district surface depletion type N ditch MOSFET.Operation principle is identical with the third embodiment device, when gate electrode applies negative voltage, depletion type N ditch MOSFET ends, enhancement mode P ditch MOSFET work, order about break-over of device, when the gate voltage absolute value drops under a certain threshold value or zero, enhancement mode P ditch MOSFET ends, depletion type N ditch MOSFET raceway groove short circuit device is penetrated knot, and device is realized closing.Be in parallel owing to be integrated in two depletion type MOS FET of She Qu and wide base, the knot short-circuit resistance of penetrating of device reduces, and the ability of close current improves.
Total going up shown in the structure, the depletion type MOS FET raceway groove that is characterized as of device of the present invention has formed the intrinsic short circuit that device is penetrated knot, the ability of close current depends primarily on the short circuit channel resistance, the current density that rational design can be closed device of the present invention is big, speed is fast, reliability is high, and the work of device only needs a unipolarity voltage control.
The manufacturing technology of device of the present invention is compatible with the MOS integrated circuit technology.Below sketch its manufacture method and basic technical process with first kind of embodiment of device of the present invention.
At first at P
+Epitaxial growth N on the single-chip
-The type layer carries out the boron diffusion (or ion injection) of localization then, forms the P of thyristor top transistor
1The base also is the collecting region of bottom transistor simultaneously.Localization phosphorous diffusion in this base (or ion injection) N
+With the N layer, form the emitter region, so far the main structure of this device is finished.In order to form the MOSFET of control thyristor, adopt certain layout diffusion or ion to inject in the transistorized at an upper portion thereof emitter region and form P
+After this inject with ion again and make shallow junction P in the district
2Bridge is with P
+The district is connected with thyristor P1 base, and then the body inner structure of device is finished.When surface texture is finished in manufacturing, at first at wafer surface growth one deck gate oxide, growth covers polysilicon or refractory metal silicon compound then, forms the mos gate electrode, again at surface gate electrode deposit multilayer dielectricity,---silicon nitride---silicon dioxide that is silicon dioxide, make gate electrode and cathode leg hole by lithography, then deposit aluminium makes negative electrode and gate electrode by lithography, through surface passivation and back face metalization, the chip of this structure devices is promptly made and is finished.
Claims (3)
1. a grid-controlled transistor comprises anode A, negative electrode K and gate electrode G and by two compound PNPN that constitute of triode, NPNP thyristor structure, and contain by P on the surface, district of penetrating of PNPN structure
+N is contained in the depletion type P ditch MOSFET drain region that the district constitutes in the NPNP structure
+The depletion type N ditch MOSFET drain region that the district constitutes is characterized in that the surface, emitter region of above-mentioned thyristor structure or emitter region and wide base region surface are integrated with depletion type MOS FET channel region, and this channel region has formed device and penetrated the knot short circuit.
2. grid-controlled transistor according to claim 1 is characterized in that the integrated depletion type MOS FET channel region (1) in surface, described emitter region is with the drain region P of bridge distribution of shapes in PNPN structure thyristor
+With source region P
1Between or the N of NPNP structure thyristor
+With N
1Between.
3. grid-controlled transistor according to claim 1 is characterized in that the integrated depletion type MOS FET channel region (1) of described emitter region and wide base region surface is with bridge distribution of shapes drain region P in PNPN structure thyristor is penetrated the district
+Source region P with the formation of narrow base
1Between or the N of NPNP structure thyristor
+With N
1Between, channel region (6) with the bridge distribution of shapes in the wide base region surface of PNPN structure thyristor drain region P
+Source region P with the formation of narrow base
1Between or NPNP structure thyristor N
+With N
1Between.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN96118670A CN1045139C (en) | 1996-04-23 | 1996-04-23 | Grid-controlled transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN96118670A CN1045139C (en) | 1996-04-23 | 1996-04-23 | Grid-controlled transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1144975A true CN1144975A (en) | 1997-03-12 |
| CN1045139C CN1045139C (en) | 1999-09-15 |
Family
ID=5125241
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96118670A Expired - Fee Related CN1045139C (en) | 1996-04-23 | 1996-04-23 | Grid-controlled transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1045139C (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964355A (en) * | 2009-09-11 | 2011-02-02 | 成都芯源系统有限公司 | Power device with self-aligned silicide contacts and method of making the same |
| CN103972086A (en) * | 2014-05-26 | 2014-08-06 | 电子科技大学 | Manufacturing method of MOS (metal oxide semiconductor) gate control thyristor |
| CN106024869A (en) * | 2016-05-24 | 2016-10-12 | 电子科技大学 | Power semiconductor device |
| WO2017215157A1 (en) * | 2016-06-13 | 2017-12-21 | 骆宁 | Semiconductor device |
| CN107527951A (en) * | 2017-09-19 | 2017-12-29 | 电子科技大学 | A kind of negative electrode short circuit grid-controlled transistor with high input capacitance |
| CN108242465A (en) * | 2016-12-23 | 2018-07-03 | 株洲中车时代电气股份有限公司 | A kind of door pole stream-exchanging thyristor and preparation method thereof |
| CN109087946A (en) * | 2018-08-27 | 2018-12-25 | 电子科技大学 | A kind of trench grate MOS control thyristor and preparation method thereof |
| CN110212027A (en) * | 2019-06-10 | 2019-09-06 | 西安理工大学 | Electron injection enhancement type double mode MOS controls thyristor and its manufacturing method |
| CN111933715A (en) * | 2020-09-25 | 2020-11-13 | 电子科技大学 | Silicon carbide MOSFET device |
| CN112382568A (en) * | 2020-10-26 | 2021-02-19 | 西安理工大学 | Manufacturing method of MOS control thyristor |
| CN114613849A (en) * | 2022-05-10 | 2022-06-10 | 深圳市威兆半导体有限公司 | Silicon carbide MOS device for improving short circuit characteristic |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2551152B2 (en) * | 1989-06-29 | 1996-11-06 | 富士電機株式会社 | MOS control thyristor |
-
1996
- 1996-04-23 CN CN96118670A patent/CN1045139C/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964355A (en) * | 2009-09-11 | 2011-02-02 | 成都芯源系统有限公司 | Power device with self-aligned silicide contacts and method of making the same |
| CN101964355B (en) * | 2009-09-11 | 2013-07-10 | 成都芯源系统有限公司 | Power device with self-aligned silicide contacts and method of making the same |
| CN103972086A (en) * | 2014-05-26 | 2014-08-06 | 电子科技大学 | Manufacturing method of MOS (metal oxide semiconductor) gate control thyristor |
| CN106024869A (en) * | 2016-05-24 | 2016-10-12 | 电子科技大学 | Power semiconductor device |
| WO2017215157A1 (en) * | 2016-06-13 | 2017-12-21 | 骆宁 | Semiconductor device |
| CN108242465A (en) * | 2016-12-23 | 2018-07-03 | 株洲中车时代电气股份有限公司 | A kind of door pole stream-exchanging thyristor and preparation method thereof |
| CN107527951A (en) * | 2017-09-19 | 2017-12-29 | 电子科技大学 | A kind of negative electrode short circuit grid-controlled transistor with high input capacitance |
| CN109087946A (en) * | 2018-08-27 | 2018-12-25 | 电子科技大学 | A kind of trench grate MOS control thyristor and preparation method thereof |
| CN109087946B (en) * | 2018-08-27 | 2021-03-16 | 电子科技大学 | Trench gate MOS control thyristor and manufacturing method thereof |
| CN110212027A (en) * | 2019-06-10 | 2019-09-06 | 西安理工大学 | Electron injection enhancement type double mode MOS controls thyristor and its manufacturing method |
| CN110212027B (en) * | 2019-06-10 | 2022-04-22 | 西安理工大学 | Electron injection enhanced dual-mode MOS control thyristor and manufacturing method thereof |
| CN111933715A (en) * | 2020-09-25 | 2020-11-13 | 电子科技大学 | Silicon carbide MOSFET device |
| CN112382568A (en) * | 2020-10-26 | 2021-02-19 | 西安理工大学 | Manufacturing method of MOS control thyristor |
| CN112382568B (en) * | 2020-10-26 | 2023-10-10 | 西安理工大学 | Manufacturing method of MOS control thyristor |
| CN114613849A (en) * | 2022-05-10 | 2022-06-10 | 深圳市威兆半导体有限公司 | Silicon carbide MOS device for improving short circuit characteristic |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1045139C (en) | 1999-09-15 |
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