JPH0624244B2 - Composite semiconductor device - Google Patents
Composite semiconductor deviceInfo
- Publication number
- JPH0624244B2 JPH0624244B2 JP62145091A JP14509187A JPH0624244B2 JP H0624244 B2 JPH0624244 B2 JP H0624244B2 JP 62145091 A JP62145091 A JP 62145091A JP 14509187 A JP14509187 A JP 14509187A JP H0624244 B2 JPH0624244 B2 JP H0624244B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor region
- semiconductor
- region
- adjacent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 36
- 239000002131 composite material Substances 0.000 title claims description 9
- 239000012535 impurity Substances 0.000 claims 4
- 239000004020 conductor Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
- H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ＭＯＳゲートでオン・オフできるサイリスタ
に係わり、特にその高速化，作り易さに好適な構造に関
る。The present invention relates to a thyristor that can be turned on / off by a MOS gate, and more particularly to a structure suitable for speeding up and easy fabrication.
従来、ＭＯＳゲートでオン・・オフできるサイリスタに
ついては、アイ・イー・イー・イー，トランザクシヨン
ズ オン エレクトロン デバイシズ，イーデイー−３
３，（１９８６年）、第1609頁から第１６１頁（ＩＥＥ
Ｅ，Transactions on Electron Devices,Vol.ＥＤ−３
３，（１９８６）pp１６０９〜１６１８）において論じ
られている。第５図は上記論文のＦig．５に記載されて
いる従来例を示す。この複合半導体装置５には例えばｐ
+基板１１上にｎ-層１２が形成されている。さらにｎ-
層１２内にｐ層１６，ｐ層１６内にｎ+層１７，ｎ+層１
７内にｐ+層１８が、そして表面に露出しているｎ-１２
を挟んでｐ+層１８と別のｐ+層１８の間にＭＯＳゲート
が形成されている。ＭＯＳゲートはゲート電極２３と絶
縁膜３１からなる。ｎ+層１７とｐ+層１８はカソード電
極２２で短絡され、もう一方の主表面にはアノード電極
２１０が低抵抗接触している。For conventional thyristors that can be turned on and off with MOS gates, see IEE, Transactions on Electron Devices, Eday-3.
3, (1986), pp. 1609 to 161 (IEEE)
E, Transactions on Electron Devices, Vol.ED-3
3, (1986) pp 1609-1618). FIG. 5 shows FIG. The conventional example described in No. 5 is shown. The composite semiconductor device 5 has, for example, p
+ An n − layer 12 is formed on the substrate 11. Furthermore, n -
P layer 16 in the layer 12, n + layer 17 in the p layer 16, n + layer 1
P + layer 18 in 7 and exposed at the surface n - 12
A MOS gate is formed between the p + layer 18 and another p + layer 18 with the gate sandwiched therebetween. The MOS gate is composed of the gate electrode 23 and the insulating film 31. N + layer 17 and p + layer 18 are short-circuited by cathode electrode 22, and anode electrode 210 is in low resistance contact with the other main surface.
このような複合半導体装置５をオン状態にするには例え
ばカソード電極２２をＯＶとし、ゲート電極２３を正の
電位にすれば良い。これにより、ｎ+層１７，ｐ層１
６，ｎ-層１２からなるｎチヤンネルMOSFETが動作し、
カソード電極２２からｎ-層１２へ電子が流れる。こ
の電子がｐ+層１１（ｐエミツタ層），ｎ-層１２（ｎ
ベース層），ｐ層１６（ｐベース），ｎ+層１７（ｎエ
ミツタ層）からなるｐｎｐｎ構造のサイリスタのベース
電流となり、ｐ+層１１（ｐエミツタ層）からホール
の注入、さらにこのホールがｎ＋層１７（ｎエミツタ
層）から電子の注入を促す結果、上記サイリスタが点
弧し、装置５はオフ状態となる。一方、この装置５をオ
フ状態に移行させるには、ゲート電極２３を負の電位に
する。その結果、ｐ+層１８，ｎ+層１７，ｐ層１６から
なるｐチヤンネルMOSFET が動き、ｐ層１６はｎ＋層１
７に所謂エミツタ短絡され、ｎ＋エミツタ層１７からの
電子の注入がなくなる。加えて短絡されたことにより、
ｐベース層１６及びｎ−ベース層１２に蓄積された過剰
キヤリアがカソード電極２２へ引き出され、装置５はタ
ーンオフする。To turn on such a composite semiconductor device 5, for example, the cathode electrode 22 may be set to OV and the gate electrode 23 may be set to a positive potential. As a result, the n + layer 17 and the p layer 1
N channel MOSFET composed of 6, n − layer 12 operates,
Electrons flow from the cathode electrode 22 to the n − layer 12. These electrons are p + layer 11 (p emitter layer), n − layer 12 (n
It becomes the base current of the pnpn structure thyristor composed of the base layer), the p layer 16 (p base), and the n + layer 17 (n emitter layer), and the holes are injected from the p + layer 11 (p emitter layer). As a result of promoting injection of electrons from the n + layer 17 (n emitter layer), the thyristor is ignited and the device 5 is turned off. On the other hand, in order to shift the device 5 to the off state, the gate electrode 23 is set to a negative potential. As a result, the p-channel MOSFET composed of the p + layer 18, the n + layer 17, and the p layer 16 moves, and the p layer 16 becomes the n + layer 1.
7 is a so-called emitter short circuit, and the injection of electrons from the n + emitter layer 17 is eliminated. In addition, due to the short circuit,
The excess carriers accumulated in the p base layer 16 and the n − base layer 12 are drawn to the cathode electrode 22, and the device 5 is turned off.
しかし上記半導体装置５は、ｐｎｐｎｐと５層構造と複
雑で、さらにｎ＋エミツタ層１７にｐチヤンネル層を形
成するためMOSFETのしきい値電圧が高くなり、引いては
チヤンネル抵抗が大きくなる結果、過剰キヤリアの引出
しが妨げられターンオフ速度が大きくなるという問題が
あつた。これを解決するためゲートで電極２３下の部分
のｎ＋層１７だけを低濃度にする方法も検討されている
が、益々製作工程が煩雑化する欠点があつた。However, the semiconductor device 5 has a complicated structure of pnpnp and a five-layer structure, and since the p channel layer is formed in the n + emitter layer 17, the threshold voltage of the MOSFET becomes high, which in turn increases the channel resistance. There was a problem that the turn-off speed was increased because the withdrawal of the carrier was blocked. In order to solve this, a method of reducing the concentration of only the n + layer 17 under the electrode 23 in the gate has been studied, but it has a drawback that the manufacturing process becomes more complicated.
本発明の目的は、作り易くしかも高速化に好適な複合半
導体装置を提供することにある。An object of the present invention is to provide a composite semiconductor device which is easy to manufacture and is suitable for high speed operation.
上記目的は、例えば５層のｐｎｐｎｐ構造を４層のｐｎ
ｐｎ構造とし、さらにｐベース層とｎ-層と新たなｐ層
によりｐチヤンネルMOSFETを形成することにより達成さ
れる。For the above-mentioned purpose, for example, a pnpnp structure of 5 layers is changed to a pnpn structure of 4 layers.
This is achieved by forming a p-channel structure and further forming a p-channel MOSFET with a p-base layer, an n − layer and a new p-layer.
また、上記導電型のｐ型，ｎ型を逆にしてもよい。Also, the conductivity types of p-type and n-type may be reversed.
本発明の複合半導体装置は、５層構造を４層構造とする
ことによつて作り易くすると同時に、ｐチヤンネル領域
にｎ−層を用いているのでしきい値電圧が下がる結果チ
ヤンネル抵抗が小さくなり、過剰キヤリアが引き出し易
くなるので、高速にターンオフする。The composite semiconductor device of the present invention is made easier by making the five-layer structure into the four-layer structure, and at the same time, since the n − layer is used in the p-channel region, the threshold voltage is lowered and the channel resistance is reduced. , Turn off at high speed because excess carriers can be pulled out easily.
以下、本発明の一実施例を第１図により説明する。本発
明の複合半導体装置１には、例えばｐ+基板１１上にｎ-
層１２，ｐ層１３，ｎ+層１５が形成されている。さら
にｐ層１３とは独立にｐ層１４が形成され、ｎ+層１
５，ｐ層１３，ｎ-層１２，ｐ層１４をまたがつて表面
にＭＯＳゲートが作られている。ｎ＋層１５とｐ層１４
４はカソード電極２２で短絡されている。一方、ｐ＋層
２１はアノード電極２１に低抵抗接触している。この装
置１をオン状態にするには、従来と同様にゲート電極２
３に正の電位を加える。これにより、ｎ-層１２，ｐ層
１３，ｎ+層１５からなるｎチヤンネルMOSFET が動作
し、電子がｎ-層１２に流れる。この電子がベース
電流となり、ｐ＋層１１，ｎ-層１２，ｐ層１３，ｎ+層
１５からなるｐｎｐｎ構造のサイリスタが点弧し、オン
状態となる。オフ状態へ移行させるにはゲート電極２３
に負の電位を加える。ｐ層１３，ｎ-層１２，ｐ層１４
からなるｐチヤンネルMOSFET が動作し、ｎ+エミツタ層
とｐ層１３が短絡され、ｎ＋エミツタ層１５からの電子
の注入がなくなる。さらに、ｐ層１３及びｎ−層に蓄
積された過剰キヤリアがｐ層１４よりカソード電極２２
へ引き出され装置２はターンオフする。An embodiment of the present invention will be described below with reference to FIG. The composite semiconductor device 1 of the present invention has, for example, n − on the p + substrate 11.
A layer 12, a p layer 13, and an n + layer 15 are formed. Further, the p layer 14 is formed independently of the p layer 13, and the n + layer 1
5, a MOS gate is formed on the surface across the p layer 13, the n − layer 12, and the p layer 14. n + layer 15 and p layer 14
4 is short-circuited by the cathode electrode 22. On the other hand, the p + layer 21 is in low resistance contact with the anode electrode 21. In order to turn on this device 1, the gate electrode 2
Apply a positive potential to 3. As a result, the n-channel MOSFET composed of the n − layer 12, the p layer 13, and the n + layer 15 operates, and electrons flow into the n − layer 12. The electrons serve as a base current, and a thyristor having a pnpn structure composed of the p + layer 11, the n − layer 12, the p layer 13, and the n + layer 15 is ignited and turned on. To shift to the off state, the gate electrode 23
Apply a negative potential to. p layer 13, n − layer 12, p layer 14
The p-channel MOSFET composed of is operated, the n + emitter layer and the p layer 13 are short-circuited, and electrons are not injected from the n + emitter layer 15. Further, the excess carriers accumulated in the p layer 13 and the n − layer are more likely to be absorbed by the cathode electrode 22 than the p layer 14.
Device 2 is turned off.
本実施例によれば、ｐｎｐｎの４層で従来の５層の装置
と同機能をもたせることができ、製作が容易になる。さ
らにｐチヤンネルMOSFETのチヤンネル層となるｎ−層１
２のキヤリア濃度を低くできるため、従来のｎ＋層１７
に比べしきい値電圧を低くできる結果、チヤンネル抵抗
が小さくなり、過剰キヤリアを引き出し易くなる。これ
により高速にターンオフする。さらに−層１２に蓄積さ
れた過剰キヤリアをｐチヤンネルを通過させることな
く、直接ｐ層１４へ引き出せることも高速にターンオフ
する要因となつている。本発明者等が検討した結果従来
より約２倍に高速化することができた。According to the present embodiment, four layers of pnpn can have the same function as a conventional five-layer device, which facilitates manufacturing. Further, n − layer 1 which becomes a channel layer of p channel MOSFET
Since the carrier concentration of 2 can be lowered, the conventional n + layer 17
As a result, the threshold voltage can be made lower than that of the above, and as a result, the channel resistance becomes small and the excess carrier is easily drawn. This turns off at high speed. Furthermore - the accumulated excess carriers in the layer 12 without passing through the p channel, and summer and Sources also be turned off at high speed to draw directly p layer 14. As a result of examination by the present inventors, the speed could be increased to about twice that of the conventional one.
第２図は本発明の変形例を示す。第１図と異なる点は、
ｐ+層１１とｎ-層１２の間にｎ層１２０を、ｎ+層１５
とｐ層１３の間にｐ+層１３０、さらにｐ層１４内に＋
層を設けた点である。ｎ層１２０に設けることにより、
ｐ層１３・ｎ−層１２接合に生じる空乏層がｐ＋層１１
に到達しリーチスルーするのを防ぐことができ、耐圧を
向上させることができる。したがつて同じ耐圧であれ
ば、ｎ層１２０を設けることにより、ｎ−層を薄くで
き、動作抵抗を小さくできる結果、大電流化が可能とな
る。さらに、ｐ+層１３０，１４０を設けることによ
り、ｐチヤンネルMOSFETの寄生抵抗が小さくなり高速化
できる。また、ｐ＋層１３０でｎ＋層１５からの電子の
注入効率を適度に制御することにより、この装置２の耐
圧をｐ層１３・ｎ−層１２・ｎ層１２０で決まる耐圧ま
で高めることができ、負のゲート電圧を加えなくても所
謂ノーマルオフの装置とすることが可能となる。FIG. 2 shows a modification of the present invention. The difference from Fig. 1 is that
An n layer 120 is provided between the p + layer 11 and the n − layer 12, and an n + layer 15
Between the p layer 13 and the p layer 13 and + in the p layer 14
The point is that layers are provided. By providing the n layer 120,
The depletion layer generated at the junction of the p layer 13 and the n − layer 12 is the p + layer 11
It is possible to prevent the reaching and reaching through and to improve the breakdown voltage. Therefore, if the withstand voltage is the same, by providing the n layer 120, the n − layer can be thinned and the operating resistance can be reduced, so that a large current can be obtained. Further, by providing the p + layers 130 and 140, the parasitic resistance of the p-channel MOSFET is reduced and the speed can be increased. By appropriately controlling the electron injection efficiency from the n + layer 15 by the p + layer 130, the breakdown voltage of the device 2 can be increased to the breakdown voltage determined by the p layer 13, n − layer 12, and n layer 120. A so-called normal-off device can be realized without applying a negative gate voltage.
図中の符号で、第１図と同一符号の部分は、同一部分又
は同等部分を示す。In the figure, the same reference numerals as those in FIG. 1 indicate the same or equivalent portions.
第３図は本発明の一変形例でｐ+層１１０とｎ+層１１１
がアノード電極に低抵抗接触している。これによりｎ−
層に蓄積された過剰キヤリアのホールをｐ層１４へ引き
出すだけでなく、電子をｎ＋層１１１を通じてアノード
電極２１へ引き出すことができる結果、装置３はより高
速にターンオフする。もちろん、第２図の特長を第３図
に適用することは言うまでもない。FIG. 3 shows a modification of the present invention in which p + layer 110 and n + layer 111 are provided.
Has low resistance contact with the anode electrode. As a result, n −
Not only can excess carrier holes accumulated in the layer be drawn to the p-layer 14, but electrons can also be drawn to the anode electrode 21 through the n + layer 111, resulting in faster turn-off of the device 3. Of course, it goes without saying that the features of FIG. 2 are applied to FIG.
第４図は本発明を横形装置に適用した一応用例を示す。
本応用例では、支持体４１内に絶縁膜３２を介してｐ＋
層１１が形成されている。アノード電極２１はカソード
電極２２と同一表面に形成されている。このような構造
とすることにより、ＩＣ等の集積回路にも応用できる。FIG. 4 shows an application example in which the present invention is applied to a horizontal device.
In this application example, p + is formed in the support body 41 via the insulating film 32.
The layer 11 is formed. The anode electrode 21 is formed on the same surface as the cathode electrode 22. With such a structure, it can be applied to an integrated circuit such as an IC.
第４図および第５図の図中の符号で、第１図と同一部号
の部分は、同一部分又は同等部分を示す。Reference numerals in FIGS. 4 and 5 that are the same as those in FIG. 1 indicate the same or equivalent portions.
以上、本発明の説明したｐ層とｎ層を逆にした場合にも
同様の効果があることは言うまでもない。Needless to say, the same effect can be obtained when the p layer and the n layer described in the present invention are reversed.
本発明によれば、従来の５層構造をｐｎｐｎの４層構造
にできるので製作が容易になるとともに、エミツタの短
絡抵抗が小さくできるので高速のターンオフが可能とな
る。According to the present invention, the conventional five-layer structure can be changed to a pnpn four-layer structure, which facilitates the manufacture. Further, since the short-circuit resistance of the emitter can be reduced, high-speed turn-off is possible.
第１図は本発明の一実施例の断面図、第２図と第３図は
本発明の変形例の断面図、第４図は本発明の応用例の断
面図、第５図は従来例の断面図である。 １１……ｐ+層、１２……ｎ-層、１３，１４……ｐ層、
１５……ｎ+層、２１……アノード電極、２２……カソ
ード電極、２３……ＭＯＳゲート電極。FIG. 1 is a sectional view of an embodiment of the present invention, FIGS. 2 and 3 are sectional views of a modification of the present invention, FIG. 4 is a sectional view of an application example of the present invention, and FIG. 5 is a conventional example. FIG. 11 ... p + layer, 12 ... n - layer, 13,14 ... p layer,
15 ... N + layer, 21 ... Anode electrode, 22 ... Cathode electrode, 23 ... MOS gate electrode.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 中野 安紀 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (56)参考文献 特開 昭57−43461（ＪＰ，Ａ) 特開 昭57−120369（ＪＰ，Ａ) 特開 昭58−108723（ＪＰ，Ａ) 特開 昭63−209172（ＪＰ，Ａ) 特開 昭60−164359（ＪＰ，Ａ) 特開 昭62−21273（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuki Nakano 4026, Kuji-machi, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-57-43461 (JP, A) JP-A-57 -120369 (JP, A) JP 58-108723 (JP, A) JP 63-209172 (JP, A) JP 60-164359 (JP, A) JP 62-21273 (JP, A) )
Claims (3)
純物濃度を有する他方導電型の第２の半導体領域と、 第２の半導体領域表面から内部に延び、第２の半導体領
域より高不純物濃度を有する複数個の一方導電型の第３
の半導体領域と、 複数個の第３の半導体領域のうち隣接する領域の一方側
に表面から内部に延び、第３の半導体領域より高不純物
濃度を有する他方導電型の第４の半導体領域と、 第１の半導体領域表面に低抵抗接触する第１の主電極
と、 隣接する第３の半導体領域のうちの一方側に形成された
第４の半導体領域表面のみ及び他方側の第３の半導体領
域表面のみに低抵抗接触する第２の主電極と、 隣接する第３の半導体領域のうち一方側に形成された第
４の半導体領域表面から一方側の第３の半導体領域表面
及び第２の半導体領域表面を経て他方側の第３の半導体
表面上にゲート絶縁膜を介して形成されたゲート電極と
を具備し、 第１の主電極と第２の主電極との間をオフ状態からオン
状態に移行させる場合、ゲート電極にその下の第３の半
導体領域表面にチャネルを形成するに十分な電位が付与
され、オン状態からオフ状態に移行させる場合、ゲート
電極にその下の第２の半導体領域表面にチャネルを形成
するに十分な電位が付与されることを特徴とする複合半
導体装置。1. A first semiconductor region of one conductivity type, a second semiconductor region of the other conductivity type, which is adjacent to the first semiconductor region and has a lower impurity concentration than that of the first semiconductor region, A plurality of third one-conductivity-type thirds extending inward from the surface of the semiconductor region and having a higher impurity concentration than the second semiconductor region.
A semiconductor region, and a fourth semiconductor region of the other conductivity type that extends inward from the surface to one side of an adjacent region of the plurality of third semiconductor regions and has a higher impurity concentration than the third semiconductor region, A first main electrode in low-resistance contact with the surface of the first semiconductor region, only a surface of a fourth semiconductor region formed on one side of an adjacent third semiconductor region, and a third semiconductor region on the other side A second main electrode that makes low-resistance contact only with the surface, and a third semiconductor region surface and a second semiconductor region on one side from a fourth semiconductor region surface formed on one side of an adjacent third semiconductor region. A gate electrode formed on the other side of the third semiconductor surface via a gate insulating film via the region surface, and between the first main electrode and the second main electrode is in an off state to an on state. When the gate electrode is moved to the third A potential sufficient to form a channel is applied to the surface of the conductor region, and when transitioning from the on state to the off state, a potential sufficient to form a channel on the surface of the second semiconductor region below the gate electrode is applied. A composite semiconductor device characterized by the following.
導体領域が第１の半導体領域に隣接する第１の部分と、
第３の半導体領域に隣接し第１の部分より低不純物濃度
を有する第２の部分とから構成されていることを特徴と
する複合半導体装置。2. The first semiconductor region according to claim 1, wherein the second semiconductor region is adjacent to the first semiconductor region,
A composite semiconductor device comprising: a second portion adjacent to the third semiconductor region and having a lower impurity concentration than the first portion.
電極が第１の半導体領域表面及び第２の半導体領域表面
に低抵抗接触していることを特徴とする複合半導体装
置。3. The composite semiconductor device according to claim 1, wherein the first main electrode is in low resistance contact with the surface of the first semiconductor region and the surface of the second semiconductor region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62145091A JPH0624244B2 (en) | 1987-06-12 | 1987-06-12 | Composite semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62145091A JPH0624244B2 (en) | 1987-06-12 | 1987-06-12 | Composite semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63310171A JPS63310171A (en) | 1988-12-19 |
| JPH0624244B2 true JPH0624244B2 (en) | 1994-03-30 |
Family
ID=15377171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62145091A Expired - Lifetime JPH0624244B2 (en) | 1987-06-12 | 1987-06-12 | Composite semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0624244B2 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2738071B2 (en) * | 1989-10-23 | 1998-04-08 | 富士電機株式会社 | MOS control thyristor |
| EP0438700A1 (en) * | 1990-01-25 | 1991-07-31 | Asea Brown Boveri Ag | Turn-off MOS-controlled power semiconductor device and method of making the same |
| JP2597412B2 (en) * | 1990-03-20 | 1997-04-09 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| US5099300A (en) * | 1990-06-14 | 1992-03-24 | North Carolina State University | Gated base controlled thyristor |
| JPH0795597B2 (en) * | 1990-08-18 | 1995-10-11 | 三菱電機株式会社 | Thyristor and manufacturing method thereof |
| EP0507974B1 (en) * | 1991-04-11 | 1995-12-20 | Asea Brown Boveri Ag | MOS-gated turn-off power semiconductor device |
| US5223732A (en) * | 1991-05-28 | 1993-06-29 | Motorola, Inc. | Insulated gate semiconductor device with reduced based-to-source electrode short |
| EP0540017B1 (en) * | 1991-10-31 | 1997-12-29 | Kabushiki Kaisha Toshiba | MOS gate controlled thyristor |
| US5225702A (en) * | 1991-12-05 | 1993-07-06 | Texas Instruments Incorporated | Silicon controlled rectifier structure for electrostatic discharge protection |
| JP2739002B2 (en) * | 1991-12-20 | 1998-04-08 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP2793925B2 (en) * | 1992-01-14 | 1998-09-03 | 松下電工株式会社 | Thyristor with control gate |
| JP2818348B2 (en) * | 1993-03-01 | 1998-10-30 | 株式会社東芝 | Semiconductor device |
| US5498884A (en) * | 1994-06-24 | 1996-03-12 | International Rectifier Corporation | MOS-controlled thyristor with current saturation characteristics |
| US5444272A (en) * | 1994-07-28 | 1995-08-22 | International Rectifier Corporation | Three-terminal thyristor with single MOS-gate controlled characteristics |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3024015A1 (en) * | 1980-06-26 | 1982-01-07 | Siemens AG, 1000 Berlin und 8000 München | CONTROLLABLE SEMICONDUCTOR SWITCH |
| SE8107136L (en) * | 1980-12-02 | 1982-06-03 | Gen Electric | STEERING ELECTRICAL EQUIPMENT |
| IE53895B1 (en) * | 1981-11-23 | 1989-04-12 | Gen Electric | Semiconductor device having rapid removal of majority carriers from an active base region thereof at device turn-off and method of fabricating this device |
| JP2557367B2 (en) * | 1987-02-26 | 1996-11-27 | 株式会社東芝 | Insulated gate type self turn-off thyristor |
-
1987
- 1987-06-12 JP JP62145091A patent/JPH0624244B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63310171A (en) | 1988-12-19 |
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