CN111933715A - Silicon carbide MOSFET device - Google Patents
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- CN111933715A CN111933715A CN202011022081.7A CN202011022081A CN111933715A CN 111933715 A CN111933715 A CN 111933715A CN 202011022081 A CN202011022081 A CN 202011022081A CN 111933715 A CN111933715 A CN 111933715A
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 31
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 2
- 229910052906 cristobalite Inorganic materials 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 229910052682 stishovite Inorganic materials 0.000 claims description 2
- 229910052905 tridymite Inorganic materials 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 6
- 230000005669 field effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
Abstract
The present invention provides a silicon carbide MOSFET device comprising: the device comprises an N-type substrate, an N-type epitaxial layer, a P-body area, an N + contact area, a P + contact area, a source electrode, a gate dielectric and a drain electrode; when the device is in short circuit, the JFET region formed by the P-body region and the P + contact region and the adjacent P + contact region are clamped off in advance, and when the current of the device is increased, the effective grid-source voltage of the silicon carbide MOSFET is reduced due to the constant grid-source voltage and the effect of the JEFT region, so that the saturation current passing through the MOSFET device is reduced, negative feedback is formed, the saturation current of the device is greatly reduced compared with the conventional structure, and the short circuit resistance of the device is improved.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and comprises a normally-on Junction Field Effect Transistor (JFET) and an insulated gate field effect transistor (MOSFET), wherein the MOSFET and the JFET are connected in series.
Background
Silicon Carbide (SiC) material, which is one of the representative third-generation wide bandgap semiconductor materials, has a wide bandgap (3.26eV) and a high critical electric field (3 × 10)6V·cm-1) High carrier saturation drift velocity (2 x 10)7cm·s-1) High thermal conductivity (W.cm)-1·K-1) The method has the advantages of being an ideal material for preparing high-voltage and ultrahigh-voltage power electronic devices, and having wide application prospect in the fields of high-power, high-temperature, high-voltage and anti-irradiation power electronics.
MOSFET devices are one of the most widely used gate-controlled device structures in silicon carbide power devices. Because the silicon carbide MOSFET device is characterized by a unipolar transport working mechanism, only one carrier of electrons or holes conducts electricity, and no charge storage effect exists, compared with a bipolar device, the silicon carbide MOSFET device has lower switching loss and higher frequency characteristic, and the silicon carbide MOSFET device becomes a new generation of competitive low-loss power device due to the low on-resistance and excellent high-temperature characteristic.
Silicon carbide MOSFET applications are commonly used to control power control from an input stage to an output stage, for example in AC/AC converters, AC/DC converters, DC/AC converters. In a typical converter topology, a short circuit condition on the load side will cause the silicon carbide MOSFET to go into a short circuit condition. When a short circuit occurs in the circuit, the power supply voltage is completely loaded at two ends of the device, and the device is still in a conducting state at the moment, so that a large drain-source current can be generated. This operating state is generally only terminated after the gate drive senses and turns off the device in time. The short circuit detection circuit can detect a short circuit condition and, when a short circuit occurs in the power circuit, can monitor and feed back to the gate drive of the power semiconductor device or/and activate a circuit breaker in the circuit to protect the safe operation of the entire power electronics device. If the device gate drive cannot detect and successfully turn off the device in time, the device may be damaged, causing the entire power electronic device to fail or even burn out.
In the industry's short-circuit capability of Si IGBTs, it is generally desirable that silicon carbide MOSFETs be able to withstand short-circuit capabilities of greater than 10 μ s, thereby allowing greater design margins for the corresponding protection circuitry. At present, because the area of a silicon carbide MOSFET chip is small, the saturation current density is high, large power density is generated instantaneously, and the temperature of a device is increased sharply by heat accumulated instantaneously, and finally the device is burnt out and fails. Thus, commercial silicon carbide MOSFETs generally have short circuit withstand times less than desired (typically 3-6 μ s). In order to overcome the problem, the saturation current of the device is reduced by optimizing the design structure under the condition of ensuring that the static parameters are not obviously degraded, so that the heat accumulation in the short-circuit process is relieved, the short-circuit tolerance capacity is improved, and the safe and reliable operation capacity of the power electronic device is improved.
Disclosure of Invention
The invention aims to provide a planar silicon carbide MOSFET device with improved short-circuit tolerance, wherein a JFET device is integrated on a source electrode, so that the MOSFET and the JFET are connected in series. When the device is in a short circuit state, the device is in a high-voltage large-current state, when saturated short-circuit current flows through the device, the integrated JFET is pinched off, and as the grid-source voltage is kept constant, the JEFT action can reduce the effective grid-source voltage of the silicon carbide MOSFET, so that the saturation current passing through the MOSFET device is reduced, negative feedback is formed, the saturation current of the device is reduced, the short-circuit capacity of the device is improved, and the reliability of the device is further improved.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a silicon carbide MOSFET device comprises an N-type substrate 9, an N-type epitaxial layer 8 positioned above the N-type substrate 9, a P-body region 7 positioned above the inner part of the N-type epitaxial layer 8, an N-body region 6 positioned above the inner part of the P-body region 7, N + contact regions 5 and P + contact regions 4 which are alternately arranged above the inner part of the N-body region 6, a gate medium 3 positioned above the N-type epitaxial layer 8, the P-body region 7 and the N-body region 6, a gate electrode 2 positioned above the gate medium 3, a source electrode 1 positioned above the N + contact regions 5 and the P + contact regions 4, and a drain electrode 10 positioned below the device and forming ohmic contact with the N-type substrate 9; the source electrode 1 is in ohmic contact with the N + contact region 5 and the P + contact region 4.
Preferably, the N + contact regions 5 and the P + contact regions 4 are alternately arranged in the gate width direction X.
Preferably, the N + contact regions 5 and the P + contact regions 4 are alternately arranged in the gate length direction Y.
The present invention also provides a second silicon carbide MOSFET device comprising: the semiconductor device comprises an N-type substrate 9, an N-type epitaxial layer 8 located above the N-type substrate 9, a P-body region 7 located above the inner portion of the N-type epitaxial layer 8, a low-doped N-body region 6 located above the P-body region 7, an N + contact region 5 and a P + contact region 4 located above the inner portion of the N-body region 6, the N + contact region 5 and the P + contact region 4 are in contact, a gate medium 3 located above the N-type epitaxial layer 8, the P-body region 7 and the N-body region 6, a gate electrode 2 located above the gate medium 3, a source electrode 1 located above the N + contact region 5 and the P + contact region 4, and a drain electrode 10 located below the device and forming ohmic contact with the N-type substrate 9.
Preferably, the gate dielectric 3 is SiO2。
Preferably, the N-type substrate 9 is doped P-type.
Preferably, each doping type in the device is correspondingly changed into opposite doping, namely, the P-type doping is changed into the N-type doping, and meanwhile, the N-type doping is changed into the P-type doping.
The material used by the device is SiC material, and can also be other semiconductor materials.
The invention has the beneficial effects that: 1: when the SiC MOSFET device provided by the invention is in short circuit, the JFET area formed by the P-body area and the P + contact area and the adjacent P + contact area are clamped off in advance, the saturation current of the device is greatly reduced, and the short circuit resistance of the device is improved.
Drawings
FIG. 1 is a diagram of a conventional SiC planar gate MOSFET device structure;
FIG. 2 is a structural view of a device of example 1 of the present invention;
FIG. 3 is a structural view of a device of embodiment 2 of the present invention;
FIG. 4A is a perspective view of a device in accordance with embodiment 3 of the present invention;
FIG. 4B is a sectional view of embodiment 3 taken along the front view direction and with the P + contact region 4 on the inside of the N-body region 6;
FIG. 4C is a sectional view of embodiment 3 of the present invention taken along the front view direction and with the N + contact region 5 on the inside of the N-body region 6;
1 is a source electrode, 2 is a gate electrode, 3 is a gate dielectric, 4 is a P + contact region, 5 is an N + contact region, 6 is an N-body region, 7 is a P-body region, 8 is an N-type epitaxial layer, 9 is an N-type substrate, and 10 is a drain electrode.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
As shown in fig. 2, a silicon carbide MOSFET device of the present embodiment includes: an N-type substrate 9, an N-type epitaxial layer 8 positioned above the N-type substrate 9, a P-body region 7 positioned above the inner part of the N-type epitaxial layer 8, an N-body region 6 positioned above the inner part of the P-body region 7, N + contact regions 5 and P + contact regions 4 which are alternately arranged above the inner part of the N-body region 6, a gate medium 3 positioned above the N-type epitaxial layer 8, the P-body region 7 and the N-body region 6, a gate electrode 2 positioned above the gate medium 3, a source electrode 1 positioned above the N + contact regions 5 and the P + contact regions 4, and a drain electrode 10 positioned below the device and forming ohmic contact with the N-type substrate 9; the source electrode 1 is in ohmic contact with the N + contact region 5 and the P + contact region 4. The N + contact regions 5 and the P + contact regions 4 are alternately arranged in the gate width direction X.
The working principle of the embodiment is as follows:
when the device works in a blocking state, a PN junction formed by the P-body region 7 and the N-type epitaxial layer 8 enables the device to bear high voltage; when the device is operated in the on-state, the forward biased gate electrode 2 induces a conductive channel at the interface of the P-body region 7 and the gate dielectric 3. When the device is in a short circuit state, the P-body region 7 and the P + contact region 4 form a JFET effect in the N-body region 6, thereby rapidly pinching off the conduction path, and the effective gate-source voltage of the designed silicon carbide MOSFET decreases because the gate-source voltage remains constant. By properly adjusting the doping concentration and size of the N-body region 6, the spacing between the N + contact region 5 and the P + contact region 4, etc., the saturation current of the silicon carbide MOSFET can be reduced, thereby improving the short circuit endurance of the device.
Example 2
As shown in fig. 3, a silicon carbide MOSFET device of the present embodiment includes: the semiconductor device comprises an N-type substrate 9, an N-type epitaxial layer 8 located above the N-type substrate 9, a P-body region 7 located above the inner portion of the N-type epitaxial layer 8, a low-doped N-body region 6 located above the P-body region 7, an N + contact region 5 and a P + contact region 4 located above the inner portion of the N-body region 6, the N + contact region 5 and the P + contact region 4 are in contact, a gate medium 3 located above the N-type epitaxial layer 8, the P-body region 7 and the N-body region 6, a gate electrode 2 located above the gate medium 3, a source electrode 1 located above the N + contact region 5 and the P + contact region 4, and a drain electrode 10 located below the device and forming ohmic contact with the N-type substrate 9.
Example 3
As shown in fig. 4A, the N + contact regions 5 and the P + contact regions 4 are alternately arranged in the gate length direction Y. FIG. 4B is a sectional view of embodiment 3 with a P + contact region 4 on the inside of the N-body region 6 in a front view, and FIG. 4C is a sectional view of embodiment 3 with an N + contact region 5 on the inside of the N-body region 6 in a front view.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (7)
1. A silicon carbide MOSFET device, comprising: the semiconductor device comprises an N-type substrate (9), an N-type epitaxial layer (8) positioned above the N-type substrate (9), a P-body region (7) positioned above the inner part of the N-type epitaxial layer (8), an N-body region (6) positioned above the inner part of the P-body region (7), N + contact regions (5) and P + contact regions (4) which are alternately arranged above the inner part of the N-body region (6), a gate medium (3) positioned above the N-type epitaxial layer (8), the P-body region (7) and the N-body region (6), a gate electrode (2) positioned above the gate medium (3), a source electrode (1) positioned above the N + contact region (5) and the P + contact region (4), and a drain electrode (10) positioned below the device and forming ohmic contact with the N-type substrate (9); the source electrode (1) is in ohmic contact with the N + contact region (5) and the P + contact region (4).
2. A silicon carbide MOSFET device as claimed in claim 1 wherein: the N + contact regions (5) and the P + contact regions (4) are alternately arranged in the gate width direction X.
3. A silicon carbide MOSFET device as claimed in claim 1 wherein: the N + contact regions (5) and the P + contact regions (4) are alternately arranged along the gate length direction Y.
4. A silicon carbide MOSFET device, comprising: the semiconductor device comprises an N-type substrate (9), an N-type epitaxial layer (8) located above the N-type substrate (9), a P-body region (7) located above the inner portion of the N-type epitaxial layer (8), a low-doped N-body region (6) located above the P-body region (7), an N + contact region (5) and a P + contact region (4) located above the inner portion of the N-body region (6), the N + contact region (5) is in contact with the P + contact region (4), a gate dielectric (3) located above the N-type epitaxial layer (8), the P-body region (7) and the N-body region (6), a gate electrode (2) located above the gate dielectric (3), a source electrode (1) located above the N + contact region (5) and the P + contact region (4), and a drain electrode (10) located below the device and forming ohmic contact with the N-type substrate (9).
5. A silicon carbide MOS according to any one of claims 1 to 4An FET device, characterized by: the gate dielectric (3) is SiO2。
6. A silicon carbide MOSFET device according to any one of claims 1 to 5, wherein: the N-type substrate (9) becomes P-type doped.
7. A silicon carbide MOSFET device according to any one of claims 1 to 6, wherein: the doping types in the device are correspondingly changed into opposite doping, namely P-type doping is changed into N-type doping, and simultaneously N-type doping is changed into P-type doping.
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| CN202011022081.7A CN111933715A (en) | 2020-09-25 | 2020-09-25 | Silicon carbide MOSFET device |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5319221A (en) * | 1991-09-24 | 1994-06-07 | Fuji Electric Co., Ltd. | Semiconductor device with MISFET-controlled thyristor |
| US5324966A (en) * | 1992-04-07 | 1994-06-28 | Toyo Denki Seizo Kabushiki Kaisha | MOS-controlled thyristor |
| US5329142A (en) * | 1991-08-08 | 1994-07-12 | Kabushiki Kaisha Toshiba | Self turn-off insulated-gate power semiconductor device with injection-enhanced transistor structure |
| CN1144975A (en) * | 1996-04-23 | 1997-03-12 | 西安电子科技大学 | Grid-controlled transistor |
| CN101478002A (en) * | 2008-11-27 | 2009-07-08 | 电子科技大学 | Thyristor controlled by accumulation layer |
| CN110634944A (en) * | 2018-06-22 | 2019-12-31 | 英飞凌科技股份有限公司 | Silicon carbide semiconductor device |
-
2020
- 2020-09-25 CN CN202011022081.7A patent/CN111933715A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5329142A (en) * | 1991-08-08 | 1994-07-12 | Kabushiki Kaisha Toshiba | Self turn-off insulated-gate power semiconductor device with injection-enhanced transistor structure |
| US5319221A (en) * | 1991-09-24 | 1994-06-07 | Fuji Electric Co., Ltd. | Semiconductor device with MISFET-controlled thyristor |
| US5324966A (en) * | 1992-04-07 | 1994-06-28 | Toyo Denki Seizo Kabushiki Kaisha | MOS-controlled thyristor |
| CN1144975A (en) * | 1996-04-23 | 1997-03-12 | 西安电子科技大学 | Grid-controlled transistor |
| CN101478002A (en) * | 2008-11-27 | 2009-07-08 | 电子科技大学 | Thyristor controlled by accumulation layer |
| CN110634944A (en) * | 2018-06-22 | 2019-12-31 | 英飞凌科技股份有限公司 | Silicon carbide semiconductor device |
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Application publication date: 20201113 |