JP3284120B2 - Static induction transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wide-gap semiconductor high-voltage electrostatic induction transistor, and more particularly to an electrostatic induction transistor having a significantly reduced conduction loss.

[0002]

2. Description of the Related Art In a device for converting power using a semiconductor switching element or a current interrupting device, a conversion capacity and a high frequency of operation are being promoted with an increase in the performance of the semiconductor element. There is a demand for a switching element that not only has a large current and voltage but also operates at a low loss and at a high speed.

In order to meet such demands, switching elements using a silicon carbide single crystal as a material instead of conventional silicon have been proposed. For example, IEEE
Electron Devices Letters, Vol. 19, No. 12,
pp. 487-489 (1998) "High-Voltage Ac
cumulation-Layer UMOSFET's in 4H-Si
C ”, IEEE Transactions on Electron Devic
es, Vol. 46, No. 3, pp. 542-545 (199)
9) "An 1800V Triple Implanted Vertical"
A power MOSFET as described in "6H-SiC MOSFET" has been studied.

However, in a channel layer serving as a current passage,
In addition to the problem that the on-voltage increases due to the use of an inversion layer with low carrier mobility, the reliability of long-term high-temperature operation is increased due to the increase in the frequency of dielectric breakdown at high temperatures of the silicon oxide film used as the gate insulating film. There is a difficult problem to be solved.

In order to avoid this problem, a semiconductor bulk layer having high carrier mobility is used without using an inversion layer as a channel layer, and a silicon oxide film is not used for insulation between a gate and a source. A static induction transistor using a pn junction formed in a bulk has been studied.

FIG. 8 shows a sectional structure of a basic segment of an electrostatic induction transistor. The semiconductor substrate 1 includes an n + type region 2, an n − type region 3, and a p type region 4, and is provided with a source electrode 7, a drain electrode 6, and a gate electrode 8.

By lowering the potential of the gate with respect to the source, a depletion layer is expanded in a so-called channel region between the adjacent p-type regions 4 and the current flowing through the drain electrode 6 and the source electrode 7 is turned off. can do.

Since the channel region uses a bulk semiconductor of SiC, there is a possibility that an extremely low on-resistance can be realized.
iconCarbide, III-Nitrides and Related Materia
ls-1997, Abstract pp. 443 (1997) "Electrical
Characteristics of A Novel Gate Structure 4H
-SiC Power Static Induction Transistor ".

FIG. 9 shows the relationship between the withstand voltage of the element of such an electrostatic induction transistor (hereinafter referred to as SIT) and the on-resistance Ron.s per unit area (SiC).
-Std.).

Ron.s is a value on the assumption that the channel resistance is ideally small. For comparison, the values when silicon is used as the semiconductor material are also shown (Si-
Std.).

As is apparent from the figure, by switching the semiconductor material from silicon to silicon carbide, Ron.s of the SIT is reduced to about 300 times. As a specific example, a high-voltage SIT of 1,000 V having an on-resistance equivalent to that of 100 V silicon SIT can be realized by silicon carbide. That is, a high-voltage, low-loss, and high-speed unipolar power device that cannot be realized by conventional silicon can be realized.

However, even if silicon carbide is used, if the withstand voltage of the element exceeds 2,500 V, the on-resistance becomes 10 mΩ · cm ² or more, and the high withstand voltage element of 5,000 V class has 40 to 50 mΩ · cm ^2. , The voltage drop inside the element during current conduction is significantly larger than that of a conventional bipolar power device such as a thyristor made of silicon. This is because the conductivity modulation of the drift layer (the n − -type region 3) due to the injection of minority carriers does not occur.

[0013] Therefore, in order to reduce the loss generated when current is supplied, the area of the element must be increased and the current density must be reduced. This leads to an increase in the size and cost of the elements, and in turn, an increase in the size of the power converter and current interrupter using these elements, resulting in an increase in the price.

On the other hand, in Japanese Patent Application Laid-Open No. 57-124469 and US Pat. No. 4,754,310,
"In a semiconductor device comprising a semiconductor body and at least a means for forming a depletion layer through a part of the semiconductor body when the device is in a high voltage operation mode, the semiconductor body forms an n-type first region. A plurality of p-type second regions are interposed between the first regions, the total number of the first and second regions is at least four, and the thickness of the first and second regions is The length (width) in the direction perpendicular to the semiconductor body should be at least 100 V between the semiconductor bodies when free charge carriers are eliminated by a depletion layer extending into the semiconductor body at least in a high-voltage operation mode of the device. And at least one first region forms an electrically parallel current path extending through the semiconductor body in at least one mode of operation of the device; and Second The thickness and doping concentration values of each of the regions are such that the first and second regions alternate between positive and negative space charge regions when the free charge carriers are excluded and the voltage is above 100 V. And the space charge per unit area in each of the alternately stacked regions is balanced to such an extent that when the electric field due to the space charge exceeds this, the avalanche breakdown becomes lower than the critical strength that can cause the semiconductor body. A semiconductor device that realizes a low loss and a high withstand voltage at the same time by setting the value so that is maintained.

A structure of a main junction called a so-called spur junction (hereinafter referred to as an SJ structure).

If the SJ structure is applied to the SIT, the doping concentration of the first or second region serving as a current flow path can be significantly higher than that of the conventional drift layer region. Does not need to be proportional to the square of the desired breakdown voltage, as in the prior art semiconductor device described above, but only increases in proportion to the square of the desired breakdown voltage. " A high-withstand-voltage SIT with significantly reduced conduction loss can be realized, and can be further applied to a high-voltage power supply circuit or power conversion circuit.

FIG. 10 shows a basic structure of a vertical field effect transistor to which the SJ structure is applied. For example, Jpn.
J. Appl. Phys. Vol. 36 (1997) pp. 625-
6262, Part 1, No. 10, October 1997,
“Theory of Semiconductor Superjunction Device
s ".

A drain (D) electrode lead is provided at one end of each of the plurality of n-type first regions, a source (S) electrode lead is provided at the other end thereof, and between the n-type first regions. The electrode lead of the gate (G) is connected to the other end on the source side of the p-type second region interposed therebetween, and the on / off of the current flowing between DS and G is changed between G and S. It is controlled by the applied gate voltage.
Since a pn junction is formed between S, it corresponds to a basic structure of a junction field effect transistor, that is, an SIT.

However, if such an SJ structure is applied as it is to a conventionally known SIT, the voltage blocking characteristics and the ON / OFF
There is a problem that the performance such as the off-control characteristic and the production yield are significantly deteriorated.

[0020]

FIG. 11 shows a sectional structure of a basic segment when the SJ structure is directly applied to a conventional SIT. This is a combination of FIG. 8 and FIG. 10, in which the drift layer of the n− type region 3 of FIG.
1 and a p-type second region 32 of the same high doping concentration sandwiching the n-type first region. The p-type second region is formed by a gate according to the basic structure of FIG. The p-type region 4 serving as a layer is connected in the base.

A drift layer having a relatively low doping concentration and a conventional structure of one conductivity type (n-type region 3 in FIG. 8);
A drift layer having an SJ structure in which n-type layers and p-type layers having a relatively high concentration and a narrow width are alternately juxtaposed (first and second layers in FIG. 11).
In order to clearly distinguish between the first region 31 and the n-type first region 31 constituting the drift layer of the SJ structure,
The p-type second region 32 is formed by an n-type column layer and a p-type
It will be referred to as the mold column layer, or simply n columns and p columns.

A problem in the case where the SJ structure is directly applied to the conventional SIT based on FIG. 11 will be described below.

The first problem is that gate drive power is significantly increased due to an increase in input capacitance.

That is, since the gate layer 4 and the p-type column layer 32 are electrically connected inside the semiconductor substrate 1, an extremely large area pn junction is formed between the gate and the source and between the gate and the drain. Intervene.

Further, the doping concentration of the n-type column layer 31 and the p-type column layer 32 constituting these junctions is
Two orders of magnitude higher than the drift layer of the conventional structure. Therefore, the gate-source junction capacitance (Cgs) and the gate-drain junction capacitance (Cgd) become extremely large.

When the voltage applied between the pn junctions increases, these junction capacitances decrease rapidly due to the expansion of the depletion layer. However, in the case of the SJ structure, the junction capacitance per unit junction area where the depletion layer expands is reduced. Being large, the reduction in Cgs and Cgd is small.

Cgs and Cgd are the input capacitance of the transistor. In particular, the feedback capacitance Cgd between the gate and drain
Is large, the gate current for charging and discharging the transistor becomes extremely large, which not only causes a significant increase in gate drive power required for controlling the on / off of the transistor, but also increases the time required for charging and discharging the gate. Another problem is that the switching loss of the transistor increases.

A second problem is that the gate-off gain decreases with an increase in the pinch-off gate voltage due to an increase in the doping concentration of the drift layer.

In FIG. 11, a transition from the on-state to the off-state causes a voltage of a negative potential with respect to the source electrode 7 to be applied to the gate electrode 8 so that a depletion layer extending from two adjacent p-type regions 4 is formed. The overlap depletes the entire channel region therebetween (this is referred to as pinch-off of the channel region). Thereafter, while the gate voltage is being applied, the blocking state is maintained between the drain and the source.

The gate voltage causing the pinch-off is preferably as low as possible. This is because a high gate-off gain can be obtained because the voltage between the drain and the source can be blocked with a low gate voltage. High off-gain is an essential requirement for high breakdown voltage transistors.

However, in FIG. 11, the channel region is an n column layer 31 having a doping concentration several tens of times higher than that of the drift layer of the conventional structure. , The gate voltage required for pinch-off is several to several tens times higher than before. As a result, the off-gain is remarkably reduced, and the blocking voltage between the drain and the source is significantly reduced in the case of the same withstand voltage of the gate-source junction as in the related art.

The third problem is that the manufacturing yield is reduced due to the alignment between the column layer and the channel region.

In order for the majority carriers flowing in the channel region to flow into the same conductive type column layer without waste, the channel region is positioned on a column layer which is repeatedly juxtaposed with a narrow width of about several microns at most. High processing accuracy for matching is required. If the accuracy is insufficient, a characteristic defect due to a position shift occurs.

As described above, in order to reduce the on-resistance of the silicon carbide based inductive transistor (SIT) in a high withstand voltage region of 2.5 kV or more, a conventionally known spur junction (SJ) structure is used. If it is applied to the SIT as it is, a remarkable increase in gate input capacitance not only causes a remarkable increase in gate control power, but also causes new performance problems such as an increase in switching loss and a decrease in off-gain. In addition to this, since extremely high precision is required for pattern matching, there is a problem that a transistor having constant characteristics cannot be manufactured with a high yield.

An object of the present invention is to provide an extremely low-loss, high-breakdown-voltage electrostatic induction transistor having excellent switching characteristics with reduced gate power required for on / off control.

Another object of the present invention is to provide a low-loss, high-withstand-voltage electrostatic induction transistor having a high off-gain.

Another object of the present invention is to provide a structure of the above-described low-loss and high-breakdown-voltage electrostatic induction transistor which can be manufactured with a high yield.

Another object of the present invention is to provide a high-efficiency power converter or power cut-off device using the above-described low-loss, high-withstand-voltage electrostatic induction transistor.

[0039]

The gist of the present invention to achieve the above object is to provide a semiconductor single crystal having a band gap energy of at least 2.0 eV between a valence band and a conduction electron band as a base material and a pair of main surfaces. A first conductivity type low resistance substrate is adjacent to one main surface of the semiconductor substrate having the first conductivity type, and a first conductivity type first buffer layer is adjacent to the other main surface. A first drift region of a first conductivity type extending long in a direction substantially perpendicular to the pair of main surfaces, and a second drift region of a second conductivity type adjacent to the first drift region.
Drift regions each have a plurality of drift regions alternately arranged in parallel, and reach the first conductive type high-concentration source layer and the second drift region from the other main surface on which the first buffer layer is formed. A second buffer layer of a second conductivity type that is deep and electrically connected to the second drift layer;
A gate layer of the second conductivity type is provided, a source electrode is provided on the high-concentration source layer and the second buffer layer, a gate electrode is provided on the gate layer, and a drain electrode is provided on the low-resistance substrate. In an operation mode in which a low resistance is connected to the exposed portion and a high voltage is blocked between the drain electrode and the source electrode, positive and negative space charge regions are alternately arranged in the first drift region and the second drift region. In the electrostatic induction transistor that supports at least half of the voltage applied between the electrodes in the space charge region, the projection in the direction in which the gate layer of the second conductivity type penetrates a pair of main surfaces of the semiconductor body is the second direction. A portion of the first buffer layer of the first conductivity type interposed between the second drift layer and the other main surface of the semiconductor substrate. Is the set static induction transistor in the depth.

That is, a relatively high concentration along the one end of a drift layer (voltage holding region) in which n layers (n column layers) and p layers (p column layers) are alternately arranged adjacently. By providing an n-type buffer layer having a concentration and providing a p-gate layer on the surface thereof, an n-type buffer layer is interposed between the p-gate layer and the p-column layer. The gate layer and the p column layer are electrically separated.

Further, a p-type buried layer connected to the source electrode with low resistance is provided in the n-type buffer layer together with the source layer, and a region between the p-type buried layer and the p-gate layer is used as a channel region. .

Further, the p-type buried layer and the p column layer are electrically connected when the voltage between the drain and the source is blocked.

As described above, since the p-type gate layer to which the gate control electrode is connected is provided separately from the p-column layer, the junction capacitance between the gate and source and between the gate and drain is limited to a small value. As a result, there is no increase in the gate current accompanying the increase in the input capacitance.

Further, by providing the p-type buried layer, the distance between the gate layer and the channel region between the buried layers can be reduced, so that the gate off gain can be increased.

Further, since there is a portion where the p-type buried layer and the p column layer are electrically connected, and the p gate layer and the p column layer are electrically separated, there is a , An n-type column layer or a newly provided n-type layer is interposed, so that a current path can be formed without pattern matching between the channel region and the column layer.

[0046]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described specifically based on embodiments.

Embodiment 1 FIG. 1 is a sectional view of a basic segment of a semiconductor device of an electrostatic induction transistor according to an embodiment of the present invention.

In FIG. 1, the present semiconductor device is a parallel-plate-shaped silicon carbide semiconductor substrate 1 having a substantially rectangular planar shape and a main surface at the top and bottom, and a drain electrode 6 on one main surface. A source electrode 7 and a gate electrode 8 are provided on the other main surface, and when a voltage is applied between the drain electrode 6 and the source electrode 7, the semiconductor substrate 1
A depletion layer is formed through a portion of the semiconductor device to prevent current from flowing between the drain electrode 6 and the source electrode 7.

On one main surface side of the semiconductor substrate 1, a low-resistance n-type substrate (n ++) 2, which has the highest doping concentration,
Between the n-type substrate 2 and the source electrode 7 on the other main surface,
The n-type first region 3 having a relatively high doping concentration as described above.
1 (n column layer) of the same concentration as the p-type second region 32
There is a voltage holding region in which (p column layers) are alternately arranged adjacently.

When a voltage for preventing current flow is applied between the drain electrode 6 and the source electrode 7, the n-type first region 31 and the p-type
The positive and negative space charges are respectively spread in the second region 32 of the mold, and they are alternately arranged to be in a neutral state when viewed on a macro scale, and are made of an intrinsic semiconductor material having a high resistivity. If the length of this region is appropriately increased, the breakdown voltage can be further increased.

On the other hand, when a voltage is applied in the direction in which current flows between the electrodes, the electron current flows to the n-type first region 31 having a relatively high doping concentration. It can be significantly lower.

In this embodiment, the n-type silicon carbide substrate (n ++) 2 having the highest doping concentration has a nitrogen doping concentration of 2 × 10 ¹⁹ , a thickness of about 200 μm, and a resistivity of about 0.1 mΩ · cm. Low resistance base.

The p-type second regions 32 (p-column layers) having substantially the same concentration as the n-type first regions 31 (n-column layers) having a relatively high doping concentration are alternately arranged in a stripe structure. The length of the voltage holding region is about 50 μm,
The doping concentration and width of the first and second regions, which are constituent elements, are substantially the same in both regions, and are respectively 2.5 × 10 ¹⁵ and 10 μm.

On one main surface side of the first and second regions, an n-type layer (31) having a thickness of about 5 μm and a doping concentration of about 2.5 × 10 ^{15 which} is almost the same as that of the n column layer is provided. It is formed between the mold base 2.

The first embodiment is different from the first embodiment in that the n-type buffer layer 33 formed on the other surface of the semiconductor substrate 1 adjacent to the voltage holding region composed of the n and p column layers is provided. is there.

The n-type buffer layer 33 has a doping concentration and a thickness of 1 × 10 ¹⁷ and about 2 μm, which are higher and thinner than the n-column layer. The n-type buffer layer 3
3 from the surface of n + source layer 51, P + buffer layer 42
And P + gate layer 41 are provided, respectively. Source electrode 7 is connected to the surface of n + source layer 51 and P + gate layer 41, and gate electrode 8 is connected to the surface of P + gate layer 41 with low resistance.

Of these layers, the P + buffer layer 42
Is a depth reaching the p column layer 32 and is electrically connected to the column layer.
Is the distance between the surface and the p column layer 32.
The + buffer layer 33 is set to a depth such that it intervenes, and the projection in the thickness direction that sees through the two main surfaces of the semiconductor substrate 1 has a portion that overlaps the p column layer 32.

In the following description of the operation of the SIT of this embodiment, the operation of each of these layers will be described.

The operation of each part when the drain and source electrodes are in the off state and the on state is as described above. During gate opening when no gate signal is applied,
This SIT exhibits a so-called normally-on characteristic,
Stay on. The transition from this state to the off state starts when a voltage signal of a negative potential is applied to the gate electrode 8 with respect to the source electrode 7.

The P + gate layer 41 and n
The pn junction formed with the + buffer layer 33 is reverse-biased, and the depletion layer starts to spread mainly into the n + buffer layer 33. Therefore, the P + gate layer 41 and the p column layer 32
Buffer layer 33 between n + source layer 51 and n +
The width of the current path of carriers (electrons) flowing in the lateral direction toward the column layer 31 is reduced.

When the gate voltage is sufficiently high and the depletion layer that expands according to the voltage reaches the p column layer 32 on the opposite side of the current path, the current path is completely shielded, that is, in a so-called pinch-off state. When the electron flow is interrupted at this point, n
Pn junction 1 composed of column layer 31 and p column layer 32
02 is reverse biased, a depletion layer spreads in each region, and positive and negative space charge regions are alternately formed to block a predetermined voltage. The blocking voltage is determined by the length of the voltage holding region and the gate-off gain.

In this embodiment, the length of the voltage holding region is about 50 μm. Further, since the width of the portion of the n + buffer layer 33 interposed between the p + gate layer 41 and the p column layer 32, which is substantially the width of the channel, is extremely narrow, about 1 μm,・ Off gain is obtained.

When a voltage of 25 V is applied as an off-gate voltage, a withstand voltage of about 5,000 V is provided. In the transition from the off-state to the on-state, the gate voltage signal applied between the gate and the source is removed or a voltage is applied to make the gate electrode 8 slightly positive (2.0 V or less). . Thereby, the P + gate layer 41 and p
The pinch-off state due to the depletion layer in the portion overlapping with the column layer 32 in the projection direction is released, and the electron conduction path of the n + buffer layer 33 in this portion is opened, and the source electrode 7
Electrons flow through the path of the n ++ source layer 51, the n ++ buffer layer 33 (channel region), the n column layer 31, the n ++ substrate 2, and the drain electrode 6, and are turned on.

In the switching operation described above,
The gate signal is a voltage signal applied between the gate and the source.

The input capacitance between the gate and the source,
As described above, if the feedback capacitance between the drains is large, there is a problem that the gate current required to charge and discharge these capacitances increases, but in the present embodiment, these capacitance components are p + gate layer 41 and n + buffer layer 3
3 is only the junction capacitance of the pn junction composed of Therefore, the total input capacitance was at most about 1,000 pF / cm ² , and the problem of the conventional SJ structure SIT in which the gate power increased due to the increase in the gate current could be solved.

Further, since the channel region is made narrower, the off-gain does not decrease and a gain of 200 or more is obtained.

In the first embodiment, the withstand voltage is 5,000.
The example is applied to SIT of silicon carbide of V.
The on-resistance Ron.s of this embodiment is represented by SiC-SJ (d
= 10 μm), about 4 mΩ.c
m ^2, and about 20Omu.Cm ² of SIT conventional structure in which the silicon as a raw material, and, with respect to the SIT 40Emuomega.Cm ² values of the conventional structure in which the silicon carbide as a material,
The on-resistance was reduced to about 1 / 5,000 and 1/10, respectively.

Although only the cross-sectional structure is disclosed in FIG. 1 of the present embodiment, the two-dimensional array has a structure in which an n-column layer 31 and a p-column layer 32 are juxtaposed in a stripe shape, Can be arranged in a mosaic or lattice arrangement.

Embodiment 2 FIG. 2 is a perspective view showing a part of a semiconductor device of an electrostatic induction transistor according to an embodiment of the present invention.

The same reference numerals as those shown in FIG. 1 denote parts having the same structure, conductivity type, and action.

This embodiment is different from the first embodiment in the structure and arrangement of the P + buffer layer 42. In this embodiment, the P + buffer layer 42 is provided inside the n + buffer
Example 1 is responsible for electrically connecting between
However, it has an inverted T-shape having a portion extending in the left-right and lateral directions at a position deeper than the surface of the n + buffer layer 33.

The feature of this embodiment is that the projection in the thickness direction, which sees through the two main surfaces of the semiconductor substrate 1, has a portion overlapping the p gate layer 41 in the left and right portions. 1 (FIG. 1) has a role to replace the requirement that the P + gate layer 41 and the p column layer 32 overlap with each other in the projection direction. That is, in this embodiment, the n + buffer layer 33 in the portion where the p + gate layer 41 and the p + buffer layer 42 overlap in the projection direction operates as a channel region.

This embodiment is different from the first embodiment in that the lateral positions of the p + gate layer 41, the p + buffer layer 42 and the n ++ source layer 51 formed in the n + buffer layer 33 are as follows. The voltage holding region provided adjacent to the n-type buffer layer 33 in the semiconductor substrate 1 can be formed irrespective of the arrangement of the n-column layer 31 and the p-column layer 32. That is, the p + gate layer 41, p
In forming the + buffer layer 42 and the n ++ source layer 51, regardless of the arrangement structure of the n column layer 31 hidden behind the n + buffer layer 33 and the p column layer 32,
In other words, it is easy to manufacture because it can be formed without alignment.

[Embodiment 3] FIG. 3 is a sectional view showing a part of a semiconductor device of an electrostatic induction transistor according to an embodiment of the present invention.

The numbers of the constituent parts given to the respective parts in FIG.
Are the parts having the same structure, conductivity type and function. Although the basic configuration is different from that of the second embodiment shown in FIG. 2, the lateral direction of the p + gate layer 41, the p + buffer layer 42, and the n ++ source layer 51 formed in the n + buffer layer 33. Is a development example of the second embodiment in which the position of the voltage holding region can be formed irrespective of the arrangement of the n column layer 31 and the p column layer 32 in the voltage holding region.

That is, in this example, the structure and dimensions of the p + gate layer 41, the p + buffer layer 42 and the n ++ source layer 51 formed in the n + buffer The width of the p-type layer 31 and the p-column layer 32 is about 1/2 of that of the second embodiment, that is, about 5 μm, and the doping concentration is higher. In this case, the on-resistance is further reduced.

Embodiment 4 FIG. 4 is a sectional view showing a part of a semiconductor device of an electrostatic induction transistor according to an embodiment of the present invention.

In the figure, the same reference numerals as those shown in FIG. 3 indicate portions having the same structure, conductivity type and function. Although the basic configuration is not different from the embodiment 2 (FIG. 2),
p + gate layer 4 formed in n + buffer layer 33
1, the lateral positions of the p ++ buffer layer 42 and the n ++ source layer 51 are the n column layers 3 of the voltage holding region.
This is another development example of the second embodiment in which it can be formed irrespective of the arrangement of the 1 and p column layers 32.

This embodiment is different from the previous embodiment in that
P + gate layer 41, p + buffer layer 42 and n +
+ The arrangement direction of the source layers 51 is n
This is an example in which the column layers 31 and the p column layers 32 are formed so as to be substantially perpendicular to the arrangement direction, and are examples showing the ease of manufacture of the second embodiment, which can be formed without alignment.

Embodiment 5 FIG. 5 is a sectional view showing a part of a semiconductor device of an electrostatic induction transistor according to an embodiment of the present invention. The same reference numerals as those shown in FIG. 3 indicate portions having the same structure, conductivity type and function.

The difference from the third embodiment is that the p + buffer layer 42 is not directly electrically connected to the p column layer 32, and a part 34 of the n + buffer layer is interposed therebetween. As a result, the junction capacitance between the source and the drain in a low bias state is reduced, and the switching time of the SIT can be further reduced.

[Embodiment 6] FIG. 6 is a sectional view showing a part of a semiconductor device of an electrostatic induction transistor according to an embodiment of the present invention.

This is a partial modification of the above-described first to fourth embodiments.
Refers to a portion having the same conductivity type and function.

The difference from the previous embodiment lies in the relationship between the n ++ source layer 51 and the p + gate layer 41 and also between the n ++ source layer 51 and the p + buffer layer 42. That is, in this embodiment, the n ++ source layer 51 and the p + gate layer 41 are in direct contact. As in the previous embodiment, even if a part of the n + buffer layer 33 does not intervene on the surface, the gate
It is sufficient that a predetermined withstand voltage is secured at the pn junction between the sources. High precision is not required for the alignment of both layers, and the ease of manufacture is improved.

In the above embodiment, a part of the p + buffer layer 42 is exposed between the n ++ source layer 51 on the other surface of the semiconductor substrate, and the p + buffer layer 42 and the source electrode 7 are connected by a low resistance connection. However, the connection portion with the electrode does not necessarily have to be on the surface of the base, but as in the present embodiment, a groove is provided with a depth reaching the p + buffer layer 42 from the surface of the base, and the source is formed at the bottom thereof. The electrode 7 may be connected with low resistance. This also improves the ease of manufacture. Furthermore, it is not necessary to apply these two deformation structures at the same time, and they may be applied individually to the actual element.

[Embodiment 7] FIG. 7 is a sectional view showing a part of a semiconductor device of an electrostatic induction transistor according to an embodiment of the present invention. The same reference numerals as those shown in FIGS. 1 to 4 indicate parts having the same structure, conductivity type and function.

The difference from the previous embodiment lies in the structure and arrangement of the p + gate layer 41. That is, the p + gate layer 41 is electrically separated from the p column layer 32,
The place provided in the n + buffer layer 33 is the same as in the first to fourth embodiments, but in this embodiment, the p + gate layer 41 is located at an intermediate position between two adjacent p + buffer layers 42. The feature is that it is provided. That is, as in the previous example, the projection of the p gate layer 41 in the thickness direction that sees through the two main surfaces of the semiconductor substrate 1 shows the portion overlapping the p + buffer layer 42 or the p column layer 32. I do not have.

The p gate layer 41 and the p + buffer layer 4
2 is turned on as the channel region described above.
Controlled off.

[Eighth Embodiment] FIG. 12 shows a basic circuit configuration of one arm constituting an inverter device using an electrostatic induction transistor according to the present invention.

FIG. 9 shows a one-phase portion of an inverter circuit that controls a DC power supply of a capacitor 70 and controls an AC output of an AC load 75. The high-speed and low-loss SITs 71 and 72 of the present invention are used for the upper and lower arms, and high-speed rectifier diodes 73 and 74 are connected in parallel to each of the SITs.

In an actual inverter, one arm is connected to two
The combination of phases or three phases functions as a single-phase or three-phase inverter. There is no recovery current, low loss, and
By using the SIT of the present invention that operates at a high speed, a high-voltage inverter having a power supply voltage of 2 kV or more is configured, and can be applied to direct conversion of high-voltage AC / DC without a transformer.

[Embodiment 9] FIG. 13 shows a basic circuit configuration of a semiconductor current breaker using a high withstand voltage static induction transistor of the present invention.

The SIT 71 of the present invention is connected between the main terminals 60 and 61 of the circuit breaker, and a snubber circuit including a capacitor 76 and a resistor 77 is connected in parallel with the SIT 71.
Clamps the voltage jump at the time of current interruption. 5kV
A semiconductor circuit breaker having an extremely low on-loss of an internal voltage drop of 0.4 V or less when a current of 100 A / cm ² is supplied can be realized while having a withstand voltage of 100 A / cm ² .

[0094]

According to the present invention, the resistance of the drift layer of a high-voltage electrostatic induction transistor made of silicon carbide can be reduced to 1/10 of the conventional one, and the distance between the gate and the source and between the gate and the drain can be reduced. It is possible to realize an ultra-low-loss, high-withstand-voltage semiconductor transistor with excellent controllability that prevents a significant increase in gate power and that is necessary for controlling the transistor on / off by significantly reducing the junction capacitance between the transistors. There is an effect.

Specifically, when applied to a silicon carbide electrostatic induction transistor having a withstand voltage of 5,000 V, the on-resistance Ron.s of the present invention is about 4 mΩ.cm ² ,
20Omu.Cm ² of static induction transistor of the conventional structure of silicon as a raw material, and, 40Emuomega.Cm ² static induction transistor of the conventional structure in which the silicon carbide as a material
, About 1 / 5,000, 1
The on-resistance can be reduced to 1/0 and the internal voltage drop is 0.4 V when a current having a current density of 100 A / cm ² is applied.
Thus, it is possible to obtain an extremely low-loss, high-withstand-voltage switching element.

Further, since a high breakdown voltage transistor in which both conduction loss and gate power are reduced can be realized, a transformer can be used by using this transistor as a semiconductor switching element of a high-voltage power conversion device having a power supply voltage of 2500 V or more. A high-voltage power conversion device can be obtained without performing high-voltage power conversion, and a high-efficiency, compact, high-voltage power conversion device with small size and high functionality can be obtained.

Further, a high-voltage semiconductor switching element with extremely reduced conduction loss can be realized.
A low-loss, high-speed semiconductor circuit breaker can be obtained by using the present invention for a high-voltage current interrupter of 500 V or more.

[Brief description of the drawings]

FIG. 1 is a sectional view of a basic segment of a semiconductor device of an electrostatic induction transistor according to a first embodiment.

FIG. 2 is a perspective view showing a part of a semiconductor device of an electrostatic induction transistor according to a second embodiment.

FIG. 3 is a sectional view showing a part of a semiconductor device of an electrostatic induction transistor according to a third embodiment;

FIG. 4 is a perspective view showing a part of a semiconductor device of an electrostatic induction transistor according to a fourth embodiment.

FIG. 5 is a sectional view showing a part of a semiconductor device of an electrostatic induction transistor according to a fifth embodiment.

FIG. 6 is a sectional view showing a part of a semiconductor device of an electrostatic induction transistor according to a sixth embodiment.

FIG. 7 is a sectional view showing a part of a semiconductor device of an electrostatic induction transistor according to a seventh embodiment.

FIG. 8 is a sectional view of a basic segment of a semiconductor device having a conventional structure of an electrostatic induction transistor.

FIG. 9 is a graph showing a relationship between withstand voltage and on-resistance of the electrostatic induction transistor.

FIG. 10 shows a basic structure of a vertical field effect transistor to which a super junction structure is applied.

FIG. 11 is a cross-sectional view of a basic segment of a conventional vertical field-effect transistor to which a super junction structure is applied.

FIG. 12 is a diagram showing a basic configuration circuit of one arm constituting an inverter device using the static induction transistor of the present invention.

FIG. 13 is a diagram showing a basic circuit configuration of a semiconductor current interrupting device using a high withstand voltage static induction transistor of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 high-concentration n-type substrate 3 relatively low-concentration n-type drift layer 4 relatively high-concentration p-type gate layer 5 relatively high-concentration n-type source layer 6 ... Drain electrode (anode electrode), 7 ... Source electrode (cathode electrode), 8 ... Gate electrode, 31 ... N-type drift layer (n column layer) with relatively high concentration, 32 ... P-type drift layer with relatively high concentration (P column layer), 33 ... relatively high concentration n-type layer (n-type buffer layer), 34 ... relatively high concentration n-type layer (n
Buffer layer), 41: relatively high concentration p-type layer (p-type gate layer), 42: relatively high concentration p-type layer (p-type buffer layer, p-type buried layer), 51: relatively high concentration N-type layers (n-type source layers), 70... DC capacitors, 71, 72
... Electrostatic induction transistor of the present invention, 73, 74 ... High-speed rectifier diode, 75 ... Load, 60,61 ... Main terminal, 76
... AC capacitor, 77 ... resistor, 78 ... gate circuit.

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Toshio Yasuda 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-2000-269518 (JP, A) 2001-144292 (JP, A) Japanese Journal of Applied Physics, Japan, October 15, 1997, Vol. 10, p. 6254-6262 (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/80 H01L 21/338

Claims (9)

(57) [Claims] 1. A semiconductor single crystal having a band gap energy of at least 2.0 eV between a valence band and a conduction electron band as a base material, and one of the main surfaces of a semiconductor substrate having a pair of main surfaces is provided with a first conductivity type. A first buffer layer of a first conductivity type is adjacent to the other main surface of the low-resistance substrate, and extends between the low-resistance substrate and the first buffer layer in a direction substantially perpendicular to the pair of main surfaces. A first drift region of a first conductivity type extending and a drift region in which a plurality of second drift regions of a second conductivity type adjacent to the first drift region are alternately arranged in parallel; From the other main surface thus formed, a high-concentration source layer of a first conductivity type, a depth reaching the second drift region, and a second conductivity type of a second conductivity type electrically connected to the second drift layer. 2 buffer layers and second conductive layer A gate electrode is provided on the high-concentration source layer and the second buffer layer, a gate electrode is provided on the gate layer, and a drain electrode is provided on the low-resistance substrate. In an operation mode in which a high voltage is blocked between the drain electrode and the source electrode, positive and negative space charge regions are alternately arranged in the first drift region and the second drift region. In the electrostatic induction transistor supporting at least half of the voltage applied between the electrodes, a portion in which the second conductive type gate layer overlaps the second drift layer in a direction in which the second conductive layer is projected through a pair of main surfaces of the semiconductor substrate. And the depth is set such that a portion of the first buffer layer of the first conductivity type is interposed between the other main surface of the semiconductor substrate and the second drift layer. Static induction transistor, characterized in that. 2. A semiconductor single crystal having a band gap energy of 2.0 eV or more between a valence band and a conduction electron band as a base material, and one of the main surfaces of a semiconductor substrate having a pair of main surfaces is provided with a first conductivity type. A first buffer layer of a first conductivity type is adjacent to the other main surface of the low-resistance substrate, and extends between the low-resistance substrate and the first buffer layer in a direction substantially perpendicular to the pair of main surfaces. A first drift region of a first conductivity type extending and a drift region in which a plurality of second drift regions of a second conductivity type adjacent to the first drift region are alternately arranged in parallel; From the other surface thus formed, a high-concentration source layer of the first conductivity type, a second
A second buffer layer of a conductivity type and a gate layer of a second conductivity type are provided, respectively.
A source electrode is connected to the buffer layer, a gate electrode is connected to the gate layer, and a drain electrode is connected to the surface of the low-resistance substrate at a low resistance to block high voltage between the drain electrode and the source electrode. In the operation mode, positive and negative space charge regions are alternately arranged in the first drift region and the second drift region, and electrostatic induction supporting more than half of the voltage applied between the electrodes in the space charge region. In the transistor, the second conductivity type second buffer layer has a region extending in a lateral direction at a position deeper than the surface of the first buffer layer, and the second conductivity type gate layer is formed of a pair of main semiconductor substrates. The projection in the direction of seeing through the surface has a portion that overlaps with a region extending in the lateral direction of the second buffer layer, and the second buffer layer is provided between the region and the second buffer layer in the region. An electrostatic induction transistor, wherein a depth of one buffer layer is set. 3. The second buffer layer according to claim 2, wherein the second buffer layer of the second conductivity type has a depth reaching the second drift region and electrically connected to the second drift layer. Static induction transistor. 4. The second buffer layer according to claim 2, wherein the second buffer layer of the second conductivity type has a depth that does not reach the second drift region of the second conductivity type. The first buffer layer of the first conductivity type is interposed, and the distance between the first buffer layers is in an operation mode in which a voltage is blocked between the drain electrode and the source electrode. An electrostatic induction transistor in which a depletion layer extending from each of the two drift layers is electrically connected at a relatively low applied voltage. 5. The high concentration source layer, the second buffer layer, the gate layer,
In addition, the source electrode and the gate electrode are respectively arranged substantially in parallel, and the arrangement direction thereof is substantially parallel to the arrangement direction of the first drift layer and the second drift layer arranged in parallel in the semiconductor substrate. Inductive transistor. 6. The high-concentration source layer, the second buffer layer, the gate layer, the source electrode, and the gate electrode, each being arranged substantially in parallel, according to claim 2, 3, or 4. An electrostatic induction transistor having a direction substantially orthogonal to an arrangement direction of the first drift layer and the second drift layer arranged in parallel in the semiconductor substrate. 7. A semiconductor substrate having a semiconductor single crystal having a band gap energy of 2.0 eV or more between a valence band and a conduction electron band as a base material, a semiconductor substrate having a pair of main surfaces, and one main surface of the semiconductor substrate. A first conductivity type low resistance substrate and a first conductivity type first buffer layer are adjacent to the other main surface, respectively, and are substantially perpendicular to the pair of main surfaces between the low resistance substrate and the first buffer layer. A first drift region of a first conductivity type extending long in a predetermined direction, and a drift region in which a plurality of second drift regions of a second conductivity type adjacent to the first drift region are alternately arranged in parallel. A first conductive type high concentration source layer, a second conductive type second buffer layer, and a second conductive type gate layer are provided from the other main surface on which the first buffer layer is formed, respectively. High concentration source layer and second buffer An operation mode in which a source electrode is connected to the gate layer, a gate electrode is connected to the low-resistance substrate, and a drain electrode is connected to the low-resistance substrate at a low-resistance portion at each exposed surface to block a high voltage between the drain electrode and the source electrode. In the above case, positive and negative space charge regions are alternately arranged in the first drift region and the second drift region, and in the electrostatic induction transistor supporting more than half of the voltage applied between the electrodes in the space charge region. The second buffer layer of the second conductivity type has a region extending in the lateral direction at a position deeper than the surface of the first buffer layer of the first conductivity type, and the gate layers of the second conductivity type are adjacent to each other. An electrostatic induction transistor, wherein the static induction transistor is interposed between two laterally expanded regions of the second buffer layer. 8. The method according to claim 1, wherein the doping concentration of the first buffer region of the first conductivity type is equal to the first buffer region.
An electrostatic induction transistor that is equal to or greater than the drift region. 9. An electrostatic induction transistor according to claim 1, wherein the semiconductor single crystal has a band gap energy between the valence band and the conduction electron band of 2.0 eV or more and is made of silicon carbide.