CN113054000A - Super junction type field effect transistor and manufacturing method thereof - Google Patents
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
- H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
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- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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Abstract
The invention provides a super junction field effect transistor, comprising: a drain metal provided with a first conductive type silicon substrate, a first conductive type epitaxial layer provided on the first conductive type silicon substrate, a first conductive type column and a second conductive type column spaced from each other in the first conductive type epitaxial layer, a second conductive type body region provided on the surface of the second conductive type column, a heavily doped second conductive type gate provided in the second conductive type body region, a gate metal connected to the heavily doped second conductive type gate, a heavily doped first conductive type source provided on the surface of the first conductive type column, a source metal connected to the heavily doped first conductive type source, an isolation oxide layer provided between the gate metal and the source metal, a contact surface between the gate metal and the heavily doped second conductive type gate being a first upper surface, a contact surface between the source metal and the heavily doped first conductive type source being a second upper surface, the second upper surface is higher than the first upper surface.
Description
Technical Field
The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a junction field effect transistor based on a super junction theory and a manufacturing method thereof.
Background
The super junction structure introduces a common PN junction into a voltage-resistant layer of the power device, and introduces a remarkable two-dimensional field effect into the voltage-resistant layer, so that the complex field modulation can greatly reduce the surface electric field peak value of the device and optimize the internal field distribution. Due to the two-dimensional field modulation effect of the super junction, the power device can obtain lower specific on-resistance (namely the on-resistance of the device per unit area) under the same withstand voltage.
The Junction Field Effect Transistor (JFET) is a three-terminal active device with an amplifying function, and the working principle of the JFET is to control output current by changing the conductivity of a channel through voltage.
The withstand voltage principle of the JFET device is consistent with that of the MOSFET, and a depletion region is formed through PN junction reverse bias to bear high voltage. Therefore, if the super junction technology is introduced into the JFET device, the best compromise between the on-voltage drop and the withstand voltage of the JFET device can be achieved.
Disclosure of Invention
The invention aims to overcome the problem that the specific on-resistance of a JFET (junction field effect transistor) device is overlarge in the prior art, and provides a super junction field effect transistor and a manufacturing method thereof.
In order to realize the technical purpose, the invention adopts the technical scheme that:
as a first aspect of the present invention, there is provided a super junction type field effect transistor comprising:
a drain metal on which a first conductivity type silicon substrate is provided, a contact surface of the first conductivity type silicon substrate and the drain metal being a lower surface, a first conductive type epitaxial layer is arranged on the first conductive type silicon substrate, a first conductive type column and a second conductive type column which are mutually spaced are arranged in the first conductive type epitaxial layer, a second conductive type body region is arranged on the surface of the second conductive type column, a heavily doped second conductive type grid electrode is arranged in the second conductive type body region, grid metal is connected with the heavily doped second conductive type grid electrode, a heavily doped first conductivity type source is arranged on the surface of the first conductivity type column, a source metal is connected with the heavily doped first conductivity type source, an isolation oxide layer is arranged between the grid metal and the source metal, and the main improvement is that:
the contact surface of the gate metal and the heavily doped second conductive type gate is a first upper surface, the contact surface of the source metal and the heavily doped first conductive type source is a second upper surface, and the second upper surface is higher than the first upper surface.
Further, for a super junction field effect transistor with an N-type channel, the first conduction type is N-type, and the second conduction type is P-type; for a super junction field effect transistor with a P-type channel, the first conduction type is P-type, and the second conduction type is N-type.
Further, the height difference between the second upper surface and the first upper surface is 0.5-5 μm.
As a second aspect of the present invention, there is provided a method for manufacturing a super junction field effect transistor, including the steps of:
the method comprises the following steps: selecting a first conductive type silicon substrate material and epitaxially growing a first conductive type epitaxial layer;
step two: selectively etching a deep groove on the second upper surface of the first conductive type epitaxial layer;
step three: depositing second conductive type silicon, and filling the deep groove to form a first conductive type column and a second conductive type column which are mutually spaced; then removing the structure above the second upper surface;
step four: selectively etching a shallow groove on the second upper surface of the first conductive type epitaxial layer, wherein the bottom of the shallow groove is the first upper surface;
step five: injecting second conductive type impurities into the first upper surface by using the mask window in an ion injection mode and carrying out thermal annealing to form a second conductive type body region;
step six: respectively injecting first conductive type impurities and second conductive type impurities into the second upper surface and the first upper surface by using the mask window, and respectively forming a heavily doped first conductive type source electrode and a heavily doped second conductive type grid electrode after activation;
step seven: and depositing an insulating medium layer, selectively etching a through hole on the insulating medium layer, depositing metal and selectively etching the metal to form source metal, grid metal and drain metal.
Compared with the prior art, the invention has the following advantages:
according to the invention, due to the introduction of the P-type column, the N-type column and the P-type column in the drift region form a super junction structure, according to the theory of the related super junction structure, the electric field of the drift region of the device can be optimized by the super junction structure, as shown in the attached figure 8, under a voltage-resistant state, the ionization donor charge in the N-type column can be matched with the ionization acceptor charge in the P-type column, and thus, the device is prevented from being longitudinally and prematurely broken down due to the continuous increase of a longitudinal electric field. Therefore, the super junction type field effect transistor can ensure that the device cannot break down in advance under the condition of high drift region concentration, and the high drift region concentration can enable the on-resistance of the device to be lower.
Drawings
Fig. 1 is a schematic cross-sectional structural diagram of a transistor in an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of an epitaxial layer formation in an embodiment of the invention.
FIG. 3 is a schematic cross-sectional structure diagram of forming deep trenches in an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional structure diagram of forming a second conductive type pillar according to an embodiment of the present invention.
FIG. 5 is a schematic cross-sectional structure diagram of forming a shallow trench in an embodiment of the invention.
Fig. 6 is a schematic cross-sectional structure diagram of forming a second conductivity type body region in an embodiment of the invention.
Fig. 7 is a schematic cross-sectional structure diagram of forming a source and a gate in an embodiment of the invention.
Fig. 8 is a schematic diagram of an internal electric field of the super junction field effect transistor in the embodiment of the invention.
Description of reference numerals: 01-drain metal; 02-a first conductivity type silicon substrate; 03 — a first conductivity type column; 04 — a second conductivity type column; 05-a second conductivity type body region; 06-a second conductivity type gate; 07 — a first conductivity type source; 08-source metal; 09-gate metal; 10-isolating oxide layer; 301 — a first upper surface; 201 — lower surface; 302 — a second upper surface; 401-deep trench; 3-epitaxial layer of first conductivity type; 402-shallow trenches.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As a first embodiment of the present invention, a super junction field effect transistor (hereinafter referred to as a device) with an N-type channel as an example is provided, in this embodiment, a first conductivity type is an N-type, a second conductivity type is a P-type, fig. 1 is a schematic structural diagram provided according to an embodiment of the present invention, and as shown in fig. 1, the super junction field effect transistor with an N-type channel as an example includes:
a drain metal 01 on which a first conductive type silicon substrate 02 is provided on the drain metal 01, the contact surface between the first conductive type silicon substrate 02 and the drain metal 01 is the lower surface 201, a first conductive type epitaxial layer 3 is arranged on the first conductive type silicon substrate 02, a first conductive type column 03 and a second conductive type column 04 which are spaced from each other are arranged in the first conductive type epitaxial layer 3, a second conductive type body region 05 is arranged on the surface of the second conductive type column 04, a heavily doped second conductive type gate 06 is arranged in the second conductive type body region 05, a gate metal 09 is connected with the heavily doped second conductive type gate 06, a heavily doped first conductive type source electrode 07 is arranged on the surface of the first conductive type column 03, a source metal 08 is connected with the heavily doped first conductive type source electrode 07, and an isolation oxide layer 10 is arranged between the gate metal 09 and the source metal 08;
the contact surface of the gate metal 09 and the heavily doped second conductive type gate 06 is a first upper surface 301, the contact surface of the source metal 08 and the heavily doped first conductive type source 07 is a second upper surface 302, and the second upper surface 302 is higher than the first upper surface 301;
the height difference between the second upper surface 302 and the first upper surface 301 is 0.5-5 μm;
as a second embodiment of the present invention, there is provided a method for manufacturing a super junction field effect transistor using an N-type channel as an example, including:
as shown in fig. 2, step one: selecting a first conductive type silicon substrate 02 material and epitaxially growing a first conductive type epitaxial layer 3;
as shown in fig. 3, step two: selectively etching a deep trench 401 on the second upper surface 302 of the first conductive type epitaxial layer 3;
as shown in fig. 4, step three: depositing second conductive type silicon, and filling the deep trench 401 to form a first conductive type column 03 and a second conductive type column 04 which are spaced from each other; the structure above the second upper surface 302 is then removed; specifically, the second conductive type silicon material protruding from the second upper surface 302 when the deep trench 401 is filled can be removed by grinding;
as shown in fig. 5, step four: selectively etching a shallow trench 402 on the second upper surface 302 of the first conductive type epitaxial layer 3, wherein the bottom of the shallow trench is the first upper surface 301;
as shown in fig. 6, step five: implanting second conductive type impurities into the first upper surface 301 by using the mask window in an ion implantation manner and performing thermal annealing to form a second conductive type body region 05;
as shown in fig. 7, step six: respectively injecting first conductive type impurities and second conductive type impurities into the second upper surface 302 and the first upper surface 301 by using the mask window, and respectively forming heavily doped first conductive type source electrodes 07 and heavily doped second conductive type grid electrodes 06 after activation;
as shown in the attached figure 1, step seven: depositing an insulating medium layer 10, selectively etching a through hole on the insulating medium layer 10, depositing metal and selectively etching the metal to form a source metal 08, a gate metal 09 and a drain metal 01.
The working principle of the invention is as follows:
when the device is in a conducting state, the source electrode and the grid electrode of the super junction type field effect transistor are grounded, the drain electrode is connected with positive voltage, electrons flow from the source electrode to the drain electrode, and the device is conducted. When the grid electrode of the device is connected with negative voltage relative to the source electrode and the drain electrode is connected with positive voltage relative to the source electrode, the P-type body region on the first upper surface can completely pinch off the N-type conductive channel due to the height difference of the first upper surface and the second upper surface, electrons of the source electrode are blocked from flowing to the drain electrode, and the device is in a pinch-off state at the moment. When the grid electrode of the device is connected with negative voltage relative to the source electrode, and the drain electrode is connected with high voltage relative to the source electrode, the device is in a voltage-resistant state, the P-type column and the N-type column in the transistor are mutually depleted to form transverse electric field distribution, so that the original stronger longitudinal electric field is reduced, and the super-junction field effect transistor can obtain higher breakdown voltage under the condition of the same concentration of a drift region, namely the N-type column.
In the above embodiment, the first conductivity type is N-type, and the second conductivity type is P-type, but in other modified embodiments, the first conductivity type may be P-type, and the second conductivity type may be N-type, and the structure of each portion of the device may also be converted by N < - > P.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
Claims (4)
1. A super junction field effect transistor, comprising:
a drain metal (01), a first conductive type silicon substrate (02) is arranged on the drain metal (01), the contact surface between the first conductive type silicon substrate (02) and the drain metal (01) is a lower surface (201), a first conductive type epitaxial layer (3) is arranged on the first conductive type silicon substrate (02), a first conductive type column (03) and a second conductive type column (04) which are mutually spaced are arranged in the first conductive type epitaxial layer (3), a second conductive type body region (05) is arranged on the surface of the second conductive type column (04), a heavily doped second conductive type grid electrode (06) is arranged in the second conductive type body region (05), a grid metal (09) is connected with the heavily doped second conductive type grid electrode (06), and a heavily doped first conductive type source electrode (07) is arranged on the surface of the first conductive type column (03), the source electrode metal (08) is connected with the heavily doped source electrode (07) of the first conduction type, an isolation oxidation layer (10) is arranged between the gate electrode metal (09) and the source electrode metal (08), and the method is characterized in that:
the contact surface of the gate metal (09) and the heavily doped second conductive type gate (06) is a first upper surface (301), the contact surface of the source metal (08) and the heavily doped first conductive type source (07) is a second upper surface (302), and the second upper surface (302) is higher than the first upper surface (301).
2. The super junction field effect transistor of claim 1,
for a super junction field effect transistor with an N-type channel, the first conduction type is N-type, and the second conduction type is P-type; for a super junction field effect transistor with a P-type channel, the first conduction type is P-type, and the second conduction type is N-type.
3. The super junction field effect transistor of claim 1,
the height difference between the second upper surface (302) and the first upper surface (301) is 0.5-5 μm.
4. A manufacturing method of a super junction field effect transistor is characterized by comprising the following steps:
the method comprises the following steps: selecting a first conductive type silicon substrate (02) material and epitaxially growing a first conductive type epitaxial layer (3);
step two: selectively etching a deep trench (401) on the second upper surface (302) of the first conduction type epitaxial layer (3);
step three: depositing second conductive type silicon, and filling the deep trench (401) to form a first conductive type column (03) and a second conductive type column (04) which are mutually separated; then removing the structure above the second upper surface (302);
step four: selectively etching a shallow groove (402) on the second upper surface (302) of the first conductive type epitaxial layer (3), wherein the bottom of the shallow groove is the first upper surface (301);
step five: implanting second conductive type impurities into the first upper surface (301) by means of ion implantation through the mask window and performing thermal annealing to form a second conductive type body region (05);
step six: respectively implanting impurities of a first conductivity type and impurities of a second conductivity type into the second upper surface (302) and the first upper surface (301) by using the mask window, and respectively forming a heavily doped source electrode (07) of the first conductivity type and a heavily doped gate electrode (06) of the second conductivity type after activation;
step seven: and depositing an insulating medium layer (10), selectively etching a through hole on the insulating medium layer (10), depositing metal and selectively etching the metal to form a source metal (08), a gate metal (09) and a drain metal (01).
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| JP2001196602A (en) * | 2000-01-12 | 2001-07-19 | Hitachi Ltd | Electrostatic induction transistor |
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