JP4122775B2 - Vertical junction field effect transistor and method of manufacturing vertical junction field effect transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a vertical junction field effect transistor and a method for manufacturing a vertical junction field effect transistor.
[0002]
[Prior art]
A lateral junction field effect transistor (JFET) is used as a voltage control element that controls a current between a source electrode and a drain electrode by a gate voltage. The lateral JFET controls the drain current by controlling the amount of majority carriers flowing through the channel region. This control is performed by changing the width of the depletion layer in the pn junction formed in the gate region.
[0003]
[Problems to be solved by the invention]
The inventor is involved in the development of JFET. The inventor believes that there is the following method to improve the drain breakdown voltage of the JFET. One is to provide a drift region between the channel portion and the drain, and another is to lower the impurity concentration of the drift region.
[0004]
However, according to the inventor's investigation, the on-resistance of the JFET increases by any of these methods. That is, there is a demand for a JFET that can suppress an increase in on-resistance. Accordingly, an object of the present invention is to provide a vertical junction field effect transistor capable of reducing the on-resistance while maintaining a drain breakdown voltage, and a method for manufacturing the vertical junction field effect transistor.
[0005]
In order to solve this problem, the inventors have studied. As a result, in the JFET formed on the substrate, the idea of a JFET having a structure in which current flows in the direction from the front surface to the back surface of the substrate (hereinafter referred to as “vertical JFET”) was obtained. As a result of continuous investigations to reduce the on-resistance in the structure of the vertical JFET, the following invention has been made.
[0006]
[Means for Solving the Problems]
  In order to solve the above problems, a vertical junction field effect transistor according to one aspect of the present invention has a main surface, a plurality of first conductivity type drain semiconductor portions, a pn semiconductor portion, and a plurality of recesses. ,Second conductivity typeA gate semiconductor part;Of the first conductivity typeA source semiconductor portion. The pn semiconductor portion is provided on the main surface of the drain semiconductor portion, and includes a plurality of pn extending along a first conductive semiconductor region, a second conductive semiconductor region, and a plane formed by these semiconductor regions and intersecting the main surface. Has a junction. In the plurality of recesses, a plurality of pn junctions of the pn semiconductor portion are provided on every other junction line among the junction lines appearing on the surface of the pn semiconductor portion. The gate semiconductor portion is provided in each recess so as to control the conductivity of the channel semiconductor region located between adjacent recesses. The source semiconductor portion is provided on the channel semiconductor region. The channel semiconductor region is located between the drain semiconductor portion and the source semiconductor portion. At least one pn junction among the plurality of pn junctions is located between the source semiconductor portion and the drain semiconductor portion.The first conductivity type semiconductor regions and the second conductivity type semiconductor regions are alternately arranged adjacent to each other in a direction parallel to the main surface, and the dopant concentration of the first conductivity type semiconductor region of the channel semiconductor region is set to the gate semiconductor portion and The dopant concentration of the second conductive type semiconductor region of the channel semiconductor region is lower than the dopant concentration of the gate semiconductor portion and the source semiconductor portion.
[0007]
  A vertical junction field effect transistor according to another aspect of the present invention has a main surface.Of the first conductivity typeA drain semiconductor portion, a pn semiconductor portion,Second conductivity typeA gate semiconductor part;Of the first conductivity typeA source semiconductor portion. The pn semiconductor portion is provided on the main surface of the drain semiconductor portion, and includes a plurality of first conductivity type semiconductor regions and second conductivity type semiconductor regions, and a plurality of these regions extending along a plane that intersects the main surface. And a protrusion extending to include at least one pn junction of the plurality of pn junctions. The gate semiconductor portion is provided on both sides of the protrusion so as to control the conductivity of the protrusion. The source semiconductor part is provided on the protrusion.The first conductivity type semiconductor regions and the second conductivity type semiconductor regions are alternately arranged adjacent to each other in a direction parallel to the main surface, and the dopant concentration of the first conductivity type semiconductor region of the protrusion is set to the gate semiconductor portion and The dopant concentration of the second conductive type semiconductor region of the protrusion is lower than the dopant concentration of the gate semiconductor portion and the source semiconductor portion..
[0008]
  A vertical junction field effect transistor according to still another aspect of the present invention includes a drain semiconductor portion, a drift semiconductor portion,Of the second conductivity typeA first gate semiconductor portion;Of the second conductivity typeA second gate semiconductor portion, a channel semiconductor portion,Of the first conductivity typeA source semiconductor portion. Drain semiconductor part is in order on its main surfaceAdjacentIt is a first conductivity type semiconductor portion having first to fourth regions provided. The drift semiconductor portion has a first conductivity type semiconductor region provided on the first and second regions and a second conductivity type semiconductor region provided on the third and fourth regions. The first gate semiconductor portion is the first regionupperIt is provided on the drift semiconductor part. The second gate semiconductor part is the fourth region.upperIt is provided on the drift semiconductor part. The channel semiconductor portion is the second regionas well asThird areaupperIt is on the drift semiconductor portion and is provided between the first gate semiconductor portion and the second gate semiconductor portion. The source semiconductor part is provided on the channel semiconductor part.The junction surface between the first region and the second region is located between the drain semiconductor portion and the first gate semiconductor portion, and the junction surface between the third region and the fourth region is the drain semiconductor portion. The channel semiconductor portion is located between the first conductive type semiconductor region provided on the drift semiconductor portion on the second region and the drift semiconductor portion on the third region. The channel semiconductor portion has a dopant concentration in the first conductivity type semiconductor region lower than that in the first and second gate semiconductor portions and the source semiconductor portion. The dopant concentration of the second conductive type semiconductor region is lower than the dopant concentrations of the first and second gate semiconductor parts and the source semiconductor part.
[0009]
In these vertical junction field effect transistors, the channel direction is the vertical direction. Therefore, the ratio of the cross-sectional area of the channel to the total cross-sectional area of the device can be increased.
[0010]
In these vertical junction field effect transistors, the channel semiconductor portion and the gate semiconductor portion can be arranged on the drift semiconductor portion. Therefore, a desired drain breakdown voltage can be obtained depending on the thickness of the drift semiconductor portion. Further, carriers flow not only under the channel semiconductor part but also in the drift semiconductor part located under the gate semiconductor part.
[0011]
According to these vertical junction field effect transistors, the drift semiconductor portion is composed of a first conductivity type semiconductor region and a second conductivity type semiconductor region. The drift semiconductor portion having such a structure is fully depleted when the high drain voltage is applied. Therefore, the maximum value of the electric field in the drift semiconductor portion is lowered. Therefore, the thickness of the drift region can be reduced. For this reason, the on-resistance is reduced.
[0012]
The channel semiconductor portion may have a structure having a first conductivity type semiconductor region provided on the second region and the drift semiconductor portion, and a second conductivity type semiconductor region provided on the third region and the drift semiconductor portion. . Further, the source semiconductor portion may be provided on the first conductivity type semiconductor region.
[0013]
Each gate semiconductor part preferably has a structure extending in a predetermined direction. In such a vertical junction field effect transistor, since the gate semiconductor portion extends in a predetermined direction, the threshold value can be controlled by these intervals.
[0014]
The width of the first conductivity type region located in each gate semiconductor part is preferably determined so that the vertical junction field effect transistor exhibits normally-off characteristics. According to such a vertical junction field effect transistor, the width of the first conductivity type region of each gate semiconductor portion is determined so as to correspond to a value equal to or smaller than the width of the depletion layer corresponding to the built-in potential. Therefore, even when no gate voltage is applied, the channel semiconductor portion is depleted, so that a normally-off transistor can be realized.
[0015]
The channel semiconductor portion is divided into a first portion and a second portion. The first portion is sandwiched between both the first gate semiconductor portion and the second gate semiconductor portion. The second portion is located on the first portion so as not to be sandwiched between the first gate semiconductor portion and the second gate semiconductor portion.
[0016]
According to such a vertical junction field effect transistor, the gate semiconductor portion can be separated from the source semiconductor portion by forming the second portion. Thereby, the breakdown voltage between the gate and the source is improved. Further, since the distance between the channel semiconductor portion and the source semiconductor portion is taken in the vertical direction, the chip size of the transistor does not increase even if this distance is taken.
[0017]
The dopant concentration and width of the first conductive type semiconductor region and the second conductive type semiconductor region of the pn semiconductor part are such that when one of the semiconductor regions is entirely depleted, the other semiconductor region is also fully depleted. Preferably, it has been determined.
[0018]
According to such a vertical junction field effect transistor, since the first conductive type semiconductor region and the second conductive type semiconductor region can be depleted in substantially the same manner, the concentration of the electric field is alleviated.
[0019]
In the vertical junction field effect transistor, the drain semiconductor part, the pn semiconductor part, and the channel semiconductor part are preferably formed of SiC. In the vertical junction field effect transistor, the junction between the gate semiconductor portion and the channel semiconductor portion may be a heterojunction.
[0020]
  According to the manufacturing method of the vertical junction field effect transistor according to the present invention, (a) the main surface of the substrate on the first conductivity type substrateAdjacent along one direction parallel toA first conductivity type semiconductor region and a second conductivity type semiconductor region;ButForming an arrayed semiconductor portion; (b) forming a source semiconductor film of a first conductivity type on the semiconductor portion; and (c) the source semiconductor film so that the semiconductor portion is exposed.TheEtchStripedForming a source semiconductor portion; and (d)Adjacent to the first conductivity type semiconductor region and the second conductivity type semiconductor region under the source semiconductor portion, respectively.Second conductivity typeFirst and secondForming a gate semiconductor part in the semiconductor part.The dopant concentration of the first conductivity type semiconductor region of the semiconductor portion is lower than the dopant concentration of the first and second gate semiconductor portions and the source semiconductor portion, and the second conductivity type semiconductor region of the semiconductor portion. The dopant concentration of the first and second gate semiconductor parts and the source semiconductor part is lower than that of the first and second gate semiconductor parts, and the first and second gate semiconductor parts include the first conductive type semiconductor region and the second conductive type. Sandwich the junction with the semiconductor region of the moldMu.
[0021]
In such a method of manufacturing a vertical junction field effect transistor, the semiconductor portion is preferably formed by repeating a step of forming a plurality of semiconductor films.
[0022]
In such a method of manufacturing a vertical junction field effect transistor, the semiconductor part, the source semiconductor part, and the gate semiconductor part preferably include SiC.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of a vertical junction field effect transistor according to the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same or corresponding elements are denoted by the same reference numerals, and duplicate descriptions are omitted. In addition, the vertical size of the transistor in the figure does not necessarily match that of an actual transistor.
[0024]
(First embodiment)
FIG. 1 is a perspective view of a vertical JFET 1 according to the first embodiment. As shown in FIG. 1, the vertical JFET 1 has n⁺Type drain semiconductor part 2, drift semiconductor part 3, channel semiconductor part 4, p⁺Type gate semiconductor parts 51, 52, 53, n⁺Type source semiconductor portions 61, 62, 63 and a drain electrode 7. The drain electrode 7 is n⁺It is provided on the other (rear surface) of the pair of surfaces of the type drain semiconductor portion 2.
[0025]
The vertical JFET 1 has a vertical structure in which majority carriers move in the channel region in a direction (hereinafter referred to as “current direction”) from one surface of the element to the other surface. FIG. 1 shows a coordinate system. This coordinate is defined so that the current direction of the JFET is aligned with the z-axis.
[0026]
n⁺The type drain semiconductor part 2 has a pair of opposing surfaces. N⁺The type drain semiconductor part 2 can be a substrate to which a dopant is added, and in a preferred embodiment, the substrate is made of SiC (silicon carbide). As a dopant added to SiC, donor impurities such as N (nitrogen), P (phosphorus), and As (arsenic), which are Group 5 elements of the periodic table, can be used.
[0027]
n⁺The type drain semiconductor portion 2 has first and second regions 2a and 2b arranged in order in the y-axis direction on its main surface. The first and second regions 2a and 2b extend in a predetermined axial direction (x-axis direction in FIG. 1). A p-type drift semiconductor region 31 is provided in the first and second regions 2a and 2b.
[0028]
N⁺The type drain semiconductor portion 2 has first to fourteenth regions 2a to 2n arranged in order in the y-axis direction on its main surface. The first to fourteenth regions 2a to 2n extend in a predetermined axial direction (x-axis direction in FIG. 1). In the preferred embodiment, the eighth region 2h and the twelfth region 21 have substantially the same shape as the fourth region 2d, and the ninth region 2i and the thirteenth region 2m. Has substantially the same shape as the fifth region 2e. Furthermore, in a preferred embodiment, the first to fourteenth regions 2a to 2n are rectangular.
[0029]
The drift semiconductor part 3 is n⁺It is provided on the main surface of the type drain semiconductor portion 2. The drift semiconductor portion 3 includes p-type drift semiconductor regions 31, 33, 35, and 37 and n-type drift semiconductor regions 32, 34, and 36. The p-type drift semiconductor region and the n-type drift semiconductor region extend along a reference plane that extends in a direction intersecting the main surface of the drift semiconductor portion 3. In the drift semiconductor portion 3, the p-type drift semiconductor regions 31, 33, 35, and 37 are alternately arranged with the n-type drift semiconductor regions 32, 34, and 36. The drift semiconductor part 3 has a plurality of pn junctions, and these pn junctions extend along the reference plane. Numbering from the left side of FIG. 1, the odd-numbered pn junction is located between the drain semiconductor portion and the gate semiconductor portion, and the even-numbered pn junction is located between the drain semiconductor portion and the source semiconductor portion. . More specifically, the pn junction between the p-type drift semiconductor region 31 and the n-type drift semiconductor region 32 is p⁺Type gate semiconductor part 51 and n⁺It is located between the type drain semiconductor part 2. The pn junction between the n-type drift semiconductor region 32 and the p-type drift semiconductor region 33 is n⁺Type source semiconductor 61 and n⁺It is located between the type drain semiconductor part 2. The pn junction between the p-type drift semiconductor region 33 and the n-type drift semiconductor region 34 is p⁺Type gate semiconductor part 52 and n⁺It is located between the type drain semiconductor part 2. The pn junction between the n-type drift semiconductor region 34 and the p-type drift semiconductor region 35 is n⁺Type source semiconductor part 62 and n⁺It is located between the type drain semiconductor part 2. The pn junction between the p-type drift semiconductor region 35 and the n-type drift semiconductor region 36 is p⁺Type gate semiconductor portion 53 and n⁺It is located between the type drain semiconductor part 2. The pn junction between the n-type drift semiconductor region 36 and the p-type drift semiconductor region 37 is n⁺Type source semiconductor part 63 and n⁺It is located between the type drain semiconductor part 2.
[0030]
The p-type drift semiconductor regions 31, 33, 35, and 37 extend in a predetermined axial direction (x-axis direction in FIG. 1). The p-type drift semiconductor regions 31, 33, 35, and 37 have a conductivity type opposite to that of the drain semiconductor portion 2. The dopant concentration of the p-type drift semiconductor regions 31, 33, 35, 37 is n⁺Lower than the dopant concentration of the type drain semiconductor portion 2.
[0031]
The n-type drift semiconductor regions 32, 34, and 36 extend in a predetermined axial direction (x-axis direction in FIG. 1). The n-type drift semiconductor regions 32, 34, 36 have the same conductivity type as that of the drain semiconductor portion 2. The dopant concentration of the n-type drift semiconductor regions 32, 34, and 36 is n⁺Lower than the dopant concentration of the type drain semiconductor portion 2. In a preferred embodiment, the drift semiconductor portion 3 is formed of SiC (silicon carbide) to which a dopant is added.
[0032]
The channel semiconductor part 41 is p⁺Type gate semiconductor part 51 and p⁺It is arranged between the type gate semiconductor part 52. The channel semiconductor part 41 has an n-type channel semiconductor region 41a and a p-type channel semiconductor region 41b. The n-type channel semiconductor region 41 a is provided on the fourth region 2 d and the n-type drift semiconductor region 32. The n-type channel semiconductor region 41a is p⁺It is adjacent to the mold gate semiconductor part 51. The p-type channel semiconductor region 41 b is provided on the fifth region 2 e and the p-type drift semiconductor region 33. The p-type channel semiconductor region 41b is p⁺It is adjacent to the mold gate semiconductor part 52.
[0033]
The channel semiconductor part 42 is p⁺Type gate semiconductor part 52 and p⁺It is arranged between the mold gate semiconductor part 53. The channel semiconductor part 42 has an n-type channel semiconductor region 42a and a p-type channel semiconductor region 42b. The n-type channel semiconductor region 42 a is provided on the eighth region 2 h and the n-type drift semiconductor region 34. The n-type channel semiconductor region 42a is p⁺It is adjacent to the mold gate semiconductor part 52. The p-type channel semiconductor region 42 b is provided on the ninth region 2 i and the p-type drift semiconductor region 35. The p-type channel semiconductor region 42b is formed of p⁺It is adjacent to the mold gate semiconductor part 53.
[0034]
The channel semiconductor part 43 is p⁺It is arranged adjacent to the mold gate semiconductor part 53. The channel semiconductor portion 43 has an n-type channel semiconductor region 43a and a p-type channel semiconductor region 43b. The n-type channel semiconductor region 43 a is provided on the twelfth region 21 and the n-type drift semiconductor region 36. The n-type channel semiconductor region 43a is p⁺It is adjacent to the mold gate semiconductor part 53. The p-type channel semiconductor region 43 b is provided on the thirteenth region 2 m and the p-type drift semiconductor region 37.
[0035]
The channel semiconductor portions 41, 42, 43 all extend in a predetermined axial direction (x-axis direction in FIG. 1). In the preferred embodiment, the channel semiconductor portions 42 and 43 have the same shape as the channel semiconductor portion 41. The n-type channel semiconductor regions 41 a, 42 a and 43 a have the same conductivity type as that of the drain semiconductor portion 2. The dopant concentration of the n-type channel semiconductor regions 41a, 42a, and 43a is p described later.⁺Lower than the dopant concentration of the type gate semiconductor part. The p-type channel semiconductor regions 41b, 42b, and 43b have a conductivity type opposite to that of the drain semiconductor portion 2. The dopant concentration of the p-type channel semiconductor regions 41b, 42b and 43b is p described later.⁺Lower than the dopant concentration of the type gate semiconductor part.
[0036]
p⁺The type gate semiconductor portions 51, 52, and 53 are alternately arranged with the channel semiconductor portions 41, 42, and 43. p⁺Since the conductivity type of the type gate semiconductor parts 51, 52, 53 is opposite to the conductivity type of the channel semiconductor parts 41, 42, 43, p⁺A pn junction is formed at the interface between the type gate semiconductor parts 51, 52, 53 and the channel semiconductor parts 41, 42, 43. P⁺The type gate semiconductor portions 51 and 52 are along the channel semiconductor portion 41 and control the conductivity of the channel semiconductor portion. p⁺The type gate semiconductor portions 52 and 53 extend along the channel semiconductor portion 42 and controls the conductivity of the channel semiconductor portion. In the vertical JFET 1, the channel semiconductor portion 41 is p⁺Type gate semiconductor part 51 and p⁺The drain current flowing through the channel semiconductor portion 41 is p.⁺It can be controlled by the mold gate semiconductor parts 51 and 52.
[0037]
P⁺Gate electrodes 81, 82, 83 are provided on the type gate semiconductor parts 51, 52, 53. The gate electrode is connected to the wiring metal film 13a through the contact holes 12a to 12c.
[0038]
In the preferred embodiment, p⁺The type gate semiconductor portions 51, 52, and 53 are formed of SiC (silicon carbide) to which a dopant is added. As this dopant, acceptor impurities such as B (boron) and Al (aluminum) which are Group 3 elements of the periodic table can be used.
[0039]
n⁺The type source semiconductor part 61 is provided on the channel semiconductor part 41. N⁺The type source semiconductor part 62 is provided on the channel semiconductor part 42. n⁺The type source semiconductor part 63 is provided on the channel semiconductor part 43.
[0040]
n⁺The type source semiconductor parts 61, 62, 63 are n⁺The drain type semiconductor portion 2 has the same conductivity type as the conductivity type. n⁺The type source semiconductor portions 61, 62, and 63 are connected to the n-type drift semiconductor regions 32, 34, and 36 via the channel semiconductor portions 41, 42, and 43, respectively. N⁺Source electrodes 91, 92, 93 are provided on the type source semiconductor portions 61, 62, 63. The source electrode is connected to the wiring metal film 13b through the contact holes 12d to 12f.
[0041]
FIG. 2 (a) shows V_G> V_TIt is a schematic diagram which shows the channel control of the vertical type JFET. As shown in FIG. 2A, the threshold voltage V_THigher gate voltage V_GHowever, when it is applied to the gate regions 51 and 52, the width of the depletion layer (the region shown inside the broken line) formed near the interface between each gate region and the channel region 41 is narrow. Therefore, an n-type conductivity portion exists between the gate regions. As a result, the resistance of the channel region is reduced, and electrons e that are majority carriers easily flow.
[0042]
On the other hand, FIG._G<V_TIt is a schematic diagram which shows the channel control of the vertical type JFET. As shown in FIG. 2B, the threshold voltage V_TLower gate voltage V_GHowever, when it is applied to the gate regions 51 and 52, a depletion layer (a region shown inside the broken line) is formed in the channel region 41. The distance between the gate regions 51 and 52 is V_G<V_TSince the width is less than the width of the depletion layer extending at this time, the channel region is almost depleted. As a result, electrons e that are majority carriers do not flow.
[0043]
In the vertical JFET as described with reference to FIG. 2A and FIG. 2B, the voltage applied to the gate region (gate voltage) is changed so that the depletion layer is formed by the pair of gate semiconductor portions. Adjust the width to control the carrier flow rate. Thereby, the drain current is controlled.
[0044]
(Second Embodiment)
Next, a method for manufacturing the vertical JFET 1 will be described. 3 (a) to 3 (c), 4 (a), 4 (b), 5 (a), 5 (b), 6 (a), 6 (b), 7 These are explanatory drawing of the manufacturing process of vertical JFET1 which concerns on 2nd Embodiment.
[0045]
(Semiconductor film formation process)
First, n⁺A type SiC semiconductor substrate is prepared. The n-type impurity concentration of the substrate is so high that the substrate can be used as a drain semiconductor portion. As shown in FIG.⁺A SiC film 3 is formed on the surface of the type drain semiconductor portion 2 by an epitaxial growth method. In a preferred embodiment assuming a 500 V breakdown voltage, the film thickness T1 of the SiC film 3 is not less than 2.0 μm and not more than 3.0 μm. The conductivity type of the SiC film 3 is n⁺It is the same as the conductivity type of the type drain semiconductor part 2. The dopant concentration of the SiC film 3 is n⁺Lower than the dopant concentration of the type drain semiconductor portion 2. In a preferred embodiment assuming a 500 V breakdown voltage, the dopant concentration of the SiC film 3 is about 2.7 × 10.¹⁷cm^-3It is. In a later manufacturing process, n-type semiconductor layers 32, 34 and 36 are formed from SiC film 3.
[0046]
(P-type semiconductor region forming step)
With reference to FIG. 3B, a process of forming the p-type semiconductor region will be described. A dopant A1 is selectively ion-implanted into the regions 31a, 31c, 31e, and 31g formed on the n-type semiconductor layer 3 using a mask M1 having a predetermined shape made of photoresist, and p having a predetermined depth. Type semiconductor regions 311, 331, 351, 371 are formed. After forming the p-type semiconductor region, the mask M1 is removed.
[0047]
(Drift semiconductor part formation process)
With reference to FIG.3 (c), the process of forming the drift semiconductor part of desired thickness is demonstrated. That is, the semiconductor film formation step and the p-type semiconductor region formation step are alternately repeated, and the n-type semiconductor region and the p-type semiconductor region are separated by n.⁺It is formed on the type drain semiconductor part 2. As a result, the semiconductor layer 3 having a predetermined thickness T2 (z-axis direction in FIG. 3C) is formed.
[0048]
(Source region formation process)
As shown in FIG. 3C, n is formed on the surface of the semiconductor layer 3 by an epitaxial growth method.⁺A SiC film 6 for the type source layer is formed. The conductivity type of the SiC film 6 is n⁺It is the same as the conductivity type of the type drain semiconductor part 2. Further, the dopant concentration of the SiC film 6 is higher than the dopant concentration of the semiconductor layer 3.
[0049]
(Source semiconductor part formation process)
With reference to FIG. 4A, a process of forming the source semiconductor portion will be described. A mask M2 having a stripe pattern in which the photoresist extends in a predetermined axial direction (x-axis direction in the drawing) is formed. N using mask M2⁺The mold source layer is selectively etched. As a result, n covered with a resist pattern⁺A portion of the mold source layer remains unetched and n⁺The mold source semiconductor portions 61, 62, and 63 are formed. After forming the source semiconductor portion, the mask M2 is removed.
[0050]
(Gate semiconductor part formation process)
With reference to FIG. 4B, a process of forming the gate semiconductor portion will be described. The dopant A2 is selectively ion-implanted into each of the regions 3a, 3b, and 3c formed on the semiconductor layer 3 using a predetermined mask M3, and p having a predetermined depth is obtained.⁺The mold gate semiconductor parts 51, 52, 53 are formed. The dopant concentration is higher than the dopant concentration of the semiconductor layer 3. After forming the gate semiconductor portion, the mask M3 is removed.
[0051]
(Thermal oxidation process)
With reference to FIG. 5A, a process of thermally oxidizing the vertical JFET 1 will be described. The vertical JFET 1 is subjected to thermal oxidation treatment. In the thermal oxidation process, when SiC is exposed to an oxidizing atmosphere A3 at a high temperature (for example, about 900 ° C.), silicon chemically reacts with oxygen to form a silicon oxide film (SiO 2).₂) Is formed. As a result, an oxide film 10 is formed on the surface of the vertical JFET 1. Thereby, the surface of each semiconductor part is covered with an oxide film.
[0052]
(Opening formation process)
With reference to FIG.5 (b), the process of forming the opening part for forming an electrode is demonstrated. Using the photoresist as a mask, the oxide film 10 is selectively etched to form an opening. In the opening, p⁺The surface portions of the mold gate semiconductor portions 51, 52, and 53 are exposed. The exposed portions become the gate electrode openings 51a to 53a. N⁺The surface portions of the type source semiconductor portions 61, 62, and 63 are exposed. The exposed portions become source electrode openings 61a to 63a. After the opening is formed, the mask is removed.
[0053]
(Electrode formation process)
With reference to Fig.6 (a), the process of forming an electrode is demonstrated. An electrode metal film such as Ni is deposited on the surface of the vertical JFET 1. Next, a stripe pattern extending in a predetermined axial direction is formed on the photoresist. The electrode metal film is selectively etched using this mask. As a result, the portion of the electrode metal film covered with the resist pattern remains without being etched, and becomes the gate electrodes 81, 82, 83 and the source electrodes 91, 92, 93. After forming the electrode, the mask is removed.
[0054]
(Insulating film formation process)
With reference to FIG. 6B, a process of forming an insulating film will be described. The surface of the vertical JFET 1 is made of SiOD by OCD (Oxide Chemical Deposition) or the like.₂The insulating film 12 is formed. Contact holes 12 a to 12 f are opened in the insulating film 12. These contact holes 12 a to 12 f are provided so as to reach the gate electrodes 81, 82, 83 and the source electrodes 91, 92, 93.
[0055]
(Wiring process)
With reference to FIG. 7, the process of wiring a metal film is demonstrated. The wiring metal film is in contact with the gate electrodes 81, 82, 83 and the source electrodes 91, 92, 93 through the contact holes 12a-12f. N⁺The drain electrode 7 is formed so as to be in contact with the back surface of the type drain semiconductor portion 2. As a material for the wiring metal film, aluminum (Al) or Al alloy is preferable from the viewpoint of low resistance, ease of fine processing, and adhesion, but copper (Cu) or tungsten (W) may be used. It is not limited to these. Then, by performing heat treatment in an inert gas atmosphere such as nitrogen or argon at a high temperature (for example, 450 ° C.), an ohmic contact with a low contact barrier between the semiconductor and the metal is formed.
[0056]
The vertical JFET 1 shown in the first embodiment is completed through the steps described above. Vertical JFET1 is p⁺Channel semiconductor parts 41, 42, 43 are provided between the type gate semiconductor parts 51, 52, 53. According to this structure, the channel direction is the vertical direction. Therefore, the ratio of the cross-sectional area of the channel to the total cross-sectional area of the device can be increased.
[0057]
In order to realize a normally-off type JFET, the channel widths W1 to W2 (in the y-axis direction in the figure) must be equal to or less than the width of the depletion layer at the time of zero bias. Therefore, the vertical JFET 1 has a structure in which the drain current is increased as a whole element while suppressing the channel width per unit of the channel semiconductor part by forming a plurality of channel semiconductor parts. By adopting such a structure, a vertical JFET that achieves both a normally-off type and a low on-resistance can be realized.
[0058]
In the present embodiment, the drain, source, and gate semiconductor portions are formed of SiC. SiC is superior to semiconductors such as Si (silicon) and GaAs (gallium arsenide) in the following points. That is, since the high melting point and the band gap (forbidden band width) are large, the device can be easily operated at a high temperature. Moreover, since the dielectric breakdown electric field is large, a high breakdown voltage can be achieved. Further, since the thermal conductivity is high, there is an advantage that a large current and a low loss can be easily achieved.
[0059]
According to the vertical JFET 1 in the present embodiment, the drift semiconductor portion is composed of a plurality of semiconductor regions having different conductivity types. The drift semiconductor portion having such a structure is fully depleted when the high drain voltage is applied. Therefore, the maximum value of the electric field in the drift semiconductor portion is lowered. Therefore, the thickness of the drift region can be reduced. For this reason, the on-resistance is reduced.
[0060]
The p-type drift semiconductor regions 31, 33, 35, and 37 and the n-type drift semiconductor regions 32, 34, and 36 preferably have substantially the same dopant concentration. In a preferred embodiment assuming a 500V breakdown voltage, the dopant concentrations of the p-type semiconductor regions 31, 33, 35, and 37 and the n-type semiconductor regions 32, 34, and 36 are approximately 2.7 × 10.¹⁷cm^-3It is. In a preferred embodiment assuming a 500V breakdown voltage, the widths (in the y-axis direction in the figure) of the p-type semiconductor regions 31, 33, 35, and 37 and the n-type semiconductor regions 32, 34, and 36 are about 0.5 μm. It is. As a result, when the entire p-type semiconductor region is depleted, the entire n-type semiconductor region is also depleted. Therefore, the concentration of the electric field is alleviated.
[0061]
According to the method for manufacturing the vertical JFET 1 in the second embodiment, the dopant is implanted when the p-type drift semiconductor region is formed. Since the diffusion coefficient of the dopant in SiC is lower than the diffusion coefficient of the dopant in Si, the widths W3 to W6 of the p-type drift semiconductor region compared to the case where the p-type drift semiconductor region is formed of Si (in FIG. 7). (y-axis direction) can be reduced.
[0062]
(Third embodiment)
The present embodiment relates to a manufacturing method different from that of the second embodiment in the source semiconductor portion forming step and the gate semiconductor portion forming step of the vertical JFET 1. That is, in the second embodiment, the gate semiconductor portion is formed by ion implantation, but in this embodiment, the gate semiconductor portion is formed through the following steps. Since steps other than the source semiconductor portion forming step and the gate semiconductor portion forming step are the same as those in the second embodiment, the same reference numerals are given to the respective components, and the description and illustration thereof are omitted.
[0063]
(Source semiconductor part formation process)
With reference to FIG. 8A, a process of forming the source semiconductor portion will be described. A mask M4 having a stripe pattern in which the photoresist extends in a predetermined axial direction (x-axis direction in the figure) is formed. N using mask M4⁺The mold source layer is selectively etched. As a result, n covered with a resist pattern⁺A portion of the mold source layer remains unetched and n⁺The mold source semiconductor portions 61, 62, and 63 are formed. In this embodiment, etching is performed deeper than in the second embodiment in order to obtain a region for forming a gate semiconductor portion. After forming the source semiconductor portion, the mask M4 is removed.
[0064]
(Gate semiconductor part formation process)
With reference to FIG. 8B, a process of forming the gate semiconductor portion will be described. Polysilicon films 51, 52, and 53 are formed in regions 3d, 3e, and 3f on the surface of the n-type semiconductor layer 3 using a predetermined mask. The polysilicon film is formed by, for example, SiH using a chemical vapor deposition method._FourGrowing by thermally decomposing (silane). The conductivity type of the polysilicon film is n⁺It is opposite in conductivity type to the type drain semiconductor part 2. Further, the dopant concentration of the polysilicon film is higher than the dopant concentration of the n-type semiconductor layer 3.
[0065]
According to the manufacturing method shown in the third embodiment, the channel semiconductor part and the gate semiconductor part can be formed in a heterojunction.
[0066]
(Fourth embodiment)
The source semiconductor portion is not limited to the shape shown in the above embodiments. FIG. 9A shows n of the vertical JFET 1 in the first embodiment.⁺It is the elements on larger scale showing the shape of a type source semiconductor part. n⁺As shown in FIG. 9A, the type source semiconductor portion 61 is disposed on the channel semiconductor regions 412a and 412b.
[0067]
On the other hand, FIG. 9B shows n of the vertical JFET in the fourth embodiment.⁺It is the elements on larger scale which show a type | mold source semiconductor part. In the vertical JFET in the present embodiment, n⁺The type source semiconductor portion 61 is disposed on the channel semiconductor region 412a as shown in FIG. 9B.
[0068]
In any of the vertical JFETs according to any of these embodiments, the channel semiconductor portion is divided into first regions 411a and 411b and second regions 412a and 412b. The first regions 411a and 411b have p⁺Type gate semiconductor part 51 and p⁺It is sandwiched between both of the gate semiconductor parts 52. The second regions 412a and 412b have p⁺Type gate semiconductor part 51 and p⁺It is located on the first regions 411a and 411b so as not to be sandwiched between the mold gate semiconductor portions 52. By forming the second regions 412a and 412b, the channel region is changed to n⁺It can be separated from the mold source semiconductor part 61. Thereby, the breakdown voltage between the gate and the source is improved. The channel semiconductor portion and n⁺Since the distance to the type source semiconductor unit 61 is taken in the current direction (the z-axis direction in FIG. 9A), the chip size of the vertical JFET 1 does not increase even if the distance is taken.
[0069]
Note that the vertical JFET 1 and the manufacturing method thereof according to the present invention are not limited to the modes described in the above embodiments, and various modifications can be made according to other conditions. For example, in each of the above embodiments, the example in which the channel region is formed using an n-type semiconductor containing a donor impurity has been described. However, the present invention can also be applied to a JFET in which the channel region is formed using a p-type semiconductor. However, in this case, the current direction and the polarity of the applied gate voltage are reversed.
[0070]
Further, the dopant concentration and thickness of the semiconductor part other than the drift semiconductor part are determined by whether or not the vertical JFET is a normally-off type and the current capacity of the entire device. Therefore, although not directly related to the realization of the high breakdown voltage vertical JFET which is the object of the present invention, in a preferred embodiment, the channel length (x-axis direction in the figure) is the channel width (y-axis direction in the figure). 15 times or more and 20 times or less.
[0071]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the vertical junction field effect transistor which can reduce on-resistance while maintaining a drain proof pressure, and a vertical junction field effect transistor can be provided.
[Brief description of the drawings]
FIG. 1 is a perspective view of a vertical JFET according to a first embodiment.
FIG. 2 (a) shows V_G> V_TIt is a schematic diagram which shows the channel control of the vertical type JFET. FIG. 2 (b) shows V_G<V_TIt is a schematic diagram which shows the channel control of the vertical type JFET.
FIG. 3A is a perspective view of a vertical JFET in a drift region forming step. FIG. 3B is a perspective view of the vertical JFET in the p-type semiconductor region forming step. FIG. 3C is a perspective view of the vertical JFET in the source region forming step.
FIG. 4A is a perspective view of a vertical JFET in a source semiconductor part formation step. FIG. 4B is a perspective view of the vertical JFET in the gate semiconductor portion forming step.
FIG. 5 (a) is a perspective view of a vertical JFET in an oxide film forming step. FIG. 5B is a perspective view of the vertical JFET in the electrode region forming step.
FIG. 6A is a perspective view of a vertical JFET in an electrode forming process. FIG. 6B is a perspective view of the vertical JFET in the insulating film forming step.
FIG. 7 is a perspective view of a vertical JFET in a wiring process.
FIG. 8A is a perspective view of a vertical JFET in a gate region forming step. FIG. 8B is a perspective view of the vertical JFET in the gate semiconductor portion forming step.
FIG. 9A is a partially enlarged view of a vertical JFET according to a fourth embodiment. FIG. 9B is a partially enlarged view of a vertical JFET showing another embodiment.
[Explanation of symbols]
1 ... Vertical JFET, 2 ... n⁺Type drain semiconductor part, 31, 33, 35, 37... P type drift semiconductor area, 32, 34, 36... N type drift semiconductor area, 41, 42, 43... Channel semiconductor part, 51, 52, 53.⁺Type gate semiconductor part, 61, 62, 63... N⁺Type source semiconductor part, 7 ... drain electrode, 81, 82, 83 ... gate electrode, 91, 92, 93 ... source electrode

Claims (13)

A drain semiconductor portion of a first conductivity type having a main surface;
Provided on the main surface of the drain semiconductor portion, a plurality of first conductive semiconductor regions, a second conductive semiconductor region, and a plurality of pn junctions formed by these semiconductor regions and extending along a plane intersecting the main surface A pn semiconductor portion having
A plurality of recesses provided on every other junction line among the junction lines appearing on the surface of the pn semiconductor portion, wherein the plurality of pn junctions of the pn semiconductor portion are;
A gate semiconductor portion of a second conductivity type provided in each recess so as to control the conductivity of a channel semiconductor region located between adjacent recesses;
A source semiconductor portion of a first conductivity type provided on the channel semiconductor region,
The first conductivity type semiconductor regions and the second conductivity type semiconductor regions are alternately arranged adjacent to each other in a direction parallel to the main surface,
The dopant concentration of the first conductivity type semiconductor region of the channel semiconductor region is lower than the dopant concentration of the gate semiconductor part and the source semiconductor part,
The dopant concentration of the second conductivity type semiconductor region of the channel semiconductor region is lower than the dopant concentration of the gate semiconductor part and the source semiconductor part,
The channel semiconductor region is located between the drain semiconductor portion and the source semiconductor portion,
At least one pn junction among the plurality of pn junctions is a vertical junction field effect transistor positioned between the source semiconductor portion and the drain semiconductor portion. A drain semiconductor portion of a first conductivity type having a main surface;
A plurality of first and second conductive semiconductor regions provided on the main surface of the drain semiconductor portion, and a plurality of pn junctions formed by these semiconductor regions and extending along a plane intersecting the main surface And a pn semiconductor portion having a protrusion extending to include at least one pn junction of the plurality of pn junctions;
A gate semiconductor portion of a second conductivity type provided on both sides of the protrusion so as to control the conductivity of the protrusion;
A source semiconductor portion of a first conductivity type provided on the protrusion ,
The first conductivity type semiconductor regions and the second conductivity type semiconductor regions are alternately arranged adjacent to each other in a direction parallel to the main surface,
The dopant concentration of the first conductive type semiconductor region of the protrusion is lower than the dopant concentration of the gate semiconductor portion and the source semiconductor portion,
A vertical junction field effect transistor , wherein a dopant concentration of the second conductive semiconductor region of the protrusion is lower than a dopant concentration of the gate semiconductor portion and the source semiconductor portion . A drain semiconductor portion of the first conductivity type having first to fourth regions provided adjacent to the main surface in order;
A drift semiconductor portion having a first conductivity type semiconductor region provided on the first and second regions and a second conductivity type semiconductor region provided on the third and fourth regions;
A first gate semiconductor portion of a second conductivity type provided on the drift semiconductor portion on the first region ;
A second gate semiconductor portion of a second conductivity type provided on the drift semiconductor portion on the fourth region ;
A channel semiconductor portion provided on the drift semiconductor portion on the second region and the third region and provided between the first gate semiconductor portion and the second gate semiconductor portion;
E Bei a first conductivity type source semiconductor portion provided on the channel semiconductor portion,
The junction surface between the first region and the second region is located between the drain semiconductor portion and the first gate semiconductor portion,
The junction surface between the third region and the fourth region is located between the drain semiconductor portion and the second gate semiconductor portion,
The channel semiconductor portion includes a first conductivity type semiconductor region provided on the drift semiconductor portion on the second region and a second conductivity type semiconductor provided on the drift semiconductor portion on the third region. Consisting of areas,
The dopant concentration of the first conductivity type semiconductor region of the channel semiconductor portion is lower than the dopant concentration of the first and second gate semiconductor portions and the source semiconductor portion,
The vertical junction field effect transistor , wherein a dopant concentration of the second conductivity type semiconductor region of the channel semiconductor portion is lower than a dopant concentration of the first and second gate semiconductor portions and a source semiconductor portion . The vertical junction field effect transistor according to claim 3 , wherein the source semiconductor portion is provided on the first conductive semiconductor region of the channel semiconductor portion . The first conductive type semiconductor region and the second conductive type semiconductor region are arranged in a first direction along the main surface,
3. The vertical junction field effect transistor according to claim 1 , wherein the gate semiconductor portion extends in a second direction that intersects the first direction and extends along the main surface . 4. 5. The vertical junction type according to claim 3 , wherein a width of the first conductivity type semiconductor region of the channel semiconductor portion is determined so that the vertical junction field effect transistor exhibits normally-off characteristics. Field effect transistor. The channel semiconductor part is further divided into a first part and a second part,
The first portion is sandwiched between both the first gate semiconductor portion and the second gate semiconductor portion,
The second portion, the first so as not to be sandwiched between the second gate semiconductor portion and the gate semiconductor unit is located on the first part, 3, 4 and The vertical junction field effect transistor according to claim 6 . The dopant concentration and width of the first conductive type semiconductor region and the second conductive type semiconductor region in the drift semiconductor portion are simultaneously depleted in the entire first conductive type semiconductor region and the second conductive type semiconductor region . The vertical junction field effect transistor according to any one of claims 3, 4, 6, and 7 , which is determined as follows. The vertical junction field effect transistor according to claim 1, wherein the drain semiconductor part and the pn semiconductor part are formed of SiC. The vertical type according to claim 3 , wherein the junction between the first and second gate semiconductor parts and the channel semiconductor part is a heterojunction. Junction field effect transistor. A semiconductor portion in which a first conductivity type semiconductor region and a second conductivity type semiconductor region are arranged adjacent to each other along one direction parallel to the main surface of the substrate is formed on the first conductivity type substrate. Process,
Forming a source semiconductor film of a first conductivity type on the semiconductor portion;
Etching the source semiconductor film to expose the semiconductor portion to form a striped source semiconductor portion;
Second conductive type first and second gate semiconductor portions are formed in the semiconductor portion so as to be adjacent to the first conductive type semiconductor region and the second conductive type semiconductor region below the source semiconductor portion, respectively. and a step seen including,
The dopant concentration of the first conductivity type semiconductor region of the semiconductor portion is lower than the dopant concentration of the first and second gate semiconductor portions and the source semiconductor portion,
The dopant concentration of the second conductivity type semiconductor region of the semiconductor portion is lower than the dopant concentration of the first and second gate semiconductor portions and the source semiconductor portion,
The first and second manufacturing method of the gate semiconductor portion sandwiched no vertical junction field effect transistor of the junction of the first conductivity type semiconductor region and the second conductivity type semiconductor region. In the step of forming the semiconductor part,
A first step of forming a semiconductor layer of a first conductivity type;
A second step of selectively ion-implanting the first conductivity type semiconductor layer to form a second conductivity type semiconductor layer having a predetermined depth;
A third step of repeating the first and second steps to form the first conductive type semiconductor region and the second conductive type semiconductor region;
The manufacturing method of the vertical junction field effect transistor of Claim 11 containing this . The method for manufacturing a vertical junction field effect transistor according to claim 11 , wherein the semiconductor part, the substrate , and the gate semiconductor part contain SiC.

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