JP2003023099A - Field effect transistor - Google Patents

Field effect transistor

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Publication number
JP2003023099A
JP2003023099A JP2001209355A JP2001209355A JP2003023099A JP 2003023099 A JP2003023099 A JP 2003023099A JP 2001209355 A JP2001209355 A JP 2001209355A JP 2001209355 A JP2001209355 A JP 2001209355A JP 2003023099 A JP2003023099 A JP 2003023099A
Authority
JP
Japan
Prior art keywords
region
type sic
effect transistor
field effect
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001209355A
Other languages
Japanese (ja)
Inventor
Masakatsu Hoshi
星　　正勝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
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Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP2001209355A priority Critical patent/JP2003023099A/en
Publication of JP2003023099A publication Critical patent/JP2003023099A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor wherein the power loss of a built-in diode is suppressed by reducing the forward voltage drop of the built-in diode which bypasses the reverse current between a drain and a source. SOLUTION: On the surface layer of one main side of a P-type SiC substrate 10, a P<+> -type SiC region 20, an N<+> -type SiC source region 30, and both N-type SiC drain region 40 and N<+> -type SiC drain region 50, located away from the P<+> -type SiC region 20 and the N<+> -type SiC source region 30, are formed. A gate insulating film 70 is formed so as to cover the surface of a P-type region between the N<+> -type SiC source region 30 and the N-type SiC drain region 40. Further, a gate electrode 80, a source electrode 100, and a drain electrode 110 are formed. A Schottky connection 120 is formed between a part of the drain electrode 110 and a P-type SiC substrate 10.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、電界効果トランジ
スタに係り、特にドレイン・基板間の逆方向電流バイパ
ス用のダイオードを内蔵した電界効果トランジスタに関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a field effect transistor having a diode for a reverse current bypass between a drain and a substrate incorporated therein.

【０００２】[0002]

【従来の技術】従来のＳｉＣ（炭化珪素）電界効果トラ
ンジスタとしては、例えば特開平９−７４１９１号公報
に記載されたものがある。図９は上記従来例の構造を示
す断面図である。2. Description of the Related Art As a conventional SiC (silicon carbide) field effect transistor, for example, there is one described in Japanese Patent Application Laid-Open No. 9-74191. FIG. 9 is a sectional view showing the structure of the conventional example.

【０００３】図９において、Ｎ＋型ＳｉＣ基板１３５の
上にＮ型ＳｉＣエピタキシャル領域１４５が形成されて
いる。さらにＮ型ＳｉＣエピタキシャル領域１４５の上
にＰ型ＳｉＣエピタキシャル領域１４０が形成され、該
Ｐ型ＳｉＣエピタキシャル領域１４５内に溝１５５およ
びＮ＋型ＳｉＣソース領域３０が形成されている。ま
た、溝１５５の側壁にＮ型ＳｉＣチャンネル領域１８０
が形成され、溝１５５内にはゲート絶縁膜７０を介して
ゲート電極８０が形成されている。そして、ゲート電極
８０とは絶縁膜９０により絶縁されてソース電極１００
が形成されている。また、Ｎ＋型ＳｉＣ基板１３５の裏
面にはドレイン電極１１０が形成されている。In FIG. 9, an N-type SiC epitaxial region 145 is formed on an N + -type SiC substrate 135. Further, a P-type SiC epitaxial region 140 is formed on the N-type SiC epitaxial region 145, and a groove 155 and an N + -type SiC source region 30 are formed in the P-type SiC epitaxial region 145. In addition, the N-type SiC channel region 180 is formed on the sidewall of the groove 155.
And a gate electrode 80 is formed in the groove 155 via the gate insulating film 70. Then, the source electrode 100 is insulated from the gate electrode 80 by the insulating film 90.
Are formed. A drain electrode 110 is formed on the back surface of the N + type SiC substrate 135.

【０００４】このＳｉＣ電界効果トランジスタは、ドレ
イン電極１１０とソース電極１００との間に電圧が印加
された状態で、ゲート電極８０に電圧が印加されると、
ゲート電極８０に対向したＮ型ＳｉＣチャンネル領域１
８０の表面にＮ型蓄積層チャンネル領域が形成され、ド
レイン電極１１０からソース電極１００に電流が流れ
る。In this SiC field effect transistor, when a voltage is applied to the gate electrode 80 while a voltage is applied between the drain electrode 110 and the source electrode 100,
N-type SiC channel region 1 facing the gate electrode 80
An N-type storage layer channel region is formed on the surface of 80, and a current flows from the drain electrode 110 to the source electrode 100.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、図９に
示した従来例においては、Ｐ型ＳｉＣエピタキシャル領
域１４０とＮ型ＳｉＣエピタキシャル領域で構成される
内蔵ダイオードをＬ負荷駆動用のフリーホイルダイオー
ドとして用いる時、ＳｉＣのビルトインポテンシャルが
高いため内蔵ダイオードの順方向電圧ドロップが大き
く、内蔵ダイオードの電力損失が大きいという問題点が
あった。また、ドレイン電極１１０に高電圧のサージ電
圧が印加されたとき、ゲート絶縁膜７０に電圧が加わる
ので、ゲート絶縁膜の信頼性が低下するという問題点が
あった。However, in the conventional example shown in FIG. 9, the built-in diode composed of the P-type SiC epitaxial region 140 and the N-type SiC epitaxial region is used as a free wheel diode for driving the L load. At this time, since the built-in potential of SiC is high, the forward voltage drop of the built-in diode is large and the power loss of the built-in diode is large. Further, when a high-voltage surge voltage is applied to the drain electrode 110, a voltage is applied to the gate insulating film 70, so that there is a problem that reliability of the gate insulating film is lowered.

【０００６】以上の問題点に鑑み、本発明の目的は、ド
レイン・ソース間の逆方向電流をバイパスする内蔵ダイ
オードの順方向電圧ドロップを低下させ、内蔵ダイオー
ドの電力損失を抑制した電界効果トランジスタを提供す
ることである。In view of the above problems, an object of the present invention is to provide a field effect transistor in which a forward voltage drop of a built-in diode that bypasses a reverse current between a drain and a source is reduced and power loss of the built-in diode is suppressed. Is to provide.

【０００７】また本発明の目的は、ドレイン電極にサー
ジ電圧が印加されてもゲート絶縁膜の信頼性を維持する
ことができる電界効果トランジスタを提供することであ
る。It is another object of the present invention to provide a field effect transistor which can maintain the reliability of the gate insulating film even when a surge voltage is applied to the drain electrode.

【０００８】[0008]

【課題を解決するための手段】請求項１記載の発明は、
上記目的を達成するために、第１導電型の半導体基板の
表層にそれぞれ形成された第２導電型のドレイン領域及
び第２導電型のソース領域と、ゲート電圧によって伝導
度が変調されるチャンネル領域と、を具備した電界効果
トランジスタにおいて、ドレイン電極、ソース電極、お
よびゲート電極が前記半導体基板の同一表面上に形成さ
れており、前記ドレイン電極が前記半導体基板の一部と
ショットキー接続されていることを要旨とする。The invention according to claim 1 is
To achieve the above object, a second conductivity type drain region and a second conductivity type source region respectively formed on a surface layer of a first conductivity type semiconductor substrate, and a channel region whose conductivity is modulated by a gate voltage. A drain electrode, a source electrode, and a gate electrode are formed on the same surface of the semiconductor substrate, and the drain electrode is Schottky-connected with a part of the semiconductor substrate. That is the summary.

【０００９】請求項２記載の発明は、上記目的を達成す
るために、請求項１に記載の電界効果トランジスタにお
いて、前記半導体基板の前記表面に前記ドレイン領域と
接する溝が形成され、該溝内に形成されたドレイン電極
が前記半導体基板の一部とショットキー接続されている
ことを要旨とする。According to a second aspect of the present invention, in order to achieve the above object, in the field effect transistor according to the first aspect, a groove which is in contact with the drain region is formed on the surface of the semiconductor substrate, and the groove is formed in the groove. The gist of the present invention is that the drain electrode formed on the substrate is Schottky-connected to a part of the semiconductor substrate.

【００１０】請求項３記載の発明は、上記目的を達成す
るために、請求項２に記載の電界効果トランジスタにお
いて、前記ショットキー接続の逆方向耐電圧が、前記第
１導電型の半導体基板と前記第２導電型のドレイン領域
との接合の逆方向耐電圧より低いことを要旨とする。According to a third aspect of the present invention, in order to achieve the above object, in the field effect transistor according to the second aspect, the reverse withstand voltage of the Schottky connection is the same as that of the semiconductor substrate of the first conductivity type. The gist is that it is lower than the reverse withstand voltage of the junction with the drain region of the second conductivity type.

【００１１】請求項４記載の発明は、上記目的を達成す
るために、請求項１乃至請求項３の何れか１項に記載の
電界効果トランジスタにおいて、前記第１導電型の半導
体基板と前記ショットキー電極との接続面に第２の第１
導電型の領域が形成されていることを要旨とする。According to a fourth aspect of the invention, in order to achieve the above object, in the field effect transistor according to any one of the first to third aspects, the semiconductor substrate of the first conductivity type and the shot are used. The second first on the connection surface with the key electrode
The gist is that a conductive type region is formed.

【００１２】請求項５記載の発明は、上記目的を達成す
るために、請求項１乃至請求項４の何れか１項に記載の
電界効果トランジスタにおいて、前記半導体基板が炭化
珪素であることを要旨とする。In order to achieve the above object, a fifth aspect of the present invention is the field effect transistor according to any one of the first to fourth aspects, wherein the semiconductor substrate is silicon carbide. And

【００１３】[0013]

【発明の効果】請求項１記載の発明によれば、第１導電
型の半導体基板の表層にそれぞれ形成された第２導電型
のドレイン領域及び第２導電型のソース領域と、ゲート
電圧によって伝導度が変調されるチャンネル領域と、を
具備した電界効果トランジスタにおいて、ドレイン電
極、ソース電極、およびゲート電極が前記半導体基板の
同一表面上に形成されており、前記ドレイン電極が前記
半導体基板の一部とショットキー接続されているので、
ドレイン・ソース間逆方向電圧をショットキー接続ダイ
オードの順方向電流としてバイパスすることができ、バ
イパス時の電圧降下量及び電力損失を小さくすることが
できるという効果がある。According to the first aspect of the present invention, the second conductivity type drain region and the second conductivity type source region respectively formed on the surface layer of the first conductivity type semiconductor substrate and the conduction by the gate voltage. In a field effect transistor having a channel region whose degree is modulated, a drain electrode, a source electrode, and a gate electrode are formed on the same surface of the semiconductor substrate, and the drain electrode is a part of the semiconductor substrate. Since it is connected with Schottky,
The reverse voltage between the drain and the source can be bypassed as the forward current of the Schottky-connected diode, and the voltage drop amount and power loss at the time of bypass can be reduced.

【００１４】また、請求項２記載の発明によれば、請求
項１記載の発明の効果に加えて、前記半導体基板の前記
表面に前記ドレイン領域と接する溝が形成され、該溝内
に形成されたドレイン電極が前記半導体基板の一部とシ
ョットキー接続されているので、素子の集積度が向上し
チップサイズを縮小することができるという効果があ
る。According to the invention of claim 2, in addition to the effect of the invention of claim 1, a groove which is in contact with the drain region is formed on the surface of the semiconductor substrate and is formed in the groove. Further, since the drain electrode is Schottky connected to a part of the semiconductor substrate, there is an effect that the integration degree of the device is improved and the chip size can be reduced.

【００１５】また、請求項３記載の発明によれば、請求
項２記載の発明の効果に加えて、前記ショットキー接続
の逆方向耐電圧が、前記第１導電型の半導体基板と前記
第２導電型のドレイン領域との接合の逆方向耐電圧より
低くしたので、サージ電圧は溝底部のショットキー接続
に印加され、ゲート絶縁膜が高電圧に曝されることがな
くなってゲート絶縁膜の信頼性を向上させることができ
るという効果がある。Further, according to the invention of claim 3, in addition to the effect of the invention of claim 2, the reverse withstand voltage of the Schottky connection has the first conductivity type semiconductor substrate and the second conductivity type. Since it is lower than the reverse withstand voltage of the junction with the conductivity type drain region, the surge voltage is applied to the Schottky connection at the bottom of the trench, and the gate insulating film is not exposed to high voltage, and the reliability of the gate insulating film is improved. There is an effect that the property can be improved.

【００１６】また、請求項４記載の発明によれば、請求
項１乃至請求項３記載の発明の効果に加えて、前記第１
導電型の半導体基板と前記ショットキー電極との接続面
に第２の第１導電型の領域が形成されるようにしたの
で、第２の第１導電型の領域が担うショットキー接続の
耐電圧をチャンネル濃度とは独立に設計できるようにな
り、電界効果トランジスタの設計が容易となるという効
果がある。According to the invention of claim 4, in addition to the effects of the invention of claims 1 to 3, the first invention
Since the second first conductivity type region is formed on the connection surface between the conductivity type semiconductor substrate and the Schottky electrode, the withstand voltage of the Schottky connection carried by the second first conductivity type region. Can be designed independently of the channel concentration, and the field effect transistor can be easily designed.

【００１７】また、請求項５記載の発明によれば、請求
項１乃至請求項４記載の発明の効果に加えて、前記半導
体基板を炭化珪素としたので、シリコンに比べてバンド
ギャップが大きく、高温度下の使用に耐える電力用制御
素子を提供できるという効果がある。Further, according to the invention of claim 5, in addition to the effects of the inventions of claims 1 to 4, since the semiconductor substrate is made of silicon carbide, the band gap is larger than that of silicon, The effect is to provide a power control element that can withstand use at high temperatures.

【００１８】[0018]

【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照して詳細に説明する。 〔第１の実施形態〕図１は、本発明に係る電界効果トラ
ンジスタの第１の実施形態の構成を説明する断面図であ
る。図１において、Ｐ型ＳｉＣ基板１０の一主面側の表
層にＰ＋型ＳｉＣ領域２０が形成され、Ｐ＋型ＳｉＣ領
域２０に接してＮ＋型ＳｉＣソース領域３０が形成され
ている。また、同じ表層に、Ｐ＋型ＳｉＣ領域２０及び
Ｎ＋型ＳｉＣソース領域３０から離隔してＮ型ＳｉＣド
レイン領域４０が形成され、Ｎ型ＳｉＣドレイン領域４
０と前記主面に接してＮ＋型ＳｉＣドレイン領域５０が
形成されている。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. [First Embodiment] FIG. 1 is a sectional view for explaining the configuration of a first embodiment of a field effect transistor according to the present invention. In FIG. 1, a P + type SiC region 20 is formed in the surface layer on the one main surface side of the P type SiC substrate 10, and an N + type SiC source region 30 is formed in contact with the P + type SiC region 20. Further, an N-type SiC drain region 40 is formed on the same surface layer apart from the P + -type SiC region 20 and the N + -type SiC source region 30, and the N-type SiC drain region 4 is formed.
An N + type SiC drain region 50 is formed in contact with 0 and the main surface.

【００１９】また、Ｐ型ＳｉＣ基板１０の前記主面側
に、Ｎ＋型ＳｉＣソース領域３０とＮ型ＳｉＣドレイン
領域４０との間のＰ型領域、及びこのＰ型領域の両端に
それぞれ接するＮ＋型ＳｉＣソース領域３０の一部とＮ
型ＳｉＣドレイン領域４０の一部との表面を覆うように
ゲート絶縁膜７０が形成されている。ゲート絶縁膜７０
のＮ型ＳｉＣドレイン領域４０側の端部は、絶縁膜６０
に接続され、絶縁膜６０は、Ｎ型ＳｉＣドレイン領域４
０の残部及びこれに接するＮ＋型ＳｉＣドレイン領域５
０の一部の表面を覆うように形成されている。Further, on the main surface side of the P-type SiC substrate 10, a P-type region between the N + -type SiC source region 30 and the N-type SiC drain region 40, and N + -type regions contacting both ends of the P-type region, respectively. Part of the SiC source region 30 and N
Gate insulating film 70 is formed so as to cover the surface of part of type SiC drain region 40. Gate insulating film 70
The end of the N type SiC drain region 40 side of the insulating film 60 is
And the insulating film 60 is connected to the N-type SiC drain region 4
The rest of 0 and N + type SiC drain region 5 in contact therewith
It is formed so as to cover a part of the surface of 0.

【００２０】また、絶縁膜６０およびゲート絶縁膜７０
を介してゲート電極８０が形成され、絶縁膜９０によっ
てゲート電極８０と絶縁されて、且つＰ＋型ＳｉＣ領域
２０及びＮ＋型ＳｉＣソース領域３０のそれぞれの表面
に接してソース電極１００が形成されている。Further, the insulating film 60 and the gate insulating film 70.
The gate electrode 80 is formed via the insulating film 90, and the source electrode 100 is formed so as to be insulated from the gate electrode 80 by the insulating film 90 and in contact with the respective surfaces of the P + type SiC region 20 and the N + type SiC source region 30. .

【００２１】さらに、絶縁膜９０によってゲート電極８
０と絶縁されて、且つＮ＋型ＳｉＣドレイン領域５０及
びＰ型ＳｉＣ基板１０のそれぞれの表面に接してドレイ
ン電極１１０が形成されている。この時、ドレイン電極
１１０の一部とＰ型ＳｉＣ基板１０との間にショットキ
ー接続１２０が形成されている。Further, the gate electrode 8 is formed by the insulating film 90.
A drain electrode 110 is formed so as to be insulated from 0 and in contact with the respective surfaces of the N + type SiC drain region 50 and the P type SiC substrate 10. At this time, the Schottky connection 120 is formed between a part of the drain electrode 110 and the P-type SiC substrate 10.

【００２２】次に、本実施形態の電界効果トランジスタ
の動作を説明する。ドレイン電極１１０とソース電極１
００との間に電圧が印加された状態で、ゲート電極８０
に電圧が印加されると、ゲート電極８０に対向したＰ型
ＳｉＣ基板の表面にＮ型反転層のチャンネル領域が形成
され、ゲート電圧に応じてドレイン電極１１０からソー
ス電極１００に電流が流れる。このとき、チャンネル領
域としてあらかじめＮ型の蓄積層型チャンネル領域を形
成してもよく、この場合反転層型のチャンネルに比べて
電子の移動度が向上し、チャンネル抵抗を低減できると
いった効果が得られる。また、半導体基板として、特に
ＳｉＣ半導体では良好なショットキー接続面が形成しや
すく、耐圧の高いショットキー接続が形成し易い。Next, the operation of the field effect transistor of this embodiment will be described. Drain electrode 110 and source electrode 1
00 and the voltage is applied between the gate electrode 80 and
When a voltage is applied to the gate electrode 80, a channel region of the N-type inversion layer is formed on the surface of the P-type SiC substrate facing the gate electrode 80, and a current flows from the drain electrode 110 to the source electrode 100 according to the gate voltage. At this time, an N-type storage layer type channel region may be formed in advance as the channel region. In this case, the electron mobility is improved and the channel resistance can be reduced as compared with the inversion layer type channel. . Further, as a semiconductor substrate, particularly a SiC semiconductor, a good Schottky connection surface is easily formed, and a Schottky connection having a high breakdown voltage is easily formed.

【００２３】次に、本実施形態の作用を説明する。ドレ
イン電極１１０の少なくともショットキー接続１２０に
面した部分に所望の仕事関数を有する電極材を用いれ
ば、該電極の仕事関数と半導体基板の電子親和力との差
のショットキー障壁高さを制御することが可能で、内蔵
ダイオードの順方向電圧ドロップの低減が可能である。Next, the operation of this embodiment will be described. If an electrode material having a desired work function is used in at least the portion of the drain electrode 110 facing the Schottky connection 120, the Schottky barrier height of the difference between the work function of the electrode and the electron affinity of the semiconductor substrate can be controlled. It is possible to reduce the forward voltage drop of the built-in diode.

【００２４】次に、第１の実施形態の電界効果トランジ
スタの製造方法を説明する。図２から図６は、第１の実
施形態の電界効果トランジスタの製造工程を示す工程順
断面図である。Next, a method of manufacturing the field effect transistor of the first embodiment will be described. 2 to 6 are cross-sectional views in order of the processes, showing the manufacturing process of the field-effect transistor of the first embodiment.

【００２５】まず、図２の工程においては、例えば不純
物濃度が１Ｅ１４〜１Ｅ１８ｃｍ-3のＰ型ＳｉＣ単結晶
基板（以下、Ｐ型ＳｉＣ基板）１０が準備され、その表
面に例えば酸化膜よりなる絶縁膜１５が一面に形成され
ている。Ｐ型ＳｉＣ基板１０は、例えばＳｉＣ多結晶粉
末から昇華法やＰＶＤ法によって、種結晶上に堆積させ
たものである。絶縁膜１５として酸化膜を用いる場合に
は、例えばＰ型ＳｉＣ基板１０を高温の酸化性雰囲気に
曝す熱酸化法により形成される。絶縁膜１５には、周知
のフォトリソグラフ法等によって、Ｐ＋型ＳｉＣ領域２
０が形成されるべき位置に孔が設けられる。First, in the step shown in FIG. 2, a P-type SiC single crystal substrate (hereinafter referred to as P-type SiC substrate) 10 having an impurity concentration of 1E14 to 1E18 cm -3 , for example, is prepared, and an insulating film made of, for example, an oxide film is formed on the surface thereof. The film 15 is formed on the entire surface. The P-type SiC substrate 10 is, for example, a SiC polycrystal powder deposited on a seed crystal by a sublimation method or a PVD method. When an oxide film is used as the insulating film 15, it is formed by, for example, a thermal oxidation method in which the P-type SiC substrate 10 is exposed to a high temperature oxidizing atmosphere. The P + type SiC region 2 is formed on the insulating film 15 by a well-known photolithography method or the like.
Holes are provided at the locations where 0s are to be formed.

【００２６】そして、絶縁膜１５をマスクとして、例え
ばイオン注入技術により不純物濃度が１Ｅ１７〜１Ｅ２
１ｃｍ-3、深さが０．１μｍ〜数μｍのＰ＋型ＳｉＣ領
域２０を形成する。Ｐ＋型ＳｉＣ領域を形成するための
アクセプター不純物としては、アルミニウム（Ａｌ）、
ホウ素（Ｂ）、ガリウム（Ｇａ）等が考えられる。Then, using the insulating film 15 as a mask, the impurity concentration is set to 1E17 to 1E2 by, for example, an ion implantation technique.
A P + type SiC region 20 having a depth of 1 cm −3 and a depth of 0.1 μm to several μm is formed. Aluminum (Al) is used as an acceptor impurity for forming the P + type SiC region.
Boron (B), gallium (Ga), etc. are considered.

【００２７】次に、図３の工程においては、同様に、図
示しないパターン化された絶縁膜をマスクとして、例え
ばイオン注入技術により不純物濃度が１Ｅ１７〜１Ｅ２
１ｃｍ-3で深さが０．１μｍ〜数μｍのＮ＋型ＳｉＣソ
ース領域３０、不純物濃度が１Ｅ１４〜１Ｅ１９ｃｍ-3
で深さが０．１μｍ〜数μｍのＮ型ＳｉＣドレイン領域
４０、不純物濃度が１Ｅ１７〜１Ｅ２１ｃｍ-3で深さが
０．１μｍ〜数μｍのＮ＋型ＳｉＣドレイン領域５０を
形成する。Ｎ＋型ＳｉＣ領域およびＮ型ＳｉＣ領域を形
成するドナー不純物としては、窒素（Ｎ）、リン
（Ｐ）、ヒ素（Ａｓ）等が考えられる。Next, in the process of FIG. 3, similarly, using a patterned insulating film (not shown) as a mask, the impurity concentration is 1E17 to 1E2 by, for example, an ion implantation technique.
1 cm -3 at a depth of 0.1μm~ number [mu] m N + -type SiC source region 30, the impurity concentration 1E14～1E19cm -3
To form an N-type SiC drain region 40 having a depth of 0.1 μm to several μm, and an N + type SiC drain region 50 having an impurity concentration of 1E17 to 1E21 cm −3 and a depth of 0.1 μm to several μm. Nitrogen (N), phosphorus (P), arsenic (As), etc. can be considered as donor impurities forming the N + type SiC region and the N type SiC region.

【００２８】この後、例えばアルゴン（Ａｒ）等の不活
性雰囲気中で９００℃〜１８００℃の熱処理を行うこと
により、各不純物領域を活性化する。このとき、Ｐ型不
純物領域とＮ型不純物領域の活性化温度を分けて別々に
行ってもよい。After that, each impurity region is activated by performing heat treatment at 900 ° C. to 1800 ° C. in an inert atmosphere such as argon (Ar). At this time, the activation temperatures of the P-type impurity region and the N-type impurity region may be separately set.

【００２９】次に、図４の工程においては、例えば酸化
膜よりなる絶縁膜６０を所望の領域に形成する。酸化膜
の形成方法は、絶縁膜１５と同様である。Next, in the process of FIG. 4, an insulating film 60 made of, for example, an oxide film is formed in a desired region. The method of forming the oxide film is the same as that of the insulating film 15.

【００３０】次に、図５の工程においては、例えば厚さ
が１０ｎｍ（１００Å）〜５００ｎｍ（５０００Å）の
酸化膜よりなるゲート絶縁膜７０と、例えば多結晶シリ
コンよりなるゲート電極８０と、例えば酸化膜よりなる
絶縁膜９０とを所望の領域に形成する。Next, in the step of FIG. 5, a gate insulating film 70 made of an oxide film having a thickness of, for example, 10 nm (100 Å) to 500 nm (5000 Å), a gate electrode 80 made of, for example, polycrystalline silicon, and an oxide, for example, are formed. An insulating film 90 made of a film is formed in a desired region.

【００３１】次に、図６の工程においては、ソース電極
１００およびドレイン電極１１０を形成して、図１に示
す本発明の電界効果トランジスタが得られる。このと
き、ドレイン電極１１０の一部と前記Ｐ型ＳｉＣ基板１
０との間にはショットキー接続１２０が形成されてい
る。ドレイン電極１１０のショットキー接続部分または
ドレイン電極１１０の全てに所望の仕事関数の電極材を
用いて、ショットキー障壁高さの低いショットキー接続
を形成すれば良い。Next, in the step shown in FIG. 6, the source electrode 100 and the drain electrode 110 are formed to obtain the field effect transistor of the present invention shown in FIG. At this time, part of the drain electrode 110 and the P-type SiC substrate 1
A Schottky connection 120 is formed between the two and 0. A Schottky connection with a low Schottky barrier height may be formed by using an electrode material having a desired work function for the Schottky connection portion of the drain electrode 110 or the entire drain electrode 110.

【００３２】以上説明してきたように、ドレイン電極と
ソース電極との間にショットキー接続を内蔵することに
より、内蔵ダイオードの順方向電圧ドロップが下げら
れ、内蔵ダイオードの損失を低減することが可能であ
る。As described above, by incorporating the Schottky connection between the drain electrode and the source electrode, the forward voltage drop of the built-in diode can be reduced and the loss of the built-in diode can be reduced. is there.

【００３３】なお、図１の構成において、ソース電極１
００とドレイン電極１１０とのいずれか一方または両方
を二層配線構造にしてもよい。In the structure of FIG. 1, the source electrode 1
00 or the drain electrode 110, or both, may have a double-layer wiring structure.

【００３４】〔第２の実施形態〕次に、図７は本発明に
係る電界効果トランジスタの第２の実施形態を示す断面
図である。Second Embodiment Next, FIG. 7 is a sectional view showing a second embodiment of the field effect transistor according to the present invention.

【００３５】図７においては、Ｐ＋型ＳｉＣ基板１３０
上に、Ｐ型ＳｉＣエピタキシャル領域１４０が形成され
ており、Ｐ型ＳｉＣエピタキシャル領域１４０の表面
に、Ｎ型ＳｉＣドレイン領域に一部が接する４０溝１５
０が形成されている。そして溝１５０は、ドレイン電極
１１０で埋められ、溝１５０の所定の領域にショットキ
ー接続１２０が形成されている。また、Ｐ＋型ＳｉＣ基
板１３０の裏面に裏面電極１６０が形成されている。裏
面電極１６０は、ソース電位もしくはグランド電位に接
続されている。その他の構成は、図１に示した第１の実
施形態と同様である。In FIG. 7, a P + type SiC substrate 130 is shown.
A P-type SiC epitaxial region 140 is formed on the upper surface of the P-type SiC epitaxial region 140, and a groove 15 is formed on the surface of the P-type SiC epitaxial region 140.
0 is formed. Then, the groove 150 is filled with the drain electrode 110, and the Schottky connection 120 is formed in a predetermined region of the groove 150. A back electrode 160 is formed on the back surface of the P + type SiC substrate 130. The back electrode 160 is connected to the source potential or the ground potential. Other configurations are similar to those of the first embodiment shown in FIG.

【００３６】ここで、ショットキー接続１２０の逆方向
耐電圧をＮ型ＳｉＣドレイン領域４０とＰ型ＳｉＣエピ
タキシャル領域１４０との接合部の逆方向耐電圧より低
く設定すれば、ドレイン電極１１０にサージ電圧が印加
された場合、サージ電流がドレイン電極１１０から裏面
電極１６０に縦方向に流れ、ゲート絶縁膜７０にサージ
電圧が印加されるのを防止でき、ゲート絶縁膜７０の信
頼性を向上することができる。If the reverse withstand voltage of the Schottky connection 120 is set lower than the reverse withstand voltage of the junction between the N-type SiC drain region 40 and the P-type SiC epitaxial region 140, the surge voltage is applied to the drain electrode 110. Is applied, it is possible to prevent a surge current from flowing vertically from the drain electrode 110 to the back surface electrode 160 and to apply a surge voltage to the gate insulating film 70, thereby improving the reliability of the gate insulating film 70. it can.

【００３７】〔第３の実施形態〕次に、図８は本発明に
係る電界効果トランジスタの第３の実施形態を示す断面
図である。図７に示した第２の実施形態と図８の第３の
実施形態との相違は、図８においては、溝１５０とＰ型
ＳｉＣエピタキシャル領域１４０との間には、Ｐ型Ｓｉ
Ｃ領域１７０が形成されていることである。これによ
り、溝１５０を埋めるドレイン電極１１０とＰ型ＳｉＣ
領域１７０とがショットキー接続することになる。[Third Embodiment] FIG. 8 is a sectional view showing a third embodiment of the field effect transistor according to the present invention. The difference between the second embodiment shown in FIG. 7 and the third embodiment shown in FIG. 8 is that in FIG. 8, the P-type Si is provided between the groove 150 and the P-type SiC epitaxial region 140.
That is, the C region 170 is formed. As a result, the drain electrode 110 filling the groove 150 and the P-type SiC
A Schottky connection is made with the area 170.

【００３８】本実施形態によれば、ショットキー接続の
逆方向耐電圧は、ショットキー接続するＰ型ＳｉＣ領域
１７０の不純物濃度に依存し、チャンネルとなるＰ型Ｓ
ｉＣエピタキシャル領域１４０の不純物濃度には依存し
ない。このため、ショットキー接続の逆方向耐電圧をチ
ャンネル濃度とは独立に設計できるので、電界効果トラ
ンジスタのしきい値とショットキー接続耐圧の設計が容
易となるという効果がある。According to this embodiment, the reverse withstand voltage of the Schottky connection depends on the impurity concentration of the P-type SiC region 170 to be Schottky connected, and the P-type S serving as the channel.
It does not depend on the impurity concentration of the iC epitaxial region 140. Therefore, since the reverse withstand voltage of the Schottky connection can be designed independently of the channel concentration, the threshold voltage of the field effect transistor and the Schottky connection breakdown voltage can be easily designed.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明に係る電界効果トランジスタの第１の実
施形態を示す断面図である。FIG. 1 is a sectional view showing a first embodiment of a field effect transistor according to the present invention.

【図２】第１の実施形態の電界効果トランジスタの製造
方法を説明する工程順断面図（１）である。2A to 2C are sectional views (1) in order of steps, illustrating a method for manufacturing the field effect transistor of the first embodiment.

【図３】第１の実施形態の電界効果トランジスタの製造
方法を説明する工程順断面図（２）である。3A to 3C are sectional views (2) in order of steps, illustrating a method for manufacturing the field effect transistor of the first embodiment.

【図４】第１の実施形態の電界効果トランジスタの製造
方法を説明する工程順断面図（３）である。4A to 4C are sectional views (3) in order of steps, illustrating a method for manufacturing the field effect transistor of the first embodiment.

【図５】第１の実施形態の電界効果トランジスタの製造
方法を説明する工程順断面図（４）である。5A to 5C are cross-sectional views in order of the processes, illustrating the method for manufacturing the field-effect transistor of the first embodiment (4).

【図６】第１の実施形態の電界効果トランジスタの製造
方法を説明する工程順断面図（５）である。FIG. 6 is a sectional view (5) in order of steps, illustrating a method for manufacturing the field effect transistor according to the first embodiment.

【図７】本発明に係る電界効果トランジスタの第２の実
施形態を示す断面図である。FIG. 7 is a sectional view showing a second embodiment of a field effect transistor according to the present invention.

【図８】本発明に係る電界効果トランジスタの第３の実
施形態を示す断面図である。FIG. 8 is a sectional view showing a third embodiment of a field effect transistor according to the present invention.

【図９】従来例のＳｉＣ電界効果トランジスタの構造を
説明する断面図である。FIG. 9 is a cross-sectional view illustrating the structure of a conventional SiC field effect transistor.

【符号の説明】[Explanation of symbols]

１０…Ｐ型ＳｉＣ基板 １５…絶縁膜 ２０…Ｐ＋型ＳｉＣ領域 ３０…Ｎ＋型ＳｉＣソース領域 ４０…Ｎ型ＳｉＣドレイン領域 ５０…Ｎ＋型ＳｉＣドレイン領域 ６０…絶縁膜 ７０…ゲート絶縁膜 ８０…ゲート電極 ９０…絶縁膜 １００…ソース電極 １１０…ドレイン電極 １２０…ショットキー接続 １３０…Ｐ＋型ＳｉＣ基板 １３５…Ｎ＋型ＳｉＣ基板 １４０…Ｐ型ＳｉＣエピタキシャル領域 １４５…Ｎ型ＳｉＣエピタキシャル領域 １５０…溝 １５５…溝 １６０…裏面電極 １７０…Ｐ型ＳｉＣ領域 １８０…Ｎ型ＳｉＣチャンネル領域 10 ... P-type SiC substrate 15 ... Insulating film 20 ... P + type SiC region 30 ... N + type SiC source region 40 ... N-type SiC drain region 50 ... N + type SiC drain region 60 ... Insulating film 70 ... Gate insulating film 80 ... Gate electrode 90 ... Insulating film 100 ... Source electrode 110 ... Drain electrode 120 ... Schottky connection 130 ... P + type SiC substrate 135 ... N + type SiC substrate 140 ... P-type SiC epitaxial region 145 ... N-type SiC epitaxial region 150 ... Groove 155 ... Groove 160 ... Back electrode 170 ... P-type SiC region 180 ... N-type SiC channel region

フロントページの続き Ｆターム(参考） 4M104 AA03 CC03 FF01 FF02 FF27 GG09 5F048 AA05 AA07 AC06 AC10 BA01 BA14 BC03 BC07 BC12 BE09 BF16 BF18 CC06 5F140 AA02 AA31 AB06 BA02 BC12 BD18 BF01 BF04 BF44 BH05 BH08 BH15 BH17 BH21 BH25 BH27 BH30 BH43 BJ01 BJ03 BJ30 BK02 BK13 BK21 DA08Continued front page    F term (reference) 4M104 AA03 CC03 FF01 FF02 FF27                       GG09                 5F048 AA05 AA07 AC06 AC10 BA01                       BA14 BC03 BC07 BC12 BE09                       BF16 BF18 CC06                 5F140 AA02 AA31 AB06 BA02 BC12                       BD18 BF01 BF04 BF44 BH05                       BH08 BH15 BH17 BH21 BH25                       BH27 BH30 BH43 BJ01 BJ03                       BJ30 BK02 BK13 BK21 DA08

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 第１導電型の半導体基板の表層にそれぞ
れ形成された第２導電型のドレイン領域及び第２導電型
のソース領域と、ゲート電圧によって伝導度が変調され
るチャンネル領域と、を具備した電界効果トランジスタ
において、 ドレイン電極、ソース電極、およびゲート電極が前記半
導体基板の同一表面上に形成されており、前記ドレイン
電極が前記半導体基板の一部とショットキー接続されて
いることを特徴とする電界効果トランジスタ。1. A drain region of a second conductivity type and a source region of a second conductivity type respectively formed on a surface layer of a semiconductor substrate of the first conductivity type, and a channel region whose conductivity is modulated by a gate voltage. In the field effect transistor provided, the drain electrode, the source electrode, and the gate electrode are formed on the same surface of the semiconductor substrate, and the drain electrode is Schottky-connected to a part of the semiconductor substrate. And a field effect transistor. 【請求項２】 前記半導体基板の前記表面に前記ドレイ
ン領域と接する溝が形成され、該溝内に形成されたドレ
イン電極が前記半導体基板の一部とショットキー接続さ
れていることを特徴とする請求項１に記載の電界効果ト
ランジスタ。2. A groove which is in contact with the drain region is formed on the surface of the semiconductor substrate, and a drain electrode formed in the groove is Schottky-connected with a part of the semiconductor substrate. The field effect transistor according to claim 1. 【請求項３】 前記ショットキー接続の逆方向耐電圧
が、前記第１導電型の半導体基板と前記第２導電型のド
レイン領域との接合の逆方向耐電圧より低いことを特徴
とする請求項２に記載の電界効果トランジスタ。3. The reverse withstand voltage of the Schottky connection is lower than the reverse withstand voltage of the junction between the semiconductor substrate of the first conductivity type and the drain region of the second conductivity type. 2. The field effect transistor according to 2. 【請求項４】 前記第１導電型の半導体基板と前記ショ
ットキー電極との接続面に第２の第１導電型の領域が形
成されていることを特徴とする請求項１乃至請求項３の
何れか１項に記載の電界効果トランジスタ。4. The second first-conductivity-type region is formed on the connection surface between the first-conductivity-type semiconductor substrate and the Schottky electrode. The field effect transistor according to any one of items. 【請求項５】 前記半導体基板が炭化珪素であることを
特徴とする請求項１乃至請求項４の何れか１項に記載の
電界効果トランジスタ。5. The field effect transistor according to claim 1, wherein the semiconductor substrate is silicon carbide.
JP2001209355A 2001-07-10 2001-07-10 Field effect transistor Pending JP2003023099A (en)

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US7432579B2 (en) 2003-10-09 2008-10-07 Kabushiki Kaisha Toshiba Semiconductor device with horizontal MOSFET and Schottky barrier diode provided on single substrate
EP1759416A2 (en) * 2004-06-23 2007-03-07 Freescale Semiconductor, Inc. Ldmos transistor
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