JP7411465B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device.

A semiconductor device manufacturing method in which impurities are added to a semiconductor substrate (impurity doping) is used as a method for forming an active region in which a semiconductor element is arranged. For example, in Patent Document 1, N A high-side transistor and a low-side transistor, which are MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), are formed, and these transistors are surrounded by a common trench isolation region. It has achieved improved heat dissipation and higher integration.

International Publication No. 2016/042971

Since the high-side transistor and the low-side transistor are N-type MOSFETs, the structure is such that the gate wiring connected to the gate electrode of the high-side transistor is placed close to the output wiring connected to the output electrode Vout. . Since the gate wiring of the high-side transistor is arranged between the high-potential electrode Vcc and the output electrode Vout, there is a problem in that noise due to potential fluctuations of the output electrode Vout affects the driving of the gate electrode of the high-side transistor.

The present invention has been made in view of the above-mentioned problems, and an object thereof is to provide a semiconductor device and a method for manufacturing the same that suppresses the influence of noise due to potential fluctuations of an output electrode on driving of a gate electrode. .

A semiconductor device according to one embodiment of the present invention includes an upper arm semiconductor element and a lower arm semiconductor element on the same plane of a substrate, and a high potential side electrode in the upper arm semiconductor element and a low potential side electrode in the lower arm semiconductor element. In between, the drift region in the upper arm semiconductor element and the low potential side electrode of the upper arm semiconductor element forming an ohmic junction are electrically connected, and the drift region in the lower arm semiconductor element and the lower arm semiconductor element forming an ohmic junction are electrically connected. The gist is that the high potential side electrode is electrically connected.

According to the present invention, it is possible to provide a semiconductor device that suppresses the influence of noise due to potential fluctuations of an output electrode on driving of a gate electrode.

FIG. 1 is a top view showing the configuration of a semiconductor device according to a first embodiment. FIG. 1 is a cross-sectional perspective view showing the configuration of a semiconductor device according to a first embodiment. FIG. 3 is a schematic process diagram (part 1) for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. 2 is a schematic process diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment (Part 2). FIG. 3 is a schematic process diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment (part 3). FIG. 4 is a schematic process diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment (Part 4). FIG. 5 is a schematic process diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment (part 5). FIG. 6 is a schematic process diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment (part 6). FIG. 7 is a schematic process diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment (Part 7). FIG. 8 is a schematic process diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment (Part 8). FIG. 9 is a schematic process diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment (No. 9); FIG. FIG. 10 is a schematic process diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment (Part 10). FIG. 11 is a schematic process diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment (Part 11). FIG. 7 is a cross-sectional perspective view showing the configuration of a semiconductor device according to a modification.

Embodiments will be described below with reference to the drawings. In the description of the drawings, the same parts are denoted by the same reference numerals and the description thereof will be omitted. However, the drawings are schematic, and the relationship between the thickness and planar dimensions, the ratio of the thickness of each layer, etc. may differ from the actual drawings. Furthermore, the drawings include portions that differ in dimensional relationships and ratios.

Furthermore, in this specification and the like, "electrically connected" includes a case where the two are connected via "something that has some kind of electrical effect." Here, "something that has some kind of electrical effect" is not particularly limited as long as it allows the transmission and reception of electrical signals between connected objects. For example, "something that has some kind of electrical action" includes electrodes, wiring, switching elements, resistance elements, inductors, capacitive elements, and other elements that have various functions.

(First embodiment)
As shown in FIGS. 1 and 2, in the semiconductor device according to this embodiment, a lower arm semiconductor element 40 made of a transistor and an upper arm semiconductor element 41 made of a transistor are installed on the same plane on a substrate 1, and the lower arm The drift region 17 of the semiconductor element 40 is of the first conductivity type, and the drift region 21 of the upper arm semiconductor element 41 is of the second conductivity type. The high potential side electrode of the lower arm semiconductor element 40 forms an ohmic contact with the drift region 17 between the source electrode 38 which is the high potential side electrode in 41, and the upper arm semiconductor element 41 forms an ohmic contact with the drift region 21. The low potential side electrodes are electrically connected.

A lower arm semiconductor element 40 and an upper arm semiconductor element 41 are formed on the surface of the substrate 1. When the substrate 1, the lower arm semiconductor element 40, and the upper arm semiconductor element 41 are made of the same material, performance deterioration such as lattice mismatch can be suppressed.

The lower arm semiconductor element 40 is an N-type MOSFET, and includes a drift region 17 of the first conductivity type (first conductivity type drift region), a well region 20 of the second conductivity type (second conductivity type well region), and a second conductivity type well region 20 (second conductivity type well region). A source region 23 (first conductivity type source region) that is of the first conductivity type, a drain region 24 (first conductivity type drain region) that is the first conductivity type, and a well contact region 43 (second conductivity type) that is the second conductivity type. type well contact area). The well region 20 is electrically connected to the source region 23, and the drift region 17 is in contact with the well region 20 and the drain region 24. The source region 23 and the drain region 24 have a higher concentration of impurities of the first conductivity type than the drift region 17 , and the well contact region 43 has a higher concentration of impurities of the second conductivity type than the well region 20 . The impurity concentration of the drift region 17 and the well region 20 is, for example, about 1×10 ¹⁵ /cm ³ to 1×10 ¹⁹ /cm ³ . Further, the impurity concentration of the source region 23, drain region 24, and well contact region 43 is, for example, about 1×10 ¹⁸ /cm ³ to 1×10 ²¹ /cm ³ .

Further, the lower arm semiconductor element 40 has a source electrode 37 which is a low potential side electrode electrically connected to the source region 23, a drain electrode 39 which is a high potential side electrode electrically connected to the drain region 24, and a drift A gate electrode 31 (first gate electrode) for current control is embedded in a part of the region 17, a part of the well region 20, and a part of the source region 23 via a gate insulating film 30 (first insulating film). and a gate wiring 34 (first gate wiring) electrically connected to the gate electrode 31.

The upper arm semiconductor element 41 is a P-type MOSFET, and includes a drift region 21 of the second conductivity type (second conductivity type drift region), a well region 18 of the first conductivity type (first conductivity type well region), and a first conductivity type well region 18 (first conductivity type well region). A source region 27 (second conductivity type source region) of second conductivity type, a drain region 26 (second conductivity type drain region) of second conductivity type, and a well contact region 44 (first conductivity type) of first conductivity type. type well contact area). Well region 18 is electrically connected to source region 27 , and drift region 21 is in contact with well region 18 and drain region 26 . The source region 27 and the drain region 26 have a higher concentration of second conductivity type impurities than the drift region 21 , and the well contact region 44 has a higher concentration of first conductivity type impurities than the well region 18 . The impurity concentration of the drift region 21 and the well region 18 is, for example, about 1×10 ¹⁵ /cm ³ to 1×10 ¹⁹ /cm ³ . Further, the impurity concentration of the source region 27, drain region 26, and well contact region 44 is, for example, about 1×10 ¹⁸ /cm ³ to 1×10 ²¹ /cm ³ .

Further, the upper arm semiconductor element 41 includes a source electrode 38 which is a high potential side electrode electrically connected to the source region 27, a drain electrode 39 electrically connected to the drain region 26, a part of the drift region 21, A gate electrode 33 (second gate electrode) for current control is embedded in a part of the well region 18 and a part of the source region 27 via a gate insulating film 32 (second insulating film); It has a gate wiring 35 (second gate wiring) that is electrically connected. In the lower arm semiconductor element 40, the drain electrode 39 functions as a high potential side electrode, and in the upper arm semiconductor element 41, the drain electrode 39 functions as a low potential side electrode. That is, the high potential side electrode of the lower arm semiconductor element 40 and the low potential side electrode of the upper arm semiconductor element 41 are the same electrode, and also serve as the drain electrode 39 which is an output electrode. Further, the drain electrode 39 forms an ohmic contact with the drift region 17 and the drift region 21 .

The drift region is a region where a main current flows through the semiconductor element in an on state. The drift region 17 and the drift region 21 form a super junction structure (SJ structure) in which first conductivity type column regions and second conductivity type column regions are alternately arranged along the direction perpendicular to the direction in which the main current flows. may have been done. By adopting the SJ structure, characteristics of high breakdown voltage and low on-resistance can be obtained.

Note that the first conductivity type and the second conductivity type are mutually different conductivity types. That is, if the first conductivity type is P type, the second conductivity type is N type, and if the first conductivity type is N type, the second conductivity type is P type. In the following, a case will be described in which the first conductivity type is N type and the second conductivity type is P type.

As shown in FIG. 1, in the semiconductor device according to this embodiment, a drain electrode 39 is arranged between a source electrode 37 in a lower arm semiconductor element 40 and a source electrode 38 in an upper arm semiconductor element 41. With such a configuration, the gate wiring 35 is spaced apart from the drain electrode 39. Specifically, the gate wiring 35 and the drain electrode 39 are spaced apart from each other with the drift region 21 in between. This configuration allows the gate electrode 33 and the gate wiring 35 to be separated from the drain electrode 39, and suppresses the influence of noise due to potential fluctuations of the drain electrode 39 on the drive of the gate electrode 33 electrically connected to the gate wiring 35. be able to.

Next, an example of the operation of the semiconductor device according to this embodiment will be described.

The lower arm semiconductor element 40 functions as a transistor by controlling the potential of the gate electrode 31 while applying a positive potential to the drain electrode 39 with the potential of the source electrode 37 as a reference. That is, when the voltage between the gate electrode 31 and the source electrode 37 is made equal to or higher than a predetermined threshold voltage, an inversion layer is formed in the channel part of the well region 20 on the side surface of the gate electrode 31 and becomes an on state, so that the voltage between the drain electrode 39 and the source electrode is increased. Current flows to 37.

On the other hand, when the voltage between the gate electrode 31 and the source electrode 37 is lowered to a predetermined threshold voltage or less, the inversion layer disappears, the device enters an off state, and the current is cut off.

The upper arm semiconductor element 41 functions as a transistor by controlling the potential of the gate electrode 33 while applying a negative potential to the drain electrode 39 with the potential of the source electrode 38 as a reference. That is, when the voltage between the gate electrode 33 and the source electrode 38 is lowered to a predetermined threshold voltage or less, an inversion layer is formed in the channel part of the well region 18 on the side surface of the gate electrode 33 and becomes an on state. Current flows to 38.

On the other hand, when the voltage between the gate electrode 33 and the source electrode 38 is made equal to or higher than a predetermined threshold voltage, the inversion layer disappears, the device enters an off state, and the current is cut off.

In the semiconductor device according to this embodiment, the gate electrode 33 and gate wiring 35 of the upper arm semiconductor element 41 can be placed away from the drain electrode, where the potential fluctuates greatly. Further, the gate wiring 34 of the lower arm semiconductor element 40 is arranged on the source region 23 whose potential is stable at a low potential, and the gate wiring 35 is arranged on the source region 27 whose potential is stable at a high potential. By doing so, the influence of noise on the gate electrode 33 and gate wiring 35 can be suppressed.

Next, an example of a method for manufacturing a semiconductor device according to this embodiment will be described with reference to FIGS. 3A to 3K.

First, a substrate 1 to which no impurities are added is prepared. Next, as shown in FIG. 3A, the mask material 16 formed on the substrate 1 is patterned to expose the regions where the drift region 17 and the well region 18 are to be formed. Then, a drift region 17 and a well region 18 are formed by ion implantation to selectively add N-type impurities into the substrate 1 using the mask material 16 as a mask.

As the substrate 1, a semi-insulating substrate or an insulating substrate can be used. Thereby, the element isolation process when a plurality of semiconductor devices are integrated on the same substrate 1 can be simplified. Furthermore, when mounting a semiconductor device on the cooler, it is possible to omit the insulating substrate installed between the substrate 1 and the cooler. Here, the insulating substrate refers to a substrate having a resistivity of several kΩ·cm or more.

For example, a silicon carbide substrate (SiC substrate) having insulating properties can be used as the substrate 1. Since SiC is a wide bandgap semiconductor and has a small number of intrinsic carriers, it is easy to obtain high insulation properties and a semiconductor device with high breakdown voltage can be realized. Although there are several polytypes (crystal polymorphisms) of SiC, a typical 4H SiC substrate can be used as the substrate 1. By using a SiC substrate for the substrate 1, the insulation and thermal conductivity of the substrate 1 can be increased. Therefore, the semiconductor device can be efficiently cooled by directly attaching the back surface of the substrate 1 to the cooling mechanism. According to this structure, since the SiC substrate has high thermal conductivity, heat generated by the main current when the semiconductor device is in the on state can be efficiently dissipated.

Furthermore, the substrate 1 is not limited to the SiC substrate, and a semiconductor substrate made of a semiconductor material with a wide band gap may be used. Examples of wide bandgap semiconductor materials include GaN, diamond, ZnO, and AlGaN.

A silicon oxide film can be used as a general mask material, and a thermal CVD method or a plasma CVD method can be used as a deposition method. A photolithography method can be used as a patterning method. That is, the mask material is etched using the patterned photoresist film as a mask. As the etching method, wet etching using hydrofluoric acid or dry etching such as reactive ion etching can be used. After etching the mask material, the photoresist film is removed using oxygen plasma, sulfuric acid, or the like. In this way, the mask material is patterned.

Next, as shown in FIG. 3B, the mask material 19 formed on the substrate 1, the drift region 17, and the well region 18 is patterned to expose the regions where the well region 20 and the drift region 21 are to be formed. Then, a well region 20 and a drift region 21 are formed by ion implantation to selectively add P-type impurities into the substrate 1 using the mask material 19 as a mask.

Note that as the N-type impurity in this embodiment, for example, nitrogen (N) can be used, and as the P-type impurity, for example, aluminum (Al) or boron (B) can be used. Note that by performing ion implantation while the substrate is heated to about 600° C., it is possible to suppress crystal defects from occurring in the ion-implanted region.

Next, as shown in FIG. 3C, the mask material 22 formed on the substrate 1, the drift region 17, the well region 18, the well region 20, and the drift region 21 is patterned to form the source region 23 and the drain region. The region forming region 24 is exposed. Then, a source region 23 and a drain region 24 are formed by ion implantation to selectively add N-type impurities into the substrate 1 using the mask material 22 as a mask.

Next, as shown in FIG. 3D, a mask material 25 is formed on the substrate 1, the drift region 17, the well region 18, the well region 20, the drift region 21, the source region 23, and the drain region 24. is patterned to expose regions where the drain region 26 and source region 27 will be formed. Then, a drain region 26 and a source region 27 in contact with the drain region 24 are formed by ion implantation to selectively add P-type impurities into the substrate 1 using the mask material 25 as a mask.

Next, as shown in FIG. 3E, on the drift region 17, on the well region 18, on the well region 20, on the drift region 21, on the source region 23, on the drain region 24, on the drain region 26, and on the source region 27. The mask material 50 formed in 1 is patterned to expose the region where the well contact region 43 is to be formed. Then, a well contact region 43 is formed by ion implantation that selectively adds P-type impurities to the well region 20 and source region 23 using the mask material 50 as a mask. Well contact region 43 can stabilize switching characteristics by electrically connecting well region 20 to source electrode 37 . For this reason, it is preferable that the well contact region 43 be formed so as to be in contact with the source electrode 37, and more preferably be formed as far as just below the source electrode 37 so as to be in contact with the source electrode 37.

Next, as shown in FIG. 3F, on the drift region 17, on the well region 18, on the well region 20, on the drift region 21, on the source region 23, on the drain region 24, on the drain region 26, on the source region 27, Then, the mask material 51 formed on the well contact region 43 is patterned to expose the region where the well contact region 44 is to be formed. Then, a well contact region 44 is formed by ion implantation to selectively add N-type impurities to the well region 18 and source region 27 using the mask material 51 as a mask. Well contact region 44 can stabilize switching characteristics by electrically connecting well region 18 to source electrode 38 . For this reason, it is preferable that the well contact region 44 be formed so as to be in contact with the source electrode 38, and it is more preferable that the well contact region 44 be formed so as to be in contact with the source electrode 38 up to just below the source electrode 38.

Note that the impurities ion-implanted in each of the above steps can be activated by heat treatment. For example, heat treatment is performed at about 1700° C. in an argon atmosphere or a nitrogen atmosphere.

In addition, the ion implantation conditions for adding impurities at high implantation energy (impurity doping) to form a high concentration impurity region and the ion implantation conditions for adding impurities at low implantation energy to form a low concentration impurity region are switched as appropriate. In this way, a high concentration impurity region and a low concentration impurity region may be continuously formed by one continuous ion implantation. For example, the drift region 17, which is a low concentration impurity region, and the source region 23, which is a high concentration impurity region, can be formed continuously.

As described above, the ion implantation conditions are changed during ion implantation to change the impurity concentration in the depth direction while forming the drift region, well region, source region, drain region, and well contact region that are part of the active region. By doing so, the impurity concentration in the depth direction can be freely designed. Thereby, concentration of the electric field can be alleviated and the maximum applied voltage of the semiconductor device can be improved.

Furthermore, by forming the N-type or P-type impurity region by ion implantation, manufacturing costs can be reduced compared to the case where it is formed by epitaxial growth.

Next, as shown in FIG. 3G, using a patterned mask material (not shown) as a mask, dry etching is performed to remove a portion of the drift region 17, a portion of the well region 18, a portion of the well region 20, and the drift region. 21, a portion of the source region 23, and a portion of the source region 27 are selectively etched to form a gate trench 28 and a gate trench 29 in which the gate electrode 31 and the gate electrode 33 are buried.

Next, as shown in FIG. 3H, a gate insulating film 30 and a gate electrode 31 are formed inside the gate trench 28, and a gate insulating film 32 and a gate electrode 33 are formed inside the gate trench 29. The gate electrode 31 is in contact with the drift region 17 , the well region 20 , and the source region 23 through the gate insulating film 30 , and the gate electrode 33 is in contact with the drift region 21 , the well region 18 through the gate insulating film 32 . , and source region 27, respectively.

The gate insulating film 30 and the gate insulating film 32 are formed on the inner wall surface of the gate groove 28 and the inner wall surface of the gate groove 29, respectively, and can be formed using, for example, a thermal oxidation method or a deposition method. For example, in the case of thermal oxidation, a silicon oxide film is formed in all parts of the substrate that come into contact with oxygen by heating the substrate to about 1100° C. in an oxygen atmosphere.

After forming the gate insulating film 30 and the gate insulating film 32, nitrogen, Annealing at about 1000° C. may be performed in an atmosphere of argon, N ₂ O, or the like. Direct thermal oxidation under an NO or N ₂ O atmosphere is also possible. In that case, the temperature is preferably 1100°C to 1400°C. The thickness of the gate insulating film 30 and the gate insulating film 32 is approximately several tens of nanometers.

The gate electrode 31 and the gate electrode 33 are formed so as to be deposited inside the gate trench 28 and inside the gate trench 29, respectively. As the material for the gate electrode 31 and the gate electrode 33, for example, a polysilicon film can be used. In this embodiment, a case will be described in which a polysilicon film is used for the gate electrode 31 and the gate electrode 33.

As a method for depositing the polysilicon film, a low pressure CVD method or the like can be used. For example, the thickness of the polysilicon film to be deposited is made larger than half the width of the gate trenches 28 and 29, and the gate trenches 28 and 29 are filled with the polysilicon film. Since a polysilicon film is formed from the inner wall surface of the gate trench 28 and from the inner wall surface of the gate trench 29, by setting the thickness of the polysilicon film as described above, the gate trench 28 and the gate trench 29 are formed with polysilicon. It can be filled with a silicon film. For example, if the width of the gate grooves 28 and 29 is 2 μm, the polysilicon film is formed to have a thickness greater than 1 μm. Further, after depositing the polysilicon film, an N-type polysilicon film is formed by annealing at 950° C. in phosphorus oxychloride (POCl ₃ ), which imparts conductivity to the gate electrodes 31 and 33. do.

The polysilicon film is planarized by etching or the like. The etching method may be isotropic etching or anisotropic selective etching. The etching amount is set so that the polysilicon film remains inside the gate trench 28 and the gate trench 29. For example, when a polysilicon film is deposited to a thickness of 1.5 μm for the gate grooves 28 and 29 having a width of 2 μm, the amount of etching of the polysilicon film is set to 1.5 μm. However, in controlling the etching, there is no problem even if the etching amount is 1.5 μm, even if the etching amount is a few percent.

Next, as shown in FIG. 3I, a gate wiring 34 is formed so as to be placed over the well region 20 and the source region 23, and the gate electrodes 31 are electrically connected to each other. Further, a gate wiring 35 is formed to be placed over the well region 18 and the source region 27, and the gate electrodes 33 are electrically connected to each other. The gate wiring 34 and the gate wiring 35 can be made of the same polysilicon as the gate electrode 31 and the gate electrode 33, or metal.

Next, as shown in FIG. 3J, an interlayer insulating film 36 is formed. For example, a silicon oxide film can be used as the interlayer insulating film 36. As a method for depositing the silicon oxide film, a thermal CVD method or a plasma CVD method can be used. Further, a silicon nitride film may be used for the interlayer insulating film 36.

Thereafter, the interlayer insulating film 36 is selectively etched using a patterned photoresist film (not shown) as a mask, and contact holes (not shown) are formed so that the upper surfaces of the source region 23 and the source region 27 are exposed. ) to form. As the etching method, for example, wet etching using hydrofluoric acid or dry etching such as reactive ion etching is used.

Next, the electrode film formed so as to fill the above-mentioned contact hole is patterned to form a source electrode 37 and a source electrode 38. As the material for the source electrodes 37 and 38, metal materials used for metal wiring, such as titanium (Ti), nickel (Ni), and molybdenum (Mo), can be suitably used. Further, a laminated film of titanium/nickel/silver (Ti/Ni/Ag) or the like may be used for the source electrode 37 and the source electrode 38. The source electrodes 37 and 38 are formed by depositing a metal material over the entire surface by sputtering, electron beam (EB) evaporation, or the like, and then etching the metal material. Alternatively, the source electrodes 37 and 38 may be formed by filling the contact holes with a metal material through a plating process.

Next, as shown in FIG. 3K, in the same manner as described above, contact holes (not shown) are formed so that the upper surfaces of the drain region 24 and the drain region 26 are exposed, and the contact holes are filled. The formed electrode film is patterned to form a drain electrode 39. As the material of the drain electrode 39, a material that forms an ohmic contact with the drift region 17 and the drift region 21, such as nickel (Ni), can be used. The drain electrode 39 is formed so as not to be short-circuited with the source electrode 37. For example, the drain electrode 39 is formed in advance so as to be divided, and the divided drain electrodes 39 are electrically connected to each other by an electrode or the like so as to straddle the source electrode 37 .

Furthermore, the source electrodes 37 and 38 and the drain electrode 39 may be formed simultaneously. At this time, the drain electrode 39 is formed so as to be divided in advance so as not to be short-circuited with the source electrode 37. Thereafter, the divided drain electrodes 39 may be electrically connected to each other using an electrode or the like so as to straddle the source electrode 37.

The drain electrode 39 is arranged between the source electrode 37 and the source electrode 38, is formed so that the gate wiring 34 is not arranged in the region between the gate electrode 31, and the drain electrode 39 is arranged in the region between the gate electrode 33. It is formed so that the gate wiring 35 is not arranged. That is, the gate wiring 35 is spaced apart from the drain electrode 39, and the gate wiring 35 and the drain electrode 39 are spaced apart from each other with the drift region 21 in between. With this configuration, it is possible to suppress the influence of noise due to potential fluctuations of the drain electrode 39 on the driving of the gate electrode 33 electrically connected to the gate wiring 35.

Next, as shown in the top view of FIG. 1, a pad electrode 45 (third pad electrode) electrically connected to the source electrode 37 and a pad electrode 46 (fourth pad electrode) electrically connected to the source electrode 38 ), a pad electrode 47 (fifth pad electrode) electrically connected to the drain electrode 39 , a pad electrode 48 (first pad electrode) electrically connected to the gate wiring 34 , and a pad electrode 48 (first pad electrode) electrically connected to the gate wiring 35 . A pad electrode 49 (second pad electrode) connected to is formed.

Pad electrode 45, pad electrode 46, pad electrode 47, pad electrode 48, and pad electrode 49 are each arranged on the same plane. For example, an interlayer insulating film is formed on the source electrode 37, the source electrode 38, and the drain electrode 39, and contact holes reaching the source electrode 37, the source electrode 38, and the drain electrode 39 are formed in the interlayer insulating film. Further, contact holes reaching the gate wiring 34 and the gate wiring 35 are formed in the interlayer insulation film and the interlayer insulation film 36. Thereafter, an electrode or the like can be formed in each contact hole, and each pad electrode can be formed on the same plane so as to be electrically connected to the electrode.

Further, each of the pad electrode 45, the pad electrode 47, and the pad electrode 48 is formed so as to sandwich the pad electrode 46 and the pad electrode 49, the lower arm semiconductor element 40, and the upper arm semiconductor element 41, respectively.

By arranging each pad electrode as described above, the source electrode 37 (pad electrode 45) and gate electrode 31 (pad electrode 48), as well as the source electrode 38 (pad electrode 46) and gate electrode 33 (pad electrode 49) They are located next to each other to minimize inductance in the gate driver circuit loop.

In the above, an example has been described in which an N-type or P-type impurity region is formed by ion-implanting impurities into the substrate 1, but the invention is not limited to this, and an N-type or P-type impurity region may be formed by epitaxial growth. .

Furthermore, in the above description, the drift region 17 and the drain region 24 are of the first conductivity type, and the drift region 21 and the drain region 26 are of the second conductivity type. The polarity of the drift region 17 may be opposite to that of the drift region 17, and the polarity of the drain region 26 may be opposite to that of the drift region 21. Specifically, for example, the drift region 17 may have a first conductivity type, the drain region 24 may have a second conductivity type, and the drain region 26 may have a polarity opposite to that of the drift region 21. The region 21 may be of the second conductivity type, and the drain region 26 may be of the first conductivity type. By having a drain region into which minority carriers are injected, it is possible to obtain IGBT (Insulated Gate Bipolar Transistor) operation that achieves both low saturation voltage and relatively fast switching characteristics.

<Modified example>
As shown in FIG. 4, the semiconductor device according to this embodiment includes, in addition to the above-described semiconductor device, an insulating region 42 between the drain region 24 and the drain region 26. The insulating region 42 can be formed by not adding impurities between the drain region 24 and the drain region 26 when forming the drain region 24 and the drain region 26.

According to this modification, by providing the insulating region 42, when the lower arm semiconductor element 40 is in the on state, hole injection from the drain region 26 to the drift region 17 can be suppressed, and the upper arm semiconductor element When 41 is in the on state, electron injection from the drain region 24 to the drift region 21 can be suppressed.

(Other embodiments)
As described above, the present invention has been described by way of embodiments, but the statements and drawings that form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, implementations, and operational techniques will be apparent to those skilled in the art from this disclosure.

Thus, it goes without saying that the present invention includes various embodiments not described here.

For example, a diode element may be connected antiparallel to each of the lower arm semiconductor element 40 and the upper arm semiconductor element 41. If the current supplied to a semiconductor element is suddenly cut off (turned off), an overvoltage will occur that exceeds the dielectric strength of the semiconductor element, and there is a risk that the semiconductor element will no longer function due to the effect of the overvoltage. By doing so, current flows through the diode element even when the semiconductor element is turned off, so that defects in the semiconductor element due to overvoltage can be suppressed.

1... Substrate 16... Mask material 17... Drift region 18... Well region 19... Mask material 20... Well region 21... Drift region 22... Mask material 23... Source region 24... Drain region 25... Mask material 26... Drain region 27... Source Region 28...Gate groove 29...Gate groove 30...Gate insulating film 31...Gate electrode 32...Gate insulating film 33...Gate electrode 34...Gate wiring 35...Gate wiring 36...Interlayer insulating film 37...Source electrode 38...Source electrode 39... Drain electrode 40... Lower arm semiconductor element 41... Upper arm semiconductor element 42... Insulating region 43... Well contact region 44... Well contact region 45... Pad electrode 46... Pad electrode 47... Pad electrode 48... Pad electrode 49... Pad electrode 50... Mask material 51...Mask material

Claims (15)

An upper arm semiconductor element consisting of a transistor and a lower arm semiconductor element consisting of a transistor are installed on the same plane on a substrate, and the drift region of the lower arm semiconductor element is of a first conductivity type, and the drift region of the upper arm semiconductor element is of a first conductivity type. Consisting of 2 conductivity types,
a low potential side electrode in the upper arm semiconductor element forming an ohmic contact with the drift region in the upper arm semiconductor element between a high potential side electrode in the upper arm semiconductor element and a low potential side electrode in the lower arm semiconductor element; and a high potential side electrode in the lower arm semiconductor element forming an ohmic junction with the drift region in the lower arm semiconductor element is electrically connected ,
The drain region of the lower arm semiconductor element and the drain region of the upper arm semiconductor element extend in parallel in the same direction,
The high potential side electrode in the lower arm semiconductor element and the low potential side electrode in the upper arm semiconductor element are the same electrode integrally formed, and the same electrode is connected to the drain region of the lower arm semiconductor element and the low potential side electrode in the upper arm semiconductor element. Connected to face the portion of the drain region of the upper arm semiconductor element extending in the same direction, and extending in the same direction.
A semiconductor device characterized by: In the upper arm semiconductor device,
a second conductivity type source region electrically connected to the high potential side electrode;
a first conductivity type well region electrically connected to the second conductivity type source region;
a second conductivity type drift region in contact with the first conductivity type well region;
a first gate electrode for current control;
a first gate wiring electrically connected to the first gate electrode;
In the lower arm semiconductor device,
a first conductivity type source region electrically connected to the low potential side electrode;
a second conductivity type well region electrically connected to the first conductivity type source region;
a first conductivity type drift region in contact with the second conductivity type well region;
a second gate electrode for current control;
a second gate wiring electrically connected to the second gate electrode ;
the second conductivity type source region, the first conductivity type well region, the second conductivity type drift region, the drain region of the upper arm semiconductor element, the drain region of the lower arm semiconductor element, the first conductivity type drift region, The well region of the second conductivity type and the source region of the first conductivity type are in contact with each other on their respective side surfaces and are arranged linearly in this order along the main surface of the substrate,
The semiconductor device according to claim 1. the first gate wiring is arranged on the second conductivity type source region and the first conductivity type well region,
3. The semiconductor device according to claim 2, wherein the second gate wiring is arranged over the first conductivity type source region and the second conductivity type well region. The first gate electrode is in contact with the first conductivity type well region, the second conductivity type drift region, and the second conductivity type source region via a first insulating film,
2. The second gate electrode is in contact with the second conductivity type well region, the first conductivity type drift region, and the first conductivity type source region via a second insulating film. or 3. The semiconductor device according to any one of 3. In the upper arm semiconductor device,
The drain region that is in contact with the second conductivity type drift region and electrically connected to the low potential side electrode has a polarity opposite to that of the second conductivity type drift region so that minority carrier injection occurs. ,
In the lower arm semiconductor device,
The drain region that is in contact with the first conductivity type drift region and electrically connected to the high potential side electrode has a polarity opposite to that of the first conductivity type drift region so that minority carrier injection occurs. The semiconductor device according to any one of claims 2 to 4, characterized in that: 2. The semiconductor device according to claim 1, wherein an insulating region extending in the same direction is disposed between a drain region of the lower arm semiconductor element and a drain region of the upper arm semiconductor element. 7. The semiconductor device according to claim 1, further comprising a diode element connected in antiparallel to each of the upper arm semiconductor element and the lower arm semiconductor element. a first pad electrode electrically connected to the first gate wiring;
a second pad electrode electrically connected to the second gate wiring;
a third pad electrode electrically connected to the low potential side electrode of the lower arm semiconductor element;
a fourth pad electrode electrically connected to the high potential side electrode of the upper arm semiconductor element;
a fifth pad electrode electrically connected to the low potential side electrode of the upper arm semiconductor element;
The first pad electrode, the second pad electrode, the third pad electrode, the fourth pad electrode, and the fifth pad electrode are arranged on the same plane,
The lower arm semiconductor element and the upper arm semiconductor element are sandwiched between the first pad electrode and the second pad electrode, and sandwiched between the third pad electrode and the fourth pad electrode,
According to any one of claims 2 to 5 , the fifth pad electrode sandwiches the lower arm semiconductor element and the upper arm semiconductor element with the second pad electrode and the fourth pad electrode. The semiconductor device described. each of the first conductivity type drift region and the second conductivity type drift region forming a superjunction structure consisting of a first conductivity type column region and a second conductivity type column region;
The semiconductor device according to any one of claims 2 to 5 , characterized in that: 10. The semiconductor device according to claim 1, wherein the upper arm semiconductor element and the lower arm semiconductor element are made of a wide bandgap semiconductor. 11. The semiconductor device according to claim 1, wherein the substrate, the upper arm semiconductor element, and the lower arm semiconductor element are made of the same material. 12. The semiconductor device according to claim 1, wherein the substrate is made of SiC. the first conductivity type well region, the second conductivity type well region, the first conductivity type drift region, the second conductivity type drift region, and the first conductivity type source region formed on the substrate; 5. The semiconductor device according to claim 2, wherein: and the second conductivity type source region are doped with impurities by ion implantation. the first conductivity type well region, the second conductivity type well region, the first conductivity type drift region, the second conductivity type drift region, and the first conductivity type source region formed on the substrate; 14. The semiconductor device according to claim 13, wherein: and the second conductivity type source region are formed by ion implantation with varying concentrations in the depth direction. the first conductivity type well region, the second conductivity type well region, the first conductivity type drift region, the second conductivity type drift region, and the first conductivity type source region formed on the substrate; 5. The semiconductor device according to claim 2, wherein: and said second conductivity type source region are formed by epitaxial growth.

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