WO2010143376A1 - Semiconductor device and process for manufacture thereof - Google Patents

Semiconductor device and process for manufacture thereof Download PDF

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Publication number
WO2010143376A1
WO2010143376A1 PCT/JP2010/003686 JP2010003686W WO2010143376A1 WO 2010143376 A1 WO2010143376 A1 WO 2010143376A1 JP 2010003686 W JP2010003686 W JP 2010003686W WO 2010143376 A1 WO2010143376 A1 WO 2010143376A1
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Prior art keywords
electrode
barrier metal
layer
film
metal wiring
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PCT/JP2010/003686
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French (fr)
Japanese (ja)
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庭山雅彦
内田正雄
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device using silicon carbide and a method for manufacturing the same.
  • Silicon carbide (silicon carbide: SiC) is a high-hardness semiconductor material with a larger band gap than silicon (Si), and is applied to various semiconductor devices such as power elements, environmental elements, high-temperature operating elements, and high-frequency elements. Has been. Especially, application to power devices, such as a switching element and a rectifier, attracts attention.
  • MOSFET Metal-semiconductor field effect transistors
  • MOSFET Metal-oxide film-semiconductor field-effect transistor
  • These switching elements can be switched between an on state and an off state by controlling a voltage applied to a gate electrode which is a component of the switching element.
  • a drain current of several A (amperes) or more can flow. Further, no drain current flows in the off state, and a high breakdown voltage of several hundred volts or more can be realized.
  • SiC has a higher dielectric breakdown electric field and a higher thermal conductivity than Si, so it is easy to increase the breakdown voltage and reduce the loss. For this reason, in order to realize the same performance, the size (area, thickness, etc.) of the device can be greatly reduced with respect to the Si power device.
  • An SiC power device such as a vertical MOSFET typically has a structure in which a plurality of unit cells are arranged.
  • a general configuration of each unit cell is described in Patent Document 1, for example.
  • the electrode of each unit cell is connected to the wiring provided above the electrode.
  • the gate electrode of each unit cell is connected to the gate electrode upper metal wiring formed on the gate electrode
  • the source electrode of each unit cell is the source electrode upper metal formed on the source electrode.
  • the source and gate electrode upper metal interconnections are preferably formed using the same conductive film (for example, Patent Document 2).
  • an aluminum (Al) film is used as the conductive film.
  • the “upper metal wiring” here may be a wiring for connecting the electrodes of each unit cell, and extends from the electrode pads (wire bonding pads) such as source pads and gate pads. Also included is a wired connection.
  • Al diffuses from the upper metal wiring (Al wiring), which may cause a decrease in reliability and a decrease in element characteristics. Therefore, in order to suppress Al diffusion, it has been proposed to dispose a barrier metal layer as a base of the upper metal wiring.
  • Patent Document 3 discloses that in a Si power device (vertical MOSFET), a barrier metal layer and a conductive layer containing Al are stacked in this order and patterned to form a gate wiring. (FIG. 9 and 31st paragraph of Patent Document 3).
  • the chip area can be significantly reduced compared to Si power devices, but since the amount of current flowing through the device does not change, the density of current flowing through the upper metal wiring (source metal upper metal wiring in MOSFET) increases. . Therefore, in order to ensure the reliability of the upper metal wiring, it is necessary to increase the thickness of the upper metal wiring.
  • the thickness of the upper metal wiring is larger than the thickness of the upper metal wiring of the Si power device, and is set to 2 ⁇ m or more (for example, about 3 ⁇ m).
  • the wiring processing technology there are mainly wet etching technology and dry etching technology.
  • dry etching technique anisotropy and dimensional accuracy are high and reproducibility is excellent.
  • dry etching is often used for wiring processing of general semiconductor elements.
  • the dimensional accuracy decreases as the wiring becomes thicker.
  • the selection ratio with a photoresist film (hereinafter referred to as “resist film”) serving as an etching mask is lower than the selection ratio of wet etching, it is applied to the processing of wiring having a thickness exceeding about 2 ⁇ m. It ’s difficult.
  • wet etching is preferably used for processing the upper metal wiring of the SiC power device.
  • a barrier metal layer for example, a titanium (Ti) layer
  • Such a wiring structure is obtained, for example, by forming a laminated film including a Ti film serving as a barrier metal layer and an Al film serving as an upper metal wiring, and patterning the laminated film. Considering the thickness of the upper metal wiring, it is preferable to use wet etching for patterning the laminated film.
  • the etching rate of Al was remarkably higher than that in the case of wet etching of a single Al film. This is presumably because the local battery was formed by the difference in standard electrode potential between Al and the barrier metal (for example, Ti). In this specification, the phenomenon that the etching rate of the upper wiring metal is increased by the local battery is referred to as “local battery effect”.
  • the present invention has been made in view of the above circumstances, and an object of the present invention is to suppress deterioration of element characteristics due to diffusion of metal from an upper metal wiring in a semiconductor device using silicon carbide, while suppressing the upper metal.
  • the purpose is to increase the dimensional accuracy of the wiring and to ensure high yield and reliability.
  • the semiconductor device includes a substrate, a silicon carbide layer formed on the surface of the substrate, a first electrode and a second electrode formed on the silicon carbide layer and electrically insulated from each other, and the carbonization.
  • a second barrier metal layer connected to the second electrode is provided, and the first barrier metal is formed inside the outline of the first metal wiring as viewed from above the substrate.
  • An outline is arranged, and the outline of the second barrier metal is arranged inside the outline of the second metal wiring.
  • each part of the entire surface of the first barrier metal layer is covered with the first electrode, the first metal wiring or the insulating film, and each part of the entire surface of the second barrier metal layer. Is covered with the second metal, the second metal wiring or the insulating film.
  • the first barrier metal layer is formed in the first contact hole and on the insulating film, and an upper surface and a side wall of the first barrier metal layer are covered with the first metal wiring.
  • the second barrier metal layer is formed in the second contact hole and on the insulating film, and an upper surface and a side wall of the second barrier metal layer are covered with the second metal wiring.
  • the first and second metal wirings are preferably formed by patterning the same conductive film.
  • the first and second metal wirings are separated from each other by an isolation region located between the first and second metal wirings, and the first barrier metal layer and the second barrier metal None of the layers are exposed in the isolation region.
  • the first and second barrier metal layers are preferably formed by patterning the same metal film.
  • the thickness of the first and second metal wirings may be 2 ⁇ m or more.
  • the shortest distance Y1 between the contour of the first metal wiring and the contour of the first barrier metal is 1 ⁇ m or more, and the contour of the second metal wiring and the second barrier
  • the shortest distance Y2 from the metal outline may be 1 ⁇ m or more.
  • the first and second metal wirings may be aluminum layers.
  • the first and second barrier metal layers may include titanium.
  • the first and second barrier metal layers may be a laminated film including a titanium film and a titanium nitride film.
  • the first electrode may be a source electrode, and the second electrode may be a gate electrode.
  • the substrate is a first conductivity type silicon carbide substrate, a second conductivity type well region formed in the silicon carbide layer, formed in the well region, and the well region A contact region containing a second conductivity type impurity at a higher concentration, a first conductivity type source region formed in the well region so as to surround the contact region, and the silicon carbide layer, A first conductivity type drift region formed in a portion where none of the well region, the contact region, and the source region is formed, a gate insulating film formed on the silicon carbide layer, and a back surface of the substrate A drain electrode formed, and the source electrode is formed on the silicon carbide layer so as to be in contact with the contact region and the source region.
  • the gate electrode is formed on the gate insulating film.
  • the method of manufacturing a semiconductor device of the present invention includes (A) a step of forming a silicon carbide layer on a substrate, and (B) a first electrode and a second electrode that are electrically insulated from each other on the silicon carbide layer. And (C) forming an insulating film on the silicon carbide layer and the first and second electrodes, and forming a first contact hole reaching the first electrode and the second electrode on the insulating film Forming a second contact hole reaching; (D) forming a metal film in the first and second contact holes and on the insulating film; and (E) patterning the metal film, A first barrier metal layer connected to the first electrode in one contact hole and electrically separated from the first barrier metal layer and connected to the second electrode in the second contact hole Second Beauty Obtaining a metal layer; (F) forming a conductive film on the first barrier metal layer, the second barrier metal layer, and the insulating film; and (G) patterning the conductive film by wet etching.
  • first metal wiring connected to the first barrier metal layer and a second metal wiring electrically isolated from the first metal wiring and connected to the second barrier metal layer.
  • the contour of the first barrier metal is disposed inside the contour of the first metal wiring
  • the contour of the second barrier metal is disposed inside the contour of the second metal wiring. The contour is arranged.
  • the step (G) includes a step of etching the conductive film to form an isolation region for isolating the first metal wiring and the second metal wiring from each other. Neither the first barrier metal layer nor the second barrier metal layer is exposed in the isolation region.
  • the thickness of the conductive film may be 2 ⁇ m or more.
  • the conductive film may be an aluminum film.
  • the metal film may be a laminated film including a titanium film and a titanium nitride film.
  • the first electrode may be a source electrode, and the second electrode may be a gate electrode.
  • the barrier metal is disposed as the base of the upper metal wiring, it is possible to suppress deterioration of element characteristics due to diffusion of the metal contained in the upper metal wiring. Further, it is possible to prevent the dimensional accuracy of the upper metal wiring from being lowered due to the barrier metal while ensuring the thickness of the upper metal wiring. Therefore, the yield can be increased and the reliability can be improved.
  • the method for manufacturing a semiconductor device of the present invention when the upper metal wiring is formed by wet etching, the local battery effect caused by the exposure of the barrier metal can be suppressed. As a result, an increase in the etching rate of the upper metal wiring can be prevented, and the dimensional accuracy of the upper metal wiring with respect to the mask pattern on the resist film can be increased.
  • FIG. 1 is a schematic plan view of a vertical MISFET 100 according to a first embodiment of the present invention.
  • (A) to (c) are partial cross-sectional views taken along lines I-I ′, II-II ′, and III-III ′ in the MISFET shown in FIG. 1, respectively.
  • (A) And (b) is sectional process drawing for demonstrating the manufacturing method of the vertical MISFET of 1st Embodiment by this invention, respectively.
  • (A) And (b) is sectional process drawing for demonstrating the manufacturing method of the vertical MISFET of 1st Embodiment by this invention, respectively.
  • (A) And (b) is sectional process drawing for demonstrating the manufacturing method of the vertical MISFET of 1st Embodiment by this invention, respectively.
  • (A) And (b) is sectional process drawing for demonstrating the manufacturing method of the vertical MISFET of 1st Embodiment by this invention, respectively. It is a typical top view of other vertical type MISFET200 of a 1st embodiment by the present invention.
  • (A) to (c) are process cross-sectional views for explaining a reference example of a method of forming a wiring by wet etching, and a diagram for explaining a local battery effect generated when the wiring is formed. is there.
  • the present inventors have found that when wet etching is used for processing the upper metal wiring and the barrier metal layer, the local battery effect is produced, resulting in a decrease in dimensional accuracy of the upper metal wiring.
  • 8A to 8C are cross-sectional process diagrams illustrating a reference example of the process of forming the upper metal wiring and the barrier metal layer.
  • a Ti film 51 and an Al film 53 are formed in this order.
  • a mask layer 55 is disposed on the Al film 53.
  • the thickness of the Al film 53 is 2 ⁇ m or more, for example, 3 ⁇ m, and the thickness of the Ti film is, for example, 50 nm.
  • wet etching is performed on the Ti film 51 and the Al film 53 using the mask layer 55 as an etching mask.
  • etching solution for example, a mixed solution of phosphoric acid and nitric acid is used.
  • Al etching proceeds at a uniform speed, and the portion of the Al film not covered with the mask layer 55 is removed, and the surface of the Ti film 51 is removed. Is exposed. A portion 53 a of the Al film that remains without being etched has a shape defined by the mask layer 55.
  • an Al layer 54 serving as an upper metal wiring and a Ti layer 52 serving as a barrier metal layer are formed.
  • the pattern of the Al layer 54 and the Ti layer 52 is smaller than the pattern defined by the mask layer 55.
  • the distance dZ between the end of the Al layer 54 and the end of the mask layer 55 may be 5 ⁇ m or more, for example.
  • the width of the mask layer 55 is small, the entire Al layer 53a may be removed due to the local battery effect.
  • the case where the Al layer is used as the upper metal wiring and the Ti layer is used as the barrier metal layer has been described as an example.
  • the local battery effect is not only when these materials are used, but also the standard electrode potential of the metal of the upper metal wiring. It may occur when the standard electrode potential of the barrier metal is smaller than that.
  • the barrier metal layer is exposed even at one location, and when a local battery is generated, the Al metal is electrically connected to the exposed portion of the barrier metal layer. It was also found that the entire Al film might be affected by the local battery.
  • the reliability of the upper metal wiring cannot be ensured in a power silicon carbide element through which a large current flows.
  • the barrier metal layer is not provided, the local battery effect does not occur, but the metal (Al) of the upper metal wiring diffuses and there is a risk of deteriorating element characteristics.
  • Al of the upper metal wiring diffuses into the gate insulating film, it causes a leakage current.
  • Al diffuses into an electrode such as a source electrode the resistance of the electrode increases, so that the on-resistance may increase.
  • the present inventor examined a configuration for suppressing the local battery effect while securing the thickness of the upper metal wiring and preventing the diffusion of the metal from the upper metal wiring using the barrier metal. It came to.
  • the semiconductor device of this embodiment is a vertical MISFET using silicon carbide.
  • FIG. 1 is a plan view of a vertical MISFET 100 using silicon carbide according to the present embodiment.
  • FIGS. 2A to 2C are views taken along lines II ′ and II ⁇ in the plan view shown in FIG.
  • FIG. 3 is a partial cross-sectional view taken along line II ′ and line III-III ′.
  • the MISFET 100 includes a substrate 1 and a plurality of unit cells 30 supported by the substrate 1. These unit cells 30 are arranged two-dimensionally. On the upper part of the unit cell 30, a wiring 11A connected to the source electrode of each unit cell 30 and a wiring 12A connected to the gate electrode 9 of each unit cell 30 are provided. These wirings 11A and 12A are separated from each other by the separation region 32.
  • the wiring 11 ⁇ / b> A includes a source electrode upper metal wiring (also referred to as “first metal wiring”) 11 and a barrier metal layer (also referred to as “first barrier metal layer”) 16.
  • the barrier metal layer 16 is disposed between the source electrode upper metal wiring 11 and the source electrode. Further, when viewed from above the substrate 1, that is, in the plan view shown in FIG. 1, the contour of the barrier metal layer 16 is arranged inside the contour of the source electrode upper metal wiring 11.
  • the wiring 12 ⁇ / b> A includes a gate electrode upper metal wiring (also referred to as “second metal wiring”) 12 and a barrier metal layer (also referred to as “second barrier metal layer”) 17.
  • the barrier metal layer 17 is disposed between the gate electrode upper metal wiring 12 and the gate electrode 9. Further, when viewed from above the substrate 1, that is, in the plan view shown in FIG. 1, the contour of the barrier metal layer 17 is arranged inside the contour of the gate electrode upper metal wiring 12.
  • the upper metal wirings 11 and 12 and the isolation region 32 are preferably formed by patterning the same conductive film (for example, an Al film).
  • the isolation region 32 is a region formed by removing a part of the conductive film, and is defined by the side surface of the upper metal wiring 11 and the side surface of the upper metal wiring 12 facing this side surface.
  • the barrier metal layers 16 and 17 are preferably formed by patterning the same metal film (for example, a Ti film, a TiN film, or a laminated film of a Ti film and a TiN film).
  • the gate electrode 9 has a gate portion 9g functioning as a gate in each unit cell 30, and a gate connection portion 9c for connecting the wiring 12A and the gate portion 9g.
  • the configuration of the gate electrode 9 of the present embodiment is not limited to the illustrated configuration.
  • the gate portion 9 g may also be connected to the gate electrode upper metal wiring 12 through the barrier metal layer 17.
  • Each unit cell 30 includes a substrate 1, a silicon carbide layer 20 formed by epitaxial growth on the main surface of the substrate 1, and a gate electrode 9 provided on the silicon carbide layer 20 via a gate insulating film 6.
  • Source electrode 8 in contact with the surface of silicon carbide layer 20 and drain electrode 7 provided on the back surface of substrate 1.
  • SiC substrate a low-resistance n-type silicon carbide substrate
  • Silicon carbide layer 20 includes well region 3 having a conductivity type (p-type in this case) different from that of SiC substrate 1 and drift region 2 including a portion of silicon carbide layer 20 where well region 3 is not formed. And are formed.
  • Drift region 2 is an n ⁇ type silicon carbide layer containing n type impurities at a lower concentration than SiC substrate 1.
  • the well region 3 is disposed so as to be surrounded by the n-type source region 5 containing high-concentration n-type impurities and the source region 5, and contains p-type impurities at a higher concentration than the well region 3.
  • a p + -type contact region 4 is formed.
  • Well region 3, source region 5 and contact region 4 are formed by implanting impurity ions into silicon carbide layer 20.
  • the contact region 4 and the source region 5 are in ohmic contact with the source electrode 8, respectively. Therefore, the well region 3 is electrically connected to the source electrode 8 through the contact region 4.
  • the gate insulating film 6 and the gate electrode 9 are connected to the end of the source region 5 in the adjacent well region 3 across the drift region 2 between the well regions from the end of the source region 5 in one well region 3. Covers up to.
  • the silicon carbide layer 20, the source electrode 8 and the gate electrode 9 are covered with an interlayer insulating film 10.
  • a contact hole 13 reaching the source electrode 8 is provided in the interlayer insulating film 10.
  • a barrier metal layer 16 is formed in the contact hole 13 so as to be in contact with the source electrode 8.
  • the source electrode upper metal interconnection 11 is formed in the contact hole 13 and on the interlayer insulating film 10 so as to be in contact with the upper surface of the barrier metal layer 16. Accordingly, the source electrode 8 of each unit cell 30 is connected to the source electrode upper metal wiring 11 via the barrier metal layer 16.
  • the gate electrodes 9 of the unit cells 30 are connected to each other as can be seen from the plan view shown in FIG. Specifically, the gate electrode 9 in the present embodiment has an opening that opens the source region 5 and the contact region 4 of each unit cell 30, but is not separated between unit cells. The gate electrode 9 is also extended to below the gate electrode upper metal wiring 12 (gate connection portion 9c).
  • the interlayer insulating film 10 is provided with a contact hole 15 reaching the gate electrode 9 (here, the gate connection portion 9c).
  • a barrier metal layer 17 is formed in the contact hole 15 so as to be in contact with the gate connection portion 9c.
  • Gate electrode upper metal interconnection 12 is formed in contact hole 15 and on interlayer insulating film 10 so as to be in contact with the upper surface of barrier metal layer 17. In this way, the gate electrode 9 is connected to the gate electrode upper metal wiring 12 through the barrier metal layer 17.
  • the side surface and the upper surface of the barrier metal layer 16 are covered with the source electrode upper metal wiring 11.
  • the side and upper surfaces of the barrier metal layer 17 are covered with the gate electrode upper metal wiring 12.
  • the barrier metal layer 16 is not provided on the side surface 11As of the wiring 11A
  • the barrier metal layer 17 is not provided on the side surface 12As of the wiring 12A.
  • FIG. 2B shows the cross-sectional structure of the portion of the peripheral portion of the wiring 11A on the separation region 32 side, the cross section of the other portion of the peripheral portion of the wiring 11A (along the line III-III ′).
  • the cross section also has a structure similar to that shown in FIG. That is, as shown in FIG. 2C, the side surface and the upper surface of the barrier metal layer 16 are covered with the source electrode upper metal wiring 11, and the barrier metal layer 16 is not provided on the side surface 11As of the wiring 11A.
  • the barrier metal layers 16 and 17 do not exist on the entire lower surface of the source electrode upper metal wiring 11 and the gate electrode upper metal wiring 12, but a part of the source electrode upper metal wiring 11 and the gate electrode upper metal wiring 12. A part of is in direct contact with the interlayer insulating film 10.
  • a film (Ti film) 51 including a barrier metal and a conductive film (Al film) 53 for forming an upper metal wiring are deposited, and these films are simultaneously wetted.
  • a barrier metal layer (Ti layer) 52 and an upper metal wiring (Al layer) 54 are formed.
  • the barrier metal layer 52 and the upper metal wiring 54 have substantially the same planar shape. Therefore, the barrier metal layer 52 exists on the entire lower surface of the upper metal wiring 54. Further, when viewed from above the substrate, the contour of the upper metal wiring 54 and the contour of the barrier metal layer 52 substantially coincide.
  • a wiring for example, an electrode pad
  • the contours of the barrier metal layers 16 and 17 are arranged inside the contours of the upper metal wirings 11 and 12, respectively, as viewed from above the substrate 1. Further, the barrier metal layers 16 and 17 are not provided on the side surfaces of the wirings 11A and 12A.
  • Such a configuration is realized by separately performing patterning for forming the barrier metal layers 16 and 17 and patterning for forming the upper metal wirings 11 and 12. For example, after the barrier metal layers 16 and 17 are formed, a conductive film that covers the barrier metal layers 16 and 17 is formed. Next, only the conductive film is etched to obtain the upper metal wirings 11 and 12. A specific manufacturing process will be described in detail later.
  • each part of the entire surface of the barrier metal layer 16 is covered with the source electrode 8, the interlayer insulating film 10, or the source electrode upper metal wiring 11.
  • each part of the entire surface of the barrier metal layer 17 is covered with the gate electrode 9, the interlayer insulating film 10, or the gate electrode upper metal wiring 12.
  • the entire surface of the barrier metal includes all of the upper surface, the lower surface and the side surface of the barrier metal.
  • the interlayer insulating film 10 refers to an insulating film in which the contact holes 13 and 15 are formed, and does not include, for example, a passivation film deposited after the formation of the upper metal wiring. Note that the configuration of the present embodiment is not limited to the above configuration. If the surfaces of the barrier metal layers 16 and 17 are not exposed immediately after the etching of the conductive film, the effect of the present invention can be obtained. For example, another layer may be interposed between the barrier metal layers 16 and 17 and the interlayer insulating film 10.
  • the shape of the barrier metal layers 16 and 17 is not limited to the shape illustrated.
  • the barrier metal layer 16 only needs to be in contact with the source electrode 8 at least in the contact hole 13, and may be disposed only inside the contact hole 13.
  • the barrier metal layer 17 only needs to be in contact with the gate electrode 9 at least in the contact hole 15, and may be disposed only inside the contact hole 15.
  • FIG. 1 shows that the barrier metal layer 16 and 17 only needs to be in contact with the source electrode 8 at least in the contact hole 13, and may be disposed only inside the contact hole 13.
  • the metal of the upper metal wirings 11 and 12 (here In this case, Al) can be more effectively prevented from diffusing into the gate insulating film 6 and the source electrode 8 from the side walls of the contact holes 13 and 15 and the upper surface of the interlayer insulating film 10.
  • the shortest distance Y1 between the side surface 11As of the wiring 11A (that is, the side surface of the source electrode upper metal wiring 11) and the side surface of the barrier metal layer 16 is Preferably it is set to 1 ⁇ m or more, more preferably 2 ⁇ m or more.
  • the barrier metal layer 16 is exposed on the side surface of the wiring 11A even when patterning of the metal film including the barrier metal and mask misalignment in patterning of the conductive film for forming the upper metal wiring are taken into consideration. This can be prevented more reliably.
  • the shortest distance Y2 between the side surface 12As of the wiring 12A (that is, the side surface of the gate electrode upper metal wiring 12) and the side surface of the barrier metal layer 17 is preferably set to 1 ⁇ m or more, more preferably 2 ⁇ m or more.
  • these distances Y1 and Y2 are 3 ⁇ m or less.
  • the shortest distance X1 between the end face of the barrier metal layer 16 and the end portion of the contact hole 13 and the shortest distance X2 between the end face of the barrier metal layer 17 and the contact hole 15 are as follows when forming the contact holes 13 and 15, respectively. In consideration of misalignment of the mask, it is preferably 0.5 ⁇ m or more. On the other hand, in order to suppress an increase in the chip area, the distances X1 and X2 may be 2.0 ⁇ m or less. In order to more reliably suppress Al diffusion, the distance X1 may be longer than 2.0 ⁇ m. For example, the entire unit cell (the entire well region 3) located at the peripheral edge of the source electrode upper metal wiring 11 ) May be set to cover.
  • the distances Y1, Y2, X1, and X2 are all distances in a plane parallel to the surface of the substrate 1.
  • the distance Y1 is the distance between the contour of the source electrode upper metal wiring 11 and the contour of the barrier metal layer 16
  • the distance Y2 is the contour of the gate electrode upper metal wiring 12 and the barrier. It is the distance from the contour of the metal layer 17.
  • the barrier metal layers 16 and 17 can be easily deposited inside the contact holes 13 and 15 and have an adhesiveness to the upper metal wiring (Al wiring) formed on the barrier metal layers 16 and 17.
  • Al wiring upper metal wiring
  • the thickness of the barrier metal layers 16 and 17 is, for example, not less than 50 nm and not more than 100 nm.
  • the chip area can be significantly reduced as compared with the Si power device, but the current density is relatively high.
  • the thicknesses of the source electrode upper metal wiring 11 and the gate electrode upper metal wiring 12 are, for example, 2 ⁇ m or more so that the current density flowing through these wirings does not increase. More preferably, it is 3 ⁇ m or more.
  • 3 to 6 are process cross-sectional views for explaining the manufacturing process of the MISFET of this embodiment, and correspond to a cross section taken along line II-II 'shown in the plan view of FIG.
  • silicon carbide layer 20 is formed by epitaxially growing silicon carbide on the main surface of substrate 1.
  • a silicon carbide substrate is used as the substrate 1.
  • a 4H—SiC substrate having an off angle of 8 degrees from the (0001) Si plane toward the ⁇ 11-20> direction is used.
  • the conductivity type of the substrate 1 is n-type, and its impurity concentration is, for example, 1 ⁇ 10 18 cm ⁇ 3 or more and 5 ⁇ 10 19 cm ⁇ 3 or less.
  • the silicon carbide layer 20 is formed by thermal CVD using, for example, silane (SiH 4 ) and propane (C 3 H 8 ) as source gases, hydrogen (H 2 ) as a carrier gas, and nitrogen (N 2 ) gas as a dopant gas. Can be formed.
  • n-type silicon carbide layer 20 having an impurity concentration lower than that of silicon carbide substrate 1 is formed by epitaxial growth.
  • the impurity concentration and thickness of the silicon carbide layer 20 vary depending on specifications required for the MISFET. For example, when an MISFET having a withstand voltage of 600 V is to be manufactured, the impurity concentration of the silicon carbide layer 20 is 1 ⁇ 10 15 cm ⁇ 3 or more. It is desirable that it is 5 ⁇ 10 16 cm ⁇ 3 or less and the thickness is 5 ⁇ m or more.
  • impurity ions are implanted into the silicon carbide layer 20 to form the p-type well region 3, the p-type contact region 4, and the n-type source region 5.
  • these regions 3, 4, and 5 are formed as follows, for example. First, after a silicon oxide film is deposited on the silicon carbide layer 20 by a CVD method, the silicon oxide film is patterned by photolithography and dry etching to obtain an implantation mask for forming a well region.
  • p-type impurity ions for example, aluminum ions, boron ions, etc.
  • p-type impurity ions for example, aluminum ions, boron ions, etc.
  • An injection layer is formed.
  • the substrate temperature at the time of ion implantation is preferably set to, for example, 500 ° C. or higher in order to reduce defects due to implantation.
  • the implantation mask is removed using hydrofluoric acid.
  • an implantation layer that becomes the p-type contact region 4 is formed by implanting p-type impurity ions into the silicon carbide layer 20.
  • an implantation layer to be the source region 5 is formed by implanting n-type impurity ions (for example, nitrogen ions, phosphorus ions, etc.) into the silicon carbide layer 20.
  • n-type impurity ions for example, nitrogen ions, phosphorus ions, etc.
  • an activation annealing for 30 minutes is performed on these implantation layers at a temperature of about 1700 ° C. in an inert atmosphere such as argon, thereby obtaining a well region 3, a contact region 4 and a source region 5, respectively.
  • the impurity concentration of the well region 3 obtained by the above method is, for example, 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 17 cm ⁇ 3 or less, and the depth of the well region 3 is, for example, 0 to prevent pinch-off. .About 5 ⁇ m.
  • the impurity concentration of the contact region 4 is higher than the impurity concentration of the well region 3 and is, for example, 1 ⁇ 10 18 cm ⁇ 3 or more. If the impurity concentration of the contact region 4 is higher than the impurity concentration of the well region 3, it is easy to form an ohmic junction between the contact region 4 and a source electrode to be formed later.
  • the depth of the contact region 4 (depth from the surface of the silicon carbide layer 20) is, for example, about 300 nm.
  • the impurity concentration of the source region 5 is at least 1 ⁇ 10 19 cm ⁇ 3 or more, preferably 6 ⁇ 10 19 cm ⁇ 3 or more, more preferably 1 ⁇ 10 20 cm ⁇ 3 .
  • the depth of the source region 5 is about 300 nm, for example.
  • the gate insulating film 6, the source electrode 8, and the gate electrode 9 are formed on the surface (main surface) of the silicon carbide layer 20, and the drain electrode 7 is formed on the back surface.
  • interlayer insulating film 10 is formed so as to cover gate insulating film 6, gate electrode 9, source electrode 8, and silicon carbide layer 20 exposed on the main surface side.
  • the gate insulating film 6 can be formed, for example, by thermally oxidizing the surface of the silicon carbide layer 20. Specifically, the wafer-like silicon carbide substrate 1 is held in a quartz tube, and bubbled oxygen is introduced at a flow rate of 2.5 SLM (l / s) while the quartz tube is kept at a temperature of 1100 ° C. The surface of silicon carbide layer 20 is thermally oxidized. The time for performing the thermal oxidation is, for example, 3 hours. Thereby, a silicon oxide film (thermal oxide film) having a thickness of about 40 nm is obtained as the gate insulating film 6 on the surface of the silicon carbide layer 20.
  • the gate electrode 9 is preferably formed using polycrystalline silicon having excellent heat resistance and conductivity. This is because the melting point of polycrystalline silicon is 1420 ° C., which is sufficiently higher than the temperature of heat treatment (for example, 1000 ° C.) at the time of forming a source electrode performed in a later step.
  • a polycrystalline silicon film (not shown) is deposited on the gate insulating film 6 by using a low pressure CVD method. Specifically, by using silane and phosphine as source gases, maintaining the pressure at 95 Pa and the growth temperature at 550 ° C. for 8 hours, the n-type impurity concentration is 7 ⁇ 10 20 cm ⁇ 3 and the thickness is 500 nm. A crystalline silicon film is obtained. The polycrystalline silicon film is patterned by photolithography and dry etching to obtain the gate electrode 9.
  • Gate electrode 9 is a portion of the surface of well region 3 where a channel is formed, that is, source region 5 and drift region 2 (a region composed of a portion of silicon carbide layer 20 where well region 3 is not formed). It suffices to cover at least the portion 34 located between them, and the pattern is not particularly limited.
  • the source electrode 8 is formed, for example, by depositing nickel on the entire surface or a part of the p-type contact region 4 and the n-type source region 5.
  • Nickel (not shown) is deposited to a thickness of 100 nm on the entire surface including the p-type contact region 4 and the n-type source region 5 by sputtering.
  • the source electrode 8 is formed by performing patterning by photolithography and etching on the nickel and leaving nickel only on the entire surface or part of the p-type contact region 4 and the n-type source region 5.
  • the source electrode 8 needs to cover a part of each of the p-type contact region 4 and the n-type source region 5, but the pattern is not particularly limited, and the p-type contact region 4 and the n-type contact region 4 There is no problem even if the entire surface of the source region 5 is covered.
  • a silicon oxide film having a high dielectric breakdown voltage and capable of being easily formed is formed as the interlayer insulating film 10.
  • the silicon oxide film can be formed using, for example, an atmospheric pressure CVD method, and the thickness thereof is, for example, 1 ⁇ m.
  • the drain electrode 7 is formed, for example, by depositing titanium on the back side of the silicon carbide substrate 1 and then performing heat treatment to form titanium silicide.
  • a contact hole 13 reaching the source electrode 8 and a contact hole 15 reaching the gate electrode 9 are formed in the interlayer insulating film 10.
  • These contact holes 13 and 15 can be formed using known photolithography and dry etching. As dry etching, for example, reactive ion etching (RIE) using CHF 3 or CF 4 may be performed.
  • RIE reactive ion etching
  • a metal film 22 including a barrier metal is formed on the entire surface of the interlayer insulating film 10 and the contact holes 13 and 15.
  • a stacked film containing titanium (Ti) and titanium nitride (TiN) is formed as the metal film 22.
  • titanium (Ti) and titanium nitride (TiN) are deposited in this order by a reactive sputtering method to obtain a metal film 22 having a total thickness of about 50 nm.
  • a photoresist is applied on the metal film 22, and a part of the photoresist is exposed and patterned. As a result, a resist layer 24 covering the contact hole 13 and its peripheral portion and a resist layer 25 covering the contact hole 15 and its peripheral portion are obtained.
  • the metal film 22 is processed by dry etching or wet etching.
  • wet etching a mixed solution of phosphoric acid and hydrogen peroxide water is used, and the etching time is set to about 10 minutes. After the metal film 22 is etched, the resist layers 24 and 25 are removed.
  • the barrier metal layer 16 and the barrier metal layer 17 separated from each other are obtained from the metal film 22.
  • the barrier metal layer 16 is in contact with the source electrode 8 in the contact hole 13, and the barrier metal layer 17 is in contact with the gate electrode 9 in the contact hole 15.
  • the barrier metal layer 16 is formed so as to cover at least a portion of the side wall of the contact hole 13 and the upper surface of the interlayer insulating film 10 located near the upper end of the contact hole 13.
  • the barrier metal layer 17 is formed so as to cover at least a portion of the side wall of the contact hole 15 and the upper surface of the interlayer insulating film 10 located near the upper end of the contact hole 15.
  • Portions of the interlayer insulating film 10 that are not covered with the barrier metal layers 16 and 17 are exposed.
  • the upper surfaces 16u and 17u and the side surfaces (etched surfaces) 16s and 17s of the barrier metal layers 16 and 17 are exposed at this time.
  • an aluminum (Al) film is deposited on the barrier metal layers 16 and 17 and the interlayer insulating film 10 by vapor deposition or sputtering.
  • the thickness of the Al film is, for example, about 3 ⁇ m.
  • the Al film is patterned using known photolithography and wet etching to form the source electrode upper metal wiring 11 and the gate electrode upper metal wiring 12.
  • a mixed solution of phosphoric acid, nitric acid and acetic acid is used for the wet etching of the Al film. In this way, a wiring 11A including the source electrode upper metal wiring 11 and the barrier metal layer 16 and a wiring 12A including the gate electrode upper metal wiring 12 and the barrier metal layer 17 are obtained.
  • the source electrode upper metal wiring 11 obtained by wet etching is formed so as to cover the entire upper surface 16 u and side surface 16 s of the barrier metal layer 16.
  • the gate electrode upper metal wiring 12 is formed so as to cover the entire upper surface 17 u and side surface 17 s of the barrier metal layer 17. Therefore, the barrier metal layers 16 and 17 are not exposed on the side surfaces 11As and 12As of the wirings 11A and 12A. Thereafter, if necessary, a passivation film may be provided so as to cover the wirings 11A and 12A. In this way, the MISFET 100 is manufactured.
  • the barrier metal layer 16 includes the source electrode 8 in the contact hole 13 and the source electrode upper metal wiring 11, the side wall of the contact hole 13 (side wall of the interlayer insulating film 10), and the source electrode. It is formed only between the upper metal wiring 11 and between the source electrode upper metal wiring 11 and the portion of the upper surface of the interlayer insulating film 10 located near the upper end of the contact hole 13.
  • the barrier metal layer 17 is formed between the gate electrode 9 in the contact hole 15 and the gate electrode upper metal wiring 12, and between the side wall of the contact hole 15 (side wall of the interlayer insulating film 10) and the gate electrode upper metal wiring 12.
  • the barrier metal layer 16 may be provided at least between the source electrode 8 and the source electrode upper metal wiring 11 and not disposed on the side surface of the wiring 11A.
  • the barrier metal layer 17 may be provided at least between the gate electrode 9 and the gate electrode upper metal wiring 12 and not disposed on the side surface of the wiring 12A.
  • etching (wet etching) of the Al film for forming the upper metal wirings 11 and 12 is performed separately from the etching of the Ti / TiN film for forming the barrier metal layers 16 and 17.
  • Ti since Ti is not exposed on the etching surface, Ti does not contact the etching solution. Therefore, the local battery effect due to the difference in the standard electrode potential between Al and Ti does not occur, the increase in Al etching rate can be suppressed, and the variation in local etching rate can also be suppressed. In addition to ensuring, the processed shape can be further stabilized.
  • the shape of the upper wiring metals 11 and 12 in the present embodiment is not limited to the shape shown in FIG.
  • the gate electrode upper metal wiring 12 may be arranged at the center of the region where the plurality of unit cells are arranged.
  • the source electrode upper metal wiring 11 may have two source pads, and a gate wiring extended from the gate pad may be arranged in a gap between these pads.
  • FIG. 7 is a plan view showing another MISFET 200 of the present embodiment.
  • the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted.
  • the source electrode upper metal wiring 11 has two source pads.
  • the gate electrode upper metal wiring 12 includes two gate pads 12p and a gate wiring 12a extending from the gate pads 12p.
  • the two gate pads 12p are connected by a gate wiring 12a.
  • the gate wiring 12 a is also disposed in the gap between the two source pads as viewed from above the substrate 1.
  • the connection portion between the gate electrode upper metal wiring 12 and the gate electrode can be provided not only on the gate pad 12p but also on the gate wiring 12a. Accordingly, it is possible to greatly reduce the wiring delay of the unit cells located at positions away from the gate pad 12p among the plurality of unit cells 30. As a result, the operation speed of the MISFET 200 can be further increased.
  • barrier metal layers 16 and 17 are provided under the upper metal wirings 11 and 12, respectively. Further, when viewed from above the substrate 1, the contours of the barrier metal layers 16 and 17 are arranged inside the contours of the upper metal wirings 11 and 12, respectively. Accordingly, the cross sections taken along lines IIa-IIa ′, IIb-IIb ′, and IIc-IIc ′ shown in FIG. 7 are all the same as the cross section shown in FIG. With such a configuration, as in the MISFET 100 shown in FIG. 1, the local battery effect can be suppressed, so that the dimensional accuracy of the upper metal wirings 11 and 12 can be improved.
  • the configuration of the unit cell 30 and the material of each component in the MISFET of the present embodiment are not limited to the configurations and materials described above with reference to FIGS.
  • a laminated film including a Ti film and a TiN film is used as the barrier metal layers 16 and 17.
  • the barrier metal layers 16 and 17 diffuse metal contained in the upper metal wirings 11 and 12. It is only necessary to include a metal having a function of suppressing the above, and the present invention is not limited to the above laminated film.
  • the barrier metal layers 16 and 17 may be a film containing, for example, Ti, TiN, tungsten, tungsten nitride, tantalum, or tantalum nitride, or may be a laminated film including two or more of these films.
  • the upper metal wirings 11 and 12 are preferably Al films.
  • the source electrode 8 and the gate electrode 9 do not have a silicide layer. However, even if both or one of these electrodes has a silicide layer, the same effect as described above can be obtained. it can. Similarly, although the drain electrode 7 in the above embodiment has a silicide layer, it may not have a silicide layer.
  • the source electrode 8 including the silicide layer is formed as follows, for example. First, a metal film (for example, Ni (nickel) film) is formed so as to be in contact with the silicon carbide layer 20. Next, annealing is performed (for example, in a nitrogen atmosphere at a temperature of 950 ° C. for about 1 minute) to react the silicon carbide layer 20 and the Ni film. Thereby, a part of Ni diffuses into the silicon carbide layer 20 and is alloyed to form a Ni silicide layer.
  • a metal film for example, Ni (nickel) film
  • a Ni silicide layer As the source electrode 8 and the drain electrode 7 because good ohmic contact with the silicon carbide layer 20 can be formed.
  • a Ti film or a cobalt (Co) film may be used as the metal film.
  • a Ti film When a Ti film is used, a Ti silicide layer is formed.
  • the Ti silicide layer does not have a function of barriering Al diffusion and is different from the “barrier metal layer” in this specification.
  • the “barrier metal layer” referred to in this specification is a metal film disposed between an electrode (for example, an electrode including a silicide layer) and an upper metal wiring, and is formed separately from the electrode.
  • the Ti silicide layer when a Ti silicide layer is formed as a source electrode, the Ti silicide layer needs to be separated for each unit cell. On the other hand, it is preferable that the barrier metal layer is not separated for each unit cell. Thereby, the spreading
  • MISFET 100 has an inverted channel structure, but may have a storage channel structure.
  • an oxide film is used as the gate insulating film 6, but an oxynitride film or a nitride film may be used.
  • a stacked film including two or more of an oxide film, an oxynitride film, and a nitride film may be used.
  • a high p + -type contact region 4 of the carrier concentration is provided than the well region 3, p + contact region 4 It may not be formed.
  • the carrier concentration of the well region 3 is sufficiently high, the high concentration p + contact region 4 may not be formed.
  • the conductivity type of silicon carbide substrate 1, silicon carbide layer 20, and source region 5 is n-type, and the conductivity type of well region 3 and contact region 4 is p-type. It is not limited.
  • the conductivity types of silicon carbide substrate 1, silicon carbide layer 20, and source region 5 may be p-type, and the conductivity types of well region 3 and contact region 4 may be n-type.
  • the 4H—SiC substrate is used as the substrate 1, other crystal planes or other polytype SiC substrates may be used.
  • the silicon carbide layer 20 may be formed on the Si surface
  • the drain electrode 7 may be formed on the C surface
  • the silicon carbide layer 20 may be formed on the C surface
  • the drain electrode 7 may be formed on the Si surface. May be.
  • the present invention is not limited to the vertical MISFET, but can be applied to other semiconductor devices using silicon carbide. More specifically, the present invention can be applied to various semiconductor devices having a silicon carbide layer, a plurality of electrodes provided on the silicon carbide layer, and upper metal wirings respectively connected to these electrodes.
  • the substrate 1 may be applied to a semiconductor device having a substrate other than a silicon carbide substrate.
  • the present invention is particularly advantageous when applied to a semiconductor device having a gate insulating film. As a result, an increase in leakage current due to diffusion of the metal of the upper metal wiring into the gate insulating film can be suppressed, so that deterioration in element characteristics can be more effectively suppressed.
  • the present invention can also be applied to a lateral MISFET.
  • the drain electrode is also formed on the silicon carbide layer.
  • the drain electrode is not provided on the back surface of the substrate 1, and one of the source electrodes 8 provided in each adjacent unit cell may be used as the source electrode and the other as the drain electrode.
  • the present invention is applied to a lateral MISFET, at least two of the wirings connected to the source electrode, the drain electrode, and the gate electrode each have a barrier metal layer and an upper metal wiring, and the barrier is viewed from above the substrate. If the contour of the metal layer has a structure arranged inside the contour of the upper metal wiring, the effect of the present invention can be obtained.
  • At least a wiring connected to the gate electrode has the above structure.
  • the metal (such as Al) contained in the upper metal wiring can be prevented from diffusing into the gate insulating film, so that the reliability of the semiconductor device can be improved more effectively.
  • each of the wirings connected to the source electrode, the drain electrode, and the gate electrode has the above structure.
  • the MISFET is manufactured using the SiC substrate 1 having the same conductivity type as that of the silicon carbide layer 20, but the insulated gate bipolar transistor (Insulated) using a SiC substrate having a conductivity type different from that of the silicon carbide layer 20.
  • Gate Bipolar Transistor (IGBT) can also be manufactured.
  • the present invention can also be applied to MESFETs.
  • the present invention it is possible to stabilize the wet etch rate when forming the wiring while securing the thickness of the wiring and to increase the dimensional accuracy with respect to the mask pattern on the resist.
  • the yield of semiconductor devices using silicon carbide can be increased and the reliability can be improved.
  • the present invention can be widely applied to semiconductor devices using silicon carbide, such as vertical MISFETs, horizontal MISFETs, IGBTs, and the like.

Abstract

Disclosed is a semiconductor device (100) which comprises: a silicon carbide layer; a first electrode and a second electrode both formed on the silicon carbide layer; an insulating film formed on the silicon carbide layer and the first and second electrodes and respectively having, formed therein, a first contact hole and a second contact hole both extending to the first electrode and the second electrode, respectively; a first metal wiring line (11) and a second metal wiring line (12) both formed on the insulating film and electrically insulated from each other; a first barrier metal layer (16) formed between the first metal wiring line (11) and the first electrode so as to contact with the first metal wiring line (11) and connected to the first electrode in the first contact hole; and a second barrier metal layer (17) formed between the second metal wiring line (12) and the second electrode so as to contact with the second metal wiring line (12) and connected to the second electrode in the second contact hole. In the semiconductor device (100), the outline form of the first barrier metal layer (16) is arranged in the inside of the outline form of the first metal wiring line (11) and the outline form of the second barrier metal layer (17) is arranged in the inside of the outline form of the second metal wiring line (12), as viewed from above a substrate (1).

Description

半導体装置およびその製造方法Semiconductor device and manufacturing method thereof
　本発明は炭化珪素を用いた半導体装置およびその製造方法に関するものである。 The present invention relates to a semiconductor device using silicon carbide and a method for manufacturing the same.
　炭化珪素（シリコンカーバイド：ＳｉＣ）は、珪素（Ｓｉ）に比べてバンドギャップの大きな高硬度の半導体材料であり、パワー素子、耐環境素子、高温動作素子、高周波素子等の種々の半導体装置に応用されている。なかでも、スイッチング素子や整流素子などのパワーデバイスへの応用が注目されている。 Silicon carbide (silicon carbide: SiC) is a high-hardness semiconductor material with a larger band gap than silicon (Si), and is applied to various semiconductor devices such as power elements, environmental elements, high-temperature operating elements, and high-frequency elements. Has been. Especially, application to power devices, such as a switching element and a rectifier, attracts attention.
　ＳｉＣを用いたパワーデバイスの代表的なスイッチング素子として、金属－半導体電界効果トランジスタ（Ｍｅｔａｌ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ、以下「ＭＥＳＦＥＴ」）と金属－絶縁体－半導体電界効果トランジスタ（Ｍｅｔａｌ　Ｉｎｓｕｌａｔｏｒ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ、以下「ＭＩＳＦＥＴ」）とがある。ＭＩＳＦＥＴとは、チャネル形成領域とゲート電極との間にゲート絶縁膜が介在された絶縁ゲート型電界効果トランジスタを指す。ＭＩＳＦＥＴのうち、ゲート絶縁膜として酸化膜を用いるものは、一般に、金属―酸化膜―半導体電界効果トランジスタ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ、以下「ＭＯＳＦＥＴ」）と呼ばれている。これらのスイッチング素子は、当該スイッチング素子の構成要素であるゲート電極への印加電圧を制御することにより、オン状態と、オフ状態とを切り替えることが出来る。オン状態では数Ａ（アンペア）以上のドレイン電流を流すことができる。また、オフ状態ではドレイン電流は流れず、数百Ｖ以上の高耐圧を実現することが出来る。 As typical switching elements of power devices using SiC, metal-semiconductor field effect transistors (Metal Semiconductor Field Effect Transistors, hereinafter referred to as “MESFET”) and metal-insulator-semiconductor field effect transistors (Metal Insulator Semiconductor Transistor, Hereinafter referred to as “MISFET”). The MISFET refers to an insulated gate field effect transistor in which a gate insulating film is interposed between a channel formation region and a gate electrode. A MISFET that uses an oxide film as a gate insulating film is generally called a metal-oxide film-semiconductor field-effect transistor (hereinafter referred to as a “MOSFET”). These switching elements can be switched between an on state and an off state by controlling a voltage applied to a gate electrode which is a component of the switching element. In the on state, a drain current of several A (amperes) or more can flow. Further, no drain current flows in the off state, and a high breakdown voltage of several hundred volts or more can be realized.
　また、他にも整流素子として、ショットキーダイオードやｐｎダイオードが報告されており、いずれも大電流、高耐圧を実現する整流素子として期待されている。 In addition, Schottky diodes and pn diodes have been reported as rectifying elements, and both are expected as rectifying elements that realize a large current and a high breakdown voltage.
　ＳｉＣはＳｉに比べ、絶縁破壊電界が高く、また熱伝導度も大きいことから、高耐圧化、低損失化が容易である。このため、同一性能を実現させるためには、Ｓｉパワーデバイスに対して、デバイスの大きさ（面積、厚さなど）を大幅に縮小することが可能となる。 SiC has a higher dielectric breakdown electric field and a higher thermal conductivity than Si, so it is easy to increase the breakdown voltage and reduce the loss. For this reason, in order to realize the same performance, the size (area, thickness, etc.) of the device can be greatly reduced with respect to the Si power device.
　縦型ＭＯＳＦＥＴなどのＳｉＣパワーデバイスは、典型的には、複数のユニットセルが配列された構造を有している。各ユニットセルの一般的な構成は、例えば特許文献１に記載されている。各ユニットセルの電極は、電極の上方に設けられた配線に接続される。具体的には、各ユニットセルのゲート電極は、ゲート電極の上部に形成されたゲート電極上部金属配線に接続され、各ユニットセルのソース電極は、ソース電極の上部に形成されたソース電極上部金属配線に接続されている。ソースおよびゲート電極上部金属配線は、同一の導電膜を用いて形成されることが好ましい（例えば特許文献２）。導電膜としては、例えばアルミニウム（Ａｌ）膜が用いられる。ここでいう「上部金属配線」とは、各ユニットセルの電極同士を接続するための配線であればよく、ソースパッドやゲートパッドなどの電極パッド（ワイヤボンディングパッド）だけでなく、電極パッドから延伸された配線をも含む。 An SiC power device such as a vertical MOSFET typically has a structure in which a plurality of unit cells are arranged. A general configuration of each unit cell is described in Patent Document 1, for example. The electrode of each unit cell is connected to the wiring provided above the electrode. Specifically, the gate electrode of each unit cell is connected to the gate electrode upper metal wiring formed on the gate electrode, and the source electrode of each unit cell is the source electrode upper metal formed on the source electrode. Connected to wiring. The source and gate electrode upper metal interconnections are preferably formed using the same conductive film (for example, Patent Document 2). For example, an aluminum (Al) film is used as the conductive film. The “upper metal wiring” here may be a wiring for connecting the electrodes of each unit cell, and extends from the electrode pads (wire bonding pads) such as source pads and gate pads. Also included is a wired connection.
　このようなＳｉＣパワーデバイスでは、上部金属配線（Ａｌ配線）からＡｌが拡散し、信頼性を低下させたり、素子特性を低下させる要因となる可能性がある。そこで、Ａｌの拡散を抑制するために、上部金属配線の下地としてバリアメタル層を配置することが提案されている。 In such a SiC power device, Al diffuses from the upper metal wiring (Al wiring), which may cause a decrease in reliability and a decrease in element characteristics. Therefore, in order to suppress Al diffusion, it has been proposed to dispose a barrier metal layer as a base of the upper metal wiring.
　例えば特許文献３には、Ｓｉパワーデバイス（縦型ＭＯＳＦＥＴ）において、バリアメタル層およびＡｌを含む導電層をこの順で積層し、これをパターニングすることによって、ゲート配線を形成することが開示されている（特許文献３の図９および第３１段落）。 For example, Patent Document 3 discloses that in a Si power device (vertical MOSFET), a barrier metal layer and a conductive layer containing Al are stacked in this order and patterned to form a gate wiring. (FIG. 9 and 31st paragraph of Patent Document 3).
特開平１１－２９７７１２号公報JP-A-11-297712 特開２００４－２８８８９０号公報JP 2004-288890 A 特開２００８－２７７３６５号公報JP 2008-277365 A
　ＳｉＣパワーデバイスでは、Ｓｉパワーデバイスよりも、チップ面積を大幅に小さくできるが、デバイスに流れる電流量は変化しないため、上部金属配線（ＭＯＳＦＥＴではソース電極上部金属配線）に流れる電流の密度が大きくなる。従って、上部金属配線の信頼性を確保するためには、上部金属配線を厚くする必要がある。一般に、ＳｉＣパワーデバイスでは、上部金属配線の厚さは、Ｓｉパワーデバイスの上部金属配線の厚さよりも大きく、２μｍ以上（例えば３μｍ程度）に設定される。 In SiC power devices, the chip area can be significantly reduced compared to Si power devices, but since the amount of current flowing through the device does not change, the density of current flowing through the upper metal wiring (source metal upper metal wiring in MOSFET) increases. . Therefore, in order to ensure the reliability of the upper metal wiring, it is necessary to increase the thickness of the upper metal wiring. Generally, in the SiC power device, the thickness of the upper metal wiring is larger than the thickness of the upper metal wiring of the Si power device, and is set to 2 μm or more (for example, about 3 μm).
　配線の加工技術としては、主に、ウェットエッチング技術とドライエッチング技術とがある。ドライエッチング技術によると、異方性および寸法精度が高く、再現性に優れている。このため、ドライエッチングは、一般の半導体素子の配線加工に用いられることが多い。ただし、ドライエッチングを用いる場合、配線が厚くなると寸法精度が低下する。また、エッチングマスクとなるフォトレジスト膜（以下、「レジスト膜」と略す。）との選択比がウェットエッチングの選択比よりも低いため、厚さが２μｍ程度を超えるような配線の加工に適用することは難しい。従って、ＳｉＣのパワーデバイスの上部金属配線の加工には、ウェットエッチングを用いることが好ましい。 As the wiring processing technology, there are mainly wet etching technology and dry etching technology. According to the dry etching technique, anisotropy and dimensional accuracy are high and reproducibility is excellent. For this reason, dry etching is often used for wiring processing of general semiconductor elements. However, when dry etching is used, the dimensional accuracy decreases as the wiring becomes thicker. Further, since the selection ratio with a photoresist film (hereinafter referred to as “resist film”) serving as an etching mask is lower than the selection ratio of wet etching, it is applied to the processing of wiring having a thickness exceeding about 2 μm. It ’s difficult. Accordingly, wet etching is preferably used for processing the upper metal wiring of the SiC power device.
　一方、上部金属配線として例えばＡｌ配線を用いる場合、上述したように、Ａｌの拡散を防止するために、Ａｌ配線の下方にバリアメタル層（例えばチタン（Ｔｉ）層）を配置することが好ましい。このような配線構造は、例えば、バリアメタル層となるＴｉ膜と、上部金属配線となるＡｌ膜とを含む積層膜を形成し、この積層膜をパターニングすることによって得られる。上部金属配線の厚さを考慮すると、積層膜のパターニングにはウェットエッチングを用いることが好ましい。 On the other hand, when, for example, an Al wiring is used as the upper metal wiring, as described above, it is preferable to dispose a barrier metal layer (for example, a titanium (Ti) layer) below the Al wiring in order to prevent Al diffusion. Such a wiring structure is obtained, for example, by forming a laminated film including a Ti film serving as a barrier metal layer and an Al film serving as an upper metal wiring, and patterning the laminated film. Considering the thickness of the upper metal wiring, it is preferable to use wet etching for patterning the laminated film.
　しかしながら、本発明者が検討したところ、上記の積層膜のパターニングをウェットエッチングによって行うと、上部金属配線を所望の寸法に加工することが困難であるという問題を見出した。この問題については、後で詳述する。 However, as a result of studies by the present inventors, it has been found that when the above-described laminated film is patterned by wet etching, it is difficult to process the upper metal wiring into a desired dimension. This problem will be described in detail later.
　具体的には、上記の積層膜のウェットエッチングでは、Ａｌ膜の単膜をウェットエッチングする場合よりもＡｌのエッチングレートが著しく大きくなった。これは、Ａｌとバリアメタル（例えばＴｉ）との標準電極電位の差により局部電池が形成されたためと考えられる。本明細書において、局部電池によって上部配線金属のエッチングレートが増大する現象を「局部電池効果」と呼ぶ。 Specifically, in the above-described wet etching of the laminated film, the etching rate of Al was remarkably higher than that in the case of wet etching of a single Al film. This is presumably because the local battery was formed by the difference in standard electrode potential between Al and the barrier metal (for example, Ti). In this specification, the phenomenon that the etching rate of the upper wiring metal is increased by the local battery is referred to as “local battery effect”.
　本発明は、上記事情を鑑みてなされたものであり、その目的は、炭化珪素を用いた半導体装置において、上部金属配線からの金属の拡散に起因する素子特性の低下を抑制しつつ、上部金属配線の寸法精度を高めて、高い歩留まりと信頼性とを確保することにある。 The present invention has been made in view of the above circumstances, and an object of the present invention is to suppress deterioration of element characteristics due to diffusion of metal from an upper metal wiring in a semiconductor device using silicon carbide, while suppressing the upper metal. The purpose is to increase the dimensional accuracy of the wiring and to ensure high yield and reliability.
　本発明の半導体装置は、基板と、前記基板の表面に形成された炭化珪素層と、前記炭化珪素層上に形成され、互いに電気的に絶縁された第１電極および第２電極と、前記炭化珪素層と前記第１および第２電極の上に形成された絶縁膜であって、前記絶縁膜には、前記第１電極に達する第１コンタクトホールおよび前記第２電極に達する第２コンタクトホールが形成されている、絶縁膜と、前記絶縁膜上に形成され、互いに電気的に絶縁された第１金属配線および第２金属配線と、前記第１金属配線と前記第１電極との間に、前記第１金属配線と接して形成され、前記第１コンタクトホール内において、前記第１電極と接続されている第１バリアメタル層と、前記第２金属配線と前記第２電極との間に、前記第２金属配線と接して形成され、前記第２コンタクトホール内において、前記第２電極と接続されている第２バリアメタル層とを備え、前記基板の上方から見て、前記第１金属配線の輪郭の内側に前記第１バリアメタルの輪郭が配置され、前記第２金属配線の輪郭の内側に前記第２バリアメタルの輪郭が配置されている。 The semiconductor device according to the present invention includes a substrate, a silicon carbide layer formed on the surface of the substrate, a first electrode and a second electrode formed on the silicon carbide layer and electrically insulated from each other, and the carbonization. An insulating film formed on the silicon layer and the first and second electrodes, wherein the insulating film has a first contact hole reaching the first electrode and a second contact hole reaching the second electrode. Between the formed insulating film, the first metal wiring and the second metal wiring formed on the insulating film and electrically insulated from each other, and between the first metal wiring and the first electrode, A first barrier metal layer formed in contact with the first metal wiring and connected to the first electrode in the first contact hole, and between the second metal wiring and the second electrode, Formed in contact with the second metal wiring; In the second contact hole, a second barrier metal layer connected to the second electrode is provided, and the first barrier metal is formed inside the outline of the first metal wiring as viewed from above the substrate. An outline is arranged, and the outline of the second barrier metal is arranged inside the outline of the second metal wiring.
　ある好ましい実施形態において、前記第１バリアメタル層の表面全体の各部は、前記第１電極、前記第１金属配線または前記絶縁膜で覆われており、前記第２バリアメタル層の表面全体の各部は、前記第２金属、前記第２金属配線または前記絶縁膜で覆われている。 In a preferred embodiment, each part of the entire surface of the first barrier metal layer is covered with the first electrode, the first metal wiring or the insulating film, and each part of the entire surface of the second barrier metal layer. Is covered with the second metal, the second metal wiring or the insulating film.
　ある好ましい実施形態において、前記第１バリアメタル層は、前記第１コンタクトホール内および前記絶縁膜上に形成され、前記第１バリアメタル層の上面および側壁は前記第１金属配線によって覆われており、前記第２バリアメタル層は、前記第２コンタクトホール内および前記絶縁膜上に形成され、前記第２バリアメタル層の上面および側壁は前記第２金属配線によって覆われている。 In a preferred embodiment, the first barrier metal layer is formed in the first contact hole and on the insulating film, and an upper surface and a side wall of the first barrier metal layer are covered with the first metal wiring. The second barrier metal layer is formed in the second contact hole and on the insulating film, and an upper surface and a side wall of the second barrier metal layer are covered with the second metal wiring.
　前記第１および第２金属配線は、同一の導電膜をパターニングすることによって形成されていることが好ましい。 The first and second metal wirings are preferably formed by patterning the same conductive film.
　ある好ましい実施形態において、前記第１および第２金属配線は、前記第１および第２金属配線の間に位置する分離領域によって互いに分離されており、前記第１バリアメタル層および前記第２バリアメタル層は、何れも、前記分離領域において露出していない。 In a preferred embodiment, the first and second metal wirings are separated from each other by an isolation region located between the first and second metal wirings, and the first barrier metal layer and the second barrier metal None of the layers are exposed in the isolation region.
　前記第１および第２バリアメタル層は、同一の金属膜をパターニングすることによって形成されていることが好ましい。 The first and second barrier metal layers are preferably formed by patterning the same metal film.
　前記第１および第２金属配線の厚さは２μｍ以上であってもよい。 The thickness of the first and second metal wirings may be 2 μm or more.
　前記基板の上方から見て、前記第１金属配線の前記輪郭と、前記第１バリアメタルの前記輪郭との最短距離Ｙ１は１μｍ以上であり、前記第２金属配線の前記輪郭と前記第２バリアメタルの前記輪郭との最短距離Ｙ２は１μｍ以上であってもよい。 When viewed from above the substrate, the shortest distance Y1 between the contour of the first metal wiring and the contour of the first barrier metal is 1 μm or more, and the contour of the second metal wiring and the second barrier The shortest distance Y2 from the metal outline may be 1 μm or more.
　前記第１および第２金属配線はアルミニウム層であってもよい。 The first and second metal wirings may be aluminum layers.
　前記第１および第２バリアメタル層は、チタンを含んでもよい。 The first and second barrier metal layers may include titanium.
　前記第１および第２バリアメタル層は、チタン膜および窒化チタン膜を含む積層膜であってもよい。 The first and second barrier metal layers may be a laminated film including a titanium film and a titanium nitride film.
　前記第１電極はソース電極であり、前記第２電極はゲート電極であってもよい。 The first electrode may be a source electrode, and the second electrode may be a gate electrode.
　ある好ましい実施形態において、前記基板は第１導電型の炭化珪素基板であり、前記炭化珪素層に形成された第２導電型のウェル領域と、前記ウェル領域内に形成され、かつ、前記ウェル領域よりも高い濃度で第２導電型の不純物を含むコンタクト領域と、前記ウェル領域内に、前記コンタクト領域を包囲するように形成された第１導電型のソース領域と、前記炭化珪素層のうち前記ウェル領域、前記コンタクト領域、前記ソース領域の何れも形成されなかった部分に形成された第１導電型のドリフト領域と、前記炭化珪素層上に形成されたゲート絶縁膜と、前記基板の裏面に形成されたドレイン電極とをさらに備え、前記ソース電極は、前記炭化珪素層上に、前記コンタクト領域および前記ソース領域と接するように形成されており、前記ゲート電極は前記ゲート絶縁膜上に形成されている。 In a preferred embodiment, the substrate is a first conductivity type silicon carbide substrate, a second conductivity type well region formed in the silicon carbide layer, formed in the well region, and the well region A contact region containing a second conductivity type impurity at a higher concentration, a first conductivity type source region formed in the well region so as to surround the contact region, and the silicon carbide layer, A first conductivity type drift region formed in a portion where none of the well region, the contact region, and the source region is formed, a gate insulating film formed on the silicon carbide layer, and a back surface of the substrate A drain electrode formed, and the source electrode is formed on the silicon carbide layer so as to be in contact with the contact region and the source region. The gate electrode is formed on the gate insulating film.
　本発明の半導体装置の製造方法は、（Ａ）基板上に炭化珪素層を形成する工程と、（Ｂ）前記炭化珪素層上に、互いに電気的に絶縁された第１電極および第２電極を形成する工程と、（Ｃ）前記炭化珪素層と前記第１および第２電極の上に絶縁膜を形成し、前記絶縁膜に、前記第１電極に達する第１コンタクトホールおよび前記第２電極に達する第２コンタクトホールを形成する工程と、（Ｄ）前記第１および第２コンタクトホール内および前記絶縁膜上に金属膜を形成する工程と、（Ｅ）前記金属膜をパターニングして、前記第１コンタクトホール内において前記第１電極に接続された第１バリアメタル層と、前記第１バリアメタル層と電気的に分離され、かつ、前記第２コンタクトホール内において前記第２電極に接続された第２バリアメタル層とを得る工程と、（Ｆ）前記第１バリアメタル層、第２バリアメタル層および前記絶縁膜上に、導電膜を形成する工程と、（Ｇ）前記導電膜をウェットエッチングによってパターニングして、前記第１バリアメタル層に接続された第１金属配線と、前記第１金属配線と電気的に分離され、かつ、前記第２バリアメタル層に接続された第２金属配線とを得る工程とを包含し、前記基板の上方から見て、前記第１金属配線の輪郭の内側に前記第１バリアメタルの輪郭が配置され、前記第２金属配線の輪郭の内側に前記第２バリアメタルの輪郭が配置されている。 The method of manufacturing a semiconductor device of the present invention includes (A) a step of forming a silicon carbide layer on a substrate, and (B) a first electrode and a second electrode that are electrically insulated from each other on the silicon carbide layer. And (C) forming an insulating film on the silicon carbide layer and the first and second electrodes, and forming a first contact hole reaching the first electrode and the second electrode on the insulating film Forming a second contact hole reaching; (D) forming a metal film in the first and second contact holes and on the insulating film; and (E) patterning the metal film, A first barrier metal layer connected to the first electrode in one contact hole and electrically separated from the first barrier metal layer and connected to the second electrode in the second contact hole Second Bali Obtaining a metal layer; (F) forming a conductive film on the first barrier metal layer, the second barrier metal layer, and the insulating film; and (G) patterning the conductive film by wet etching. And obtaining a first metal wiring connected to the first barrier metal layer and a second metal wiring electrically isolated from the first metal wiring and connected to the second barrier metal layer. And when viewed from above the substrate, the contour of the first barrier metal is disposed inside the contour of the first metal wiring, and the contour of the second barrier metal is disposed inside the contour of the second metal wiring. The contour is arranged.
　ある好ましい実施形態において、前記工程（Ｇ）は、前記導電膜をエッチングして、前記第１金属配線と前記第２金属配線とを互いに分離するための分離領域を形成する工程を含み、前記第１バリアメタル層および前記第２バリアメタル層は、何れも、前記分離領域において露出していない。 In a preferred embodiment, the step (G) includes a step of etching the conductive film to form an isolation region for isolating the first metal wiring and the second metal wiring from each other. Neither the first barrier metal layer nor the second barrier metal layer is exposed in the isolation region.
　前記導電膜の厚さは２μｍ以上であってもよい。 The thickness of the conductive film may be 2 μm or more.
　前記導電膜はアルミニウム膜であってもよい。 The conductive film may be an aluminum film.
　前記金属膜は、チタン膜および窒化チタン膜を含む積層膜であってもよい。 The metal film may be a laminated film including a titanium film and a titanium nitride film.
　前記第１電極はソース電極であり、前記第２電極はゲート電極であってもよい。 The first electrode may be a source electrode, and the second electrode may be a gate electrode.
　ある好ましい実施形態において、前記工程（Ａ）の後に行われ、前記炭化珪素層にウェル領域、ソース領域、およびコンタクト領域を形成する工程と、前記炭化珪素層上にゲート絶縁膜を形成する工程と、前記基板の裏面にドレイン電極を形成する工程とをさらに包含し、前記ゲート電極は、前記ゲート絶縁膜上に形成され、前記ソース電極は、前記ソース領域および前記コンタクト領域と接するように形成される。 In a preferred embodiment, a step of forming a well region, a source region, and a contact region in the silicon carbide layer after the step (A), and a step of forming a gate insulating film on the silicon carbide layer, Forming a drain electrode on the back surface of the substrate, wherein the gate electrode is formed on the gate insulating film, and the source electrode is formed in contact with the source region and the contact region. The
　本発明の半導体装置によると、上部金属配線の下地としてバリアメタルが配置されているので、上部金属配線に含まれる金属の拡散による素子特性の低下を抑制できる。また、上部金属配線の厚さを確保しつつ、バリアメタルに起因する上部金属配線の寸法精度の低下を防止できる。従って、歩留まりを高め、信頼性を向上できる。 According to the semiconductor device of the present invention, since the barrier metal is disposed as the base of the upper metal wiring, it is possible to suppress deterioration of element characteristics due to diffusion of the metal contained in the upper metal wiring. Further, it is possible to prevent the dimensional accuracy of the upper metal wiring from being lowered due to the barrier metal while ensuring the thickness of the upper metal wiring. Therefore, the yield can be increased and the reliability can be improved.
　本発明の半導体装置の製造方法によると、上部金属配線をウェットエッチングで形成する際に、バリアメタルが露出することによって生じる局部電池効果を抑制できる。この結果、上部金属配線のエッチングレートが増大することを防止でき、レジスト膜上のマスクパターンに対する上部金属配線の寸法精度を高めることができる。 According to the method for manufacturing a semiconductor device of the present invention, when the upper metal wiring is formed by wet etching, the local battery effect caused by the exposure of the barrier metal can be suppressed. As a result, an increase in the etching rate of the upper metal wiring can be prevented, and the dimensional accuracy of the upper metal wiring with respect to the mask pattern on the resist film can be increased.
本発明による第１実施形態の縦型ＭＩＳＦＥＴ１００の模式的な平面図である。1 is a schematic plan view of a vertical MISFET 100 according to a first embodiment of the present invention. （ａ）～（ｃ）は、それぞれ、図１に示すＭＩＳＦＥＴにおけるＩ－Ｉ’線、ＩＩ－ＩＩ’線、およびＩＩＩ－ＩＩＩ’線に沿った部分断面図である。(A) to (c) are partial cross-sectional views taken along lines I-I ′, II-II ′, and III-III ′ in the MISFET shown in FIG. 1, respectively. （ａ）および（ｂ）は、それぞれ、本発明による第１実施形態の縦型ＭＩＳＦＥＴの製造方法を説明するための断面工程図である。(A) And (b) is sectional process drawing for demonstrating the manufacturing method of the vertical MISFET of 1st Embodiment by this invention, respectively. （ａ）および（ｂ）は、それぞれ、本発明による第１実施形態の縦型ＭＩＳＦＥＴの製造方法を説明するための断面工程図である。(A) And (b) is sectional process drawing for demonstrating the manufacturing method of the vertical MISFET of 1st Embodiment by this invention, respectively. （ａ）および（ｂ）は、それぞれ、本発明による第１実施形態の縦型ＭＩＳＦＥＴの製造方法を説明するための断面工程図である。(A) And (b) is sectional process drawing for demonstrating the manufacturing method of the vertical MISFET of 1st Embodiment by this invention, respectively. （ａ）および（ｂ）は、それぞれ、本発明による第１実施形態の縦型ＭＩＳＦＥＴの製造方法を説明するための断面工程図である。(A) And (b) is sectional process drawing for demonstrating the manufacturing method of the vertical MISFET of 1st Embodiment by this invention, respectively. 本発明による第１実施形態の他の縦型ＭＩＳＦＥＴ２００の模式的な平面図である。It is a typical top view of other vertical type MISFET200 of a 1st embodiment by the present invention. （ａ）～（ｃ）は、それぞれ、ウェットエッチングによって配線を形成する方法の参考例を説明するための工程断面図であり、配線の形成の際に生じる局部電池効果を説明するための図である。(A) to (c) are process cross-sectional views for explaining a reference example of a method of forming a wiring by wet etching, and a diagram for explaining a local battery effect generated when the wiring is formed. is there.
　上述したように、本発明者は、上部金属配線およびバリアメタル層の加工にウェットエッチングを用いると、局部電池効果が生じる結果、上部金属配線の寸法精度が低下することを見出した。 As described above, the present inventors have found that when wet etching is used for processing the upper metal wiring and the barrier metal layer, the local battery effect is produced, resulting in a decrease in dimensional accuracy of the upper metal wiring.
　以下、図面を参照しながら、上部金属配線としてＡｌ配線、バリアメタル層としてＴｉ層を形成する場合を例に、局部電池効果をより具体的に説明する。 Hereinafter, the local battery effect will be described more specifically with reference to the drawings, taking as an example the case of forming an Al wiring as the upper metal wiring and a Ti layer as the barrier metal layer.
　図８（ａ）～（ｃ）は、上部金属配線およびバリアメタル層の形成工程の参考例を示す断面工程図である。 8A to 8C are cross-sectional process diagrams illustrating a reference example of the process of forming the upper metal wiring and the barrier metal layer.
　まず、図８（ａ）に示すように、Ｔｉ膜５１およびＡｌ膜５３をこの順で形成する。次いで、Ａｌ膜５３の上にマスク層５５を配置する。Ａｌ膜５３の厚さは２μｍ以上、例えば３μｍとし、Ｔｉ膜の厚さは例えば５０ｎｍとする。 First, as shown in FIG. 8A, a Ti film 51 and an Al film 53 are formed in this order. Next, a mask layer 55 is disposed on the Al film 53. The thickness of the Al film 53 is 2 μm or more, for example, 3 μm, and the thickness of the Ti film is, for example, 50 nm.
　続いて、マスク層５５をエッチングマスクとして、Ｔｉ膜５１およびＡｌ膜５３に対してウェットエッチングを行う。エッチング液としては、例えば燐酸と硝酸の混合液を用いる。 Subsequently, wet etching is performed on the Ti film 51 and the Al film 53 using the mask layer 55 as an etching mask. As the etching solution, for example, a mixed solution of phosphoric acid and nitric acid is used.
　エッチング工程では、図８（ｂ）に示すように、まず、一様なスピードでＡｌのエッチングが進み、Ａｌ膜のうちマスク層５５で覆われていない部分が除去されて、Ｔｉ膜５１の表面が露出する。Ａｌ膜のうちエッチングされずに残った部分５３ａは、マスク層５５によって規定される形状を有する。 In the etching process, as shown in FIG. 8B, first, Al etching proceeds at a uniform speed, and the portion of the Al film not covered with the mask layer 55 is removed, and the surface of the Ti film 51 is removed. Is exposed. A portion 53 a of the Al film that remains without being etched has a shape defined by the mask layer 55.
　Ｔｉ膜５１の表面が露出してウェットエッチングの薬液に触れると、Ｔｉ膜５１、Ａｌ膜のうちエッチングされずに残った部分５３ａ、およびエッチング液によって局部電池が形成される。このため、Ｔｉ膜５１の表面のうちエッチング液と接する部分で電子の消費反応（一般には、２Ｈ+＋２ｅ-によって、Ｈ2が発生）が起こり、Ａｌのエッチング時に発生した電子を消費する反応を引き起こしてしまう。この結果、電子を供給するＡｌのエッチングレートが著しく増大し（局部電池効果）、Ｔｉ膜５１がエッチングされる間に、Ａｌ層５３ａのエッチングが進み、オーバーエッチングが著しくなる。このようにして、図８（ｃ）に例示するように、上部金属配線となるＡｌ層５４と、バリアメタル層となるＴｉ層５２とが形成される。Ａｌ層５４およびＴｉ層５２のパターンは、マスク層５５によって規定されるパターンよりも小さくなる。エッチング条件や各層の厚さによって異なるが、Ａｌ層５４の端部とマスク層５５の端部との距離ｄＺが例えば５μｍ以上となることもある。また、例えばマスク層５５の幅が小さいと、局部電池効果によってＡｌ層５３ａの全体が除去されてしまうこともある。 When the surface of the Ti film 51 is exposed and touched with a chemical solution for wet etching, a local battery is formed by the Ti film 51, the portion 53a of the Al film that remains unetched, and the etching solution. Therefore, an electron consumption reaction (generally, H 2 is generated by 2H + + 2e − ) occurs in the portion of the surface of the Ti film 51 in contact with the etching solution, and a reaction that consumes the electrons generated during the etching of Al occurs. It will cause. As a result, the etching rate of Al supplying electrons is remarkably increased (local cell effect), and while the Ti film 51 is etched, the etching of the Al layer 53a proceeds and over-etching becomes remarkable. In this way, as illustrated in FIG. 8C, an Al layer 54 serving as an upper metal wiring and a Ti layer 52 serving as a barrier metal layer are formed. The pattern of the Al layer 54 and the Ti layer 52 is smaller than the pattern defined by the mask layer 55. Depending on the etching conditions and the thickness of each layer, the distance dZ between the end of the Al layer 54 and the end of the mask layer 55 may be 5 μm or more, for example. For example, if the width of the mask layer 55 is small, the entire Al layer 53a may be removed due to the local battery effect.
　このように、上部金属配線を厚くし、その加工にウェットエッチングを用いると、上述したような局部電池効果を引き起こすことが分かった。局部電池効果が生じると、上部金属配線の寸法精度（マスク層５５によって規定される寸法に対する精度）が低下し、歩留まりが低くなる。 Thus, it has been found that when the upper metal wiring is made thicker and wet etching is used for the processing, the local battery effect as described above is caused. When the local battery effect occurs, the dimensional accuracy of the upper metal wiring (accuracy with respect to the size defined by the mask layer 55) decreases, and the yield decreases.
　上記では、上部金属配線としてＡｌ層、バリアメタル層としてＴｉ層を用いる場合を例に説明したが、局部電池効果は、これらの材料を用いる場合のみでなく、上部金属配線の金属の標準電極電位よりも、バリアメタルの標準電極電位の方が小さい場合に生じ得る。 In the above description, the case where the Al layer is used as the upper metal wiring and the Ti layer is used as the barrier metal layer has been described as an example. However, the local battery effect is not only when these materials are used, but also the standard electrode potential of the metal of the upper metal wiring. It may occur when the standard electrode potential of the barrier metal is smaller than that.
　また、本発明者が検討したところ、Ａｌ膜の加工の際に１箇所でもバリアメタル層が露出し、局部電池が生じてしまうと、バリアメタル層の露出した部分と電気的に接続されているＡｌ膜全体が局部電池の影響を受けるおそれがあることもわかった。 Further, as a result of examination by the present inventor, when the Al metal film is processed, the barrier metal layer is exposed even at one location, and when a local battery is generated, the Al metal is electrically connected to the exposed portion of the barrier metal layer. It was also found that the entire Al film might be affected by the local battery.
　なお、ドライエッチングを適用できる程度まで上部金属配線を薄くすると、大電流の流れるパワー炭化珪素素子において、上部金属配線の信頼性を確保できない。一方、バリアメタル層を設けなければ、局部電池効果も生じないが、上部金属配線の金属（Ａｌ）が拡散し、素子特性を低下させるおそれがある。本発明者が検討したところ、特に、上部金属配線のＡｌがゲート絶縁膜に拡散すると、リーク電流を増大させる要因となることを見出した。また、Ａｌがソース電極などの電極に拡散すると、電極の抵抗が高くなるので、オン抵抗が増大するおそれがある。 Note that if the upper metal wiring is thinned to such an extent that dry etching can be applied, the reliability of the upper metal wiring cannot be ensured in a power silicon carbide element through which a large current flows. On the other hand, if the barrier metal layer is not provided, the local battery effect does not occur, but the metal (Al) of the upper metal wiring diffuses and there is a risk of deteriorating element characteristics. As a result of investigation by the present inventor, it has been found that particularly when Al of the upper metal wiring diffuses into the gate insulating film, it causes a leakage current. Further, when Al diffuses into an electrode such as a source electrode, the resistance of the electrode increases, so that the on-resistance may increase.
　そこで、本発明者は、上部金属配線の厚さを確保し、かつ、バリアメタルを用いて上部金属配線からの金属の拡散を防止しつつ、局部電池効果を抑制する構成を検討し、本願発明に至った。 Therefore, the present inventor examined a configuration for suppressing the local battery effect while securing the thickness of the upper metal wiring and preventing the diffusion of the metal from the upper metal wiring using the barrier metal. It came to.
　（実施の形態１）
　以下、図面を参照しながら、本発明による半導体装置の第１の実施形態を説明する。本実施形態の半導体装置は、炭化珪素を用いた縦型ＭＩＳＦＥＴである。 (Embodiment 1)
A semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings. The semiconductor device of this embodiment is a vertical MISFET using silicon carbide.
　図１は、本実施形態の炭化珪素を用いた縦型ＭＩＳＦＥＴ１００の平面図であり、図２（ａ）～（ｃ）は、それぞれ、図１に示す平面図におけるＩ－Ｉ’線、ＩＩ－ＩＩ’線、およびＩＩＩ－ＩＩＩ’線に沿った部分断面図である。 FIG. 1 is a plan view of a vertical MISFET 100 using silicon carbide according to the present embodiment. FIGS. 2A to 2C are views taken along lines II ′ and II− in the plan view shown in FIG. FIG. 3 is a partial cross-sectional view taken along line II ′ and line III-III ′.
　図１に示すように、ＭＩＳＦＥＴ１００は、基板１と、基板１に支持された複数のユニットセル３０とを有している。これらのユニットセル３０は二次元的に配列されている。ユニットセル３０の上部には、各ユニットセル３０のソース電極に接続された配線１１Ａと、各ユニットセル３０のゲート電極９に接続された配線１２Ａとが設けられている。これらの配線１１Ａ、１２Ａは、分離領域３２によって互いに分離されている。 As shown in FIG. 1, the MISFET 100 includes a substrate 1 and a plurality of unit cells 30 supported by the substrate 1. These unit cells 30 are arranged two-dimensionally. On the upper part of the unit cell 30, a wiring 11A connected to the source electrode of each unit cell 30 and a wiring 12A connected to the gate electrode 9 of each unit cell 30 are provided. These wirings 11A and 12A are separated from each other by the separation region 32.
　配線１１Ａは、ソース電極上部金属配線（「第１金属配線」ともいう）１１とバリアメタル層（「第１バリアメタル層」ともいう）１６とを含んでいる。バリアメタル層１６は、ソース電極上部金属配線１１とソース電極との間に配置されている。また、基板１の上方から見て、すなわち図１に示す平面図において、ソース電極上部金属配線１１の輪郭の内側にバリアメタル層１６の輪郭が配置されている。 The wiring 11 </ b> A includes a source electrode upper metal wiring (also referred to as “first metal wiring”) 11 and a barrier metal layer (also referred to as “first barrier metal layer”) 16. The barrier metal layer 16 is disposed between the source electrode upper metal wiring 11 and the source electrode. Further, when viewed from above the substrate 1, that is, in the plan view shown in FIG. 1, the contour of the barrier metal layer 16 is arranged inside the contour of the source electrode upper metal wiring 11.
　配線１２Ａは、ゲート電極上部金属配線（「第２金属配線」ともいう）１２とバリアメタル層（「第２バリアメタル層」ともいう）１７とを含んでいる。バリアメタル層１７は、ゲート電極上部金属配線１２とゲート電極９との間に配置されている。また、基板１の上方から見て、すなわち図１に示す平面図において、ゲート電極上部金属配線１２の輪郭の内側にバリアメタル層１７の輪郭が配置されている。 The wiring 12 </ b> A includes a gate electrode upper metal wiring (also referred to as “second metal wiring”) 12 and a barrier metal layer (also referred to as “second barrier metal layer”) 17. The barrier metal layer 17 is disposed between the gate electrode upper metal wiring 12 and the gate electrode 9. Further, when viewed from above the substrate 1, that is, in the plan view shown in FIG. 1, the contour of the barrier metal layer 17 is arranged inside the contour of the gate electrode upper metal wiring 12.
　上部金属配線１１、１２および分離領域３２は、同一の導電膜（例えばＡｌ膜）をパターニングすることによって形成されていることが好ましい。分離領域３２は、導電膜の一部を除去することによって形成された領域であり、上部金属配線１１の側面と、この側面に対向する上部金属配線１２の側面とによって規定される。また、バリアメタル層１６、１７は、好ましくは、同一の金属膜（例えばＴｉ膜、ＴｉＮ膜、あるいはＴｉ膜とＴｉＮ膜との積層膜）をパターニングすることによって形成されている。 The upper metal wirings 11 and 12 and the isolation region 32 are preferably formed by patterning the same conductive film (for example, an Al film). The isolation region 32 is a region formed by removing a part of the conductive film, and is defined by the side surface of the upper metal wiring 11 and the side surface of the upper metal wiring 12 facing this side surface. The barrier metal layers 16 and 17 are preferably formed by patterning the same metal film (for example, a Ti film, a TiN film, or a laminated film of a Ti film and a TiN film).
　図示する例では、ゲート電極９は、各ユニットセル３０においてゲートとして機能するゲート部９ｇと、配線１２Ａとゲート部９ｇとを接続するためのゲート接続部９ｃとを有している。なお、本実施形態のゲート電極９の構成は図示する構成に限定されない。例えばゲート部９ｇも、バリアメタル層１７を介してゲート電極上部金属配線１２と接続されていてもよい。 In the illustrated example, the gate electrode 9 has a gate portion 9g functioning as a gate in each unit cell 30, and a gate connection portion 9c for connecting the wiring 12A and the gate portion 9g. Note that the configuration of the gate electrode 9 of the present embodiment is not limited to the illustrated configuration. For example, the gate portion 9 g may also be connected to the gate electrode upper metal wiring 12 through the barrier metal layer 17.
　次いで、図２（ａ）を参照しながら、各ユニットセル３０の断面構造を説明する。各ユニットセル３０は、基板１と、基板１の主面上に、エピタキシャル成長により形成された炭化珪素層２０と、炭化珪素層２０の上にゲート絶縁膜６を介して設けられたゲート電極９と、炭化珪素層２０の表面に接するソース電極８と、基板１の裏面上に設けられたドレイン電極７とを備えている。ここでは、基板１として、低抵抗のｎ型の炭化珪素基板（以下、ＳｉＣ基板）を用いる。 Next, the cross-sectional structure of each unit cell 30 will be described with reference to FIG. Each unit cell 30 includes a substrate 1, a silicon carbide layer 20 formed by epitaxial growth on the main surface of the substrate 1, and a gate electrode 9 provided on the silicon carbide layer 20 via a gate insulating film 6. Source electrode 8 in contact with the surface of silicon carbide layer 20 and drain electrode 7 provided on the back surface of substrate 1. Here, a low-resistance n-type silicon carbide substrate (hereinafter, SiC substrate) is used as the substrate 1.
　炭化珪素層２０には、ＳｉＣ基板１の導電型と異なる導電型（ここではｐ型）を有するウェル領域３と、炭化珪素層２０のうちウェル領域３が形成されていない部分を含むドリフト領域２とが形成されている。ドリフト領域２は、ＳｉＣ基板１よりも低濃度でｎ型不純物を含むｎ-型の炭化珪素層である。さらに、ウェル領域３の内部には、高濃度でｎ型不純物を含むｎ型ソース領域５、および、ソース領域５に囲まれるように配置され、ウェル領域３よりも高い濃度でｐ型不純物を含むｐ+型コンタクト領域４が形成されている。ウェル領域３、ソース領域５およびコンタクト領域４は、炭化珪素層２０に対して不純物イオンを注入することによって形成されている。 Silicon carbide layer 20 includes well region 3 having a conductivity type (p-type in this case) different from that of SiC substrate 1 and drift region 2 including a portion of silicon carbide layer 20 where well region 3 is not formed. And are formed. Drift region 2 is an n − type silicon carbide layer containing n type impurities at a lower concentration than SiC substrate 1. Further, the well region 3 is disposed so as to be surrounded by the n-type source region 5 containing high-concentration n-type impurities and the source region 5, and contains p-type impurities at a higher concentration than the well region 3. A p + -type contact region 4 is formed. Well region 3, source region 5 and contact region 4 are formed by implanting impurity ions into silicon carbide layer 20.
　コンタクト領域４およびソース領域５は、それぞれ、ソース電極８に対してオーミック接触を形成している。従って、ウェル領域３は、コンタクト領域４を介してソース電極８と電気的に接続される。 The contact region 4 and the source region 5 are in ohmic contact with the source electrode 8, respectively. Therefore, the well region 3 is electrically connected to the source electrode 8 through the contact region 4.
　ゲート絶縁膜６およびゲート電極９は、１つのウェル領域３の内部のソース領域５の端部から、ウェル領域間のドリフト領域２をまたいで隣接するウェル領域３の内部のソース領域５の端部までを覆っている。 The gate insulating film 6 and the gate electrode 9 are connected to the end of the source region 5 in the adjacent well region 3 across the drift region 2 between the well regions from the end of the source region 5 in one well region 3. Covers up to.
　炭化珪素層２０、ソース電極８およびゲート電極９は、層間絶縁膜１０によって覆われている。層間絶縁膜１０には、ソース電極８に達するコンタクトホール１３が設けられている。コンタクトホール１３内には、ソース電極８と接するようにバリアメタル層１６が形成されている。ソース電極上部金属配線１１は、コンタクトホール１３内および層間絶縁膜１０上に、バリアメタル層１６の上面と接するように形成されている。従って、各ユニットセル３０のソース電極８は、バリアメタル層１６を介して、ソース電極上部金属配線１１に接続されている。 The silicon carbide layer 20, the source electrode 8 and the gate electrode 9 are covered with an interlayer insulating film 10. A contact hole 13 reaching the source electrode 8 is provided in the interlayer insulating film 10. A barrier metal layer 16 is formed in the contact hole 13 so as to be in contact with the source electrode 8. The source electrode upper metal interconnection 11 is formed in the contact hole 13 and on the interlayer insulating film 10 so as to be in contact with the upper surface of the barrier metal layer 16. Accordingly, the source electrode 8 of each unit cell 30 is connected to the source electrode upper metal wiring 11 via the barrier metal layer 16.
　一方、各ユニットセル３０のゲート電極９は、図１に示す平面図からもわかるように、互いに接続されている。具体的には、本実施形態におけるゲート電極９は、各ユニットセル３０のソース領域５およびコンタクト領域４を開口する開口部を有しているが、ユニットセル間で分離されていない。ゲート電極９は、また、ゲート電極上部金属配線１２の下方まで延伸されている（ゲート接続部９ｃ）。 On the other hand, the gate electrodes 9 of the unit cells 30 are connected to each other as can be seen from the plan view shown in FIG. Specifically, the gate electrode 9 in the present embodiment has an opening that opens the source region 5 and the contact region 4 of each unit cell 30, but is not separated between unit cells. The gate electrode 9 is also extended to below the gate electrode upper metal wiring 12 (gate connection portion 9c).
　次に、図２（ｂ）を参照しながら、ゲート電極９とゲート電極上部金属配線１２とを接続する断面構造、および、配線１１Ａ、１１Ｂの周縁部近傍における断面構造を説明する。 Next, a cross-sectional structure for connecting the gate electrode 9 and the gate electrode upper metal wiring 12 and a cross-sectional structure in the vicinity of the periphery of the wirings 11A and 11B will be described with reference to FIG.
　層間絶縁膜１０には、ゲート電極９（ここではゲート接続部９ｃ）に達するコンタクトホール１５が設けられている。コンタクトホール１５内には、ゲート接続部９ｃと接するようにバリアメタル層１７が形成されている。ゲート電極上部金属配線１２は、コンタクトホール１５内および層間絶縁膜１０上に、バリアメタル層１７の上面と接するように形成されている。このようにして、ゲート電極９は、バリアメタル層１７を介して、ゲート電極上部金属配線１２に接続されている。 The interlayer insulating film 10 is provided with a contact hole 15 reaching the gate electrode 9 (here, the gate connection portion 9c). A barrier metal layer 17 is formed in the contact hole 15 so as to be in contact with the gate connection portion 9c. Gate electrode upper metal interconnection 12 is formed in contact hole 15 and on interlayer insulating film 10 so as to be in contact with the upper surface of barrier metal layer 17. In this way, the gate electrode 9 is connected to the gate electrode upper metal wiring 12 through the barrier metal layer 17.
　また、図２（ｂ）からわかるように、バリアメタル層１６の側面および上面は、ソース電極上部金属配線１１によって覆われている。同様に、バリアメタル層１７の側面および上面は、ゲート電極上部金属配線１２によって覆われている。言い換えると、配線１１Ａの側面１１Ａｓにバリアメタル層１６は設けられておらず、配線１２Ａの側面１２Ａｓにバリアメタル層１７は設けられていない。 Further, as can be seen from FIG. 2B, the side surface and the upper surface of the barrier metal layer 16 are covered with the source electrode upper metal wiring 11. Similarly, the side and upper surfaces of the barrier metal layer 17 are covered with the gate electrode upper metal wiring 12. In other words, the barrier metal layer 16 is not provided on the side surface 11As of the wiring 11A, and the barrier metal layer 17 is not provided on the side surface 12As of the wiring 12A.
　なお、図２（ｂ）では、配線１１Ａの周縁部のうち分離領域３２側の部分の断面構造を示したが、配線１１Ａの周縁部の他の部分の断面（ＩＩＩ－ＩＩＩ’線に沿った断面）も、図２（ｂ）と同様の構造を有している。すなわち、図２（ｃ）に示すように、バリアメタル層１６の側面および上面は、ソース電極上部金属配線１１によって覆われており、配線１１Ａの側面１１Ａｓにバリアメタル層１６が設けられていない。 2B shows the cross-sectional structure of the portion of the peripheral portion of the wiring 11A on the separation region 32 side, the cross section of the other portion of the peripheral portion of the wiring 11A (along the line III-III ′). The cross section also has a structure similar to that shown in FIG. That is, as shown in FIG. 2C, the side surface and the upper surface of the barrier metal layer 16 are covered with the source electrode upper metal wiring 11, and the barrier metal layer 16 is not provided on the side surface 11As of the wiring 11A.
　本実施形態では、バリアメタル層１６、１７は、ソース電極上部金属配線１１及びゲート電極上部金属配線１２の下面全面に存在せず、ソース電極上部金属配線１１の一部およびゲート電極上部金属配線１２の一部が層間絶縁膜１０と直接接する。 In the present embodiment, the barrier metal layers 16 and 17 do not exist on the entire lower surface of the source electrode upper metal wiring 11 and the gate electrode upper metal wiring 12, but a part of the source electrode upper metal wiring 11 and the gate electrode upper metal wiring 12. A part of is in direct contact with the interlayer insulating film 10.
　図８を参照しながら前述した参考例では、バリアメタルを含む膜（Ｔｉ膜）５１と、上部金属配線を形成するための導電膜（Ａｌ膜）５３とを堆積し、これらの膜を同時にウェットエッチングすることによって、バリアメタル層（Ｔｉ層）５２および上部金属配線（Ａｌ層）５４を形成している。このため、バリアメタル層５２と上部金属配線５４とは略同一の平面形状を有している。従って、バリアメタル層５２は、上部金属配線５４の下面全体に存在している。また、基板上方から見ると、上部金属配線５４の輪郭とバリアメタル層５２の輪郭とは略一致している。バリアメタル層５２および上部金属配線５４から配線（例えば電極パッド）を構成すると、その配線の側面の一部には必ずバリアメタル層５２が設けられる。 In the reference example described above with reference to FIG. 8, a film (Ti film) 51 including a barrier metal and a conductive film (Al film) 53 for forming an upper metal wiring are deposited, and these films are simultaneously wetted. By etching, a barrier metal layer (Ti layer) 52 and an upper metal wiring (Al layer) 54 are formed. For this reason, the barrier metal layer 52 and the upper metal wiring 54 have substantially the same planar shape. Therefore, the barrier metal layer 52 exists on the entire lower surface of the upper metal wiring 54. Further, when viewed from above the substrate, the contour of the upper metal wiring 54 and the contour of the barrier metal layer 52 substantially coincide. When a wiring (for example, an electrode pad) is formed from the barrier metal layer 52 and the upper metal wiring 54, the barrier metal layer 52 is always provided on a part of the side surface of the wiring.
　これに対し、本実施形態では、基板１の上方から見て、上部金属配線１１、１２の輪郭の内側に、それぞれ、バリアメタル層１６、１７の輪郭が配置されている。また、配線１１Ａ、１２Ａの側面に、バリアメタル層１６、１７が設けられていない。このような構成は、バリアメタル層１６、１７を形成するためのパターニングと、上部金属配線１１、１２を形成するためのパターニングとを別々に行うことによって実現される。例えば、バリアメタル層１６、１７を形成した後、バリアメタル層１６、１７を覆う導電膜を形成する。次いで、導電膜のみをエッチングして、上部金属配線１１、１２を得る。具体的な製造プロセスは後で詳しく説明する。これにより、導電膜と金属膜とを同時にエッチングする際に生じる問題、すなわち、導電膜と金属膜との間に局部電池が形成されることに起因する導電膜のエッチングレートの増大を抑制できる。この結果、上部金属配線１１、１２をより安定したエッチングレートで形成できるので、上部金属配線１１、１２の寸法精度を向上できる。 On the other hand, in the present embodiment, the contours of the barrier metal layers 16 and 17 are arranged inside the contours of the upper metal wirings 11 and 12, respectively, as viewed from above the substrate 1. Further, the barrier metal layers 16 and 17 are not provided on the side surfaces of the wirings 11A and 12A. Such a configuration is realized by separately performing patterning for forming the barrier metal layers 16 and 17 and patterning for forming the upper metal wirings 11 and 12. For example, after the barrier metal layers 16 and 17 are formed, a conductive film that covers the barrier metal layers 16 and 17 is formed. Next, only the conductive film is etched to obtain the upper metal wirings 11 and 12. A specific manufacturing process will be described in detail later. Accordingly, it is possible to suppress a problem that occurs when the conductive film and the metal film are etched at the same time, that is, an increase in the etching rate of the conductive film due to the formation of a local battery between the conductive film and the metal film. As a result, since the upper metal wirings 11 and 12 can be formed at a more stable etching rate, the dimensional accuracy of the upper metal wirings 11 and 12 can be improved.
　図２に示す例では、バリアメタル層１６の表面全体の各部は、ソース電極８、層間絶縁膜１０またはソース電極上部金属配線１１によって覆われている。同様に、バリアメタル層１７の表面全体の各部は、ゲート電極９、層間絶縁膜１０またはゲート電極上部金属配線１２によって覆われている。ここでいう「バリアメタルの表面全体」は、バリアメタルの上面、下面、側面を全て含む。また、層間絶縁膜１０は、コンタクトホール１３、１５が形成された絶縁膜を指し、例えば上部金属配線の形成後に堆積させるパッシベーション膜などは含まない。なお、本実施形態の構成は、上記構成に限定されない。導電膜のエッチング直後において、バリアメタル層１６、１７の表面が露出していなければ、本願発明の効果は得られる。例えばバリアメタル層１６、１７と層間絶縁膜１０との間に他の層が介在していてもよい。 In the example shown in FIG. 2, each part of the entire surface of the barrier metal layer 16 is covered with the source electrode 8, the interlayer insulating film 10, or the source electrode upper metal wiring 11. Similarly, each part of the entire surface of the barrier metal layer 17 is covered with the gate electrode 9, the interlayer insulating film 10, or the gate electrode upper metal wiring 12. Here, “the entire surface of the barrier metal” includes all of the upper surface, the lower surface and the side surface of the barrier metal. The interlayer insulating film 10 refers to an insulating film in which the contact holes 13 and 15 are formed, and does not include, for example, a passivation film deposited after the formation of the upper metal wiring. Note that the configuration of the present embodiment is not limited to the above configuration. If the surfaces of the barrier metal layers 16 and 17 are not exposed immediately after the etching of the conductive film, the effect of the present invention can be obtained. For example, another layer may be interposed between the barrier metal layers 16 and 17 and the interlayer insulating film 10.
　バリアメタル層１６、１７の形状は図示する形状に限定されない。バリアメタル層１６は、少なくともコンタクトホール１３内でソース電極８と接していればよく、コンタクトホール１３の内部にのみ配置されていてもよい。同様に、バリアメタル層１７は、少なくともコンタクトホール１５内でゲート電極９と接していればよく、コンタクトホール１５の内部にのみ配置されていてもよい。ただし、図２に示すように、バリアメタル層１６、１７がコンタクトホール１３、１５の側壁および層間絶縁膜１０の上面を覆うように配置されていると、上部金属配線１１、１２の金属（ここではＡｌ）が、コンタクトホール１３、１５の側壁や層間絶縁膜１０の上面からゲート絶縁膜６やソース電極８に拡散することをより効果的に防止できる。 The shape of the barrier metal layers 16 and 17 is not limited to the shape illustrated. The barrier metal layer 16 only needs to be in contact with the source electrode 8 at least in the contact hole 13, and may be disposed only inside the contact hole 13. Similarly, the barrier metal layer 17 only needs to be in contact with the gate electrode 9 at least in the contact hole 15, and may be disposed only inside the contact hole 15. However, as shown in FIG. 2, when the barrier metal layers 16 and 17 are arranged so as to cover the side walls of the contact holes 13 and 15 and the upper surface of the interlayer insulating film 10, the metal of the upper metal wirings 11 and 12 (here In this case, Al) can be more effectively prevented from diffusing into the gate insulating film 6 and the source electrode 8 from the side walls of the contact holes 13 and 15 and the upper surface of the interlayer insulating film 10.
　バリアメタル層１６の一部が層間絶縁膜１０の上面に形成される場合、配線１１Ａの側面１１Ａｓ（すなわちソース電極上部金属配線１１の側面）とバリアメタル層１６の側面との最短距離Ｙ１は、好ましくは１μｍ以上、より好ましくは２μｍ以上に設定される。これにより、バリアメタルを含む金属膜のパターニング、および、上部金属配線を形成するための導電膜のパターニングの際のマスク合わせのズレを考慮しても、バリアメタル層１６が配線１１Ａの側面で露出することをより確実に防止できる。同様に、配線１２Ａの側面１２Ａｓ（すなわちゲート電極上部金属配線１２の側面）とバリアメタル層１７の側面との最短距離Ｙ２も、好ましくは１μｍ以上、より好ましくは２μｍ以上に設定される。一方、上部金属配線１１、１２からの金属の拡散をより確実に抑制するためには、これらの距離Ｙ１、Ｙ２は、３μｍ以下であることが好ましい。 When a part of the barrier metal layer 16 is formed on the upper surface of the interlayer insulating film 10, the shortest distance Y1 between the side surface 11As of the wiring 11A (that is, the side surface of the source electrode upper metal wiring 11) and the side surface of the barrier metal layer 16 is Preferably it is set to 1 μm or more, more preferably 2 μm or more. As a result, the barrier metal layer 16 is exposed on the side surface of the wiring 11A even when patterning of the metal film including the barrier metal and mask misalignment in patterning of the conductive film for forming the upper metal wiring are taken into consideration. This can be prevented more reliably. Similarly, the shortest distance Y2 between the side surface 12As of the wiring 12A (that is, the side surface of the gate electrode upper metal wiring 12) and the side surface of the barrier metal layer 17 is preferably set to 1 μm or more, more preferably 2 μm or more. On the other hand, in order to more reliably suppress metal diffusion from the upper metal wirings 11 and 12, it is preferable that these distances Y1 and Y2 are 3 μm or less.
　バリアメタル層１６の端面とコンタクトホール１３の端部との最短距離Ｘ１、および、バリアメタル層１７の端面とコンタクトホール１５との最短距離Ｘ２は、それぞれ、コンタクトホール１３、１５を形成する際のマスクの合わせズレを考慮して、０．５μｍ以上であることが好ましい。一方、チップ面積の増大を抑えるためには、距離Ｘ１、Ｘ２は２．０μｍ以下であってもよい。なお、Ａｌの拡散をより確実に抑制するためには、距離Ｘ１は、２．０μｍよりも長くてもよく、例えばソース電極上部金属配線１１の周縁部に位置するユニットセル全体（ウェル領域３全体）を覆うように設定されていてもよい。 The shortest distance X1 between the end face of the barrier metal layer 16 and the end portion of the contact hole 13 and the shortest distance X2 between the end face of the barrier metal layer 17 and the contact hole 15 are as follows when forming the contact holes 13 and 15, respectively. In consideration of misalignment of the mask, it is preferably 0.5 μm or more. On the other hand, in order to suppress an increase in the chip area, the distances X1 and X2 may be 2.0 μm or less. In order to more reliably suppress Al diffusion, the distance X1 may be longer than 2.0 μm. For example, the entire unit cell (the entire well region 3) located at the peripheral edge of the source electrode upper metal wiring 11 ) May be set to cover.
　なお、上記距離Ｙ１、Ｙ２、Ｘ１、Ｘ２は何れも基板１の表面に平行な面内における距離を指すものとする。また、基板１の上方から見て、上記距離Ｙ１は、ソース電極上部金属配線１１の輪郭とバリアメタル層１６の輪郭との距離であり、距離Ｙ２は、ゲート電極上部金属配線１２の輪郭とバリアメタル層１７の輪郭との距離である。 The distances Y1, Y2, X1, and X2 are all distances in a plane parallel to the surface of the substrate 1. When viewed from above the substrate 1, the distance Y1 is the distance between the contour of the source electrode upper metal wiring 11 and the contour of the barrier metal layer 16, and the distance Y2 is the contour of the gate electrode upper metal wiring 12 and the barrier. It is the distance from the contour of the metal layer 17.
　バリアメタル層１６、１７は、コンタクトホール１３、１５の内部への堆積を容易に実現し、かつ、このバリアメタル層１６、１７上に形成される上部金属配線（Ａｌ配線）との密着性を高めるために、Ｔｉ及びＴｉＮの積層膜から形成されることが望ましい。また、密着性を確保しながらＡｌに対するバリア性を確保するために、バリアメタル層１６、１７の厚さは例えば５０ｎｍ以上１００ｎｍ以下であることが望ましい。さらに、ＳｉＣパワーデバイスにおいては、Ｓｉパワーデバイスよりもチップ面積を大幅に小さくできるが、電流密度は相対的に高くなる。このため、ソース電極上部金属配線１１及びゲート電極上部金属配線１２の厚さは、これらの配線に流れる電流密度が高くならないように、例えば２μｍ以上であることが好ましい。より好ましくは３μｍ以上である。 The barrier metal layers 16 and 17 can be easily deposited inside the contact holes 13 and 15 and have an adhesiveness to the upper metal wiring (Al wiring) formed on the barrier metal layers 16 and 17. In order to increase the thickness, it is desirable to form a laminated film of Ti and TiN. Further, in order to ensure the barrier property against Al while ensuring the adhesion, it is desirable that the thickness of the barrier metal layers 16 and 17 is, for example, not less than 50 nm and not more than 100 nm. Further, in the SiC power device, the chip area can be significantly reduced as compared with the Si power device, but the current density is relatively high. For this reason, it is preferable that the thicknesses of the source electrode upper metal wiring 11 and the gate electrode upper metal wiring 12 are, for example, 2 μm or more so that the current density flowing through these wirings does not increase. More preferably, it is 3 μm or more.
　次に、ＭＩＳＦＥＴ１００の製造方法の一例を説明する。図３～図６は、それぞれ、本実施形態のＭＩＳＦＥＴの製造工程を説明するための工程断面図であり、図１の平面図に示すＩＩ－ＩＩ’線に沿った断面に相当する。 Next, an example of a method for manufacturing the MISFET 100 will be described. 3 to 6 are process cross-sectional views for explaining the manufacturing process of the MISFET of this embodiment, and correspond to a cross section taken along line II-II 'shown in the plan view of FIG.
　まず、図３（ａ）に示すように、基板１の主面上に炭化珪素をエピタキシャル成長させることにより、炭化珪素層２０を形成する。基板１として、炭化珪素基板を用いる。ここでは、（０００１）Ｓｉ面より＜１１－２０＞方向に向かって８度のオフ角を有する４Ｈ－ＳｉＣ基板を用いる。基板１の導電型はｎ型であり、その不純物濃度は例えば１×１０18ｃｍ-3以上５×１０19ｃｍ-3以下である。炭化珪素層２０は、例えば原料ガスとしてシラン（ＳｉＨ4）およびプロパン（Ｃ3Ｈ8）、キャリアガスとして水素（Ｈ2）、ドーパントガスとして窒素（Ｎ2）ガスを用いて、熱ＣＶＤ法で形成することができる。ここでは、炭化珪素基板１よりも不純物濃度の低いｎ型の炭化珪素層２０をエピタキシャル成長によって形成する。炭化珪素層２０の不純物濃度や厚さは、ＭＩＳＦＥＴに要求される仕様によって異なるが、例えば耐圧が６００ＶのＭＩＳＦＥＴを製造しようとすると、炭化珪素層２０の不純物濃度が１×１０15ｃｍ-3以上５×１０16ｃｍ-3以下、厚さが５μｍ以上であることが望ましい。 First, as shown in FIG. 3A, silicon carbide layer 20 is formed by epitaxially growing silicon carbide on the main surface of substrate 1. A silicon carbide substrate is used as the substrate 1. Here, a 4H—SiC substrate having an off angle of 8 degrees from the (0001) Si plane toward the <11-20> direction is used. The conductivity type of the substrate 1 is n-type, and its impurity concentration is, for example, 1 × 10 18 cm −3 or more and 5 × 10 19 cm −3 or less. The silicon carbide layer 20 is formed by thermal CVD using, for example, silane (SiH 4 ) and propane (C 3 H 8 ) as source gases, hydrogen (H 2 ) as a carrier gas, and nitrogen (N 2 ) gas as a dopant gas. Can be formed. Here, n-type silicon carbide layer 20 having an impurity concentration lower than that of silicon carbide substrate 1 is formed by epitaxial growth. The impurity concentration and thickness of the silicon carbide layer 20 vary depending on specifications required for the MISFET. For example, when an MISFET having a withstand voltage of 600 V is to be manufactured, the impurity concentration of the silicon carbide layer 20 is 1 × 10 15 cm −3 or more. It is desirable that it is 5 × 10 16 cm −3 or less and the thickness is 5 μm or more.
　次に、図３（ｂ）に示すように、炭化珪素層２０に不純物イオンを注入することにより、ｐ型のウェル領域３、ｐ型のコンタクト領域４、およびｎ型のソース領域５を形成する。図示していないが、これらの領域３、４、５は、例えば次のようにして形成される。まず、炭化珪素層２０の上にＣＶＤ法で酸化シリコン膜を堆積した後、フォトリソグラフィーおよびドライエッチングによって、酸化シリコン膜のパターニングを行い、ウェル領域形成用の注入マスクを得る。この後、注入マスクの上方から、炭化珪素層２０にｐ型の不純物イオン（例えばアルミニウムイオン、ホウ素イオンなど）を注入することにより、炭化珪素層２０の表面領域にｐ型のウェル領域３となる注入層を形成する。イオン注入の際の基板温度は、注入による欠陥を低減するために、例えば５００℃以上に設定されることが好ましい。注入後、フッ酸を用いて注入マスクを除去する。続いて、同様の方法で、コンタクト領域形成用の注入マスクを形成した後、炭化珪素層２０にｐ型の不純物イオンを注入することにより、ｐ型のコンタクト領域４となる注入層を形成する。さらに、ソース領域形成用の注入マスクを形成した後、炭化珪素層２０にｎ型の不純物イオン（例えば窒素イオン、リンイオンなど）を注入することにより、ソース領域５となる注入層を形成する。次いで、これらの注入層に対して、アルゴンなどの不活性雰囲気中で１７００℃程度の温度で３０分間の活性化アニールを行うことにより、それぞれ、ウェル領域３、コンタクト領域４およびソース領域５を得る。 Next, as shown in FIG. 3B, impurity ions are implanted into the silicon carbide layer 20 to form the p-type well region 3, the p-type contact region 4, and the n-type source region 5. . Although not shown, these regions 3, 4, and 5 are formed as follows, for example. First, after a silicon oxide film is deposited on the silicon carbide layer 20 by a CVD method, the silicon oxide film is patterned by photolithography and dry etching to obtain an implantation mask for forming a well region. Thereafter, p-type impurity ions (for example, aluminum ions, boron ions, etc.) are implanted into silicon carbide layer 20 from above the implantation mask to form p-type well region 3 in the surface region of silicon carbide layer 20. An injection layer is formed. The substrate temperature at the time of ion implantation is preferably set to, for example, 500 ° C. or higher in order to reduce defects due to implantation. After the implantation, the implantation mask is removed using hydrofluoric acid. Subsequently, after an implantation mask for forming a contact region is formed by a similar method, an implantation layer that becomes the p-type contact region 4 is formed by implanting p-type impurity ions into the silicon carbide layer 20. Further, after forming an implantation mask for forming the source region, an implantation layer to be the source region 5 is formed by implanting n-type impurity ions (for example, nitrogen ions, phosphorus ions, etc.) into the silicon carbide layer 20. Next, an activation annealing for 30 minutes is performed on these implantation layers at a temperature of about 1700 ° C. in an inert atmosphere such as argon, thereby obtaining a well region 3, a contact region 4 and a source region 5, respectively. .
　上記方法で得られたウェル領域３の不純物濃度は、例えば１×１０15ｃｍ-3以上１×１０17ｃｍ-3以下であり、ウェル領域３の深さは、ピンチオフを防止するために例えば０．５μｍ前後とする。コンタクト領域４の不純物濃度は、ウェル領域３の不純物濃度よりも高く、例えば１×１０18ｃｍ-3以上である。コンタクト領域４の不純物濃度がウェル領域３の不純物濃度よりも高いと、コンタクト領域４と、後に形成するソース電極との間にオーミック接合を形成しやすくなる。また、コンタクト領域４の深さ（炭化珪素層２０の表面からの深さ）は例えば３００ｎｍ程度とする。ソース領域５の不純物濃度は、少なくとも１×１０19ｃｍ-3以上、好ましくは６×１０19ｃｍ-3以上、より好ましくは１×１０20ｃｍ-3である。ソース領域５の深さは例えば３００ｎｍ程度である。 The impurity concentration of the well region 3 obtained by the above method is, for example, 1 × 10 15 cm −3 or more and 1 × 10 17 cm −3 or less, and the depth of the well region 3 is, for example, 0 to prevent pinch-off. .About 5 μm. The impurity concentration of the contact region 4 is higher than the impurity concentration of the well region 3 and is, for example, 1 × 10 18 cm −3 or more. If the impurity concentration of the contact region 4 is higher than the impurity concentration of the well region 3, it is easy to form an ohmic junction between the contact region 4 and a source electrode to be formed later. Further, the depth of the contact region 4 (depth from the surface of the silicon carbide layer 20) is, for example, about 300 nm. The impurity concentration of the source region 5 is at least 1 × 10 19 cm −3 or more, preferably 6 × 10 19 cm −3 or more, more preferably 1 × 10 20 cm −3 . The depth of the source region 5 is about 300 nm, for example.
　次いで、図４（ａ）に示すように、炭化珪素層２０の表面（主面）にゲート絶縁膜６、ソース電極８、ゲート電極９を、裏面にドレイン電極７を形成する。続いて、ゲート絶縁膜６、ゲート電極９、ソース電極８および主面側に露出している炭化珪素層２０を覆うように層間絶縁膜１０を形成する。 Next, as shown in FIG. 4A, the gate insulating film 6, the source electrode 8, and the gate electrode 9 are formed on the surface (main surface) of the silicon carbide layer 20, and the drain electrode 7 is formed on the back surface. Subsequently, interlayer insulating film 10 is formed so as to cover gate insulating film 6, gate electrode 9, source electrode 8, and silicon carbide layer 20 exposed on the main surface side.
　ゲート絶縁膜６は、例えば炭化珪素層２０の表面を熱酸化することによって形成できる。具体的には、ウェハ状の炭化珪素基板１を石英管内に保持し、石英管内を１１００℃の温度に保った状態で、バブリングした酸素を流量２．５ＳＬＭ（ｌ／ｓ）で導入して、炭化珪素層２０の表面を熱酸化させる。熱酸化を行う時間は、例えば３時間とする。これにより、炭化珪素層２０の表面に、ゲート絶縁膜６として、厚さが約４０ｎｍのシリコン酸化膜（熱酸化膜）が得られる。 The gate insulating film 6 can be formed, for example, by thermally oxidizing the surface of the silicon carbide layer 20. Specifically, the wafer-like silicon carbide substrate 1 is held in a quartz tube, and bubbled oxygen is introduced at a flow rate of 2.5 SLM (l / s) while the quartz tube is kept at a temperature of 1100 ° C. The surface of silicon carbide layer 20 is thermally oxidized. The time for performing the thermal oxidation is, for example, 3 hours. Thereby, a silicon oxide film (thermal oxide film) having a thickness of about 40 nm is obtained as the gate insulating film 6 on the surface of the silicon carbide layer 20.
　この後、ゲート絶縁膜６上にゲート電極９を形成する。ゲート電極９は、耐熱性および導電性に優れた多結晶シリコンを用いて形成されることが好ましい。多結晶シリコンの融点は１４２０℃であり、後の工程で行われるソース電極を形成する際の熱処理の温度（例えば１０００℃）よりも十分に高いからである。 Thereafter, a gate electrode 9 is formed on the gate insulating film 6. The gate electrode 9 is preferably formed using polycrystalline silicon having excellent heat resistance and conductivity. This is because the melting point of polycrystalline silicon is 1420 ° C., which is sufficiently higher than the temperature of heat treatment (for example, 1000 ° C.) at the time of forming a source electrode performed in a later step.
　ゲート電極９の形成方法の一例を詳しく説明する。まず、ゲート絶縁膜６の上に、減圧ＣＶＤ法を用いて多結晶シリコン膜（図示せず）を堆積させる。具体的には、原料ガスとしてシラン、ホスフィンを用い、圧力を９５Ｐａ、成長温度を５５０℃に８時間保つことによって、ｎ型の不純物濃度が７×１０20ｃｍ-3、厚さが５００ｎｍの多結晶シリコン膜を得る。この多結晶シリコン膜に対して、フォトリソグラフィーおよびドライエッチングによりパターニングを行い、ゲート電極９を得る。ゲート電極９は、ウェル領域３の表面のうちチャネルが形成される部分、すなわち、ソース領域５とドリフト領域２（炭化珪素層２０のうちウェル領域３が形成されていない部分から構成される領域）の間に位置する部分３４を少なくとも覆っていればよく、そのパターンは特に限定されない。 An example of a method for forming the gate electrode 9 will be described in detail. First, a polycrystalline silicon film (not shown) is deposited on the gate insulating film 6 by using a low pressure CVD method. Specifically, by using silane and phosphine as source gases, maintaining the pressure at 95 Pa and the growth temperature at 550 ° C. for 8 hours, the n-type impurity concentration is 7 × 10 20 cm −3 and the thickness is 500 nm. A crystalline silicon film is obtained. The polycrystalline silicon film is patterned by photolithography and dry etching to obtain the gate electrode 9. Gate electrode 9 is a portion of the surface of well region 3 where a channel is formed, that is, source region 5 and drift region 2 (a region composed of a portion of silicon carbide layer 20 where well region 3 is not formed). It suffices to cover at least the portion 34 located between them, and the pattern is not particularly limited.
　また、ソース電極８は、例えばｐ型のコンタクト領域４、およびｎ型のソース領域５の全面もしくは一部の上にニッケルを堆積することによって形成される。 The source electrode 8 is formed, for example, by depositing nickel on the entire surface or a part of the p-type contact region 4 and the n-type source region 5.
　ソース電極８の形成方法の一例を詳しく説明する。ｐ型のコンタクト領域４、およびｎ型のソース領域５を含む全面にニッケル（図示せず）をスパッタ法を用いて１００ｎｍ堆積させる。このニッケル上にフォトリソグラフィー及びエッチングによるパターニングを行い、ｐ型のコンタクト領域４、およびｎ型のソース領域５の全面もしくは一部の上のみにニッケルを残すことにより、ソース電極８が形成される。 An example of a method for forming the source electrode 8 will be described in detail. Nickel (not shown) is deposited to a thickness of 100 nm on the entire surface including the p-type contact region 4 and the n-type source region 5 by sputtering. The source electrode 8 is formed by performing patterning by photolithography and etching on the nickel and leaving nickel only on the entire surface or part of the p-type contact region 4 and the n-type source region 5.
　ソース電極８は、ｐ型のコンタクト領域４、およびｎ型のソース領域５の各々の領域の一部分を覆う必要があるが、パターンは特に限定されず、ｐ型のコンタクト領域４、およびｎ型のソース領域５の全面を覆っていても問題はない。 The source electrode 8 needs to cover a part of each of the p-type contact region 4 and the n-type source region 5, but the pattern is not particularly limited, and the p-type contact region 4 and the n-type contact region 4 There is no problem even if the entire surface of the source region 5 is covered.
　本実施形態では、層間絶縁膜１０として、高い絶縁破壊電圧を有し、かつ、容易に形成できる酸化シリコン膜を形成する。酸化シリコン膜は、例えば常圧ＣＶＤ法を用いて形成でき、その厚さは例えば１μｍである。 In this embodiment, a silicon oxide film having a high dielectric breakdown voltage and capable of being easily formed is formed as the interlayer insulating film 10. The silicon oxide film can be formed using, for example, an atmospheric pressure CVD method, and the thickness thereof is, for example, 1 μm.
　ドレイン電極７は、例えば炭化珪素基板１の裏面側にチタンを堆積後、熱処理を行ってチタンシリサイド化させることによって形成される。 The drain electrode 7 is formed, for example, by depositing titanium on the back side of the silicon carbide substrate 1 and then performing heat treatment to form titanium silicide.
　具体的には、炭化珪素基板１の裏面に２００ｎｍのチタンをスパッタ法や蒸着法を用いて堆積後、窒素雰囲気下で９００℃１分の熱処理を行うことにより、炭化珪素基板中のシリコンとチタンを反応させ、チタンシリサイド層を形成する。 Specifically, after depositing 200 nm of titanium on the back surface of the silicon carbide substrate 1 by sputtering or vapor deposition, heat treatment is performed at 900 ° C. for 1 minute in a nitrogen atmosphere, so that silicon and titanium in the silicon carbide substrate are obtained. To form a titanium silicide layer.
　続いて、図４（ｂ）に示すように、層間絶縁膜１０に、ソース電極８に到達するコンタクトホール１３と、ゲート電極９に到達するコンタクトホール１５とを形成する。これらのコンタクトホール１３、１５は、公知のフォトリソグラフィーおよびドライエッチングを用いて形成できる。ドライエッチングとして、例えばＣＨＦ3やＣＦ4を用いた反応性イオンエッチング（Ｒｅａｃｔｉｖｅ　Ｉｏｎ　Ｅｔｃｈｉｎｇ；　ＲＩＥ）を行ってもよい。 Subsequently, as shown in FIG. 4B, a contact hole 13 reaching the source electrode 8 and a contact hole 15 reaching the gate electrode 9 are formed in the interlayer insulating film 10. These contact holes 13 and 15 can be formed using known photolithography and dry etching. As dry etching, for example, reactive ion etching (RIE) using CHF 3 or CF 4 may be performed.
　次に、図５（ａ）に示すように、層間絶縁膜１０、コンタクトホール１３、１５上の全面に、バリアメタルを含む金属膜２２を形成する。ここでは、金属膜２２として、チタン（Ｔｉ）及び窒化チタン（ＴｉＮ）を含む積層膜を形成する。具体的には、チタン（Ｔｉ）及び窒化チタン（ＴｉＮ）をこの順で反応性スパッタ法によって堆積させ、合計厚さが５０ｎｍ程度の金属膜２２を得る。 Next, as shown in FIG. 5A, a metal film 22 including a barrier metal is formed on the entire surface of the interlayer insulating film 10 and the contact holes 13 and 15. Here, a stacked film containing titanium (Ti) and titanium nitride (TiN) is formed as the metal film 22. Specifically, titanium (Ti) and titanium nitride (TiN) are deposited in this order by a reactive sputtering method to obtain a metal film 22 having a total thickness of about 50 nm.
　次に、図５（ｂ）に示すように、金属膜２２の上にフォトレジストを塗布し、この一部を露光してパターニングする。これにより、コンタクトホール１３およびその周辺部を覆うレジスト層２４と、コンタクトホール１５およびその周辺部を覆うレジスト層２５とを得る。 Next, as shown in FIG. 5B, a photoresist is applied on the metal film 22, and a part of the photoresist is exposed and patterned. As a result, a resist layer 24 covering the contact hole 13 and its peripheral portion and a resist layer 25 covering the contact hole 15 and its peripheral portion are obtained.
　レジスト層２４、２５をマスクとして、金属膜２２をドライエッチングもしくはウェットエッチングによって加工する。ウェットエッチングを行う場合、燐酸と過酸化水素水の混合溶液を用い、エッチング時間を１０分程度とする。金属膜２２のエッチングを行った後、レジスト層２４、２５を除去する。 Using the resist layers 24 and 25 as masks, the metal film 22 is processed by dry etching or wet etching. When wet etching is performed, a mixed solution of phosphoric acid and hydrogen peroxide water is used, and the etching time is set to about 10 minutes. After the metal film 22 is etched, the resist layers 24 and 25 are removed.
　これにより、図６（ａ）に示すように、金属膜２２から、互いに分離されたバリアメタル層１６およびバリアメタル層１７が得られる。バリアメタル層１６は、コンタクトホール１３内でソース電極８と接し、バリアメタル層１７は、コンタクトホール１５内でゲート電極９と接する。ここでは、バリアメタル層１６は、コンタクトホール１３の側壁、および、層間絶縁膜１０の上面のうち少なくともコンタクトホール１３の上端部近傍に位置する部分を覆うように形成される。また、バリアメタル層１７は、コンタクトホール１５の側壁、および、層間絶縁膜１０の上面のうち少なくともコンタクトホール１５の上端部近傍に位置する部分を覆うように形成される。層間絶縁膜１０のうちバリアメタル層１６、１７によって覆われていない部分は表出する。図示する例では、このとき、バリアメタル層１６、１７の上面１６ｕ、１７ｕおよび側面（エッチング面）１６ｓ、１７ｓは露出している。 Thereby, as shown in FIG. 6A, the barrier metal layer 16 and the barrier metal layer 17 separated from each other are obtained from the metal film 22. The barrier metal layer 16 is in contact with the source electrode 8 in the contact hole 13, and the barrier metal layer 17 is in contact with the gate electrode 9 in the contact hole 15. Here, the barrier metal layer 16 is formed so as to cover at least a portion of the side wall of the contact hole 13 and the upper surface of the interlayer insulating film 10 located near the upper end of the contact hole 13. The barrier metal layer 17 is formed so as to cover at least a portion of the side wall of the contact hole 15 and the upper surface of the interlayer insulating film 10 located near the upper end of the contact hole 15. Portions of the interlayer insulating film 10 that are not covered with the barrier metal layers 16 and 17 are exposed. In the illustrated example, the upper surfaces 16u and 17u and the side surfaces (etched surfaces) 16s and 17s of the barrier metal layers 16 and 17 are exposed at this time.
　次に、図６（ｂ）に示すように、バリアメタル層１６、１７および層間絶縁膜１０の上に、蒸着もしくはスパッタ法により、アルミニウム（Ａｌ）膜を堆積させる。Ａｌ膜の厚さは例えば３μｍ程度とする。この後、Ａｌ膜を、公知のフォトリソグラフィーおよびウェットエッチングを用いてパターニングして、ソース電極上部金属配線１１とゲート電極上部金属配線１２とを形成する。Ａｌ膜のウェットエッチングには燐酸、硝酸、酢酸の混合溶液を用いる。このようにして、ソース電極上部金属配線１１とバリアメタル層１６とを含む配線１１Ａ、および、ゲート電極上部金属配線１２とバリアメタル層１７とを含む配線１２Ａを得る。 Next, as shown in FIG. 6B, an aluminum (Al) film is deposited on the barrier metal layers 16 and 17 and the interlayer insulating film 10 by vapor deposition or sputtering. The thickness of the Al film is, for example, about 3 μm. Thereafter, the Al film is patterned using known photolithography and wet etching to form the source electrode upper metal wiring 11 and the gate electrode upper metal wiring 12. For the wet etching of the Al film, a mixed solution of phosphoric acid, nitric acid and acetic acid is used. In this way, a wiring 11A including the source electrode upper metal wiring 11 and the barrier metal layer 16 and a wiring 12A including the gate electrode upper metal wiring 12 and the barrier metal layer 17 are obtained.
　Ａｌ膜のウェットエッチングでは、Ａｌ膜のうち、その下にバリアメタル層１６、１７が配置されていない部分をエッチングによって除去する。従って、ウェットエッチングの際にバリアメタル層１６、１７は露出しない。 In the wet etching of the Al film, a portion of the Al film where the barrier metal layers 16 and 17 are not disposed is removed by etching. Therefore, the barrier metal layers 16 and 17 are not exposed during wet etching.
　図示する例では、ウェットエッチングによって得られるソース電極上部金属配線１１は、バリアメタル層１６の上面１６ｕおよび側面１６ｓの全体を覆うように形成される。ゲート電極上部金属配線１２は、バリアメタル層１７の上面１７ｕおよび側面１７ｓの全体を覆うように形成される。従って、配線１１Ａ、１２Ａの側面１１Ａｓ、１２Ａｓにおいて、バリアメタル層１６、１７は露出しない。この後、必要に応じて、配線１１Ａ、１２Ａを覆うようにパッシベーション膜が設けられてもよい。このようにして、ＭＩＳＦＥＴ１００が製造される。 In the illustrated example, the source electrode upper metal wiring 11 obtained by wet etching is formed so as to cover the entire upper surface 16 u and side surface 16 s of the barrier metal layer 16. The gate electrode upper metal wiring 12 is formed so as to cover the entire upper surface 17 u and side surface 17 s of the barrier metal layer 17. Therefore, the barrier metal layers 16 and 17 are not exposed on the side surfaces 11As and 12As of the wirings 11A and 12A. Thereafter, if necessary, a passivation film may be provided so as to cover the wirings 11A and 12A. In this way, the MISFET 100 is manufactured.
　上記方法で得られたＭＩＳＦＥＴ１００では、バリアメタル層１６は、コンタクトホール１３内のソース電極８とソース電極上部金属配線１１との間、コンタクトホール１３の側壁（層間絶縁膜１０の側壁）とソース電極上部金属配線１１との間、および、層間絶縁膜１０の上面のうちコンタクトホール１３の上端部近傍に位置する部分とソース電極上部金属配線１１との間にのみ形成されている。また、バリアメタル層１７は、コンタクトホール１５内のゲート電極９とゲート電極上部金属配線１２との間、コンタクトホール１５の側壁（層間絶縁膜１０の側壁）とゲート電極上部金属配線１２との間、および、層間絶縁膜１０の上面のうちコンタクトホール１５の上端部近傍に位置する部分とゲート電極上部金属配線１２との間にのみ形成されている。なお、上述したように、バリアメタル層１６、１７の位置はこの例に限定されない。バリアメタル層１６は、少なくともソース電極８とソース電極上部金属配線１１との間に設けられ、かつ、配線１１Ａの側面に配置されていなければよい。同様に、バリアメタル層１７は、少なくともゲート電極９とゲート電極上部金属配線１２との間に設けられ、かつ、配線１２Ａの側面に配置されていなければよい。 In the MISFET 100 obtained by the above method, the barrier metal layer 16 includes the source electrode 8 in the contact hole 13 and the source electrode upper metal wiring 11, the side wall of the contact hole 13 (side wall of the interlayer insulating film 10), and the source electrode. It is formed only between the upper metal wiring 11 and between the source electrode upper metal wiring 11 and the portion of the upper surface of the interlayer insulating film 10 located near the upper end of the contact hole 13. The barrier metal layer 17 is formed between the gate electrode 9 in the contact hole 15 and the gate electrode upper metal wiring 12, and between the side wall of the contact hole 15 (side wall of the interlayer insulating film 10) and the gate electrode upper metal wiring 12. In addition, it is formed only between the portion of the upper surface of the interlayer insulating film 10 located near the upper end portion of the contact hole 15 and the gate electrode upper metal wiring 12. As described above, the positions of the barrier metal layers 16 and 17 are not limited to this example. The barrier metal layer 16 may be provided at least between the source electrode 8 and the source electrode upper metal wiring 11 and not disposed on the side surface of the wiring 11A. Similarly, the barrier metal layer 17 may be provided at least between the gate electrode 9 and the gate electrode upper metal wiring 12 and not disposed on the side surface of the wiring 12A.
　上記方法によると、バリアメタル層１６、１７を形成するためのＴｉ／ＴｉＮ膜のエッチングとは別に、上部金属配線１１、１２を形成するためのＡｌ膜のエッチング（ウェットエッチング）を行う。Ａｌ膜のエッチング工程において、エッチング面にＴｉが露出されないので、Ｔｉはエッチング液に接触しない。従って、ＡｌとＴｉとの標準電極電位の差による局部電池効果は発生せず、Ａｌエッチングレートの増大を抑制でき、かつ、局所的なエッチングレートのばらつきも抑制することができるので、寸法精度を確保するとともに、加工形状をより安定化できる。 According to the above method, etching (wet etching) of the Al film for forming the upper metal wirings 11 and 12 is performed separately from the etching of the Ti / TiN film for forming the barrier metal layers 16 and 17. In the etching process of the Al film, since Ti is not exposed on the etching surface, Ti does not contact the etching solution. Therefore, the local battery effect due to the difference in the standard electrode potential between Al and Ti does not occur, the increase in Al etching rate can be suppressed, and the variation in local etching rate can also be suppressed. In addition to ensuring, the processed shape can be further stabilized.
　本実施形態における上部配線金属１１、１２の形状は、図１に示す形状に限定されない。例えば、配線遅延を低減する目的で、ゲート電極上部金属配線１２が、複数のユニットセルが配列された領域の中央に配置されていてもよい。あるいは、以下に説明するように、ソース電極上部金属配線１１は、２つのソースパッドを有し、これらのパッドの隙間に、ゲートパッドから延伸されたゲート配線が配置されていてもよい。 The shape of the upper wiring metals 11 and 12 in the present embodiment is not limited to the shape shown in FIG. For example, for the purpose of reducing the wiring delay, the gate electrode upper metal wiring 12 may be arranged at the center of the region where the plurality of unit cells are arranged. Alternatively, as described below, the source electrode upper metal wiring 11 may have two source pads, and a gate wiring extended from the gate pad may be arranged in a gap between these pads.
　図７は、本実施形態の他のＭＩＳＦＥＴ２００を示す平面図である。簡単のため、図１および図２と同様の構成要素には同じ参照符号を付し、説明を省略する。 FIG. 7 is a plan view showing another MISFET 200 of the present embodiment. For simplicity, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted.
　ＭＩＳＦＥＴ２００では、ソース電極上部金属配線１１は、２つのソースパッドを有している。また、ゲート電極上部金属配線１２は、２つのゲートパッド１２ｐと、これらのゲートパッド１２ｐから延伸されたゲート配線１２ａとを有している。２つのゲートパッド１２ｐはゲート配線１２ａによって接続されている。また、ゲート配線１２ａは、基板１の上方から見て、２つのソースパッドの隙間にも配置されている。 In the MISFET 200, the source electrode upper metal wiring 11 has two source pads. The gate electrode upper metal wiring 12 includes two gate pads 12p and a gate wiring 12a extending from the gate pads 12p. The two gate pads 12p are connected by a gate wiring 12a. Further, the gate wiring 12 a is also disposed in the gap between the two source pads as viewed from above the substrate 1.
　ＭＩＳＦＥＴ２００では、ゲート電極上部金属配線１２とゲート電極との接続部を、ゲートパッド１２ｐのみでなく、ゲート配線１２ａにも設けることができる。従って、複数のユニットセル３０のうちゲートパッド１２ｐから離れた位置にあるユニットセルの配線遅延を大幅に低減できる。この結果、ＭＩＳＦＥＴ２００の動作速度をより高めることが可能になる。 In the MISFET 200, the connection portion between the gate electrode upper metal wiring 12 and the gate electrode can be provided not only on the gate pad 12p but also on the gate wiring 12a. Accordingly, it is possible to greatly reduce the wiring delay of the unit cells located at positions away from the gate pad 12p among the plurality of unit cells 30. As a result, the operation speed of the MISFET 200 can be further increased.
　このような構成のＭＩＳＦＥＴ２００においても、上部金属配線１１、１２の下に、それぞれ、バリアメタル層１６、１７を設ける。また、基板１の上方から見て、上部金属配線１１、１２の輪郭の内側に、それぞれ、バリアメタル層１６、１７の輪郭を配置する。従って、図７に示すＩＩａ－ＩＩａ’線、ＩＩｂ－ＩＩｂ’線およびＩＩｃ－ＩＩｃ’線に沿った断面は、何れも、図２（ｂ）に示す断面と同様となる。このような構成により、図１に示すＭＩＳＦＥＴ１００と同様に、局部電池効果を抑制することができるので、上部金属配線１１、１２の寸法精度を向上できる。 Also in the MISFET 200 having such a configuration, barrier metal layers 16 and 17 are provided under the upper metal wirings 11 and 12, respectively. Further, when viewed from above the substrate 1, the contours of the barrier metal layers 16 and 17 are arranged inside the contours of the upper metal wirings 11 and 12, respectively. Accordingly, the cross sections taken along lines IIa-IIa ′, IIb-IIb ′, and IIc-IIc ′ shown in FIG. 7 are all the same as the cross section shown in FIG. With such a configuration, as in the MISFET 100 shown in FIG. 1, the local battery effect can be suppressed, so that the dimensional accuracy of the upper metal wirings 11 and 12 can be improved.
　本実施形態のＭＩＳＦＥＴにおけるユニットセル３０の構成や各構成要素の材料も、図１～図６を参照しながら前述した構成や材料に限定されない。 The configuration of the unit cell 30 and the material of each component in the MISFET of the present embodiment are not limited to the configurations and materials described above with reference to FIGS.
　上述した実施形態では、バリアメタル層１６、１７として、Ｔｉ膜とＴｉＮ膜とを含む積層膜を用いているが、バリアメタル層１６、１７は、上部金属配線１１、１２に含まれる金属の拡散を抑制する機能を有する金属を含んでいればよく、上記の積層膜に限定されない。バリアメタル層１６、１７は、例えばＴｉ、ＴｉＮ、タングステン、窒化タングステン、タンタルまたは窒化タンタルを含む膜であってもよいし、これらのうち２以上の膜を含む積層膜であってもよい。また、上部金属配線１１、１２はＡｌ膜であることが好ましい。 In the embodiment described above, a laminated film including a Ti film and a TiN film is used as the barrier metal layers 16 and 17. However, the barrier metal layers 16 and 17 diffuse metal contained in the upper metal wirings 11 and 12. It is only necessary to include a metal having a function of suppressing the above, and the present invention is not limited to the above laminated film. The barrier metal layers 16 and 17 may be a film containing, for example, Ti, TiN, tungsten, tungsten nitride, tantalum, or tantalum nitride, or may be a laminated film including two or more of these films. The upper metal wirings 11 and 12 are preferably Al films.
　また、上記実施形態では、ソース電極８およびゲート電極９はシリサイド層を有していないが、これらの電極の両方もしくは一方がシリサイド層を有していても、上記と同様の効果を得ることができる。同様に、上記実施形態におけるドレイン電極７はシリサイド層を有するが、シリサイド層を有していなくてもよい。 In the above embodiment, the source electrode 8 and the gate electrode 9 do not have a silicide layer. However, even if both or one of these electrodes has a silicide layer, the same effect as described above can be obtained. it can. Similarly, although the drain electrode 7 in the above embodiment has a silicide layer, it may not have a silicide layer.
　シリサイド層を含むソース電極８は、例えば次のようにして形成される。まず、炭化珪素層２０と接するように金属膜（例えばＮｉ（ニッケル）膜）を形成する。次いで、アニール処理（例えば窒素雰囲気中、９５０℃の温度で１分間程度）を行うことにより、炭化珪素層２０とＮｉ膜とを反応させる。これにより、Ｎｉの一部が炭化珪素層２０へ拡散して合金化され、Ｎｉシリサイド層が形成される。 The source electrode 8 including the silicide layer is formed as follows, for example. First, a metal film (for example, Ni (nickel) film) is formed so as to be in contact with the silicon carbide layer 20. Next, annealing is performed (for example, in a nitrogen atmosphere at a temperature of 950 ° C. for about 1 minute) to react the silicon carbide layer 20 and the Ni film. Thereby, a part of Ni diffuses into the silicon carbide layer 20 and is alloyed to form a Ni silicide layer.
　ソース電極８およびドレイン電極７として、Ｎｉシリサイド層を形成すると、炭化珪素層２０と良好なオーミック接触を形成できるので好ましい。なお、上記金属膜として、Ｎｉの他にＴｉ膜、コバルト（Ｃｏ）膜を用いてもよい。Ｔｉ膜を用いる場合、Ｔｉシリサイド層が形成されるが、Ｔｉシリサイド層は、Ａｌの拡散をバリアする機能を有さず、本明細書でいう「バリアメタル層」とは異なる。また、本明細書でいう「バリアメタル層」は、電極（例えばシリサイド層を含む電極）と上部金属配線との間に配置される金属膜であり、電極とは別個に形成される。さらに、ソース電極としてＴｉシリサイド層を形成すると、そのＴｉシリサイド層は、ユニットセル毎に分離されている必要がある。これに対し、バリアメタル層は、ユニットセル毎に分離されていないことが好ましい。これにより、上部金属配線からの金属の拡散をより確実に抑制できる。 It is preferable to form a Ni silicide layer as the source electrode 8 and the drain electrode 7 because good ohmic contact with the silicon carbide layer 20 can be formed. In addition to the Ni, a Ti film or a cobalt (Co) film may be used as the metal film. When a Ti film is used, a Ti silicide layer is formed. However, the Ti silicide layer does not have a function of barriering Al diffusion and is different from the “barrier metal layer” in this specification. The “barrier metal layer” referred to in this specification is a metal film disposed between an electrode (for example, an electrode including a silicide layer) and an upper metal wiring, and is formed separately from the electrode. Further, when a Ti silicide layer is formed as a source electrode, the Ti silicide layer needs to be separated for each unit cell. On the other hand, it is preferable that the barrier metal layer is not separated for each unit cell. Thereby, the spreading | diffusion of the metal from upper metal wiring can be suppressed more reliably.
　ＭＩＳＦＥＴ１００は反転チャネル構造を有するが、蓄積チャネル構造を有していてもよい。また、ＭＩＳＦＥＴ１００では、ゲート絶縁膜６として酸化膜を用いているが、酸窒化膜や窒化膜を用いてもよい。あるいは、酸化膜、酸窒化膜および窒化膜のうちの２以上の膜を含む積層膜を用いてもよい。 MISFET 100 has an inverted channel structure, but may have a storage channel structure. In the MISFET 100, an oxide film is used as the gate insulating film 6, but an oxynitride film or a nitride film may be used. Alternatively, a stacked film including two or more of an oxide film, an oxynitride film, and a nitride film may be used.
　さらに、ＭＩＳＦＥＴ１００では、ウェル領域３とソース電極８との間の抵抗を低くするために、ウェル領域３よりもキャリア濃度の高いｐ+型コンタクト領域４を設けているが、ｐ+コンタクト領域４が形成されていなくてもよい。例えばウェル領域３のキャリア濃度が十分に高ければ、高濃度のｐ+コンタクト領域４を形成しなくてもよい。 Furthermore, the MISFET 100, in order to lower the resistance between the well region 3 and the source electrode 8, a high p + -type contact region 4 of the carrier concentration is provided than the well region 3, p + contact region 4 It may not be formed. For example, if the carrier concentration of the well region 3 is sufficiently high, the high concentration p + contact region 4 may not be formed.
　上述した実施形態においては、炭化珪素基板１、炭化珪素層２０、ソース領域５の導電型をｎ型とし、ウェル領域３とコンタクト領域４の導電型をｐ型としたが、本発明はこれに限定されることない。これらの導電型を逆転させ、炭化珪素基板１、炭化珪素層２０、ソース領域５の導電型をｐ型とし、ウェル領域３とコンタクト領域４の導電型をｎ型としてもよい。 In the embodiment described above, the conductivity type of silicon carbide substrate 1, silicon carbide layer 20, and source region 5 is n-type, and the conductivity type of well region 3 and contact region 4 is p-type. It is not limited. The conductivity types of silicon carbide substrate 1, silicon carbide layer 20, and source region 5 may be p-type, and the conductivity types of well region 3 and contact region 4 may be n-type.
　また、基板１として４Ｈ－ＳｉＣ基板を用いているが、他の結晶面や他のポリタイプのＳｉＣ基板を用いてもよい。４Ｈ－ＳｉＣ基板を用いる場合、そのＳｉ面に炭化珪素層２０を形成し、Ｃ面にドレイン電極７を形成してもよいし、Ｃ面に炭化珪素層２０、Ｓｉ面にドレイン電極７を形成してもよい。 Further, although the 4H—SiC substrate is used as the substrate 1, other crystal planes or other polytype SiC substrates may be used. When a 4H—SiC substrate is used, the silicon carbide layer 20 may be formed on the Si surface, the drain electrode 7 may be formed on the C surface, the silicon carbide layer 20 may be formed on the C surface, and the drain electrode 7 may be formed on the Si surface. May be.
　本発明は、縦型ＭＩＳＦＥＴに限定されず、炭化珪素を用いた他の半導体装置にも適用され得る。より具体的には、炭化珪素層と、炭化珪素層上に設けられた複数の電極と、これらの電極にそれぞれ接続された上部金属配線とを有する種々の半導体装置に適用され得る。基板１として、炭化珪素基板以外の基板を有する半導体装置に適用してもよい。 The present invention is not limited to the vertical MISFET, but can be applied to other semiconductor devices using silicon carbide. More specifically, the present invention can be applied to various semiconductor devices having a silicon carbide layer, a plurality of electrodes provided on the silicon carbide layer, and upper metal wirings respectively connected to these electrodes. The substrate 1 may be applied to a semiconductor device having a substrate other than a silicon carbide substrate.
　本発明は、ゲート絶縁膜を有する半導体装置に適用すると特に有利である。これにより、上部金属配線の金属がゲート絶縁膜に拡散することによるリーク電流の増加を抑えることができるので、素子特性の低下をより効果的に抑制できる。 The present invention is particularly advantageous when applied to a semiconductor device having a gate insulating film. As a result, an increase in leakage current due to diffusion of the metal of the upper metal wiring into the gate insulating film can be suppressed, so that deterioration in element characteristics can be more effectively suppressed.
　本発明は横型ＭＩＳＦＥＴにも適用できる。横型ＭＩＳＦＥＴでは、ドレイン電極も炭化珪素層上に形成される。例えば図２（ａ）に示す縦型ＭＩＳＦＥＴにおいて、基板１の裏面にドレイン電極を設けず、隣接するユニットセルにそれぞれ設けられたソース電極８の一方をソース電極、他方をドレイン電極として用いればよい。横型ＭＩＳＦＥＴに本発明を適用する場合、ソース電極、ドレイン電極およびゲート電極にそれぞれ接続された配線のうち少なくとも２つが、バリアメタル層および上部金属配線を有し、かつ、基板上方から見て、バリアメタル層の輪郭が上部金属配線の輪郭の内側に配置された構造を有していれば、本願発明の効果が得られる。好ましくは、少なくともゲート電極に接続された配線が上記構造を有する。これにより、上部金属配線に含まれる金属（Ａｌなど）がゲート絶縁膜に拡散することを抑制できるので、半導体装置の信頼性をより効果的に高めることができる。より好ましくは、ソース電極、ドレイン電極およびゲート電極にそれぞれ接続された配線が何れも上記構造を有する。 The present invention can also be applied to a lateral MISFET. In the lateral MISFET, the drain electrode is also formed on the silicon carbide layer. For example, in the vertical MISFET shown in FIG. 2A, the drain electrode is not provided on the back surface of the substrate 1, and one of the source electrodes 8 provided in each adjacent unit cell may be used as the source electrode and the other as the drain electrode. . When the present invention is applied to a lateral MISFET, at least two of the wirings connected to the source electrode, the drain electrode, and the gate electrode each have a barrier metal layer and an upper metal wiring, and the barrier is viewed from above the substrate. If the contour of the metal layer has a structure arranged inside the contour of the upper metal wiring, the effect of the present invention can be obtained. Preferably, at least a wiring connected to the gate electrode has the above structure. As a result, the metal (such as Al) contained in the upper metal wiring can be prevented from diffusing into the gate insulating film, so that the reliability of the semiconductor device can be improved more effectively. More preferably, each of the wirings connected to the source electrode, the drain electrode, and the gate electrode has the above structure.
　また、上記実施形態では、炭化珪素層２０と同じ導電型のＳｉＣ基板１を用いてＭＩＳＦＥＴを製造しているが、炭化珪素層２０と異なる導電型のＳｉＣ基板を用いて絶縁ゲートバイポーラトランジスタ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ：ＩＧＢＴ）を製造することもできる。さらに、本発明はＭＥＳＦＥＴに適用することもできる。 In the above embodiment, the MISFET is manufactured using the SiC substrate 1 having the same conductivity type as that of the silicon carbide layer 20, but the insulated gate bipolar transistor (Insulated) using a SiC substrate having a conductivity type different from that of the silicon carbide layer 20. Gate Bipolar Transistor (IGBT) can also be manufactured. Furthermore, the present invention can also be applied to MESFETs.
　本発明によると、配線の厚さを確保しつつ、配線を形成する際のウェットエッチレートを安定化させ、レジスト上のマスクパターンに対する寸法精度を高めることができる。よって、炭化珪素を用いた半導体装置の歩留まりを高め、信頼性を向上できる。 According to the present invention, it is possible to stabilize the wet etch rate when forming the wiring while securing the thickness of the wiring and to increase the dimensional accuracy with respect to the mask pattern on the resist. Thus, the yield of semiconductor devices using silicon carbide can be increased and the reliability can be improved.
　本発明は、炭化珪素を用いた半導体装置、例えば縦型ＭＩＳＦＥＴ、横型ＭＩＳＦＥＴ、ＩＧＢＴなどに広く適用できる。 The present invention can be widely applied to semiconductor devices using silicon carbide, such as vertical MISFETs, horizontal MISFETs, IGBTs, and the like.
　１　　ｎ型ＳｉＣ基板
　２　　ドリフト領域
　３　　ウェル領域
　４　　ｐ+型コンタクト領域
　５　　ソース領域
　６　　ゲート絶縁膜
　８　　ソース電極
　９　　ゲート電極
　１０　　層間絶縁膜
　１１　　ソース電極上部金属配線
　１２　　ゲート電極上部金属配線
　１１Ａ、１２Ａ　　配線
　１１Ａｓ、１２Ａｓ　　配線の側面
　１３　　ソース部コンタクトホール
　１５　　ゲート部コンタクトホール
　１６、１７　　バリアメタル層
　２０　　炭化珪素層
　３０　　ユニットセル
　１００　ＭＩＳＦＥＴ 1 n-type SiC substrate 2 drift region 3 well region 4 p + type contact region 5 source region 6 gate insulating film 8 source electrode 9 gate electrode 10 interlayer insulating film 11 source electrode upper metal wiring 12 gate electrode upper metal wiring 11A, 12A wiring 11 As, 12 As Wiring side surface 13 Source portion contact hole 15 Gate portion contact hole 16, 17 Barrier metal layer 20 Silicon carbide layer 30 Unit cell 100 MISFET

Claims (20)

  1. 　基板と、
    　前記基板の表面に形成された炭化珪素層と、
    　前記炭化珪素層上に形成され、互いに電気的に絶縁された第１電極および第２電極と、
    　前記炭化珪素層と前記第１および第２電極の上に形成された絶縁膜であって、前記絶縁膜には、前記第１電極に達する第１コンタクトホールおよび前記第２電極に達する第２コンタクトホールが形成されている、絶縁膜と、
    　前記絶縁膜上に形成され、互いに電気的に絶縁された第１金属配線および第２金属配線と、
    　前記第１金属配線と前記第１電極との間に、前記第１金属配線と接して形成され、前記第１コンタクトホール内において、前記第１電極と接続されている第１バリアメタル層と、
    　前記第２金属配線と前記第２電極との間に、前記第２金属配線と接して形成され、前記第２コンタクトホール内において、前記第２電極と接続されている第２バリアメタル層と
    を備え、
    　前記基板の上方から見て、前記第１金属配線の輪郭の内側に前記第１バリアメタルの輪郭が配置され、前記第２金属配線の輪郭の内側に前記第２バリアメタルの輪郭が配置されている半導体装置。     A substrate,
    A silicon carbide layer formed on the surface of the substrate;
    A first electrode and a second electrode formed on the silicon carbide layer and electrically insulated from each other;
    An insulating film formed on the silicon carbide layer and the first and second electrodes, the first contact hole reaching the first electrode and the second contact reaching the second electrode An insulating film in which holes are formed; and
    A first metal wiring and a second metal wiring formed on the insulating film and electrically insulated from each other;
    A first barrier metal layer formed between and in contact with the first metal wiring between the first metal wiring and the first electrode and connected to the first electrode in the first contact hole;
    A second barrier metal layer formed between the second metal wiring and the second electrode in contact with the second metal wiring and connected to the second electrode in the second contact hole; Prepared,
    When viewed from above the substrate, the outline of the first barrier metal is arranged inside the outline of the first metal wiring, and the outline of the second barrier metal is arranged inside the outline of the second metal wiring. A semiconductor device.
  2. 　前記第１バリアメタル層の表面全体の各部は、前記第１電極、前記第１金属配線または前記絶縁膜で覆われており、前記第２バリアメタル層の表面全体の各部は、前記第２金属、前記第２金属配線または前記絶縁膜で覆われている請求項１に記載の半導体装置。 Each part of the whole surface of the first barrier metal layer is covered with the first electrode, the first metal wiring or the insulating film, and each part of the whole surface of the second barrier metal layer is covered with the second metal. The semiconductor device according to claim 1, wherein the semiconductor device is covered with the second metal wiring or the insulating film.
  3. 　前記第１バリアメタル層は、前記第１コンタクトホール内および前記絶縁膜上に形成され、前記第１バリアメタル層の上面および側壁は前記第１金属配線によって覆われており、
    　前記第２バリアメタル層は、前記第２コンタクトホール内および前記絶縁膜上に形成され、前記第２バリアメタル層の上面および側壁は前記第２金属配線によって覆われている請求項２に記載の半導体装置。     The first barrier metal layer is formed in the first contact hole and on the insulating film, and an upper surface and a side wall of the first barrier metal layer are covered with the first metal wiring,
    The said 2nd barrier metal layer is formed in the said 2nd contact hole and on the said insulating film, The upper surface and side wall of the said 2nd barrier metal layer are covered with the said 2nd metal wiring. Semiconductor device.
  4. 　前記第１および第２金属配線は、同一の導電膜をパターニングすることによって形成されている請求項１から３のいずれかに記載の半導体装置。 4. The semiconductor device according to claim 1, wherein the first and second metal wirings are formed by patterning the same conductive film.
  5. 　前記第１および第２金属配線は、前記第１および第２金属配線の間に位置する分離領域によって互いに分離されており、前記第１バリアメタル層および前記第２バリアメタル層は、何れも、前記分離領域において露出していない請求項４に記載の半導体装置。 The first and second metal wirings are separated from each other by an isolation region located between the first and second metal wirings, and the first barrier metal layer and the second barrier metal layer are both The semiconductor device according to claim 4, wherein the semiconductor device is not exposed in the isolation region.
  6. 　前記第１および第２バリアメタル層は、同一の金属膜をパターニングすることによって形成されている請求項１から５のいずれかに記載の半導体装置。 6. The semiconductor device according to claim 1, wherein the first and second barrier metal layers are formed by patterning the same metal film.
  7. 　前記第１および第２金属配線の厚さは２μｍ以上である請求項１から５のいずれかに記載の半導体装置。 The semiconductor device according to claim 1, wherein the first and second metal wirings have a thickness of 2 μm or more.
  8. 　前記基板の上方から見て、前記第１金属配線の前記輪郭と、前記第１バリアメタルの前記輪郭との最短距離Ｙ１は１μｍ以上であり、前記第２金属配線の前記輪郭と前記第２バリアメタルの前記輪郭との最短距離Ｙ２は１μｍ以上である請求項１から７のいずれかに記載の半導体装置。 When viewed from above the substrate, the shortest distance Y1 between the contour of the first metal wiring and the contour of the first barrier metal is 1 μm or more, and the contour of the second metal wiring and the second barrier The semiconductor device according to any one of claims 1 to 7, wherein a shortest distance Y2 from the contour of the metal is 1 µm or more.
  9. 　前記第１および第２金属配線はアルミニウム層である請求項１から８のいずれかに記載の半導体装置。 9. The semiconductor device according to claim 1, wherein the first and second metal wirings are aluminum layers.
  10. 　前記第１および第２バリアメタル層は、チタンを含む請求項１から９のいずれかに記載の半導体装置。 10. The semiconductor device according to claim 1, wherein the first and second barrier metal layers contain titanium.
  11. 　前記第１および第２バリアメタル層は、チタン膜および窒化チタン膜を含む積層膜である請求項１０に記載の半導体装置。 The semiconductor device according to claim 10, wherein the first and second barrier metal layers are laminated films including a titanium film and a titanium nitride film.
  12. 　前記第１電極はソース電極であり、前記第２電極はゲート電極である請求項１から１１のいずれかに記載の半導体装置。 The semiconductor device according to claim 1, wherein the first electrode is a source electrode and the second electrode is a gate electrode.
  13. 　前記基板は第１導電型の炭化珪素基板であり、
    　前記炭化珪素層に形成された第２導電型のウェル領域と、
    　前記ウェル領域内に形成され、かつ、前記ウェル領域よりも高い濃度で第２導電型の不純物を含むコンタクト領域と、
    　前記ウェル領域内に、前記コンタクト領域を包囲するように形成された第１導電型のソース領域と、
    　前記炭化珪素層のうち前記ウェル領域、前記コンタクト領域、前記ソース領域の何れも形成されなかった部分に形成された第１導電型のドリフト領域と、
    　前記炭化珪素層上に形成されたゲート絶縁膜と、
    　前記基板の裏面に形成されたドレイン電極と
    をさらに備え、
    　前記ソース電極は、前記炭化珪素層上に、前記コンタクト領域および前記ソース領域と接するように形成されており、
    　前記ゲート電極は前記ゲート絶縁膜上に形成されている請求項１２に記載の半導体装置。     The substrate is a first conductivity type silicon carbide substrate;
    A second conductivity type well region formed in the silicon carbide layer;
    A contact region formed in the well region and containing an impurity of a second conductivity type at a higher concentration than the well region;
    A source region of a first conductivity type formed so as to surround the contact region in the well region;
    A drift region of a first conductivity type formed in a portion of the silicon carbide layer where none of the well region, the contact region, and the source region is formed;
    A gate insulating film formed on the silicon carbide layer;
    A drain electrode formed on the back surface of the substrate;
    The source electrode is formed on the silicon carbide layer so as to be in contact with the contact region and the source region,
    The semiconductor device according to claim 12, wherein the gate electrode is formed on the gate insulating film.
  14. 　（Ａ）基板上に炭化珪素層を形成する工程と、
    　（Ｂ）前記炭化珪素層上に、互いに電気的に絶縁された第１電極および第２電極を形成する工程と、
    　（Ｃ）前記炭化珪素層と前記第１および第２電極の上に絶縁膜を形成し、前記絶縁膜に、前記第１電極に達する第１コンタクトホールおよび前記第２電極に達する第２コンタクトホールを形成する工程と、
    　（Ｄ）前記第１および第２コンタクトホール内および前記絶縁膜上に金属膜を形成する工程と、
    　（Ｅ）前記金属膜をパターニングして、前記第１コンタクトホール内において前記第１電極に接続された第１バリアメタル層と、前記第１バリアメタル層と電気的に分離され、かつ、前記第２コンタクトホール内において前記第２電極に接続された第２バリアメタル層とを得る工程と、
    　（Ｆ）前記第１バリアメタル層、第２バリアメタル層および前記絶縁膜上に、導電膜を形成する工程と、
    　（Ｇ）前記導電膜をウェットエッチングによってパターニングして、前記第１バリアメタル層に接続された第１金属配線と、前記第１金属配線と電気的に分離され、かつ、前記第２バリアメタル層に接続された第２金属配線とを得る工程と
    を包含し、
    　前記基板の上方から見て、前記第１金属配線の輪郭の内側に前記第１バリアメタルの輪郭が配置され、前記第２金属配線の輪郭の内側に前記第２バリアメタルの輪郭が配置されている半導体装置の製造方法。     (A) forming a silicon carbide layer on the substrate;
    (B) forming a first electrode and a second electrode electrically insulated from each other on the silicon carbide layer;
    (C) forming an insulating film on the silicon carbide layer and the first and second electrodes, and forming a first contact hole reaching the first electrode and a second contact hole reaching the second electrode in the insulating film; Forming a step;
    (D) forming a metal film in the first and second contact holes and on the insulating film;
    (E) patterning the metal film to electrically isolate the first barrier metal layer connected to the first electrode in the first contact hole from the first barrier metal layer; and Obtaining a second barrier metal layer connected to the second electrode in two contact holes;
    (F) forming a conductive film on the first barrier metal layer, the second barrier metal layer, and the insulating film;
    (G) patterning the conductive film by wet etching to electrically isolate the first metal wiring connected to the first barrier metal layer from the first metal wiring, and the second barrier metal layer; And obtaining a second metal wiring connected to
    When viewed from above the substrate, the outline of the first barrier metal is arranged inside the outline of the first metal wiring, and the outline of the second barrier metal is arranged inside the outline of the second metal wiring. A method for manufacturing a semiconductor device.
  15. 　前記工程（Ｇ）は、前記導電膜をエッチングして、前記第１金属配線と前記第２金属配線とを互いに分離するための分離領域を形成する工程を含み、前記第１バリアメタル層および前記第２バリアメタル層は、何れも、前記分離領域において露出していない請求項１４に記載の半導体装置の製造方法。 The step (G) includes a step of etching the conductive film to form an isolation region for separating the first metal wiring and the second metal wiring from each other, and the first barrier metal layer and the step The method for manufacturing a semiconductor device according to claim 14, wherein none of the second barrier metal layer is exposed in the isolation region.
  16. 　前記導電膜の厚さは２μｍ以上である請求項１４または１５に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 14 or 15, wherein the conductive film has a thickness of 2 µm or more.
  17. 　前記導電膜はアルミニウム膜である請求項１４から１６のいずれかに記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 14, wherein the conductive film is an aluminum film.
  18. 　前記金属膜は、チタン膜および窒化チタン膜を含む積層膜である請求項１４から１７のいずれかに記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 14, wherein the metal film is a laminated film including a titanium film and a titanium nitride film.
  19. 　前記第１電極はソース電極であり、前記第２電極はゲート電極である請求項１４から１８のいずれかに記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 14, wherein the first electrode is a source electrode and the second electrode is a gate electrode.
  20. 　前記工程（Ａ）の後に行われ、前記炭化珪素層にウェル領域、ソース領域、およびコンタクト領域を形成する工程と、前記炭化珪素層上にゲート絶縁膜を形成する工程と、
    　前記基板の裏面にドレイン電極を形成する工程と
    をさらに包含し、
    　前記ゲート電極は、前記ゲート絶縁膜上に形成され、
    　前記ソース電極は、前記ソース領域および前記コンタクト領域と接するように形成される請求項１９に記載の半導体装置の製造方法。     Performed after the step (A), forming a well region, a source region, and a contact region in the silicon carbide layer; forming a gate insulating film on the silicon carbide layer;
    Further comprising the step of forming a drain electrode on the back surface of the substrate,
    The gate electrode is formed on the gate insulating film,
    The method of manufacturing a semiconductor device according to claim 19, wherein the source electrode is formed in contact with the source region and the contact region.
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