CN113851521A - High-voltage field effect tube structure for improving on-resistance characteristic and manufacturing method - Google Patents
High-voltage field effect tube structure for improving on-resistance characteristic and manufacturing method Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
Abstract
The invention provides a high-voltage field effect transistor structure for improving the on-resistance characteristic and a manufacturing method thereof. The P-type doped region under the field oxygen of the drift region is injected into the N-type drift region through high-energy injection, the P-type doped region is far away from a silicon-oxygen interface of the field oxygen region, the P-type doped region is connected with a P well section at a certain distance in the width direction of a high-voltage field effect transistor, the unconnected part forms an upper channel and a lower channel of the drift region, a current path in an on state is reduced, the on-resistance of a device is reduced, and the problem that the on-resistance is increased due to incomplete depletion recovery in the on state is solved by the connected part.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a high-voltage field effect transistor structure for improving on-resistance characteristics and a manufacturing method thereof.
Background
In order to increase BV (breakdown voltage) in an off state in a conventional ultra-high voltage field effect transistor (with a withstand voltage of more than 300V) in a high voltage BCD process (as shown in fig. 1), a layer of PTOP implantation is usually introduced at the position of an N-type drift region to increase the withstand voltage through charge balance.
The structure has two problems, one is that the ultra-high voltage field effect transistor is usually used in a switch state, when the ultra-high voltage field effect transistor is in an off state, a grid (Gate) and a Source (Source) are grounded, a high voltage is applied to a Drain (Drain), and at the moment, N-type charges and P-type charges in a P-type P-type P-type P-type P-type P-type P-. When the device is in an on state, the grid (Gate) is connected with power voltage, the Source (Source) is grounded, the Drain (Drain) is connected with low voltage, the device is positioned in a linear working area, and the output current realizes the driving function. When the switch is in an operating state, the off state is switched to the on state, and the drift region is recovered from the depletion state, because the PTOP is suspended in the drift region N type, no hole is supplemented, and a certain time is required for recovering from the depletion state, so that the PTOP has enough time to recover in the low-frequency operating state, but when the frequency is higher, the PTOP recovery time is longer than the switching speed, the PTOP depletion recovery is incomplete when the off state is switched to the on state (as shown in fig. 2), which causes that the current needs to bypass the depletion region to lengthen the path when the on state is switched (as shown in fig. 3), which causes the on resistance to become larger, and the on resistance becomes larger as the switching frequency is higher.
Secondly, the PTOP is injected under the field oxide in the drift region and close to the silicon-oxygen boundary, and when the device is in an on state, because the PTOP is a hole, the current must flow by bypassing the PTOP, so that the current path is longer, and the on-resistance characteristic is affected.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a high voltage fet structure with improved on-resistance characteristics and a manufacturing method thereof, which are used to solve the problems of increased on-resistance and increased device on-resistance caused by incomplete depletion of the high voltage fet in the on state in the prior art.
To achieve the above and other related objects, the present invention provides a high voltage fet structure with improved on-resistance characteristics, comprising:
a silicon substrate, a drain region located on the silicon substrate; the drain region is provided with an N-type drift region; the N-type drift region is provided with a field oxide isolation region; a P-type doped region is arranged below the field oxide isolation region; the P-type doped region is far away from the bottom of the field oxide isolation region;
a P-well on the silicon substrate; an N-type accumulation region between the P-well and the P-type doped region; the P-type doped region extends to the P-well through the accumulation region;
one side of the field oxide isolation region close to the accumulation region is covered with a polysilicon field plate; a grid polysilicon extending to the upper surface of the accumulation region is arranged on the P well; the grid polysilicon is connected with the polysilicon field plate;
the field oxide isolation region close to the drain region is covered with polycrystalline silicon; the polysilicon is connected with the drain region through metal.
Preferably, the silicon substrate is a P-type substrate.
Preferably, the P-well is a source region of the high-voltage field effect transistor structure.
Preferably, the P well is provided with a P + region and an N + region, which are connected by a metal.
Preferably, the polysilicon on the field oxide isolation region is connected with the drain region through metal aluminum.
Preferably, the polysilicon on the field oxide isolation region is connected with the drain region to form a drain region field plate.
Preferably, the gate polysilicon is connected with the polysilicon field plate to form a gate field plate.
Preferably, the drain region is provided with an N + region.
Preferably, the planar structure of the P-type doped region extending to the P-well is a plurality of strip-shaped structures, and adjacent strip-shaped structures are mutually distributed at intervals between the P-wells of the P-type doped region below the field oxide isolation region.
Preferably, in the planar structure of the high voltage field effect transistor structure, the drain region is surrounded by the source region.
Preferably, in the planar structure of the high-voltage field effect transistor structure, the drain regions or the source regions at the corners are connected by arcs.
Preferably, the planar structure of the high-voltage field effect tube structure is an egg shape formed by connecting a middle rectangle and two semicircular ends.
Preferably, the planar structure of the high-voltage field effect transistor structure is a circular structure with a drain region outside an inner source region.
The invention also provides a manufacturing method of the high-voltage field effect tube structure for improving the on-resistance characteristic, which at least comprises the following steps:
providing a silicon substrate, and forming an N-type drift region on the silicon substrate; the N-type drift region is used as a drain region drift region; forming a P well in the N-type drift region; forming a field oxide isolation region on the upper surface of the N-type drift region; forming a P-type doped region in the N-type drift region 102 under the field oxide isolation region; the P-type doped region is far away from the bottom of the field oxide isolation region; an accumulation region between the P-well and the P-type doped region;
covering a polysilicon field plate on one side of the field oxide isolation region close to the accumulation region; covering the field oxide isolation region close to the drain region with polycrystalline silicon; covering the upper surface of the accumulation region with gate polysilicon connected with the polysilicon field plate; connecting the polycrystalline silicon with the drain region through metal;
and step three, extending the P-type doped region to the P well through the accumulation region to form a PTOP.
Preferably, an N-type drift region is formed in step two by implantation and high temperature drive-in.
Preferably, in the first step, the P-type doping is performed to the N-type drift region by high energy implantation.
Preferably, the P-type doped region is far away from the bottom of the field oxide isolation region, so that the N-type drift region forms a dual current channel in upper and lower regions of the P-type doped region.
As described above, the high voltage fet structure with improved on-resistance characteristics and the manufacturing method according to the present invention have the following advantageous effects: according to the invention, the P-type doped region under the field oxygen of the drift region is connected with the P well, so that enough holes are ensured to supplement the P-type doped region in a depletion state when the off-state is switched to the on-state, the depletion recovery speed of the P-type doped region is improved, and the problem of the increase of the on-resistance caused by incomplete depletion in the on-state is solved. Meanwhile, the P-type doped region under the field oxygen of the drift region is injected into the N-type drift region through high-energy injection, and a silicon-oxygen interface of the field oxygen region is far away, so that an upper channel and a lower channel of the drift region are formed, a current path in an on state is reduced, and the on resistance of the device is reduced.
Drawings
FIG. 1 is a schematic diagram of a prior art high voltage FET device;
FIG. 2 is a partial schematic diagram illustrating the depletion recovery of a prior art high voltage field effect device during switching;
FIG. 3 is a schematic diagram of an on-state current path of a prior art high voltage field effect device when depletion recovery is incomplete;
fig. 4 is a plan view of a high voltage fet device according to the present invention;
FIG. 5 is a cross-sectional view of a high voltage FET AA cross-section device according to the present invention;
fig. 6 shows a cross-sectional structure diagram of a high voltage fet BB cross-section device according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 4 to 6. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides a high-voltage field effect tube structure for improving on-resistance characteristics, which at least comprises:
a silicon substrate, a drain region located on the silicon substrate; the drain region is provided with an N-type drift region; the N-type drift region is provided with a field oxide isolation region; a P-type doped region is arranged below the field oxide isolation region; the P-type doped region is far away from the bottom of the field oxide isolation region;
a P-well on the silicon substrate; an accumulation region between the P-well and the P-type doped region; the P-type doped region extends to the P-well through the accumulation region;
one side of the field oxide isolation region close to the accumulation region is covered with a polysilicon field plate; a grid polysilicon extending to the upper surface of the accumulation region is arranged on the P well; the overlapping part of the P well and the polycrystalline silicon is a channel region; the grid polysilicon is connected with the polysilicon field plate;
the field oxide isolation region close to the drain region is covered with polycrystalline silicon; the polysilicon is connected with the drain region through metal.
As shown in fig. 5 and 6, the high voltage fet structure with improved on-resistance characteristics according to the present invention at least includes: a silicon substrate 101, a drain region on the silicon substrate 101; the drain region is provided with an N-type drift region 202; a field oxide isolation region 105 is arranged on the upper surface of the N-type drift region 202; a P-type doped region (PTOP)104 is arranged below the field oxide isolation region 105; the P-type doped region is far away from the bottom of the field oxide isolation region, namely the P-type doped region is at a certain distance from the bottom of the field oxide isolation region;
further comprising: a P-well (PW)103 on the silicon substrate 101; an accumulation region between the P-well (PW)103 and the P-type doped region (PTOP) 104; the P-type doped region (PTOP)104 extends to the P-well (PW)103 through the accumulation region as shown in fig. 6, wherein the extended portion is PTOP (104').
One side of the field oxide isolation region 105 close to the accumulation region is covered with a polysilicon field plate 107; a grid polysilicon 204 extending to the upper surface of the accumulation region is arranged on the P well; the grid polysilicon is connected with the polysilicon field plate;
the field oxide isolation region 105 close to the drain region is covered with polysilicon 106; the polysilicon 106 is connected to the drain region 201 through a metal 111.
Further, the silicon substrate of this embodiment is a P-type substrate. The P trap is a source region of the high-voltage field effect tube structure. The P-well is provided with a P + region (P +) and an N + region (N +), which are connected by a metal 112. The polysilicon 106 on the field oxide isolation region is connected with the drain region 201 through metal aluminum. And the polycrystalline silicon positioned on the field oxide isolation region is connected with the drain region to form a drain region field plate. The grid polysilicon is connected with the polysilicon field plate to form a grid field plate. The drain region is provided with an N + region (N +).
According to the invention, a field oxide isolation region is generated in the N-type drift region of the drain region, P-type doping of a type different from that of ion implantation of the drift region is implanted below the field isolation region, and high-energy implantation is used to enable the P-type doping to be far away from the bottom position of the field oxide, and when high voltage is applied to the drain region, hole ions are provided to more easily generate a depletion region so as to improve the withstand voltage of the drain region.
In a part of the trench width region of the high-voltage field effect transistor, P-type doping under the field oxygen of the drain region extends to the PW substrate region and is connected with a P-type well (103) of the substrate, and when the off-state voltage resistance of the high-voltage field effect transistor is switched to on-state driving current, hole ions are provided for P-type doping depletion recovery below the field oxygen isolation, and depletion recovery is accelerated.
As shown in fig. 4, in this embodiment, the planar structure of the P-type doped region ((PTOP (104')) extending to the P-well is a plurality of strip-shaped structures, and adjacent strip-shaped structures are spaced apart from each other and distributed between the P-wells in the P-type doped region under the field oxide isolation region, in the planar structure of the high voltage field effect transistor structure, the drain region 201 is surrounded by the source region 202.
The invention also provides a manufacturing method of the high-voltage field effect tube structure for improving the on-resistance characteristic, which at least comprises the following steps:
providing a silicon substrate 101, and forming an N-type drift region 102 on the silicon substrate; the N-type drift region is used as a drain region drift region 202; forming a P well 103 in the N-type drift region; forming field oxide isolation regions 105 on the upper surface of the N-type drift region; forming a P-type doped region 104 in the N-type drift region 102 under the field oxide isolation region 105; the P-type doped region is far away from the bottom of the field oxide isolation region; an accumulation region between the P-well and the P-type doped region; the overlapping part of the P well and the polycrystalline silicon is a channel region; (ii) a
Further, in the first step of this embodiment, the P-type doping is implanted into the N-type drift region by high energy implantation.
Further, in the present invention, in the first step of this embodiment, the P-type doped region is far away from the bottom of the field oxide isolation region, so that the N-type drift region forms dual current channels in the upper and lower regions of the P-type doped region.
Covering a polysilicon field plate 107 on one side of the field oxide isolation region close to the accumulation region; covering the field oxide isolation regions 105 close to the drain region with polysilicon 106; covering the upper surface of the accumulation region with gate polysilicon 204 connected with the polysilicon field plate 107; connecting the polycrystalline silicon with the drain region through metal;
furthermore, in the second step of this embodiment, an N-type drift region is formed by implantation and high temperature well-driving.
Step three, extending the P-type doped region 104 to the P-well through the accumulation region to form a PTOP 104'.
In summary, the P-type doped region under the field oxygen of the drift region is connected with the P-well, so that sufficient holes supplement the P-type doped region in a depletion state when the off-state is switched to the on-state, the depletion recovery speed of the P-type doped region is improved, and the problem that the on-resistance is increased due to incomplete depletion in the on-state is solved. Meanwhile, the P-type doped region under the field oxygen of the drift region is injected into the N-type drift region through high-energy injection, and a silicon-oxygen interface of the field oxygen region is far away, so that an upper channel and a lower channel of the drift region are formed, a current path in an on state is reduced, and the on resistance of the device is reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (17)
1. A high voltage fet structure with improved on-resistance characteristics, comprising:
a silicon substrate, an N-type drift region on the silicon substrate; the N-type drift region is provided with a field oxide isolation region; a P-type doped region is arranged below the field oxide isolation region; the P-type doped region is far away from the bottom of the field oxide isolation region;
a P-well on the silicon substrate; an N-type accumulation region between the P-well and the P-type doped region; the P-type doped region extends to the P-well through the accumulation region;
one side of the field oxide isolation region close to the accumulation region is covered with a polysilicon field plate; a grid polysilicon extending to the upper surface of the accumulation region is arranged on the P well; the overlapping part of the P well and the polycrystalline silicon is a channel region; the grid polysilicon is connected with the polysilicon field plate;
the field oxide isolation region close to the drain region is covered with polycrystalline silicon; the polysilicon is connected with the drain region through metal.
2. The high voltage fet structure with improved on-resistance characteristics as claimed in claim 1, wherein: the silicon substrate is a P-type substrate.
3. The high voltage fet structure with improved on-resistance characteristics as claimed in claim 1, wherein: the P trap is a source region of the high-voltage field effect tube structure.
4. The high voltage fet structure with improved on-resistance characteristics as claimed in claim 1, wherein: the P trap is provided with a P + region and an N + region which are connected through metal.
5. The high voltage fet structure with improved on-resistance characteristics as claimed in claim 1, wherein: and the polycrystalline silicon positioned on the field oxide isolation region is connected with the drain region through metal aluminum.
6. The high voltage fet structure with improved on-resistance characteristics as claimed in claim 1, wherein: and the polycrystalline silicon positioned on the field oxide isolation region is connected with the drain region to form a drain region field plate.
7. The high voltage fet structure with improved on-resistance characteristics as claimed in claim 1, wherein: the grid polysilicon is connected with the polysilicon field plate to form a grid field plate.
8. The high voltage fet structure with improved on-resistance characteristics as claimed in claim 1, wherein: the drain region is provided with an N + region.
9. The high voltage fet structure with improved on-resistance characteristics as claimed in claim 1, wherein: the plane structure of the P-type doped region extending to the P-well is a plurality of strip-shaped structures, and the adjacent strip-shaped structures are mutually distributed between the P-wells of the P-type doped region below the field oxide isolation region at intervals.
10. The high voltage fet structure with improved on-resistance characteristics as claimed in claim 1, wherein: in the planar structure of the high-voltage field effect transistor structure, the drain region is surrounded by the source region.
11. The high voltage fet structure with improved on-resistance characteristics as claimed in claim 1, wherein: in the plane structure of the high-voltage field effect tube structure, the drain regions or the source regions at the corners are connected by adopting circular arcs.
12. The high voltage fet structure with improved on-resistance characteristics as claimed in claim 1, wherein: the plane structure of the high-voltage field effect tube structure is an egg shape formed by connecting a middle rectangle and two semicircular ends.
13. The high voltage fet structure with improved on-resistance characteristics as claimed in claim 1, wherein: the planar structure of the high-voltage field effect tube structure is a circular structure with a drain region outside an inner source region.
14. The method of manufacturing a high voltage fet structure with improved on-resistance characteristics as claimed in any one of claims 1 to 13, wherein the method comprises at least the steps of:
providing a silicon substrate, and forming an N-type drift region on the silicon substrate; the N-type drift region is used as a drain region drift region; forming a P well in the N-type drift region; forming a field oxide isolation region on the upper surface of the N-type drift region; forming a P-type doped region in the N-type drift region below the field oxide isolation region; the P-type doped region is far away from the bottom of the field oxide isolation region; an accumulation region between the P-well and the P-type doped region; the overlapping part of the P well and the polycrystalline silicon is a channel region;
covering a polysilicon field plate on one side of the field oxide isolation region close to the accumulation region; covering the field oxide isolation region close to the drain region with polycrystalline silicon; covering grid polysilicon connected with the polysilicon field plate on the upper surface of the channel region; connecting the polycrystalline silicon with the drain region through metal;
and step three, extending the P-type doped region 104 to the P-well through the accumulation region to form a PTOP.
15. The method of claim 14, wherein the step of forming the high voltage fet structure further comprises the steps of: and in the second step, an N-type drift region is formed through injection and high-temperature drive-in.
16. The method of claim 14, wherein the step of forming the high voltage fet structure further comprises the steps of: in the first step, the P-type doping is injected into the N-type drift region by high-energy injection.
17. The method of claim 14, wherein the step of forming the high voltage fet structure further comprises the steps of: the P-type doped region in the first step is far away from the bottom of the field oxide isolation region, so that the N-type drift region forms double current channels in the upper and lower regions of the P-type doped region.
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