CN108987572B - Semiconductor structure for forming resistor and forming method of resistor - Google Patents
Semiconductor structure for forming resistor and forming method of resistor Download PDFInfo
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- CN108987572B CN108987572B CN201810867447.7A CN201810867447A CN108987572B CN 108987572 B CN108987572 B CN 108987572B CN 201810867447 A CN201810867447 A CN 201810867447A CN 108987572 B CN108987572 B CN 108987572B
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 36
- 229920005591 polysilicon Polymers 0.000 claims description 36
- 230000000694 effects Effects 0.000 description 16
- 241000293849 Cordylanthus Species 0.000 description 12
- 239000000463 material Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 10
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 238000002513 implantation Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
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Abstract
A semiconductor structure for forming a resistor and a method of forming a resistor. The semiconductor structure for forming the resistor comprises a field oxide layer positioned on a semiconductor substrate, wherein the field oxide layer isolates a first active region; a first mask layer over a first side of the first active region width; a second mask layer located over a second side of the first active region width; the distance between the first mask layer and the second mask layer is equal to the width of the resistor. The semiconductor structure for forming the resistor can improve the dimensional accuracy of the formed resistor.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor structure for forming a resistor and a method for forming a resistor.
Background
The type of devices required for the integrated circuit varies from one end application to another. But the resistive device is not available for any application. The dimensional accuracy of the resistive device is an important consideration in making and using the resistive device because the dimensional accuracy of the resistive device directly affects the accuracy of the resistance value of the resistor.
The Chinese patent publication No. CN107331695A discloses an N-well resistor and a method for generating the same. However, when the size of the resistor is considered and controlled in the prior art, the considered factors are not accurate enough, and the adopted scheme cannot well control the size precision of the corresponding resistor.
Disclosure of Invention
The invention solves the problem of providing a semiconductor structure for forming a resistor and a forming method of the resistor, which are used for precisely controlling the size of the resistor and reducing the error between the actual size and the design size of the resistor.
In order to solve the above problems, the present invention provides a semiconductor structure for forming a resistor, comprising: the field oxide layer is positioned on the semiconductor substrate and isolates the first active region; a first mask layer over a first side of the first active region width; a second mask layer located over a second side of the first active region width; the distance between the first mask layer and the second mask layer is equal to the width of the resistor.
Optionally, the semiconductor structure for forming a resistor further includes a third mask layer located over the first active region length first side; or the first active area and the second active area are respectively arranged on the first side and the second side of the first active area, and the distance between the third mask layer and the fourth mask layer is larger than the length of the resistor.
Optionally, the first mask layer is a polysilicon layer, and the second mask layer is a polysilicon layer.
Optionally, the first mask layer is entirely located directly above the first active region, or the first mask layer is partially located directly above the field oxide layer; the second mask layer is entirely located right above the first active region, or the second mask layer is partially located right above the field oxide layer.
Optionally, the width direction of the first mask layer is parallel to the width direction of the first active region, and the width of the first mask layer is more than 0.5 μm; the width direction of the second mask layer is parallel to the width direction of the first active region, and the width of the second mask layer is more than 0.5 mu m.
In order to solve the above problems, the present invention further provides a method for forming a resistor, including: forming a field oxide layer on a semiconductor substrate, wherein the field oxide layer isolates a first active region; forming a first mask layer over a first side of the first active region width; forming a second mask layer over the first active region width second side; the distance between the first mask layer and the second mask layer is equal to the width of the resistor; and carrying out resistance doping on the first active region by taking the first mask layer and the second mask layer as masks.
Optionally, the method further includes forming a third mask layer over the first active region length first side; or further comprising forming a third mask layer over the first active region length first side while forming a fourth mask layer over the first active region length second side, a distance between the third mask layer and the fourth mask layer being greater than a length of the resistor.
Optionally, the first mask layer is formed by polysilicon, and the second mask layer is formed by polysilicon.
Optionally, when the gate of the transistor is formed on the second active region by using polysilicon, the first mask layer and the second mask layer are formed simultaneously.
Optionally, the first mask layer is formed entirely over the first active region, or the first mask layer is partially formed over the field oxide layer; the second mask layer is formed entirely over the first active region or partially over the field oxide layer.
In one aspect of the technical scheme, the first mask layer and the second mask layer are adopted as masks, and the first active region is subjected to resistance doping to form a corresponding resistor, so that the influence of the difference between the design width and the actual width of the active region on the resistor width in the forming process of the active region can be eliminated. At this time, the width of the resistor is determined by the distance between the first mask layer and the second mask layer, and therefore, the accuracy of the resistor width can be improved.
Further, since the corresponding mask layers are made of polysilicon, and the resistor width boundaries are defined by the mask layers of polysilicon, the mask layers can be fabricated together when fabricating other polysilicon structure layers, so that the resistor width can be made to be consistent with the width dimension of the layout design, and adverse effects on the resistor width caused by various process steps (such as oxide layer removal step, sacrificial oxidation step, gate oxidation step, etc.) can be eliminated.
Drawings
Fig. 1 to 3 are schematic cross-sectional views corresponding to steps of a conventional resistor forming method;
FIG. 4 is a schematic top view of the structure shown in FIG. 3;
Fig. 5 to fig. 7 are schematic cross-sectional views corresponding to each step of the resistor forming method according to the embodiment of the present invention;
FIG. 8 is a schematic top view of the structure of FIG. 7;
FIG. 9 is a schematic cross-sectional view illustrating steps of a resistor forming method according to another embodiment of the present invention;
FIG. 10 is a schematic top view of the structure of FIG. 9;
FIG. 11 is a schematic cross-sectional view illustrating steps of a resistor forming method according to another embodiment of the present invention;
Fig. 12 is a schematic top view of the structure shown in fig. 11.
Detailed Description
Please refer to fig. 1 to 3 for a conventional resistor manufacturing method.
As shown in fig. 1, a semiconductor substrate 100 is provided, a pad oxide layer 110 is deposited on the semiconductor substrate 100, and then a hard mask layer 120 is formed.
As shown in fig. 2, under the protection of the hard mask layer 120, the field oxide layer 130 is grown, and the substrate under the protection of the hard mask layer 120 does not form a field oxide layer, i.e., the field oxide layer 130 defines the location of an active region (not labeled).
The length and width of the active region may be set arbitrarily in the practical application of the chip, for example, the length may be 1 μm or 1000 μm, the width may be 1 μm to 10 μm, etc., and the corresponding range may be set according to the requirements of the circuit.
As shown in fig. 3, the hard mask layer 120 is removed, and thereafter, the field oxide layer 130 is directly used as a mask to perform doping implantation for resistor formation, thereby forming a resistor 140.
Fig. 4 shows a schematic top view of the resistor 140 in fig. 3, where the resistor 140 has vias (not labeled) at both ends of its length for connection to subsequent conductive structures. Fig. 4 also shows that resistor 140 has a length L.
However, in the above process, since the field oxide layer 130 is directly used as a mask for implantation, the actual width W' of the finally formed resistor 140 will be greatly different from the designed resistor width for the following reasons:
Initially, the width W of the hard mask layer 120 shown in fig. 1 is considered to be the width of the corresponding active region, and this width is typically the resistance design width at the beginning of the design;
however, when the field oxide layer 130 is grown as shown in fig. 2, oxygen permeates from the bottoms of the two sides of the hard mask layer 120 to embed into the two sides of the field oxide layer, so that the edge of the field oxide layer 130 forms a bird's beak-like structure, which is commonly referred to as bird's beak effect;
The actual width of the active region is already smaller than the width W of the hard mask layer 120 due to the bird's beak effect of the field oxide layer 130;
Therefore, the field oxide 130 mask resistor implantation must be used when initially designing the boundary of the active region as the boundary of the resistor, which results in the final resistor having a width that is necessarily smaller than that when initially designed; moreover, it is easy to know that the thicker the field oxide layer 130 is, the more serious the bird's beak effect is, the longer the field oxide layer 130 is embedded in the active region, resulting in a larger difference between the actual width and the design width of the corresponding resistor; in fig. 3, the original width W of the hard mask layer 120 is shown, and the width W' of the final resistor 140 is shown at the same time, just to visually show the above-mentioned width difference.
In addition, in addition to the bird's beak effect, in the conventional resistor manufacturing method, after the hard mask layer 120 is removed, a plurality of corresponding process steps, such as a sacrificial oxidation step, an oxide layer etching step, a gate oxidation step, and the like, are performed between the doping steps for forming the resistor, and the fluctuation of these process steps also affects the boundary (particularly the boundary of the width) of the active region, so that the accuracy of the actual width of the resistor is further affected, particularly for the resistor with smaller width, which is more serious.
In summary, in the conventional resistor manufacturing method, the width direction dimension affecting the maximum resistor dimension is not controlled, and the relationship between the resistor manufacturing and the preceding and following process steps is not found, so that the resistor dimension cannot be accurately controlled.
Therefore, the present invention provides a new resistor forming method and a corresponding semiconductor structure to solve the above-mentioned drawbacks.
The present invention will be described in detail with reference to the accompanying drawings for more clear illustration.
An embodiment of the invention provides a method for forming a resistor, please refer to fig. 5 to 8.
A field oxide layer 230 is formed on the semiconductor substrate 200 (as shown in fig. 6), the field oxide layer 230 isolating a first active region (not labeled). This process may be combined with reference to fig. 5 and 6. As shown in fig. 5, a pad oxide layer 210 may be deposited on a semiconductor substrate 200, and then a hard mask layer 220 may be formed. The thickness of the pad oxide layer 210 may be approximatelyThe thickness of the hard mask layer 220 may be approximately/>The process of forming the hard mask layer 220 may include photolithography and etching.
As shown in fig. 6, under the protection of the hard mask layer 220, the field oxide layer 230 is grown, and the substrate under the protection of the hard mask layer 220 does not form the field oxide layer 230, i.e. the field oxide layer 230 defines the location of the first active region (not labeled). Note that in fig. 6, the field oxide layer 230 and the remaining pad oxide layer are not shown separately, and are integrally connected (because they are typically silicon dioxide), and the remaining pad oxide layer is omitted from fig. 6.
In this embodiment, the semiconductor substrate 200 may be a P-type silicon substrate. In other embodiments, the semiconductor substrate 200 may be an N-type silicon substrate, or a substrate of another type semiconductor may be used depending on the resistance to be formed.
In this embodiment, the first active region provides a region for forming a resistor later, or the first active region is used for forming a corresponding resistor.
In this embodiment, the field oxide layer 230 may be formed by a selective oxidation of silicon (LOCOS) process, and the field oxide layer 230 may have a thickness of aboutAs previously described, the field oxide layer 230 has a bird's beak effect. The width W1 of the hard mask layer 220 is generally considered to be the width of the first active region. However, as previously analyzed, the width W1 of the hard mask layer 220 and the width of the first active region (not labeled, reference may be made to the width of the middle of the two field oxide layers 230 in fig. 6, or the width of the remaining pad oxide layer) have been different due to the bird's beak effect of the field oxide layer 230.
Referring to fig. 7, a first mask layer 251 is formed over a first side of the first active region width, and a second mask layer 252 is formed over a second side of the first active region width. The process includes the steps of removing the hard mask layer 220, forming a corresponding mask material layer after removing the hard mask layer 220, and etching the mask material layer to form each mask layer.
Note that, above the first side of the width of the first active region generally refers to above the vicinity of the first end of the width of the first active region. Typically a distance within one end of the width. Alternatively, and as shown directly above the first side of the first active region width, the first mask layer 251 is not located above a majority of the first active region width intermediate. The second mask layer 252 is similar.
In this embodiment, the method designs the distance W2 between the first mask layer 251 and the second mask layer 252 to be equal to the width of the resistor.
In this embodiment, after the first mask layer 251 and the second mask layer 252 are formed, the first active region is resistance doped by using the first mask layer 251 and the second mask layer 252 as masks, so as to form the resistor 240, where the resistor 240 is one region of the first active region. As described above, the width W3 of the resistor 240 is equal to the distance W2 between the first mask layer 251 and the second mask layer 252.
Referring to fig. 8, a schematic top view of the corresponding structure of fig. 7 is shown, and as can be seen from fig. 8, the forming method provided in this embodiment further includes forming a third mask layer 253 over a first side of the length of the first active region, and forming a fourth mask layer 254 over a second side of the length of the first active region, wherein a distance between the third mask layer 253 and the fourth mask layer 254 is greater than a length of the resistor 240, because the length of the resistor 240 is determined by vias (not labeled) located on both sides of the length, as shown in fig. 8, to be a length L3 (the vias are not affected by the bird's beak effect of the field oxide layer 230, and therefore, the length L3 of the resistor 240 is generally more accurate). In this embodiment, the first mask layer 251, the second mask layer 252, the third mask layer 253 and the fourth mask layer 254 are integrally connected, and the whole is one mask layer connected end to end, and in fig. 8, the edges of the mask layers are not shown in a dividing manner, but it is understood that they respectively correspond to one side of the rectangular ring, and different dividing manners are possible.
Since the first mask layer 251 and the second mask layer 252 are used as masks, the first active region is doped with resistance to form the corresponding resistor 240, and at this time, the influence of the difference between the width of the hard mask layer 220 and the width of the first active region has been eliminated, and the width of the resistor is directly determined by the distance between the first mask layer 251 and the second mask layer 252, so that the accuracy of the resistor width can be improved.
In other embodiments, the forming method may include forming a third mask layer only over the first side of the length of the first active region, i.e., without a fourth mask layer.
In this embodiment, the first mask layer 251 is formed of polysilicon, and the second mask layer 252 is formed of polysilicon.
In this embodiment, when the gate electrode of the transistor is formed on the second active region by using polysilicon, the first mask layer and the second mask layer 252 are formed simultaneously. The second active region is any other active region except the first active region on the semiconductor substrate 200, and is an active region for fabricating a corresponding transistor structure. When manufacturing a MOS transistor, the manufacturing of a gate is usually involved, and the gate may be made of a polysilicon material, so that such a process step may be utilized to simultaneously form each mask layer, thereby saving the process step.
In this embodiment, the first mask layer 251 is formed entirely over the first active region, and the second mask layer 252 is formed entirely over the first active region.
The final formation of this embodiment is an N-doped resistor (P-doped resistor in other embodiments, which may be different depending on the type of semiconductor substrate 200 and the doping type), i.e., a heavily doped N-type region (P-type region in other embodiments).
The method provided in this embodiment uses the first mask layer 251 and the second mask layer 252 to define the resistor width, so as to eliminate the influence of the bird's beak effect, and thus make the design width of the resistor equal to the final actual width.
Meanwhile, since the first mask layer 251 and the second mask layer 252 are both made of polysilicon, and polysilicon forming steps are simultaneously formed when forming the gate electrode by using other active regions (second active regions), it is unnecessary to undergo the effects of a sacrificial oxidation step, an oxide layer removal step, a gate oxidation step, and the like before the resistor is manufactured, so that the width of the resistor actually produced can be further kept consistent with the width dimension in layout design, and errors can be reduced. In addition, polysilicon is a common material in the CMOS process, special material selection is not needed, new processing steps are not needed, and the practicability is high.
The above-described forming process further includes providing a semiconductor structure for forming a resistor, as shown in fig. 7 and 8.
The semiconductor structure for forming the resistor comprises a field oxide layer 230 on the semiconductor substrate 200, wherein the field oxide layer 230 isolates the first active region, a first mask layer 251 above a first side of the width of the first active region, a second mask layer 252 above a second side of the width of the first active region, and a distance between the first mask layer 251 and the second mask layer 252 is equal to the width of the resistor.
The semiconductor structure for forming a resistor further includes both a third mask layer 253 over a first side of the first active area length and a fourth mask layer 254 over a second side of the first active area length, a distance between the third mask layer 253 and the fourth mask layer 254 being greater than a length of the resistor.
In other embodiments, the semiconductor structure may include only the third mask layer over the first side of the first active region length.
In this embodiment, the first mask layer 251 is a polysilicon layer, and the second mask layer 252 is a polysilicon layer.
In this embodiment, the first mask layer 251 is located entirely over the first active region, and the second mask layer 252 is located entirely over the first active region.
In this embodiment, the width direction of the first mask layer 251 is parallel to the width direction of the first active region, and the width of the first mask layer 251 is more than 0.5 μm; the width of the second mask layer 252 is parallel to the width of the first active region, and the width of the second mask layer 252 is more than 0.5 μm.
In this embodiment, the width direction of the third mask layer 253 is perpendicular to the width direction of the first active region, and the width of the third mask layer 253 is more than 0.5 μm; the width of the fourth mask layer 254 is perpendicular to the width of the first active region, and the width of the fourth mask layer 254 is more than 0.5 μm.
As described above, in fig. 7, the resistor 240 is shown to have a length L3, where the length L3 is the distance between the vias on two sides corresponding to the resistor, i.e., the vias on two sides define the length L3 of the resistor 240. Accordingly, resistor 240 has a width W3.
Wherein the minimum distance of the via to the edge of the length L3 may typically be 0.4 μm.
When the implantation is performed, a normal implantation range is shown by a dashed box (not shown) in fig. 7, that is, a region slightly larger than the regions surrounded by the first mask layer 251, the second mask layer 252, the third mask layer 253, and the fourth mask layer 254. This ensures that a full implant is ensured during implantation. The distance of the dashed box to the inside of each mask layer may be about 0.5 μm.
The resistor is manufactured by adopting the structure shown in fig. 7, the area where the whole resistor 240 is located is surrounded by the first mask layer 251, the second mask layer 252, the third mask layer 253 and the fourth mask layer 254, and the width W3 of the resistor 240 is defined by the first mask layer 251 and the second mask layer 252 (the length L3 of the resistor 240 is defined by the position of the via hole and is not defined by each mask layer), so that high-precision injection of the resistor is realized, the design deviation of the resistor width is reduced, and the influence of the beak effect in the conventional structure is eliminated.
Further, since the resistor width boundaries are defined by mask layers of polysilicon material, which may be fabricated together with other polysilicon structure layers, it is possible to make the resistor width uniform with the width dimension of the layout design, and to eliminate adverse effects of various process steps (e.g., oxide layer removal step, sacrificial oxidation step, gate oxidation step, etc.) on the resistor width.
Another embodiment of the present invention provides another method for forming a resistor, please refer to fig. 9 to 10.
A field oxide layer 330 is formed on the semiconductor substrate 300 (as shown in fig. 9), the field oxide layer 330 isolating a first active region (not labeled). This process may include depositing a pad oxide layer (not shown) on the semiconductor substrate 300, followed by forming a hard mask layer (not shown). Under the protection of the hard mask layer, a field oxide layer 330 is grown, the field oxide layer 330 defining the location of the first active region (not labeled). Note that in fig. 9, the field oxide layer 330 and the pad oxide layer are not shown differently, and reference is made to the corresponding contents of the foregoing embodiments.
In this embodiment, the first active region provides a region for forming a resistor later, or the first active region is used for forming a corresponding resistor.
Referring to fig. 9, a first mask layer 351 is formed over a first side of the first active region width, and a second mask layer 352 is formed over a second side of the first active region width. The process comprises the steps of removing the hard mask layer, forming a corresponding mask material layer after removing the hard mask layer, and etching the mask material layer to form each mask layer.
In this embodiment, the method designs the distance W4 between the first mask layer 351 and the second mask layer 352 to be equal to the width of the resistor.
In this embodiment, after the first mask layer 351 and the second mask layer 352 are formed, the first active region is resistance doped to form the resistor 340 by using the first mask layer 351 and the second mask layer 352 as masks. As described above, the width W5 of the resistor 340 is equal to the distance W4 between the first mask layer 351 and the second mask layer 352.
Referring to fig. 10, which is a schematic top view of the corresponding structure of fig. 9, as can be seen from fig. 10, the forming method provided in this embodiment further includes forming a third mask layer 353 over a first side of the length of the first active region, and forming a fourth mask layer 354 over a second side of the length of the first active region, wherein a distance between the third mask layer 353 and the fourth mask layer 354 is greater than a length of the resistor 340, because the length of the resistor 340 is determined by vias (not labeled) located on both sides of the length, as shown in fig. 10, and is a length L5. In this embodiment, the first mask layer 351, the second mask layer 352, the third mask layer 353 and the fourth mask layer 354 are integrally connected, and the whole is a mask layer connected end to end, but in fig. 10, the edges of the mask layers are not shown in a dividing manner, but it is understood that they respectively correspond to one side of the rectangular ring, and different dividing manners are possible.
Since the first mask layer 351 and the second mask layer 352 are used as masks, the first active region is doped with resistance to form the corresponding resistor 340, and at this time, the influence of the difference between the width of the hard mask layer and the width of the first active region has been eliminated, and the width W5 of the resistor 340 is directly determined by the distance W4 between the first mask layer 351 and the second mask layer 352, so that the accuracy of the resistor width can be improved.
In other embodiments, the forming method may include forming a third mask layer only over the first side of the length of the first active region, i.e., without a fourth mask layer.
In this embodiment, the first mask layer 351 is formed of polysilicon, and the second mask layer 352 is formed of polysilicon.
In this embodiment, when the gate of the transistor is formed using polysilicon on the second active region, the first mask and the second mask layer 352 are formed simultaneously. The second active region is any other active region except the first active region on the semiconductor substrate 300, and is an active region for fabricating a corresponding transistor structure. When manufacturing a MOS transistor, the manufacturing of a gate is usually involved, and the gate may be made of a polysilicon material, so that such a process step may be utilized to simultaneously form each mask layer, thereby saving the process step.
In this embodiment, the first mask layer 351 is partially formed directly over the first active region, i.e., a portion of the first mask layer 351 is already located directly over the field oxide layer 330. Likewise, a second mask layer 352 is formed partially over the first active region, i.e., a portion of the second mask layer 352 is already located directly over the field oxide layer 330.
The method provided in this embodiment uses the first mask layer 351 and the second mask layer 352 to define the resistor width, so as to eliminate the influence of the bird's beak effect, and thus the design width of the resistor is equal to the final actual width.
The above-described forming process further includes providing a semiconductor structure for forming a resistor, as shown in fig. 9 and 10.
The semiconductor structure for forming the resistor comprises a field oxide layer 330 on the semiconductor substrate 300, wherein the field oxide layer 330 isolates the first active region, a first mask layer 351 is arranged above a first side of the width of the first active region, a second mask layer 352 is arranged above a second side of the width of the first active region, and the distance between the first mask layer 351 and the second mask layer 352 is equal to the width of the resistor.
The semiconductor structure for forming a resistor further includes both a third mask layer 353 over the first active region length first side and a fourth mask layer 354 over the first active region length second side, a distance between the third mask layer 353 and the fourth mask layer 354 being greater than a length L5 of the resistor 340.
In this embodiment, the first mask layer 351 is a polysilicon layer, and the second mask layer 352 is a polysilicon layer.
In this embodiment, the first mask layer 351 is partially located directly above the first active region, the first mask layer 351 is partially located directly above the field oxide layer 330, the second mask layer 352 is partially located directly above the first active region, and the second mask layer 352 is partially located directly above the oxide layer 330.
In this embodiment, the direction in which the width of the first mask layer 351 is located is parallel to the direction in which the width of the first active region is located; the width of the second mask layer 352 is parallel to the width of the first active region. The width direction of the third mask layer 353 is perpendicular to the width direction of the first active region; the width of the fourth mask layer 354 is perpendicular to the width of the first active area. In fig. 9, the width of the first mask layer 351 is not equal to the width of the third mask layer 353, and the width of the second mask layer 352 is not equal to the width of the fourth mask layer 354.
As described above, in fig. 9, the resistor 340 is shown to have a length L5, where the length L5 is the spacing between the vias on two sides corresponding to the resistor 340, i.e., the vias on two sides define the length L5 of the resistor 340. Accordingly, resistor 340 has a width W5.
The resistor is manufactured by adopting the structure shown in fig. 9, the area where the whole resistor 340 is located is defined by using the first mask layer 351, the second mask layer 352, the third mask layer 353 and the fourth mask layer 354, and the width W5 of the resistor 340 is defined by using the first mask layer 351 and the second mask layer 352 (the length L5 of the resistor 340 is defined by the position of the via hole and is not defined by each mask layer), so that high-precision injection of the resistor is realized, design deviation of the resistor width is reduced, and the influence of bird's beak effect in the conventional structure is eliminated.
Another embodiment of the present invention provides another method for forming a resistor, please refer to fig. 11-12.
A field oxide layer 430 is formed on the semiconductor substrate 400 (as shown in fig. 11), the field oxide layer 430 isolating a first active region (not labeled). This process may include depositing a pad oxide layer (not shown) on the semiconductor substrate 400, followed by forming a hard mask layer (not shown). Under the protection of the hard mask layer, a field oxide layer 430 is grown, the field oxide layer 430 defining the location of the first active region (not labeled). Note that in fig. 11, the field oxide layer 430 and the pad oxide layer are not shown differently, and reference is made to the corresponding contents of the foregoing embodiments.
In this embodiment, the first active region provides a region for forming a resistor later, or the first active region is used for forming a corresponding resistor.
Referring to fig. 11, a first mask layer 451 is formed over a first side of the first active region width, and a second mask layer 452 is formed over a second side of the first active region width. The process comprises the steps of removing the hard mask layer, forming a corresponding mask material layer after removing the hard mask layer, and etching the mask material layer to form each mask layer.
In this embodiment, the method designs the distance W6 between the first mask layer 451 and the second mask layer 452 to be equal to the width of the resistor.
In this embodiment, after the first mask layer 451 and the second mask layer 452 are formed, the first active region is resistance doped to form the resistor 440 by using the first mask layer 451 and the second mask layer 452 as masks. As described above, the width W7 of the resistor 440 is equal to the distance W6 between the first mask layer 451 and the second mask layer 452.
Referring to fig. 12, a schematic top view of the corresponding structure of fig. 11 is shown, wherein the length of the resistor 440 is determined by vias (not labeled) located on both sides of the length, as shown in fig. 12, which is the length L7. Also, in this embodiment, only the first mask layer 451 and the second mask layer 452 are located above the two sides of the width of the first active region, respectively.
Since the first mask layer 451 and the second mask layer 452 are used as masks to perform resistance doping on the first active region to form the corresponding resistor 440, at this time, the influence of the difference between the width of the hard mask layer and the width of the first active region has been eliminated, and the width W7 of the resistor is directly determined by the distance W6 between the first mask layer 451 and the second mask layer 452, so that the accuracy of the resistor width can be improved.
In this embodiment, the first mask layer 451 is formed of polysilicon, and the second mask layer 452 is formed of polysilicon.
In this embodiment, when the gate of the transistor is formed on the second active region by using polysilicon, the first mask and the second mask layer 452 are formed simultaneously. The second active region is any other active region except the first active region on the semiconductor substrate 400, and is an active region for fabricating a corresponding transistor structure. When manufacturing a MOS transistor, the manufacturing of a gate is usually involved, and the gate may be made of a polysilicon material, so that such a process step may be utilized to simultaneously form each mask layer, thereby saving the process step.
In this embodiment, the first mask layer 451 is formed just above the first active region, and the outer edge of the first mask layer 451 is already adjacent to the field oxide layer 430. Likewise, the second mask layer 452 is formed just entirely over the first active region.
The method provided in this embodiment uses the first mask layer 451 and the second mask layer 452 to define the resistor width, so as to eliminate the influence of the bird's beak effect, and thus make the design width of the resistor equal to the final actual width.
The above-described forming process further includes providing a semiconductor structure for forming a resistor, as shown in fig. 11 and 12.
The semiconductor structure for forming the resistor comprises a field oxide layer 430 on the semiconductor substrate 400, wherein the field oxide layer 430 isolates the first active region, a first mask layer 451 positioned above a first side of the width of the first active region, a second mask layer 452 positioned above a second side of the width of the first active region, and a distance between the first mask layer 451 and the second mask layer 452 is equal to the width of the resistor.
In this embodiment, the first mask layer 451 is a polysilicon layer, and the second mask layer 452 is a polysilicon layer.
In this embodiment, the first mask layer 451 is located right above the first active region, and the second mask layer 452 is located right above the first active region. In other embodiments, one portion of the first mask layer and the second mask layer may be located on the field oxide layer.
In this embodiment, the width direction of the first mask layer 451 is parallel to the width direction of the first active region; the width of the second mask layer 452 is parallel to the width of the first active region. The width of the first mask layer 451 and the width of the second mask layer 452 may not be equal.
As described above, in fig. 11, the resistor 440 is shown to have a length L7, where the length L7 is the distance between the vias on two sides corresponding to the resistor 440, i.e., the vias on two sides define the length L7 of the resistor 440. Accordingly, resistor 440 has a width W7.
The resistor is manufactured by adopting the structure shown in fig. 11, the boundaries of the first mask layer 451, the second mask layer 452 and the active region together define the area where the whole resistor 440 is located, and the width W7 of the resistor 440 is defined by the first mask layer 451 and the second mask layer 452 (the length L7 of the resistor 440 is defined by the position of the via hole and is not defined by each mask layer), so that high-precision injection of the resistor is realized, design deviation of the resistor width is reduced, and the influence of bird's beak effect in the conventional structure is eliminated.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (7)
1. A semiconductor structure for forming a resistor, comprising:
the field oxide layer is positioned on the semiconductor substrate and isolates the first active region;
a first mask layer over a first side of the first active region width;
a second mask layer located over a second side of the first active region width;
The distance between the first mask layer and the second mask layer is equal to the width of the resistor;
the third mask layer is positioned above the first side of the first active area length;
Or further comprising a third mask layer positioned above a first side of the first active area length and a fourth mask layer positioned above a second side of the first active area length, wherein the distance between the third mask layer and the fourth mask layer is greater than the length of the resistor;
The width direction of the first mask layer is parallel to the width direction of the first active region, and the width of the first mask layer is more than 0.5 mu m; the width direction of the second mask layer is parallel to the width direction of the first active region, and the width of the second mask layer is more than 0.5 mu m;
The width direction of the third mask layer is perpendicular to the width direction of the first active region, and the width of the third mask layer is more than 0.5 mu m; the width direction of the fourth mask layer is perpendicular to the width direction of the first active region, and the width of the fourth mask layer is more than 0.5 mu m.
2. The semiconductor structure of claim 1, wherein the first mask layer is a polysilicon layer and the second mask layer is a polysilicon layer.
3. The semiconductor structure of claim 1, wherein the first mask layer is entirely located directly above the first active region or the first mask layer is partially located directly above the field oxide layer; the second mask layer is entirely located right above the first active region, or the second mask layer is partially located right above the field oxide layer.
4. A method of forming a resistor, comprising:
forming a field oxide layer on a semiconductor substrate, wherein the field oxide layer isolates a first active region;
Forming a first mask layer over a first side of the first active region width;
forming a second mask layer over the first active region width second side;
The distance between the first mask layer and the second mask layer is equal to the width of the resistor;
Performing resistance doping on the first active region by taking the first mask layer and the second mask layer as masks;
Further comprising forming a third mask layer over the first active region length first side;
Or further comprising forming a third mask layer over a first side of the first active region length while forming a fourth mask layer over a second side of the first active region length, a distance between the third mask layer and the fourth mask layer being greater than a length of the resistor;
The width direction of the formed first mask layer is parallel to the width direction of the first active region, and the width of the first mask layer is more than 0.5 mu m; the width direction of the formed second mask layer is parallel to the width direction of the first active region, and the width of the second mask layer is more than 0.5 mu m;
The width direction of the formed third mask layer is perpendicular to the width direction of the first active region, and the width of the third mask layer is more than 0.5 mu m; the width direction of the fourth mask layer is perpendicular to the width direction of the first active region, and the width of the fourth mask layer is more than 0.5 mu m.
5. The method of claim 4, wherein the first mask layer is formed of polysilicon and the second mask layer is formed of polysilicon.
6. The method of claim 5, wherein the first mask and the second mask layer are formed simultaneously when polysilicon is used to form a gate of a transistor over the second active region.
7. The method of claim 4, wherein the first mask layer is entirely formed directly over the first active region or the first mask layer is partially formed directly over the field oxide layer; the second mask layer is formed entirely over the first active region or partially over the field oxide layer.
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| US5149669A (en) * | 1987-03-06 | 1992-09-22 | Seiko Instruments Inc. | Method of forming an isolation region in a semiconductor device |
| CN103633089A (en) * | 2012-08-20 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | A polycrystalline silicon resistor and a manufacturing method thereof |
| CN106158936A (en) * | 2015-04-16 | 2016-11-23 | 北大方正集团有限公司 | The preparation method of bipolar transistor and bipolar transistor |
| CN208706683U (en) * | 2018-08-01 | 2019-04-05 | 深圳元顺微电子技术有限公司 | It is used to form the semiconductor structure of resistance |
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|---|---|---|---|---|
| US5149669A (en) * | 1987-03-06 | 1992-09-22 | Seiko Instruments Inc. | Method of forming an isolation region in a semiconductor device |
| CN103633089A (en) * | 2012-08-20 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | A polycrystalline silicon resistor and a manufacturing method thereof |
| CN106158936A (en) * | 2015-04-16 | 2016-11-23 | 北大方正集团有限公司 | The preparation method of bipolar transistor and bipolar transistor |
| CN208706683U (en) * | 2018-08-01 | 2019-04-05 | 深圳元顺微电子技术有限公司 | It is used to form the semiconductor structure of resistance |
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