CN103633089A - A polycrystalline silicon resistor and a manufacturing method thereof - Google Patents
A polycrystalline silicon resistor and a manufacturing method thereof Download PDFInfo
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- CN103633089A CN103633089A CN201210297949.3A CN201210297949A CN103633089A CN 103633089 A CN103633089 A CN 103633089A CN 201210297949 A CN201210297949 A CN 201210297949A CN 103633089 A CN103633089 A CN 103633089A
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Abstract
The invention discloses a polycrystalline silicon resistor. A field oxide layer forms on a silicon substrate. The polycrystalline silicon resistor is arranged on the field oxide layer of a drain terminal of an LDMOS device. In a width direction, a first resistor electrode and a second resistor electrode respectively form at the two ends of the polycrystalline silicon resistor. A first drain terminal electrode and a second drain terminal electrode respectively form on positions of a same width at the two ends of a drain region. In a usage process, same voltages are applied to the first drain terminal electrode and the first resistor electrode, and the same voltages are applied to the second drain terminal electrode and the second resistor electrode. The invention also discloses the manufacturing method of the polycrystalline silicon resistor. According to the invention, a working voltage of the polycrystalline silicon resistor can be raised, and the polycrystalline silicon resistor can work at a bias voltage of 700V or to more than 700V.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of polysilicon resistance.The invention still further relates to a kind of manufacture method of polysilicon resistance.
Background technology
As shown in Figure 1, be the structural representation of existing polysilicon resistance, the structure of existing polysilicon resistance comprises: substrate 101; Well region 102, is formed on substrate 101, can be P type well region or N-type well region; Local field oxide layer (LOCOS) 103, for isolating active area on substrate 101; Polysilicon resistance 104, is formed at the top of described local field oxide layer 103.Existing polysilicon resistance is generally applied to the occasion that operating voltage is lower, when operating voltage is lower, the thickness of local field oxide layer 103 can hold the poor of the voltage can stood on polysilicon resistance 104 and the voltage in the well region 102 under local field oxide 103 completely.If but when existing polysilicon resistance is applied to the higher occasion of operating voltage, local field oxide layer 103 can be breakdown, suppose that the needed operating voltage of polysilicon resistance 104 is 700V, and when the breakdown electric field of local field oxide layer 103 is 1E6V/cm, the thickness of required local field oxide layer 103 is at least 7 μ m, and so the local field oxide layer 103 of thickness is can not be getable.The operating voltage of existing polysilicon resistance is to reach more than 700V high pressure.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of polysilicon resistance, can improve the operating voltage of polysilicon resistance, make polysilicon resistance can be more than 700V or-more than 700V under the bias voltage of (more than absolute value), work.For this reason, the present invention also provides a kind of manufacture method of polysilicon resistance.
For solving the problems of the technologies described above, the invention provides a kind of polysilicon resistance, on silicon substrate, be formed with field oxide, polysilicon resistance is arranged on LDMOS(Laterally Diffused Metal Oxide Semiconductor) on the field oxide of the drain terminal of device, direction from the source region of described LDMOS device to drain region is length direction, and with described surface of silicon parallel direction vertical with this length direction is Width, on Width, the two ends of described polysilicon resistance are formed with respectively the first resistance electrode and the second resistance electrode, the two ends in described drain region are formed with respectively the first drain terminal electrode and the second drain terminal electrode, described the first drain terminal electrode and described the first resistance electrode are positioned on the line of same length direction, described the second drain terminal electrode and described the second resistance electrode are positioned on the line of same length direction, described drain region is not connected with described polysilicon resistance, in use, described the first drain terminal electrode is identical with the added voltage of described the first resistance electrode, described the second drain terminal electrode is identical with the added voltage of described the second resistance electrode, and on the source electrode of described LDMOS device, grid, channel region extraction electrode and silicon substrate electrode, institute's making alive is zero.
Further improving is that described LDMOS device comprises:
Channel region, is comprised of the second conduction type well region.
Drift region, is comprised of the first conduction type well region, and described drift region and described channel region are adjacent in a lateral direction.
Described source region is comprised of the heavily doped region that is formed at the first conduction type in described channel region.
Described drain region is comprised of the heavily doped region that is formed at the first conduction type in described drift region; Described drain region and the described channel region segment distance of being separated by, the field oxide that makes drain terminal is the first field oxide, described the first field oxide is between described drain region and described channel region, one side autoregistration of described drain region and described the first field oxide, the opposite side of described the first field oxide and the described channel region segment distance of being separated by.
The draw-out area of channel region, is comprised of the heavily doped region that is formed at the second conduction type in described channel region.
Grid polycrystalline silicon, be formed at the surface of silicon top of described channel region, one side autoregistration of described source region and described grid polycrystalline silicon, the opposite side of described grid polycrystalline silicon extends to described the first field oxide top, and the above grid polycrystalline silicon of the direction from described source region to described drain region covers described channel region, the described drift region described the first field oxide and described channel region and described the first field oxide of part successively; Between the described channel region of described grid polycrystalline silicon and its covering and described drift region, isolation has gate oxide.
The second conduction type top layer, is formed in described drift region and the lower surface of close described the first field oxide.
Described polysilicon resistance and described grid polycrystalline silicon are formed by same layer etching polysilicon, described polysilicon resistance and the described grid polycrystalline silicon segment distance of being separated by.
Further improve and be, described LDMOS device is N-type LDMOS device, described the first conduction type is N-type, described the second conduction type is P type, described the second conduction type well region is that P type well region, described the first conduction type well region are N-type well region, and described the second conduction type top layer is P type top layer; Or, described LDMO
S device is P type LDMOS device, described the first conduction type is P type, described the second conduction type is N-type, and described the second conduction type well region is that N-type well region, described the first conduction type well region are P type well region, and described the second conduction type top layer is N-type top layer.
For solving the problems of the technologies described above, the manufacture method of polysilicon resistance provided by the invention comprises the steps:
On silicon substrate, form LDMOS device.
On the field oxide of the drain terminal of described LDMOS device, form polysilicon resistance.
From the source region of described LDMOS device to the direction in drain region, be that length direction and with described surface of silicon parallel direction vertical with this length direction is Width; Two ends on the Width of described polysilicon resistance form respectively the first resistance electrode and the second resistance electrode, two ends on the Width in described drain region form respectively the first drain terminal electrode and the second drain terminal electrode, and described the first drain terminal electrode and described the first resistance electrode are positioned on the line of same length direction, described the second drain terminal electrode and described the second resistance electrode are positioned on the line of same length direction.
Further improving is that the step that forms described LDMOS device is:
Step 5, at positive gate oxide, the depositing polysilicon layer on described gate oxide of forming of described silicon substrate.
Step 6, described polysilicon is carried out to chemical wet etching form grid polycrystalline silicon and described polysilicon resistance simultaneously, described polysilicon resistance and the described grid polycrystalline silicon segment distance of being separated by; Described grid polycrystalline silicon is positioned at the surface of silicon top of described channel region, one side autoregistration of described source region and described grid polycrystalline silicon, the opposite side of described grid polycrystalline silicon extends to described the first field oxide top, and the above grid polycrystalline silicon of the direction from described source region to described drain region covers described channel region, the described drift region described the first field oxide and described channel region and described the first field oxide of part successively.
Step 7, carry out the heavily doped region that the first conduction type be infused in described channel region and form in described drift region is leaked in the source of the first conduction type, described source region is comprised of the heavily doped region that is formed at the first conduction type in described channel region; Described drain region is comprised of the heavily doped region that is formed at the first conduction type in described drift region; One side autoregistration of described source region and described grid polycrystalline silicon, a side autoregistration of described drain region and described the first field oxide.
Step 8, the heavy doping ion of carrying out the second conduction type are infused in the draw-out area that forms channel region in described channel region.
Further improve and be, described LDMOS device is N-type LDMOS device, described the first conduction type is N-type, described the second conduction type is P type, described the second conduction type well region is that P type well region, described the first conduction type well region are N-type well region, and described the second conduction type top layer is P type top layer.
Further improve and be, the well region of N-type described in step 1 is increased temperature and is pushed away trap and form by Implantation, and the implanted dopant of the Implantation of described N-type well region is that phosphorus, Implantation Energy are that 100keV～300keV, implantation dosage are 10
11cm
-2～10
14cm
-2, the temperature that the high temperature of described N-type well region pushes away trap is that 1000 ℃～1200 ℃, time are 100 minutes～500 minutes; Described P type well region in step 3 is formed in described N-type well region by Implantation, and the implanted dopant of the Implantation of described P type well region is that boron, Implantation Energy are that 0keV～2000keV, implantation dosage are 10
11cm
-2～10
15cm
-2, to inject number of times be that one or many injects.
Further improving is that the implanted dopant of the Implantation of the described P type top layer in step 4 is that boron, Implantation Energy are that 100keV～2000keV, implantation dosage are 10
11cm
-2～10
15cm
-2.
Further improve is that the implanted dopant phosphorus that the described source leakage of step 7 is injected or arsenic, Implantation Energy are that 0keV～200keV, implantation dosage are 10
13cm
-2～10
16cm
-2, to inject number of times be that single or multiple injects;
The implanted dopant boron of the Implantation of the draw-out area of described channel region, Implantation Energy are that 0keV～200keV, implantation dosage are 10
13cm
-2～10
16cm
-2, to inject number of times be that single or multiple injects.
Further improve and be, described LDMOS device is P type LDMOS device, described the first conduction type is P type, described the second conduction type is N-type, described the second conduction type well region is that N-type well region, described the first conduction type well region are P type well region, and described the second conduction type top layer is N-type top layer.
The present invention is by being arranged on polysilicon resistance on the field oxide of drain terminal of LDMOS device, and in use, in the voltage that the first resistance electrode of polysilicon resistance and the second resistance electrode are added, at the first drain terminal electrode in drain region and the second drain terminal electrode, also add corresponding voltage identical, and the source electrode of LDMOS device, grid, on channel region extraction electrode and silicon substrate electrode, institute's making alive is zero, when the first drain terminal electrode or the added voltage of the second drain terminal electrode are increased to 700V(corresponding to N-type LDMOS device gradually from 0V) time, or when the first drain terminal electrode or the added voltage of the second drain terminal electrode from 0V increase gradually (increase of absolute value) to-700V(corresponding to P type LDMOS device) time, in drift region, can form Qie Gai depletion region, depletion region can be along with the increase of the voltage of drain terminal electrode broadening gradually.
When the voltage of the first drain terminal electrode or the second drain terminal electrode is lower, when depletion region does not have under field oxide that broadening covers to polysilicon resistance, polysilicon resistance is identical with the current potential in silicon under its field oxide, as identical with the first drain terminal electrode in current potential in the silicon under the field oxide of the first resistance electrode below, therefore in the silicon under the field oxide of the first resistance electrode below, current potential is also just identical with the polysilicon resistance current potential at the first resistance electrode place, so now field oxide does not bear voltage.
When the voltage of the first drain terminal electrode or the second drain terminal electrode higher, in the time of under the field oxide that depletion region broadening covers to polysilicon resistance, because a part of drain terminal electrode institute making alive can be shared in depletion region, so have potential difference between the silicon depletion region under the field oxide of polysilicon resistance and drain terminal electrode, therefore also have identical potential difference between the silicon depletion region under the field oxide of polysilicon resistance and polysilicon resistance, this potential difference is that polysilicon resistance is to the width of formed silicon depletion region between the lateral separation in drain region, the Breadth Maximum of this depletion region is also that polysilicon resistance is to the lateral separation in drain region, relatively more close drain region due to polysilicon resistance setting, therefore therefore the potential difference in the silicon under polysilicon resistance and its field oxide covering can be very not large, general thickness as the field oxide of 4000 dusts be can be proof.Therefore,, as long as institute's making alive is lower than the puncture voltage of this LDMOS on drain region and polysilicon resistance, polysilicon resistance of the present invention just can work.So, on Width, drain region and polysilicon resistance can be taken as 0V to 700V(corresponding to N-type LDMOS device) or 0V to-700V(corresponding to P type LDMOS device) between any value.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of existing polysilicon resistance;
Fig. 2 is the structural representation of embodiment of the present invention polysilicon resistance;
Fig. 3 is the voltage-current curve figure of embodiment of the present invention polysilicon resistance;
Fig. 4 A-Fig. 4 D is the device architecture schematic diagram in each step of manufacture method of embodiment of the present invention polysilicon resistance.
Embodiment
As shown in Figure 2, be the structural representation of embodiment of the present invention polysilicon resistance.Embodiment of the present invention polysilicon resistance, the LDMOS device adopting in embodiment of the present invention polysilicon resistance be take N-type LDMOS device and is described as example, and embodiment of the present invention polysilicon resistance comprises:
One P type silicon substrate 1 is formed with N-type well region 2 on described silicon substrate 1, is also formed with field oxide 3 on silicon substrate 1.Described N-type well region 2 is by Implantation, to be increased temperature and pushed away trap and form before forming described field oxide 3, and the implanted dopant of the Implantation of described N-type well region 2 is that phosphorus, Implantation Energy are that 100keV～300keV, implantation dosage are 10
11cm
-2～10
14cm
-2, the temperature that the high temperature of described N-type well region 2 pushes away trap is that 1000 ℃～1200 ℃, time are 100 minutes～500 minutes.Described field oxide 3 is local field oxide layer (LOCOS), and thickness is 4000 dust～8000 dusts.
On described P type silicon substrate 1, be formed with LDMOS device, described LDMOS device comprises:
Drift region, is comprised of N-type well region 2, and described drift region and described channel region 4 are adjacent in a lateral direction.
Source region 8, is comprised of the JiN+ district, heavily doped region that is formed at the N-type in described channel region 4.
Drain region 9, is comprised of the JiN+ district, heavily doped region that is formed at the N-type in described drift region.Described source region 8 and 9 N+ districts, described drain region leak to inject simultaneously by source to form, described source is leaked and injected is after follow-up grid polycrystalline silicon 6 forms, utilize grid polycrystalline silicon 6 and field oxide 3 to do that hardmask injects, the implanted dopant phosphorus that injects or arsenic are leaked in described source, Implantation Energy is that 0keV～200keV, implantation dosage are 10
13cm
-2～10
16cm
-2, to inject number of times be that single or multiple injects.
Described drain region 9 and described channel region 4 segment distance of being separated by, the field oxide 3 that makes drain terminal is the first field oxide 3, described the first field oxide 3 is between described drain region 9 and described channel region 4, one side autoregistration of described drain region 9 and described the first field oxide 3, the opposite side of described the first field oxide 3 and described channel region 4 segment distance of being separated by.
The draw-out area 10 of channel region, is comprised of the JiP+ district, heavily doped region that is formed at the P type in described channel region 4.Forming by Implantation of the draw-out area 10 of described channel region, the implanted dopant boron of this Implantation, Implantation Energy are that 0keV～200keV, implantation dosage are 10
13cm
-2～10
16cm
-2, to inject number of times be that single or multiple injects.
Grid polycrystalline silicon 6, be formed at silicon substrate 1 surface of described channel region 4, one side autoregistration of described source region 8 and described grid polycrystalline silicon 6, the opposite side of described grid polycrystalline silicon 6 extends to described the first field oxide 3 tops, and the above grid polycrystalline silicon 6 of the direction from described source region 8 to described drain region 9 covers described channel region 4, the described drift region described the first field oxide 3 and described channel region 4 and described the first field oxide 3 of part successively; Between the described channel region 4 of described grid polycrystalline silicon 6 and its covering and described drift region, isolation has gate oxide.
P type top layer 5, is formed in described drift region and the lower surface of close described the first field oxide 3.Described P type top layer after N-type well region 2 and P type well region form, gate oxide forms by Implantation before forming, the implanted dopant of the Implantation of described P type top layer is that boron, Implantation Energy are that 100keV～2000keV, implantation dosage are 10
11cm
-2～10
15cm
-2.Described P type top layer 5 is also formed in the described drift region and described channel region 4 outside described the first field oxide 3 simultaneously, owing to there is no stopping of described the first field oxide 3, the degree of depth that the described drift region of described P type top layer 5 outside described the first field oxide 3 and the degree of depth in described channel region 4 are less than the described P type top layer 5 that is positioned at described the first field oxide 3 bottoms.
Polysilicon resistance 7, be formed on the field oxide 3 of drain terminal of LDMOS device, described polysilicon resistance 7 and described grid polycrystalline silicon 6 are formed by same layer etching polysilicon, described polysilicon resistance 7 and described grid polycrystalline silicon 6 segment distance of being separated by, by adulterating and can regulate the resistance value of described polysilicon resistance described polysilicon resistance 7.From the source region 8 of described LDMOS device to drain region, 9 direction is length direction, vertical with this length direction and and the surperficial parallel direction of described silicon substrate 1 be Width, on Width, the two ends of described polysilicon resistance 7 are formed with respectively the first resistance electrode 7a and the second resistance electrode 7b, the two ends in described drain region 9 are formed with respectively the first drain terminal electrode 9a and the second drain terminal electrode 9b, described the first drain terminal electrode 9a and described the first resistance electrode 7a are positioned on the line of same length direction, described the second drain terminal electrode 9b and described the second resistance electrode 7b are positioned on the line of same length direction, described drain region 9 is not connected with described polysilicon resistance 7.Described the first resistance electrode 7a, the second resistance electrode 7b, described the second drain terminal electrode 9b and described the second resistance electrode 7b draw by metal contact hole.On described source region 8, by metal contact hole, draw source electrode, on the draw-out area 10 of described channel region, by metal contact hole, draw channel region extraction electrode, on described grid polycrystalline silicon 6, by metal contact hole, draw grid, described P type silicon substrate 1 is also connected with silicon substrate electrode.In use, described the first drain terminal electrode 9a is identical with the added voltage of described the first resistance electrode 7a, described the second drain terminal electrode 9b is identical with the added voltage of described the second resistance electrode 7b, and on described source electrode, described grid, described channel region extraction electrode and described silicon substrate electrode, institute's making alive is zero.
The embodiment of the present invention is by being arranged on polysilicon resistance 7 on the field oxide of drain terminal of N-type LDMOS device, and in use, in the voltage that the first resistance electrode 7a of polysilicon resistance 7 and the second resistance electrode 7b are added, in drain region, also to add corresponding voltage identical for the first drain terminal electrode 9a of 9 and the second drain terminal electrode 9b, and the source electrode of N-type LDMOS device, grid, on channel region extraction electrode and silicon substrate electrode, institute's making alive is zero, when the first drain terminal electrode 9a or the added voltage of the second drain terminal electrode 9b are increased to 700V gradually from 0V, in drift region, can form Qie Gai depletion region, depletion region can be along with the increase of the voltage of drain terminal electrode broadening gradually.
When the voltage of the first drain terminal electrode 9a or the second drain terminal electrode 9b is lower, when depletion region does not have under field oxide 3 that broadening covers to polysilicon resistance 7, polysilicon resistance 7 is identical with the current potential in silicon under its field oxide 3, as identical with the first drain terminal electrode 9a in current potential in the silicon under the field oxide 3 of the first resistance electrode 7a below, therefore in the silicon under the field oxide 3 of the first resistance electrode 7a below, current potential is also just identical with polysilicon resistance 7 current potentials at the first resistance electrode 7a place, so now field oxide 3 does not bear voltage.
When the voltage of the first drain terminal electrode 9a or the second drain terminal electrode 9b higher, in the time of under the field oxide 3 that depletion region broadening covers to polysilicon resistance 7, because a part of drain terminal electrode institute making alive can be shared in depletion region, so have potential difference between the silicon depletion region under the field oxide 3 of polysilicon resistance 7 and drain terminal electrode, wherein drain terminal electrode potential wants large, therefore also have identical potential difference between the silicon depletion region under the field oxide 3 of polysilicon resistance 7 and polysilicon resistance 7, this potential difference is that polysilicon resistance 7 is to the width of formed silicon depletion region between the lateral separation in drain region 9, the Breadth Maximum of this depletion region is also that polysilicon resistance 7 is to the lateral separation in drain region 9, relatively more close drain region 9 due to polysilicon resistance 7 settings, therefore therefore the potential difference in the silicon under polysilicon resistance 7 and its field oxide covering 3 can be very not large, general thickness as the field oxide 3 of 4000 dusts be can be proof.Therefore,, as long as institute's making alive is lower than the puncture voltage of this N-type LDMOS on drain region 9 and polysilicon resistance 7, polysilicon resistance 7 of the present invention just can work.So on Width, drain region and polysilicon resistance can be taken as 0V to any value between 700V.
In the embodiment of the present invention, more than the puncture voltage of LDMOS device can reach 700V, the voltage endurance capability of the drift region of LDMOS device is more than 700V, therefore more than the operating voltage of polysilicon resistance 7 also can reach 700V.As shown in Figure 3, be the polysilicon resistance of the embodiment of the present invention and the voltage-current curve figure between silicon substrate; Can find out on the longitudinal direction between polysilicon resistance and silicon substrate, only have operating voltage on polysilicon resistance to be greater than 800V when above, just there will be leakage current, therefore the operating voltage of the polysilicon resistance of the embodiment of the present invention is all right within above-mentioned withstand voltage, so the embodiment of the present invention can realize operating voltage, be polysilicon resistance more than 700V.
As shown in Fig. 4 A to Fig. 4 D, it is the device architecture schematic diagram in each step of manufacture method of embodiment of the present invention polysilicon resistance.The manufacture method of embodiment of the present invention polysilicon resistance comprises the steps:
Described P type top layer 5 is also formed in the described drift region and described channel region 4 outside described the first field oxide 3 simultaneously, owing to there is no stopping of described the first field oxide 3, the degree of depth that the described drift region of described P type top layer 5 outside described the first field oxide 3 and the degree of depth in described channel region 4 are less than the described P type top layer 5 that is positioned at described the first field oxide 3 bottoms.
Step 5, as shown in Figure 4 D, at positive gate oxide, the depositing polysilicon layer on described gate oxide of forming of described silicon substrate 1.
Step 6, as shown in Figure 4 D, carries out chemical wet etching to described polysilicon and forms grid polycrystalline silicon 6 and polysilicon resistance 7 simultaneously, described polysilicon resistance 7 and described grid polycrystalline silicon 6 segment distance of being separated by.
Described grid polycrystalline silicon 6 is positioned at silicon substrate 1 surface of described channel region 4, one side autoregistration of described source region 8 and described grid polycrystalline silicon 6, the opposite side of described grid polycrystalline silicon 6 extends to described the first field oxide 3 tops, and the above grid polycrystalline silicon 6 of the direction from described source region 8 to described drain region 9 covers described channel region 4, the described drift region described the first field oxide 3 and described channel region 4 and described the first field oxide 3 of part successively.
Described polysilicon resistance 7 is positioned on described the first field oxide 3, by described polysilicon resistance 7 is adulterated and can regulate the resistance value of described polysilicon resistance 7.
Step 7, as shown in Figure 4 D, the source of carrying out N-type leak be infused in described channel region 4 and described drift region in the heavily doped region of the N-type that forms, described source region 8 is comprised of the heavily doped region that is formed at the N-type in described channel region 4; Described drain region 9 is comprised of the heavily doped region that is formed at the N-type in described drift region;
Described source is leaked to inject and is utilized grid polycrystalline silicon 6 and field oxide 3 to do hardmask to inject, and the implanted dopant phosphorus that injects or arsenic are leaked in described source, Implantation Energy is that 0keV～200keV, implantation dosage are 10
13cm
-2～10
16cm
-2, to inject number of times be that single or multiple injects.Because described source is leaked and injected is to utilize grid polycrystalline silicon 6 and field oxide 3 to do hardmask, thus a side autoregistration of described source region 8 and described grid polycrystalline silicon 6, a side autoregistration of described drain region 9 and described the first field oxide 3.
Step 8, as shown in Figure 4 D, the heavy doping ion of carrying out P type is infused in the draw-out area 10 that forms channel region in described channel region 4.The implanted dopant boron of the Implantation of the draw-out area 10 of described channel region, Implantation Energy are that 0keV～200keV, implantation dosage are 10
13cm
-2～10
16cm
-2, to inject number of times be that single or multiple injects.
Finally do source electrode, the i.e. drain electrode of drain terminal electrode, grid, channel region extraction electrode and the silicon substrate electrode of the described N-type LDMOS device that metal contact hole draws.Source electrode and described source region 8 contact, and described grid and described grid polycrystalline silicon 6 contact, and the draw-out area 10 of described channel region extraction electrode and described channel region contacts, and silicon substrate electrode and described silicon substrate 1 contact.And the resistance electrode that forms described polysilicon resistance 7.
As shown in Figure 2, from the source region 8 of described N-type LDMOS device to drain region, 9 direction is that length direction is vertical with this length direction and be Width with the described silicon substrate 1 parallel direction in surface, on Width, described resistance electrode comprises the first resistance electrode 7a and the second resistance electrode 7b that is formed at respectively described polysilicon resistance 7 two ends, and described drain terminal electrode comprises the first drain terminal electrode 9a and the second drain terminal electrode 9b that is formed at 9 two ends, described drain region.Described the first drain terminal electrode 9a and described the first resistance electrode 7a are positioned on the line of same length direction, described the second drain terminal electrode 9b and described the second resistance electrode 7b are positioned on the line of same length direction, can find out, length between described the first resistance electrode 7a and described the second resistance electrode 7b equals the length between described the first drain terminal electrode 9a and described the second drain terminal electrode 9b, and described the first drain terminal electrode 9a is also identical with the position of described the second resistance electrode 7b with described the first resistance electrode 7a with described the second drain terminal electrode 9b residing position on Width.Described drain region 9 is not connected with described polysilicon resistance 7.In use, described the first drain terminal electrode 9a is identical with the added voltage of described the first resistance electrode 7a, and described the second drain terminal electrode 9b is identical with the added voltage of described the second resistance electrode 7b; On described source electrode, described grid, described channel region extraction electrode and described silicon substrate electrode, institute's making alive is zero.
In the embodiment of the present invention, be all to take N-type LDMOS device to describe as example, for P type LDMOS device, only need corresponding doped region to do corresponding conversion, as being that the doping type of N-type, drift region is P type by the doping type of channel region, the doping type of source-drain area is N-type, other structure and N-type LDMOS device are similar, and the embodiment of the present invention is not just described in detail P type LDMOS device.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. a polysilicon resistance, is characterized in that: on silicon substrate, be formed with field oxide, polysilicon resistance is arranged on the field oxide of drain terminal of LDMOS device, direction from the source region of described LDMOS device to drain region is length direction, and with described surface of silicon parallel direction vertical with this length direction is Width, on Width, the two ends of described polysilicon resistance are formed with respectively the first resistance electrode and the second resistance electrode, the two ends in described drain region are formed with respectively the first drain terminal electrode and the second drain terminal electrode, described the first drain terminal electrode and described the first resistance electrode are positioned on the line of same length direction, described the second drain terminal electrode and described the second resistance electrode are positioned on the line of same length direction, described drain region is not connected with described polysilicon resistance, in use, described the first drain terminal electrode is identical with the added voltage of described the first resistance electrode, described the second drain terminal electrode is identical with the added voltage of described the second resistance electrode, and on the source electrode of described LDMOS device, grid, channel region extraction electrode and silicon substrate electrode, institute's making alive is zero.
2. polysilicon resistance as claimed in claim 1, is characterized in that: described LDMOS device comprises:
Channel region, is comprised of the second conduction type well region;
Drift region, is comprised of the first conduction type well region, and described drift region and described channel region are adjacent in a lateral direction;
Described source region is comprised of the heavily doped region that is formed at the first conduction type in described channel region;
Described drain region is comprised of the heavily doped region that is formed at the first conduction type in described drift region; Described drain region and the described channel region segment distance of being separated by, the field oxide that makes drain terminal is the first field oxide, described the first field oxide is between described drain region and described channel region, one side autoregistration of described drain region and described the first field oxide, the opposite side of described the first field oxide and the described channel region segment distance of being separated by;
The draw-out area of channel region, is comprised of the heavily doped region that is formed at the second conduction type in described channel region;
Grid polycrystalline silicon, be formed at the surface of silicon top of described channel region, one side autoregistration of described source region and described grid polycrystalline silicon, the opposite side of described grid polycrystalline silicon extends to described the first field oxide top, and the above grid polycrystalline silicon of the direction from described source region to described drain region covers described channel region, the described drift region described the first field oxide and described channel region and described the first field oxide of part successively; Between the described channel region of described grid polycrystalline silicon and its covering and described drift region, isolation has gate oxide;
The second conduction type top layer, is formed in described drift region and the lower surface of close described the first field oxide;
Described polysilicon resistance and described grid polycrystalline silicon are formed by same layer etching polysilicon, described polysilicon resistance and the described grid polycrystalline silicon segment distance of being separated by.
3. polysilicon resistance as claimed in claim 2, it is characterized in that: described LDMOS device is N-type LDMOS device, described the first conduction type is N-type, described the second conduction type is P type, described the second conduction type well region is that P type well region, described the first conduction type well region are N-type well region, and described the second conduction type top layer is P type top layer;
Or, described LDMOS device is P type LDMOS device, described the first conduction type is P type, described the second conduction type is N-type, described the second conduction type well region is that N-type well region, described the first conduction type well region are P type well region, and described the second conduction type top layer is N-type top layer.
4. a manufacture method for polysilicon resistance, is characterized in that, comprises the steps:
On silicon substrate, form LDMOS device;
On the field oxide of the drain terminal of described LDMOS device, form polysilicon resistance;
From the source region of described LDMOS device to the direction in drain region, be that length direction and with described surface of silicon parallel direction vertical with this length direction is Width; Two ends on the Width of described polysilicon resistance form respectively the first resistance electrode and the second resistance electrode, two ends on the Width in described drain region form respectively the first drain terminal electrode and the second drain terminal electrode, and described the first drain terminal electrode and described the first resistance electrode are positioned on the line of same length direction, described the second drain terminal electrode and described the second resistance electrode are positioned on the line of same length direction.
5. method as claimed in claim 4, is characterized in that: the step that forms described LDMOS device is:
Step 1, on described silicon substrate, form the first conduction type well region, by described the first conduction type well region, form drift region;
Step 2, on silicon substrate, form field oxide;
Step 3, on described silicon substrate, form the second conduction type well region, by described the second conduction type well region, form channel region; Described drift region and described channel region are adjacent in a lateral direction; The field oxide that makes drain terminal is the first field oxide, and described the first field oxide is between described drain region and described channel region;
Step 4, by ion implantation technology, form the second conduction type top layer, described the second conduction type top layer is arranged in described drift region and near the lower surface of described the first field oxide;
Step 5, at positive gate oxide, the depositing polysilicon layer on described gate oxide of forming of described silicon substrate;
Step 6, described polysilicon is carried out to chemical wet etching form grid polycrystalline silicon and described polysilicon resistance simultaneously, described polysilicon resistance and the described grid polycrystalline silicon segment distance of being separated by; Described grid polycrystalline silicon is positioned at the surface of silicon top of described channel region, one side autoregistration of described source region and described grid polycrystalline silicon, the opposite side of described grid polycrystalline silicon extends to described the first field oxide top, and the above grid polycrystalline silicon of the direction from described source region to described drain region covers described channel region, the described drift region described the first field oxide and described channel region and described the first field oxide of part successively;
Step 7, carry out the heavily doped region that the first conduction type be infused in described channel region and form in described drift region is leaked in the source of the first conduction type, described source region is comprised of the heavily doped region that is formed at the first conduction type in described channel region; Described drain region is comprised of the heavily doped region that is formed at the first conduction type in described drift region; One side autoregistration of described source region and described grid polycrystalline silicon, a side autoregistration of described drain region and described the first field oxide;
Step 8, the heavy doping ion of carrying out the second conduction type are infused in the draw-out area that forms channel region in described channel region.
6. method as claimed in claim 5, it is characterized in that: described LDMOS device is N-type LDMOS device, described the first conduction type is N-type, described the second conduction type is P type, described the second conduction type well region is that P type well region, described the first conduction type well region are N-type well region, and described the second conduction type top layer is P type top layer.
7. method as claimed in claim 6, is characterized in that: the well region of N-type described in step 1 is increased temperature and pushed away trap and form by Implantation, and the implanted dopant of the Implantation of described N-type well region is that phosphorus, Implantation Energy are that 100keV～300keV, implantation dosage are 10
11cm
-2～10
14cm
-2, the temperature that the high temperature of described N-type well region pushes away trap is that 1000 ℃～1200 ℃, time are 100 minutes～500 minutes;
Described P type well region in step 3 is formed in described N-type well region by Implantation, and the implanted dopant of the Implantation of described P type well region is that boron, Implantation Energy are that 0keV～2000keV, implantation dosage are 10
11cm
-2～10
15cm
-2, to inject number of times be that one or many injects.
8. method as claimed in claim 6, is characterized in that: the implanted dopant of the Implantation of the described P type top layer in step 4 is that boron, Implantation Energy are that 100keV～2000keV, implantation dosage are 10
11cm
-2～10
15cm
-2.
9. method as claimed in claim 6, is characterized in that: the implanted dopant phosphorus that the described source leakage of step 7 is injected or arsenic, Implantation Energy are that 0keV～200keV, implantation dosage are 10
13cm
-2～10
16cm
-2, to inject number of times be that single or multiple injects;
The implanted dopant boron of the Implantation of the draw-out area of described channel region, Implantation Energy are that 0keV～200keV, implantation dosage are 10
13cm
-2～10
16cm
-2, to inject number of times be that single or multiple injects.
10. method as claimed in claim 5, it is characterized in that: described LDMOS device is P type LDMOS device, described the first conduction type is P type, described the second conduction type is N-type, described the second conduction type well region is that N-type well region, described the first conduction type well region are P type well region, and described the second conduction type top layer is N-type top layer.
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