JP2007081243A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of forming a drift region with good position controllability and securing breakdown voltage, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device includes: a gate electrode having a first region extending in a first horizontal direction and a second region extending in a second horizontal direction orthogonal to the first horizontal direction; first and second sidewall insulation films on both sidewalls of the gate electrode; a high resistance semiconductor region opposite to the gate electrode at position and in size to be incorporated in a plane figure of the gate electrode; a drift region extending from a position opposite to the gate electrode through a gate insulation film to a lower position of the first sidewall insulation film, with a length in the first horizontal direction opposite to the second region of the gate electrode longer than that in the second horizontal direction opposite to the first region of the gate electrode; a drain region adjacent to the drift region; a lightly doped source region extending from a position opposite to the gate electrode through the gate insulation film to a lower position of the second sidewall insulation film; and a source region adjacent to the low concentration source region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device suitable for application of a fine process and a manufacturing method thereof.

  In recent years, miniaturization has rapidly progressed in the field of LDMOS (lateral diffused MOSFET) as a semiconductor device, and application of a fine process such as a 0.35 μm rule and a 0.18 μm rule, which has been applied in CMOS, is increasing. In the fine process, it becomes more difficult to ensure the formation accuracy of each region due to mask misalignment or the like. Even if it cannot be ensured, it is usually manufactured so that there is no inconvenience by looking at the design margin.

In LDMOS, the drift region has the greatest influence on the breakdown voltage, and appropriate consideration is necessary for forming the region. As an example for this purpose, there is an LDMOS in which a side wall insulating film is formed in contact with a side wall of a gate electrode, and this side wall insulating film is used as a part of an impurity implantation mask to form a drift region with high positional accuracy ( For example, the following patent document 1).
JP 2004-288777 A

  It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can ensure a breakdown voltage by forming a drift region with good position controllability.

  A semiconductor device according to one embodiment of the present invention includes a first portion extending in the first horizontal direction and a second portion extending in the second horizontal direction perpendicular to the first horizontal direction from an end portion of the first portion. A gate insulating film positioned on the lower side in the vertical direction of the gate electrode, first and second side wall insulating films formed on both side walls of the gate electrode, and the gate electrode, respectively. A high-resistance semiconductor region that is opposed to the gate electrode through only the gate insulating film at a position and size included in the planar figure, and is adjacent to the high-resistance semiconductor region and the first of the gate electrode 1. The first portion extending from a position facing the second portion through the gate insulating film to a lower position of the first sidewall insulating film and facing the second portion of the gate electrode The horizontal length of 1 is the game A drift region that is longer than the second horizontal length facing the first portion of the electrode; a drain region adjacent to the drift region; the high resistance semiconductor region; and the gate electrode A lightly doped source region extending from a position facing the first and second parts through the gate insulating film to a lower position of the second sidewall insulating film, and a source region adjacent to the lightly doped source region It comprises.

  The method for manufacturing a semiconductor device according to one embodiment of the present invention includes a first part extending in the first horizontal direction on the high-resistance semiconductor region and the first horizontal direction from an end of the first part. Forming a laminated structure having a gate electrode having a second portion extending in the second horizontal direction perpendicular to the gate electrode and a gate insulating film positioned on the lower side in the vertical direction of the gate electrode; As a part of the mask, impurities are implanted substantially vertically into the high resistance semiconductor region located on one side of the gate electrode where the first and second portions are continuous. And forming the drift region, and using the mask, the impurity is implanted at an intentional angle so that the impurity is also implanted below the second portion of the gate electrode. Forming a second drift region continuous to the drift region A step of forming first and second sidewall insulating films on both side walls of the gate electrode, and a substantially vertical direction using the first and second sidewall insulating films as a part of another mask. And forming a drain region and a source region by implanting impurities.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can form a drift region with sufficient position control property, and can ensure a proof pressure, and its manufacturing method can be provided.

  As an embodiment of the semiconductor device according to the present invention, the length in the first horizontal direction of the second portion of the gate electrode is the length in the second horizontal direction of the first portion of the gate electrode. Longer than that.

  In one embodiment, the source region is the low-concentration source region and is located under the second sidewall insulating film from a position facing the second part of the gate electrode with the gate insulating film interposed therebetween. The low concentration source region extending to the side position may not be adjacent.

  As an embodiment, the drain region and the source region may be n-type.

  As an embodiment, the gate electrode may have two parts as the first and second parts, respectively, and may be ring-shaped as a whole.

  As an embodiment of the manufacturing method of the present invention, the gate electrode in the step of forming a laminated structure has the first horizontal length of the second portion as the first length of the gate electrode. Longer than the second horizontal length of the region.

  In one embodiment, the step of forming the drain region and the source region includes the step of forming the sidewall insulating film formed on the sidewall of the second portion of the sidewall insulating film formed on the sidewall of the gate electrode. May not be part of the mask for forming the source region.

  Further, as an embodiment, the gate electrode in the step of forming a stacked structure may have two portions as the first and second portions, respectively, and may be ring-shaped as a whole.

  As an embodiment, the intentional angle in the step of forming the second drift region may be 30 degrees or more with respect to the vertical direction.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic layout diagram virtually showing the upper surface of a semiconductor region of a semiconductor device (LDMOS) according to an embodiment of the present invention. 2 is a cross-sectional structure diagram schematically showing a cross-section in the direction of the arrow corresponding to the position A-Aa shown in FIG. 3 is a cross-sectional structure diagram schematically showing a cross-section in the direction of the arrow corresponding to the B-Ba position shown in FIG. 2 and 3 mainly show structures on the semiconductor region omitted in FIG. For example, a contact or a wiring is omitted as an omitted configuration as it is not the main one.

  As shown in these drawings, this LDMOS appears on the upper surface of the semiconductor region as an n-type drain region 10, a high-resistance p-type semiconductor region 20, an n-type source region 30, a p-type contact region 40, a p-type well. The semiconductor region further includes a buried p-type region 70 and a p-type semiconductor substrate 80 that are not exposed on the upper surface. On the upper surface of the semiconductor region, a gate electrode 60, a gate insulating film 105, sidewall insulating films 91 and 92, and an interlayer insulating film 100 are provided. The n-type drain region 10 includes a drift region 12 and an n-type drain region 11 excluding the drift region 12. The n-type source region 30 includes a low-concentration source region 32 and an n-type source region 31 excluding this.

  As shown in FIG. 1, the upper surface of the semiconductor region has an n-type drain region 11, a drift region 12, a high-resistance p-type semiconductor region 20, a low-concentration source region 32, an n-type source region 31, and a p-type contact region 40 from the inside. The p-type well region 50 is arranged. Except for the n-type source region 31 (and the innermost n-type drain region 11), each has a frame shape.

  As shown in FIG. 2, the n-type drain region 10 is positioned so that the drift region 12 slightly faces the gate electrode 60 in the horizontal direction of the drawing. On the side opposite to the side where the drift region 12 of the gate electrode 60 is located, the low-concentration source region 32 of the n-type source region 30 is located slightly opposite the gate electrode 60. With such an arrangement and the gate insulating film 105, a channel can be formed in the high resistance p-type semiconductor region 20 immediately below the gate insulating film 105. A so-called channel implant region may be additionally formed in the high resistance p-type semiconductor region 20 immediately below the gate insulating film 105. With this implant, the threshold voltage can be set to a predetermined value.

  In FIG. 2, the boundary between the drift region 12 of the n-type drain region 10 and the n-type drain region 11 excluding this corresponds to the planar position of the sidewall insulating film 92 formed on one sidewall of the gate electrode 60. Yes. The boundary between the low-concentration source region 32 of the n-type source region 30 and the n-type source region 31 excluding this corresponds to the planar position of the sidewall insulating film 91 formed on the other sidewall of the gate electrode 60. ing.

  As shown in FIG. 3, in the vertical direction of the figure, the n-type drain region 10 is positioned such that its drift region 12 faces the gate electrode 60 with a dimension longer than that in FIG. 2 (the opposing length Ld2 is For example, 0.1 μm). On the side opposite to the side where the drift region 12 of the gate electrode 60 is located, the low-concentration source region 32 of the n-type source region 30 is located slightly opposite the gate electrode 60 as in FIG. . A so-called channel implant region may be formed near the low-concentration source region 32 in the high-resistance p-type semiconductor region 20 immediately below the gate insulating film 105.

  In FIG. 3, the boundary between the drift region 12 of the n-type drain region 10 and the n-type drain region 11 excluding this corresponds to the planar position of the sidewall insulating film 92 formed on one side wall of the gate electrode 60. Yes. The illustrated Ld1 corresponding to the planar position of the sidewall insulating film 92 is, for example, 0.1 μm. The low concentration source region 32 corresponds to the planar position of the sidewall insulating film 91 formed on the other sidewall of the gate electrode 60. Here, the n-type source region 31 is not formed adjacent to the low concentration source region 32. Instead, a p-type contact region 40 is formed.

  In the present embodiment, the length of the gate electrode 60 in the direction shown in FIG. 3 is longer than the length of the gate electrode 60 in the direction shown in FIG. By doing so, the length of the region that substantially becomes the channel below the gate electrode is not shortened, and the risk of breakdown voltage deterioration is eliminated. On the other hand, in a design in which the channel length is sufficiently long, the length of the gate electrode may be the same in the direction shown in FIG. 2 and the direction shown in FIG.

  As a whole, the gate electrode 60 includes a first portion extending in the first horizontal direction (vertical direction in FIG. 1) and a second horizontal direction (rightward from the end of the first portion) perpendicular to the first horizontal direction ( And a second portion extending in the left-right direction in FIG. 1 and having two portions as the first and second portions, respectively, and having a ring shape as a whole.

  During operation, the high resistance p-type semiconductor region 20 is adjacent to and formed on the p-type well region 50 adjacent to the high-resistance p-type semiconductor region 20 below the n-type source region 30 and a part on the upper layer side thereof. A constant potential (usually the same potential as that of the n-type source region 31) is maintained by electrical conduction of contacts on the type contact region 40 and the p-type contact region 40 (not shown).

  For example, the buried p-type region 70, the p-type well region 50, and the high-resistance p-type semiconductor region 20 on the p-type semiconductor substrate 80 are formed as follows. First, a p-type semiconductor substrate 80 is prepared, and a buried p-type region 70 is formed at a certain depth of the substrate 80 by, for example, high acceleration implantation of p-type impurities. Next, the p-type well region 50 is formed in a predetermined partial region of the surface layer of the substrate 80. Here, the remaining surface layer of the substrate 80 that has not become the p-type well region 50 becomes the high-resistance p-type semiconductor region 20.

  The substrate 80 and the buried p-type region 70 in FIGS. 2 and 3 can be made to have a conductivity type different from the illustrated conductivity type by employing a manufacturing method different from the above. In either case, the impurity concentration has a considerable degree of freedom.

  According to the structure shown in the present embodiment, the drift region 12 is formed longer in the vertical direction of FIG. 1, and a sufficient margin is secured against the formation position shift of each region that may occur in manufacturing. Therefore, even if the formation position deviation actually occurs in this direction, the breakdown voltage does not deteriorate. In this regard, the same contribution is made in that the length of the gate electrode 60 in the direction shown in FIG. 3 is longer than the length of the gate electrode 60 in the direction shown in FIG. For example, the present embodiment can be applied as an LDMOS with a 5V breakdown voltage specification, and a breakdown voltage of 7V to 10V can actually be achieved. Further, since the n-type source region 31 is not formed in the B-Ba direction shown in FIG. 3, the gate-drain capacitance in this direction does not increase, and high-speed operation is possible.

  Next, the main part of the manufacturing process of the LDMOS according to the above embodiment will be described with reference to FIGS. FIG. 4 is a cross-sectional view schematically showing one of the steps for manufacturing the LDMOS shown in FIG. FIG. 5 is a cross-sectional view schematically showing one of the steps for manufacturing the LDMOS shown in FIG. 1, which is performed after the step shown in FIG. The same or equivalent parts as those already described in FIGS. 4 and 5 are denoted by the same reference numerals. In both figures, (a) is equivalent to the position A-Aa in FIG. 1, and (b) is equivalent to the position B-Ba in FIG.

  In the stage shown in FIG. 4, the drift region 12 is formed. At this stage, the low concentration source region 32 has already been formed as shown in the figure. The low concentration source region 32 can be formed in advance in a region as shown by using the gate electrode 60 as a part of a mask. The drift region 12 is formed by providing the illustrated mask 110 so that the side of the gate electrode 60 opposite to the side where the low concentration source region 32 is located is part of the mask.

  More specifically, on the surface projected in the A-Aa direction, as shown in FIG. 4A, impurity implantation is performed substantially perpendicular to the semiconductor region. “Substantially vertical” may be an angle, for example, and may be, for example, 7 degrees (vertical is 0 degree). On the surface projected in the B-Ba direction, as shown in FIG. 4B, impurity implantation is performed at an intentional angle so that the impurity is also implanted below the gate electrode 60. The intentional angle can be, for example, 30 degrees or more (vertical is 0 degree). In this way, drift regions 12 having different lengths depending on directions are formed.

  The step shown in FIG. 5 is a step of forming the n-type drain region 11 excluding the drift region 12 in the n-type drain region 10 and the n-type source region 31 excluding the low-concentration source region 32 in the n-type source region 30. is there. Note that sidewall insulating films 91 and 92 are formed in advance so as to be in contact with both side walls of the gate electrode 60 between the stage shown in FIG. 4 and the stage shown in FIG. The sidewall insulating films 91 and 92 are formed by, for example, removing the mask 110 after forming the drift region 12 shown in FIG. 4 and depositing an insulating film on the entire surface, and etching the deposited insulating film to an intermediate stage. That's fine. The intermediate residue is the side wall insulating films 91 and 92.

  The n-type drain region 11 and the n-type source region 31 are formed in such a manner that the positions corresponding to the n-type drain region 11 and the n-type source region 31 to be formed are missing on the plane projected in the A-Aa direction. Then, a mask 120 in which all of the side wall insulating films 91 and 92 appear is formed (FIG. 5A). The mask 120 is formed up to the middle of the position of the gate electrode 60 so that the position of the n-type drain region 11 to be formed is removed on the plane projected in the B-Ba direction (FIG. 5B). Impurity implantation using the mask 120 is performed in a direction substantially perpendicular to the semiconductor region as shown in the figure.

  By the impurity implantation using the mask 120 as shown in FIG. 5, the gate electrode 60 and the sidewall insulating films 91 and 92 also actually function as masks. As a result of the formation of the n-type drain region 11 and the n-type source region 31, the drift region 12 (and the low-concentration source region 31) can exist with good position controllability with respect to the gate electrode 60. After the stage shown in FIG. 5, the p-type contact region 40 is formed using another predetermined mask.

  According to the present embodiment, even in the process of using the sidewall insulating films 91 and 92 as a mask for forming the drift region 12 with the application of a fine process, the drift region 12 in the B-Ba direction shown in FIG. The length can be surely longer than the length of the drift region 12 in the A-Aa direction, which is involved in characteristics such as element on-resistance. Thus, breakdown voltage degradation does not occur due to the length of the drift region 12 in the B-Ba direction that is not directly related to characteristics such as the on-resistance of the element.

  Although the embodiments of the present invention have been described in detail above, various modifications can be made. For example, the n-type source region 31 may be formed so as to appear even at the cross section at the B-Ba position if the application does not require a very high speed operation. Moreover, the conductivity type of each semiconductor region can be reversed to form a p-channel device. further. A device having a plurality of units shown in FIG. 1 on a substrate may be used.

FIG. 3 is a schematic layout diagram virtually showing an upper surface of a semiconductor region of a semiconductor device (LDMOS) according to an embodiment of the present invention. FIG. 2 is a cross-sectional structure diagram schematically showing a cross-section in the direction of the arrow corresponding to the position A-Aa shown in FIG. 1. FIG. 2 is a cross-sectional structure diagram schematically showing a cross-section in the direction of the arrow corresponding to the B-Ba position shown in FIG. 1. Sectional drawing which shows typically one of the processes for manufacturing LDMOS shown in FIG. FIG. 5 is a cross-sectional view schematically showing one of the steps for manufacturing the LDMOS shown in FIG. 1 and performed after the step shown in FIG. 4.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... n-type drain region, 11 ... n-type drain region (except drift region), 12 ... Drift region, 20 ... High-resistance p-type semiconductor region, 30 ... n-type source region, 31 ... n-type source region (low concentration source) 32) low concentration source region, 40 ... p-type contact region, 50 ... p-type well region, 60 ... gate electrode, 70 ... buried p-type region, 80 ... p-type semiconductor substrate, 91, 92 ... sidewall insulation Reference numerals: 100, interlayer insulating film, 105, gate insulating film, 110, mask (for forming the drift region 12), 120, mask (for forming the n-type drain region 11 and the n-type source region 31)

Claims (5)

A gate electrode having a first part extending in the first horizontal direction and a second part extending in the second horizontal direction perpendicular to the first horizontal direction from an end of the first part;
A gate insulating film located on the lower side in the vertical direction of the gate electrode;
First and second sidewall insulating films respectively formed on both side walls of the gate electrode;
A high-resistance semiconductor region located opposite to the gate electrode only through the gate insulating film at a position and size contained in the plane figure of the gate electrode;
Extending from a position adjacent to the high resistance semiconductor region and facing the first and second portions of the gate electrode through the gate insulating film to a lower position of the first sidewall insulating film. A drift region in which the first horizontal length of the gate electrode facing the second portion is longer than the second horizontal length of the gate electrode facing the first portion; ,
A drain region adjacent to the drift region;
Extending from a position adjacent to the high resistance semiconductor region and facing the first and second portions of the gate electrode through the gate insulating film to a lower position of the second sidewall insulating film A low concentration source region;
A semiconductor device comprising: a source region adjacent to the low-concentration source region.   The length in the first horizontal direction of the second portion of the gate electrode is longer than the length in the second horizontal direction of the first portion of the gate electrode. Semiconductor device.   The source region is the low concentration source region and extends from a position facing the second portion of the gate electrode through the gate insulating film to a lower position of the second sidewall insulating film. 2. The semiconductor device according to claim 1, wherein the semiconductor device is not adjacent to the low concentration source region. A first portion extending in the first horizontal direction and a second portion extending in the second horizontal direction perpendicular to the first horizontal direction from an end of the first portion on the high-resistance semiconductor region. Forming a laminated structure having a gate electrode provided, and a gate insulating film located on the lower side in the vertical direction of the gate electrode;
Using the gate electrode as a part of a mask, an impurity is implanted in a substantially vertical direction with respect to the high resistance semiconductor region located on one side of the gate electrode where the first and second portions are continuous. Forming a first drift region by:
Using the mask, a second drift is formed by implanting the impurity at an intentional angle so that the impurity is also implanted below the second portion of the gate electrode and continuing to the first drift region. Forming a region;
Forming first and second sidewall insulating films on both side walls of the gate electrode,
Forming a drain region and a source region by implanting impurities in a substantially vertical direction using the first and second sidewall insulating films as part of another mask. Manufacturing method.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the intentional angle in the step of forming the second drift region is 30 degrees or more with respect to a vertical direction.

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