CN103426760B - The manufacturing process of P-type LDMOS surface channel component - Google Patents
The manufacturing process of P-type LDMOS surface channel component Download PDFInfo
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- CN103426760B CN103426760B CN201210153599.3A CN201210153599A CN103426760B CN 103426760 B CN103426760 B CN 103426760B CN 201210153599 A CN201210153599 A CN 201210153599A CN 103426760 B CN103426760 B CN 103426760B
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Abstract
The invention discloses a kind of manufacturing process of P-type LDMOS surface channel component, adopt polysilicon and metal silicide as grid, and have adjusted the process sequences of Channeling implantation, long-time high temperature propelling, the doping of polysilicon gate boron ion P type, doped with boron impurity is not had when grid is formed, so just can carry out long-time high temperature propelling to form enough wide raceway groove, avoid the device that short-channel effect causes and penetrate or leak electricity; Then form low-doped drain terminal drift region and ion implantation is carried out to grid, owing to advancing technique without long-time high temperature after boron injection, therefore avoiding boron penetration gate oxide.The device performance of such formation is stablized, and technological process is also simply easy to implement.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly a kind of manufacturing process of P-type LDMOS surface channel component.
Background technology
To the electronic devices and components of battery powered handheld electronics, less volume and lower electric leakage are necessary performance requirements, in addition also need fast switching speed.P type LDMOS(LaterallyDiffusedMetalOxideSemiconductor, i.e. Laterally Diffused Metal Oxide Semiconductor) form array to obtain being greater than the output current of 10A by multiple grid, be widely used in the electric power management circuit of handheld electronics.Large array means that grid overall width is very large, and the uniformity how to have reached is very large problem to keep Low dark curient.Simultaneously in order to obtain high switching speed, threshold voltage is lower, but lower threshold voltage can cause higher leakage current.Compare buried channel, surface channel device can be compromised low threshold voltage and Low dark curient.At present, P type surface channel device needs to use the polysilicon of P type doping, and boron-doping is common selection, but boron easily penetrates gate oxide 6 when follow-up long-time high temperature advances enters raceway groove 5.And existing technique grid polysilicon 7 adds tungsten silicon lamination 13, due to tungsten silicon to the solid solubility of boron higher than polysilicon, boron can be diffused in tungsten silicon layer.These two effects all can cause threshold voltage and other key index instability of device.In addition, in order to avoid short-channel effect, long high temperature propelling must be carried out after grid is formed, in existing technique, boron is mixed into polysilicon before grid is formed, as carry out long-time high temperature propelling then boron to be diffused in tungsten silicon layer the less device that causes in polysilicon and to exhaust, if do not carried out then, raceway groove is shorter, and these all unavoidably affect uniformity and the stability of device.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of manufacturing process of P-type LDMOS surface channel component, can form enough wide raceway groove, and the device avoiding short-channel effect to cause penetrates or leaks electricity, and can avoid the boron penetration gate oxide in grid.
For solving the problems of the technologies described above, the manufacturing process of P-type LDMOS surface channel component provided by the invention, comprises the following steps:
1st step, N-type substrate grows N-type epitaxial region; Deposit one silica layer above N-type epitaxial region, opens silicon oxide layer by photoetching and dry quarter, and form deep trench in opened areas etching N type epitaxial region, the bottom of described deep trench is arranged in N-type substrate;
2nd step, deposit N-type heavily doped polysilicon on silicon oxide layer, makes N-type heavily doped polysilicon fill deep trench and forms N-type heavily doped polysilicon electrical connection sinking passage; Return carve polysilicon be parked on silicon oxide layer;
3rd step, remove silicon oxide layer, regrowth silicon monoxide barrier layer, carries out first time P type ion implantation in drain region, forms the first light dope diffused drain of classification;
4th step, removes silica barrier layer, growth gate oxide, and on gate oxide the polysilicon of deposit undoped;
5th step, photoetching and dry quarter form polysilicon gate, utilize photoresist to cover drain region and partial polysilicon grid, and source region and remainder polysilicon gate expose, and carry out N-type ion implantation, ion implantation energy is lower than the penetration depth of gate polysilicon layer;
6th step, removes photoresist, carries out high temperature and advances formation N-type raceway groove; Carry out second time ion implantation in drain region, form the second light dope diffused drain of classification;
7th step, deposit one deck silica, deposit one deck organic media again on it; Return and carve organic media and silica, remove organic media and the silica at polysilicon gate top, and form monox lateral wall at multi-crystal silicon grid side, reserve part organic media and whole silica above source region and drain region;
8th step, carries out P type ion implantation to polysilicon gate, and Implantation Energy does not penetrate organic media and the silica of source-drain area;
9th step, removes organic media, lithographic definition source-drain area, and wet method removes part silica, carries out source-drain area ion implantation and rapid thermal annealing, removes beneath portions form drain electrode and source electrode at silica;
10th step, opens the region that source-drain area needs metal silication, carries out silication technique for metal, forms metal silicide in source and drain and grid.
Wherein, in the 1st step, described N-type substrate is heavy doping, and doping content is 10
20cm
-3above, N-type epitaxial region is light dope, and doping content is 10
14~ 10
16cm
-3, wherein N-type epitaxial region thickness often increases by 1 μm, and the puncture voltage of device improves 10 ~ 12 volts; The thickness of described silicon oxide layer is 3000 ~ 6000 dusts.
Wherein, in the 2nd step, the Doped ions of described N-type heavily doped polysilicon is phosphorus or arsenic, and concentration is greater than 10
20cm
-3; The thickness being positioned at the N-type heavily doped polysilicon on silicon oxide layer is more than 1.2 times of deep trench width; Polysilicon in the polysilicon electrical connection sinking passage of Hui Kehou exceeds 0 ~ 300 dust than the surface of N-type epitaxial region.
Wherein, in the 3rd step, first time P type ion implantation undertaken by repeatedly different-energy, injection ion is boron, and Implantation Energy is 5 ~ 120keV, and dosage is 10
11~ 10
13cm
-2.
Wherein, in the 4th step, the polysilicon thickness of described undoped is 1500 ~ 4000 dusts.
Wherein, in the 5th step, the injection ion of N-type ion implantation is phosphorus, and Implantation Energy is below 80keV, and dosage is 10
12~ 10
14cm
-2.
Wherein, in the 6th step, the temperature that high temperature advances is 900 ~ 1050 DEG C, and the time is 30 ~ 180 minutes; The injection ion of second time P type ion implantation is boron, and Implantation Energy is 5 ~ 120keV, and dosage is 10
11~ 10
13cm
-2.
Wherein, in the 7th step, the thickness of described silica is 500 ~ 1000 dusts, and the thickness of organic media is 1000 ~ 5000 dusts.
Wherein, in the 8th step, the impurity of P type ion implantation is boron, and Implantation Energy is 2 ~ 10keV, and dosage is 10
15cm
-2above.
Wherein, in the 9th step, the injection ion of source-drain area is boron, and Implantation Energy is 5 ~ 80keV, and dosage is 10
15cm
-2above, the temperature of rapid thermal annealing is 1000 ~ 1100 DEG C, and the time is 5 ~ 30 seconds.
Beneficial effect of the present invention is, adopt polysilicon and metal silicide as grid, and have adjusted the process sequences of Channeling implantation, long-time high temperature propelling, the doping of polysilicon gate boron ion P type, doped with boron impurity is not had when grid is formed, so just can carry out long-time high temperature propelling to form enough wide raceway groove, avoid the device that short-channel effect causes and penetrate or leak electricity; Then form low-doped drain terminal drift region and ion implantation is carried out to grid, owing to advancing technique without long-time high temperature after boron injection, therefore avoiding boron penetration gate oxide.The device performance of such formation is stablized, and technological process is also simply easy to implement.
Accompanying drawing explanation
Fig. 1 is the sectional view of existing P-type LDMOS surface channel component;
Fig. 2-Figure 12 is the device schematic cross-section in P-type LDMOS surface channel component manufacture process of the present invention;
Figure 13 is the manufacturing process flow diagram of P-type LDMOS surface channel component of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation.
The manufacturing process of P-type LDMOS surface channel component of the present invention, as shown in figure 13, comprises the following steps:
1st step, heavily doped N-type substrate 1 grows lightly doped N-type epitaxial region 2; Above N-type epitaxial region 2, deposition thickness is the silicon oxide layer of 3000 ~ 6000 dusts, opens silicon oxide layer by photoetching and dry quarter, forms deep trench in opened areas etching N type epitaxial region 2, and the bottom of described deep trench is arranged in N-type substrate 1, as shown in Figure 2; The doping content of described N-type substrate 1 is 10
20cm
-3above, the doping content of N-type epitaxial region 2 is 10
14~ 10
16cm
-3, wherein N-type epitaxial region 2 thickness often increases by 1 μm, and the puncture voltage of device improves 10 ~ 12 volts;
2nd step, deposit N-type heavily doped polysilicon on silicon oxide layer, make N-type heavily doped polysilicon fill deep trench and form N-type heavily doped polysilicon electrical connection sinking passage 3, wherein the Doped ions of N-type heavily doped polysilicon is phosphorus or arsenic, and concentration is greater than 10
20cm
-3; The thickness being positioned at the N-type heavily doped polysilicon on silicon oxide layer is more than 1.2 times of deep trench width, as shown in Figure 3;
3rd step, return carve polysilicon be parked on silicon oxide layer, polysilicon electrical connection sinking passage 3 in polysilicon exceed 0 ~ 300 dust than the surface of N-type epitaxial region 2; As shown in Figure 4;
4th step, removes silicon oxide layer, regrowth silicon monoxide barrier layer, carries out the first light dope diffused drain 4 of first time P type ion implantation formation classification in drain region; Ion implantation can repeatedly be carried out with different-energy, can form certain thickness Uniform Doped district like this, and implanted dopant is boron, and Implantation Energy is 5 ~ 120keV, and dosage is 10
11~ 10
13cm
-2, as shown in Figure 5;
5th step, removes silica barrier layer, growth gate oxide 6, and on gate oxide 6 polysilicon of deposit undoped; The polysilicon thickness of described undoped is 1500 ~ 4000 dusts, as shown in Figure 6; Polysilicon can also deposition thickness be the dielectric layer of 200 ~ 800 dusts, as silica, not shown;
6th step, photoetching and dry quarter form polysilicon gate 7, utilize photoresist to cover drain region and partial polysilicon grid 7, source region and remainder polysilicon gate expose, and carry out N-type ion implantation, as shown in Figure 7, injection ion is phosphorus, due to phosphorus be easier to be picked into, therefore ion implantation energy is lower than the penetration depth of grid polycrystalline silicon, Implantation Energy is below 80keV, and dosage is 10
12~ 10
14cm
-2;
7th step, removes photoresist, and carry out high temperature and advance formation N-type raceway groove 5, advance temperature to be 900 ~ 1050 DEG C, the time is 30 ~ 180 minutes, and channel length advances the degree of depth to determine by high temperature, and adjustable temperature and time obtains required channel length; Carry out second time P type ion implantation in drain region, injection ion is boron, and Implantation Energy is 5 ~ 120keV, and dosage is 10
11~ 10
13cm
-2, form the second light dope diffused drain 8 of classification, as shown in Figure 8;
8th step, the silica of deposit one deck 500 ~ 1000 dust, the organic media 20 of deposit one deck 1000 ~ 5000 dust again on it, as shown in Figure 9;
9th step, returns and carves organic media 20 and silica, removes organic media 20 and the silica at polysilicon gate 7 top, and forms monox lateral wall 11 in polysilicon gate 7 side, reserve part organic media 20 and whole silica above source region and drain region;
10th step, carries out P type ion implantation to polysilicon gate 7, and as shown in Figure 10, impurity is boron, and Implantation Energy is 2 ~ 10keV, and dosage is 10
15cm
-2above; Implantation Energy should ensure organic media 20 and the silicon oxide stack that can not penetrate source-drain area;
11st step, removes the organic media 20 of source-drain area, lithographic definition source-drain area, and wet method removes part silica, and carry out source-drain area ion implantation, impurity is boron, and Implantation Energy is 5 ~ 80keV, and dosage is 10
15cm
-2above; Then carry out the rapid thermal annealing that temperature is 1000 ~ 1100 DEG C, the time is 5 ~ 30 seconds, remove beneath portions at silica and form P type heavy doping drain electrode 9 and P type heavy doping source electrode 10, as shown in figure 11;
12nd step, opens the region that source-drain area needs metal silication, carries out silication technique for metal, forms metal silicide 12, as shown in figure 12 in source and drain and grid.
P type LDMOS of the present invention is by multiple gate connected in parallel and the discrete device of array, its total output current is greater than 10 amperes, its total grid width is greater than 50 millimeters, Figure 12 is the schematic cross-section of device, wherein 1 is heavily doped N-type substrate, 2 is lightly doped N-type epitaxial regions, 3 is N-type heavily doped polysilicon electrical connection sinking passages, source is electrically connected to N-type substrate by it, 4 and 8 is light dope diffused drains of classification, 5 is N-type raceway grooves, it and polysilicon electrical connection sinking passage 3 form electrical connection, 10 is the N-type heavy doping source electrodes connected together with polysilicon electrical connection sinking passage 3, respectively there is a grid both sides of P type heavy doping drain electrode 9 and polysilicon electrical connection sinking passage 3, namely two grids have drain electrode 9 and sinking passage 3.
The present invention adopts polysilicon and metal silicide as grid, and have adjusted the process sequences of Channeling implantation, long-time high temperature propelling, the doping of polysilicon gate boron ion P type, doped with boron impurity is not had when grid is formed, so just can carry out long-time high temperature propelling to form enough wide raceway groove, avoid the device that short-channel effect causes and penetrate or leak electricity; Then form low-doped drain terminal drift region and ion implantation is carried out to grid, owing to advancing technique without long-time high temperature after boron injection, therefore avoiding boron penetration gate oxide, and be diffused in tungsten silicon layer.The device performance of such formation is stablized, and technological process is also simply easy to implement.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. a manufacturing process for P-type LDMOS surface channel component, is characterized in that, comprises the following steps:
1st step, in N-type substrate (1) upper growth N-type epitaxial region (2); In N-type epitaxial region (2) top deposit one silica layer, open silicon oxide layer by photoetching and dry quarter, form deep trench in opened areas etching N type epitaxial region (2), the bottom of described deep trench is arranged in N-type substrate (1);
2nd step, deposit N-type heavily doped polysilicon on silicon oxide layer, makes N-type heavily doped polysilicon fill deep trench and forms heavily doped polysilicon electrical connection sinking passage (3) of N-type; Return carve polysilicon be parked on silicon oxide layer;
3rd step, remove silicon oxide layer, regrowth silicon monoxide barrier layer, carries out first time P type ion implantation in drain region, forms the first light dope diffused drain (4) of classification;
4th step, removes silica barrier layer, growth gate oxide (6), and the polysilicon going up deposit undoped at gate oxide (6);
5th step, photoetching and dry quarter form polysilicon gate (7), utilize photoresist to cover drain region and partial polysilicon grid (7), and source region and remainder polysilicon gate expose, carry out N-type ion implantation, ion implantation energy is lower than the penetration depth of gate polysilicon layer;
6th step, removes photoresist, carries out high temperature and advances formation N-type raceway groove (5); Carry out second time P type ion implantation in drain region, form the second light dope diffused drain (8) of classification;
7th step, deposit one deck silica, deposit one deck organic media (20) again on it; Return and carve organic media (20) and silica, remove organic media (20) and the silica at polysilicon gate (7) top, and form monox lateral wall (11) in polysilicon gate (7) side, reserve part organic media (20) and whole silica above source region and drain region;
8th step, carries out P type ion implantation to polysilicon gate (7), and Implantation Energy does not penetrate organic media and the silica of source-drain area;
9th step, removes organic media (20), lithographic definition source-drain area, and wet method removes part silica, carries out source-drain area ion implantation and rapid thermal annealing, removes beneath portions form drain electrode (9) and source electrode (10) at silica;
10th step, opens the region that source-drain area needs metal silication, carries out silication technique for metal, forms metal silicide (12) in source and drain and grid.
2. the manufacturing process of P-type LDMOS surface channel component according to claim 1, is characterized in that, in the 1st step, described N-type substrate (1) is heavy doping, and doping content is 10
20cm
-3above, N-type epitaxial region (2) are light dope, and doping content is 10
14~ 10
16cm
-3, wherein N-type epitaxial region (2) thickness often increases by 1 μm, and the puncture voltage of device improves 10 ~ 12 volts; The thickness of described silicon oxide layer is 3000 ~ 6000 dusts.
3. the manufacturing process of P-type LDMOS surface channel component according to claim 1, is characterized in that, in the 2nd step, the Doped ions of described N-type heavily doped polysilicon is phosphorus or arsenic, and concentration is greater than 10
20cm
-3; The thickness being positioned at the N-type heavily doped polysilicon on silicon oxide layer is more than 1.2 times of deep trench width; Polysilicon in polysilicon electrical connection sinking passage (3) of Hui Kehou exceeds 0 ~ 300 dust than the surface of N-type epitaxial region (2).
4. the manufacturing process of P-type LDMOS surface channel component according to claim 1, is characterized in that, in the 3rd step, first time P type ion implantation undertaken by repeatedly different-energy, injection ion is boron, and Implantation Energy is 5 ~ 120keV, and dosage is 10
11~ 10
13cm
-2.
5. the manufacturing process of P-type LDMOS surface channel component according to claim 1, is characterized in that, in the 4th step, the polysilicon thickness of described undoped is 1500 ~ 4000 dusts.
6. the manufacturing process of P-type LDMOS surface channel component according to claim 1, is characterized in that, in the 5th step, the injection ion of N-type ion implantation is phosphorus, and Implantation Energy is below 80keV, and dosage is 10
12~ 10
14cm
-2.
7. the manufacturing process of P-type LDMOS surface channel component according to claim 1, is characterized in that, in the 6th step, the temperature that high temperature advances is 900 ~ 1050 DEG C, and the time is 30 ~ 180 minutes; The injection ion of second time P type ion implantation is boron, and Implantation Energy is 5 ~ 120keV, and dosage is 10
11~ 10
13cm
-2.
8. the manufacturing process of P-type LDMOS surface channel component according to claim 1, is characterized in that, in the 7th step, the thickness of described silica is 500 ~ 1000 dusts, and the thickness of organic media (20) is 1000 ~ 5000 dusts.
9. the manufacturing process of P-type LDMOS surface channel component according to claim 1, is characterized in that, in the 8th step, the impurity of P type ion implantation is boron, and Implantation Energy is 2 ~ 10keV, and dosage is 10
15cm
-2above.
10. the manufacturing process of P-type LDMOS surface channel component according to claim 1, is characterized in that, in the 9th step, the injection ion of source-drain area is boron, and Implantation Energy is 5 ~ 80keV, and dosage is 10
15cm
-2above, the temperature of rapid thermal annealing is 1000 ~ 1100 DEG C, and the time is 5 ~ 30 seconds.
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| CN104183632B (en) * | 2014-08-13 | 2017-08-29 | 昆山华太电子技术有限公司 | The self aligned drain terminal field plate structures of RF LDMOS and preparation method |
| US9512517B2 (en) * | 2015-01-23 | 2016-12-06 | Varian Semiconductor Equipment Associates, Inc. | Multiple exposure treatment for processing a patterning feature |
| CN109192780B (en) * | 2018-08-29 | 2020-11-27 | 电子科技大学 | Transverse MOSFET device and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0462416A2 (en) * | 1990-05-24 | 1991-12-27 | Micron Technology, Inc. | Process for N-well and P-well creation on a silicon substrate using a blanket P-well implant and no N-well steam oxidation step |
| EP0789401A2 (en) * | 1995-08-25 | 1997-08-13 | Matsushita Electric Industrial Co., Ltd. | LD MOSFET or MOSFET with an integrated circuit containing thereof and manufacturing method |
| US6746928B1 (en) * | 2001-05-08 | 2004-06-08 | Newport Fab, Llc | Method for opening a semiconductor region for fabricating an HBT |
| CN201570499U (en) * | 2009-11-03 | 2010-09-01 | 苏州远创达科技有限公司 | LDMOS device with transverse-diffusion buried layer under grid |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5350491A (en) * | 1992-09-18 | 1994-09-27 | Advanced Micro Devices, Inc. | Oxide removal method for improvement of subsequently grown oxides for a twin-tub CMOS process |
-
2012
- 2012-05-16 CN CN201210153599.3A patent/CN103426760B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0462416A2 (en) * | 1990-05-24 | 1991-12-27 | Micron Technology, Inc. | Process for N-well and P-well creation on a silicon substrate using a blanket P-well implant and no N-well steam oxidation step |
| EP0789401A2 (en) * | 1995-08-25 | 1997-08-13 | Matsushita Electric Industrial Co., Ltd. | LD MOSFET or MOSFET with an integrated circuit containing thereof and manufacturing method |
| US6746928B1 (en) * | 2001-05-08 | 2004-06-08 | Newport Fab, Llc | Method for opening a semiconductor region for fabricating an HBT |
| CN201570499U (en) * | 2009-11-03 | 2010-09-01 | 苏州远创达科技有限公司 | LDMOS device with transverse-diffusion buried layer under grid |
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