CN106972047B - LDMOS devices - Google Patents

LDMOS devices Download PDF

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CN106972047B
CN106972047B CN201610025460.9A CN201610025460A CN106972047B CN 106972047 B CN106972047 B CN 106972047B CN 201610025460 A CN201610025460 A CN 201610025460A CN 106972047 B CN106972047 B CN 106972047B
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region
type
drift region
well region
substrate
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CN106972047A (en
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张广胜
张森
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CSMC Technologies Corp
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CSMC Technologies Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/1025—Channel region of field-effect devices
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    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
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    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Abstract

The invention provides LDMOS devices, which relate to the technical field of semiconductors and comprise a substrate with a conductive type, a 0 drift region with a second conductive type positioned in the substrate, a well region positioned in the substrate, adjacent to and spaced from the drift region and having a conductive type, an epitaxial layer positioned on the substrate, wherein the epitaxial layer comprises a second drift region with the second conductive type, a second well region with a conductive type and a doped region with the second conductive type respectively positioned at two sides of the second drift region, the second well region is positioned on a well region, a buried layer positioned in an drift region and the second drift region and having the conductive type.

Description

LDMOS devices
Technical Field
The invention relates to the technical field of semiconductors, in particular to LDMOS devices.
Background
Lateral double-Diffused Metal oxide semiconductor (LDMOS) devices are widely used in smart power integrated circuits due to their high voltage resistance characteristics, the off-state high voltage resistance and the on-resistance are important indexes for characterizing the characteristics of LDMOS devices, and are pair contradictions in the process of manufacturing devices, and in order to further improve the characteristics of devices and solve the contradictions, the concept of Reduced Surface Field (LDMOS) devices is introduced and widely used.
Fig. 1 shows a cross-sectional view of conventional three-layered RESURF LDMOS, which includes a P-type substrate 101, a P-type deep well 102 in the P-type substrate 101 and an N-type deep well 104 adjacent to the P-type deep well 102, an N-type epitaxy 107 on the P-type substrate 101, a P-type well region 106 formed on the P-type deep well 102 on the side of the N-type epitaxy 107 , the P-type well region 106 being used for a conduction channel of the LDMOS, an N-type doped region 112 formed on the N-type deep well 104 on the other side of the N-type epitaxy 107, a P-type buried layer 105 formed in the N-type epitaxy 107 and the N-type deep well 104, and a P-type buried layer 105 formed in the P-type deep well and the P-type well region, a source/drain lead-out region 108, a body lead-out region 109 and a gate lead-out region 113, an interconnection metal layer 110 connected to the source lead-out region and the body lead-out region, and an interconnection metal layer 111 connected to the drain lead-out region.
In the traditional ultrahigh voltage three-layer RESURF LDMOS, junction-depth P-type doping is formed in a drift region through injection or epitaxy, so that depletion between upper and lower regions of P-type impurities in the drift region is realized, and the purpose of RESURF is achieved.
Therefore, it is necessary to provide new LDMOS devices to solve the above technical problems.
Disclosure of Invention
The concept of series in simplified form is introduced in the summary of the invention section, which is described in further detail in the detailed description section the summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to identify key features or essential features of the claimed subject matter.
In view of the deficiencies of the prior art, the present invention provides LDMOS devices, comprising:
a substrate having an th conductivity type;
an drift region in the substrate having a second conductivity type;
an well region in the substrate adjacent to and spaced from the drift region having a conductivity type;
the epitaxial layer is positioned on the substrate and comprises a second drift region with a second conduction type, a second well region with th conduction type and a doped region with the second conduction type, wherein the second well region is positioned on the th well region;
an buried layer in the drift region and the second drift region, having the conductivity type;
a second buried layer in said well region and said second well region having said conductivity type.
, further comprising:
the source electrode lead-out area and the body lead-out area are adjacent to each other, are positioned in the second well region and have opposite conductive types;
the drain electrode leading-out region is positioned in the doped region and has a second conductive type;
a field oxide layer on the second drift region;
and the gate structure is positioned on the epitaxial layer, the side edge of the gate structure extends to the field oxide layer, and the other side edge of the gate structure extends to the second well region.
, the conductivity type is P-type and the second conductivity type is N-type.
, the second drift region extends from over the well region to over the drift region.
Further , the interval has a length of 0.
And , the material of the gate structure comprises polysilicon.
And , further comprising contacts respectively connected to the body pull-out region, the source pull-out region, the drain pull-out region and the gate structure, and an interconnection metal layer connected to the contacts.
And , the second drift region is an N-type epitaxial layer.
In summary, the structure of the present invention mainly optimizes the JFET region of the source end, increases the width of the current path, and injects P-type impurities (i.e., buried layer) under the N-type epitaxy to assist in depletion, thereby obtaining a lower on-resistance while obtaining a high breakdown voltage. In addition, the invention realizes the structure of the multilayer RESURF, thereby improving the high-voltage resistance of the device.
Drawings
The following drawings of the present invention are included to provide an understanding of the invention as part of and are included to provide a further understanding of the invention.
In the drawings:
FIG. 1 shows a cross-sectional schematic of a prior art three-layer RESUF LDMOS device;
fig. 2 shows a cross-sectional schematic of a resurf LDMOS device of an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, it will be apparent to those skilled in the art that the present invention may be practiced without or more of these details.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on.. another," "adjacent to.," connected to, "or" coupled to "other elements or layers, it can be directly on, adjacent to, connected to, or coupled to the other elements or layers, or intervening elements or layers may be present.
For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" would then be oriented "on" other elements or features.
As used herein, the singular forms "," "," and "the/the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, it is also to be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Thus, the implanted regions shown as rectangles typically have rounded or curved features at their edges and/or implant concentration gradients, rather than binary changes from implanted regions to non-implanted regions.
In order to provide a thorough understanding of the present invention, a detailed structure will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Referring now to fig. 2, an LDMOS device of an embodiment of the invention is described in detail, wherein fig. 2 shows a cross-sectional view of a resurf LDMOS device of an embodiment of the invention.
The resurf LDMOS device of the present invention is explained by taking NLDMOS as an example, and specifically includes the following structure:
the resurf LDMOS device of the present invention includes a substrate 201 the substrate 201 may be at least of the following mentioned materials, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), etc. in this embodiment, the substrate 201 is a silicon substrate the substrate 201 is doped with P-type impurities such as B.
Also included is a P-type well region 202, which is located in substrate 201. The P-type well region 202 is in contact with the substrate and realizes that the source terminal is depleted to the N-type region when the reverse voltage is withstood. The P-well 202 may be formed by implanting or diffusing P-type dopant ions, including but not limited to boron ions, into the substrate 201.
An th drift region 204 is also included, which is located in the substrate 201 adjacent to the P-type well 202 and has a conductivity type of N-type the th drift region 204 may be formed by implanting or diffusing N-type dopant ions, including but not limited to phosphorous or arsenic ions, into the substrate 201.
Illustratively, the th drift region 204 may be adjacent to and spaced from the P-type well region 202, as shown in fig. 2, with a spacer region 203 in between, the spacer region 203 being part of the substrate 201.
The depths of the P-type well 202 and th drift 204 may be chosen appropriately according to the specific type of device, and are not limited herein.
The epitaxial layer comprises a second drift region with the second conductivity type, and a second well region with the th conductivity type and a doped region with the second conductivity type which are respectively positioned at two sides of and adjacent to the second drift region, wherein the second well region is positioned on the th well region.
For an NLDMOS device, the th conductivity type is P-type and the second conductivity type is N-type, then as shown in fig. 2, the epitaxial layer includes an N-type second drift region 207, and a P-type well region 206 (i.e., a second well region) and an N-type doped region 212 respectively located on both sides of and adjacent to the second drift region 207, the P-type well region 206 being located on the P-type well region 202 (i.e., a th well region), the N-type doped region 212 being located on the th drift region 204, illustratively, at least a portion of the second drift region 207 being located on the P-type well region 202 and the th drift region 204, step by step, when there is a spacer region 203 between the P-type well region 202 and the th drift region 204, then the second drift region 207 is located on the spacer region 203, and the -side edge of the second drift region 207 extends to the P-type well region 202, and the other -side edge of the second drift region 207 extends to the th drift region 204.
As an example, when at least a portion of the second drift region 207 is located on the P-type well region 202 and the th drift region 204, the length of the space between the P-type well region 202 and the th drift region 204 may also be 0, for example, as shown in fig. 2, the same effect may be achieved by extending the P-type well region 202 to connect with the th drift region 204 near the side of the th drift region 204.
Optionally, the N-type second drift region 207 is an N-type epitaxial layer. The entire epitaxial layer is formed as an N-type epitaxial layer, and a portion of the N-type epitaxial layer is implanted with P-type or N-type doped ions, so that the P-type well region 206 and the N-type doped region 212 are formed, and the remaining N-type epitaxial layer directly serves as the N-type second drift region 207.
The resurf LDMOS device of the present invention further includes a buried layer 205 located in the th drift region 204 and the second drift region 207, illustratively, the conductivity type of the buried layer 205 is P-type for NLDMOS , wherein the width of the th buried layer 205 is maintained equal to or longer than that of the buried layer in the prior art structure.
The th buried layer 205 and the th drift region 204 thereunder, the th buried layer 205 and the second drift region 207, the th drift region 204 and the substrate 201 thereabove all form a PN junction to form a three-layer (tripple) RESURF structure.
Meanwhile, the second drift region 207 forms a PN junction with the P-well 202 to form a RESURF structure, and when the P-well 202 and the th drift region 204 have a spacer 203 therebetween, the P-substrate at the second drift region 207 and the spacer 203 also forms a PN junction to form a RESURF structure.
The resurf LDMOS device of the present invention further includes a second buried layer 205 located in the P-well 202 and the P-well 208. illustratively, the conductivity type of the second buried layer 205 is P-type for NLDMOS, there is a possibility that it can be formed simultaneously between the buried layer 205 and the second buried layer 205, with the same implantation depth.
, source strap region 2081 and body strap region 209 are adjacent and within P-well region 206, having opposite conductivity types, for example, source strap region 2081 is heavily doped N-type (N +), and body strap region 209 is heavily doped P-type (P +).
The N-type doped region 212 is located in the drain extension region 2082, and for NLDMOS, its conductivity type is heavily doped N-type (N +).
A field oxide layer is further included on the second drift region 207, which may be silicon oxide or other suitable material, and may be formed by thermal oxidation, chemical vapor deposition, or the like.
, a gate structure 213 is further included on the epi layer, with a side edge of the gate structure 213 extending over the field oxide layer and another side edge of the gate structure 213 extending over the P-well region 206.
As an example, contacts respectively connected with the body lead-out region 209, the source lead-out region 2081, the drain lead-out region 2082, and the gate structure 213, and interconnection metal layers 210 and 211 connected with the contacts are further included.
It is worth to mention that, in the embodiment of the present invention, only the structure of the NLDMOS device is described, and the structure of the present invention is also applicable to the PLDMOS device, and details are not described herein again.
In addition, the invention forms a three-layer RESURF structure formed by the drift region 204, the buried layer 205 and the second drift region 207 in addition to the RESURF structure formed by the spacer region 203, the P-type well region 202 and the second drift region 207 shown in FIG. 2, thereby realizing a multi-layer RESURF structure and further improving the high voltage resistance of the device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (7)

  1. An LDMOS device, comprising:
    a substrate having an th conductivity type;
    an drift region in the substrate having a second conductivity type;
    an well region in the substrate adjacent to and spaced from the drift region having a conductivity type;
    the epitaxial layer is positioned on the substrate and comprises a second drift region with a second conduction type, a second well region with th conduction type and a doped region with the second conduction type, wherein the second well region is positioned on the th well region;
    an buried layer in the drift region and the second drift region, having the conductivity type;
    and a second buried layer located in the th well region and the second well region and having the th conductivity type, wherein the second drift region extends from over the th well region to over the th drift region.
  2. 2. The LDMOS device of claim 1, further comprising:
    the source electrode lead-out area and the body lead-out area are adjacent to each other, are positioned in the second well region and have opposite conductive types;
    the drain electrode leading-out region is positioned in the doped region and has a second conductive type;
    a field oxide layer on the second drift region;
    and the gate structure is positioned on the epitaxial layer, the side edge of the gate structure extends to the field oxide layer, and the other side edge of the gate structure extends to the second well region.
  3. 3. The LDMOS device of claim 1, wherein the th conductivity type is P-type and the second conductivity type is N-type.
  4. 4. The LDMOS device of claim 1, wherein the length of the space is 0.
  5. 5. The LDMOS device of claim 2, wherein a material of the gate structure comprises polysilicon.
  6. 6. The LDMOS device of claim 2 further including contacts connected to the body pull out region, source pull out region, drain pull out region and the gate structure, respectively, and an interconnect metal layer connected to the contacts.
  7. 7. The LDMOS device of claim 2, wherein the second drift region is an N-type epitaxial layer.
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CN106972047B true CN106972047B (en) 2020-01-31

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