CN114551574B - High-voltage single-particle reinforced LDMOS device - Google Patents
High-voltage single-particle reinforced LDMOS device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention provides a high-voltage single-particle reinforced LDMOS device, which comprises a P-type substrate, a deep N-type well region, a P-type buried layer, an N-type drift region, a P-type well region, a P+ injection of a source region, an N+ injection of a source region, a gate oxide layer, a Ptop injection of a source region, an N+ injection of a drain electrode and polysilicon. Below the safe BV, with the increase of Vth-SEB, the safety and reliability of the LDMOS system can be greatly improved.
Description
Technical Field
The invention relates to the field of semiconductor power devices, in particular to a high-voltage SEB-harded LDMOS device structure.
Background
With the widespread use of spacecraft in military and civil aerospace industries, more and more electronic devices are applied to space environments, such as a satellite-borne Beidou system, a satellite communication system, a remote sensing system and the like. When a spacecraft works in a cosmic space, radiation particles in a radiation environment have adverse radiation effects on electronic components on the spacecraft, so that higher requirements are put on the reliability of the spacecraft.
When the LDMOS device is applied to a switching power supply, an LDO and a charging circuit of a spacecraft, the LDMOS device is necessarily affected by disturbance irradiation. There are a large number of charged particles and cosmic rays in the space, and when the high-energy particle beam in the space "bombards" the device, high-density unbalanced electron-hole pairs are generated along the heavy ion trajectories and drift under the action of a strong electric field, and once the parasitic bipolar transistor is turned on, its positive feedback will result in a large current and a low voltage. If the transient current propagates through the combinational logic of the digital circuit and is latched in the memory element, the single event current may cause a single event disturbance.
The single event effect can be categorized into recoverable and non-recoverable. The single event upset, single event transient pulse, single event function interruption and the like belong to recoverable effects, and generally occur on a CMOS device, and the soft errors are insufficient to damage the device, so that normal operation can be recovered through means such as current limiting resistance, power supply reset and the like. While unrecoverable means that a single event causes physical damage or permanent functional damage to the device, such as a single event latch, single event burn-out and single event gate wear are two unrecoverable effects that occur on a power MOSFET.
A cross-sectional view of a conventional LDMOS device is shown in fig. 1. A P-type substrate 1 at the bottom is included; the deep N-type well region 2 is positioned at the upper right of the P-type substrate 1; a P-type buried layer 3 positioned at the left upper part of the P substrate 1; an N-type drift region 4 positioned on the right side of the P-type buried layer 3; the P-type well region 5 is positioned at the left upper part of the P-type buried layer 3; the source region P+ injection 7 is positioned at the left upper part of the P-type well region 5; source region n+ implant 8 located to the right of source region p+ implant 7; a gate oxide layer 9 positioned on the upper right of the P-type well region 5; a source region Ptop implant 10 located above the local buried oxide layer 6; a local field oxide layer 11 located above the Ptop implant 10; a drain n+ implant 12 located on the upper right of the local buried oxide layer 6; polysilicon 13 over gate oxide 9.
As shown in fig. 2, when a single particle is driven into the device, due to the existence of the voltage of the drain terminal and the substrate, the electron hole pairs on the incident track of the particle generate diffusion drift movement under the action of the electric field formed by the voltage, and finally, larger transient current is formed by collecting the electron hole pairs at the drain terminal. For single event transient pulses, it is important that the output of the drive circuit driven by the previous stage propagates to the input of the next stage, creating a so-called "glitch" that, when the pulse width of this "glitch" is sufficiently wide, can cause the circuit to malfunction.
As shown in fig. 3, a schematic view of single particle burnout is shown, when the device is in an off state, particles are driven into the device from the drain electrode, a large number of electron hole pairs are generated in the particle track, and according to the "funnel effect" theory, electrons initially move in the direction of the high potential electrode, and the holes move in the direction of the low potential to form a funnel. Over time, electron hole pairs diffuse to two sides of a particle track under the action of drain terminal voltage, current flows to a P well region, potential is generated between the P well and an N+ source, when the potential is high enough, the PN junction of the P well/the N+ source is forward biased, and meanwhile, due to the fact that the drain terminal is high in potential, an NPN parasitic transistor formed by an N drift region, the P well and the N+ source is in an amplifying state, and finally along with the increase of leakage current, the LDMOS device is burnt. Yet another possible explanation is that electron hole pairs on the particle trajectories impact ionization in the depletion region, causing avalanche breakdown of the device, eventually an excessive current flows through the device, eventually leading to thermal burnout of the device.
Fig. 4 shows a schematic diagram of single particle irradiation and heavy ion beam parameters. In order to analyze the response of LDMOS devices of different structures to heavy ion beam implantation, necessary simulations were performed using Sentaurus TCAD. In the simulation, the heavy ion beam was implanted using a gaussian distribution simulation, the characteristic radius of the gaussian distribution being 0.5 μm and the distribution range being 30 μm (the longitudinal length of the device being 100 μm). In order to accurately reflect the response mechanism under irradiation, all simulations used physical models of (1) doping dependent SRH recombination and auger recombination, (2) thermodynamic models, (3) temperature, doping, electric field and carrier-scattering effects on mobility; meanwhile, siO2 is considered as an equivalent semiconductor material considering the role of heavy ions in SiO 2. Experiments prove that the obtained simulation result is basically consistent with experimental data in the high-voltage transistor. The response of the LDMOS to SEB is largely dependent on the bias voltage of the drain and the LET of the heavy ions. As shown in FIG. 4, the mechanism of analysis of SEB was simpler and more intuitive, the LET of heavy ions was set to 0.2 pC/. Mu.m (1 pC/. Mu.m is about 96.53 MeV.cm 2/mg) and the incident direction of heavy ions was 90 DEG, varying with the drain voltage, while the incident range was also fixed at 30. Mu.m.
The drain current response of whether or not the SEB occurs after the heavy ion beam is incident from the conventional LDMOS drift region is shown in fig. 5. SEB is related to the LET orbitals of heavy ions and also to the bias conditions. From the orbital point of view, the sensitive location is in a region where the electric field is relatively high or fully depleted. The results indicate that the state where the LDMOS device is most sensitive to the SEB response is the OFF state. Thus, before performing the SEE simulation, the gate, source and substrate are placed on a common ground (0V), with reference to the device cross section of the conventional LDMOS in fig. 1. The drain is set to a relatively positive bias voltage from a low voltage to a high voltage with respect to ground. As shown in fig. 4, the heavy ion beam only generates transient currents when the drain voltage does not exceed 196V. When the SEE gradually disappears, the transient current decreases with the recombination of electron-hole pairs, and finally returns to the original state, which is called a safety response in the actual LDMOS circuit. However, impact ionization by the current-induced electric field occurs when the drain voltage reaches 197V and above. Impact ionization of the generated electron holes can turn on the fragile parasitic p-n-p transistor (T1), resulting in a large current of the lateral parasitic transistor (T1). Positive current feedback between T1 and T2 and avalanche breakdown by impact ionization inside the device will work together to generate a lot of heat, resulting in final device destruction.
Aiming at the problems, a high-voltage SEB-harded LDMOS device structure is provided.
Disclosure of Invention
The invention aims at that after single particle irradiation, for a traditional LDMOS device, positive feedback of a parasitic p-n-p-n (SCR) structure of a source and avalanche breakdown of a drain can cause burning of the whole device. In consideration of the randomness of single particle irradiation and the severity of SEB, a feasible SEB-hardided LDMOS structure is provided, and the safety and reliability of an LDMOS system can be greatly improved along with the increase of Vth-SEB below a safety BV. .
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a high-voltage single-particle reinforced LDMOS device comprises a P-type substrate 1 positioned at the bottom, a deep N-type well region 2 positioned at the right upper part of the P-type substrate 1, a P-type buried layer 3 positioned at the left upper part of the P-type substrate 1, an N-type drift region 4 positioned at the right side of the P-type buried layer 3, a P-type well region 5 positioned above the P-type buried layer 3, a source region P+ injection 7 positioned at the left upper part inside the P-type well region 5, a source region N+ injection 8 positioned at the right side of the source region P+ injection 7 inside the P-type well region 5, a gate oxide layer 9 positioned at the right upper part of the P-type well region 5, a source region Ptop injection 10 positioned above the N-type drift region 4, a local field oxide layer 11 positioned above the source region Ptop injection 10, a drain N-injection 14 positioned at the right upper part inside the deep N-type well region 2, a drain N+ injection 12 positioned at the right upper part of the N-type drift region 4, and a polysilicon layer 13 positioned above the gate oxide layer 9.
Preferably, the depth of the drain n+ implant 12 is shallower than the drain N-implant 14, the length of the drain n+ implant 12 in the horizontal direction is smaller than the drain N-implant 14, the horizontal direction is the direction parallel to the surface of the device, the N-drift region 4-drain N-implant 14-N-drift region 4 forms two diodes, the 2 diodes are connected by two anodes, and at the same time, the drain N-implant 14 and the drain n+ implant 12+ also form a new reverse diode from the N-drift region 4 to the channel, thereby reducing the possibility of avalanche breakdown, and at the same time, the drain N-implant 14 is located in the drain region and does not affect the channel, and therefore has no effect on the threshold voltage of the LDMOS.
Preferably, with the addition of N-doping, the threshold Vth-SEB for single particle reinforcement increases with increasing N-doping concentration, but when the N-doping concentration exceeds 1.17cm -3 When the concentration of the single particle reinforced threshold Vth-SEB increases, the threshold Vth-SEB is reduced; due to the introduction of N-doping, the original surface field structure is damaged, so that the breakdown voltage BV in the LDMOS is reduced along with the increase of N-concentration, the single-particle reinforced threshold Vth-SEB can be improved under the condition that the breakdown voltage BV of the LDMOS device in the working state is ensured, and the safety of the device is ensured.
The working principle of the invention is as follows: the invention reduces the possibility of avalanche breakdown by shortening the lateral width of the original N + doping of the drain region and adding N-doping in the prior art device, whereby the pn junction (Ndrift-n+) in the prior art device becomes two diodes (Ndrift-N-Ndrift) and has two positive connections, while at the same time N-N + can form a new reverse diode that drifts from the drain. Meanwhile, N-doping is located in the drain region and does not affect the channel, so that the threshold voltage of the LDMOS is not affected. For reliability and safety reasons, the N-doping concentration corresponding to the Vth-SEB maximum should be the best. At this concentration, the BV of the SEB-reinforced LDMOS was 569V, which is 13.7% lower than 660V of the conventional LDMOS. The BV can still maintain a high voltage 569V without irradiation, so it can be used in an operating environment above 500V, but once single particle irradiation occurs, the Vth-SEB of the LDMOS can be increased from 197V to 291V, and the safe operating voltage can be increased by 47.7%.
The beneficial effects of the invention are as follows: as shown in fig. 7, for the conventional LDMOS device, when the drain voltage is 197V and above, the p-n-p-n structure of the parasitic transistor is turned on, and the current is continuously increased until thermal burnout occurs. Meanwhile, under the action of a high electric field, collision ionization of injected carriers can cause avalanche breakdown of a drain region. For SEB-ruggedized LDMOS, a drain voltage of 290V or less may ensure the safety and reliability of the high-voltage LDMOS circuit. Although the BV of the LDMOS drops from 660V to 569V by 13.7%, the Vth-SEB increases from 197V to 291V by 47.7%. Once SEB occurs, the LDMOS will be destroyed. Considering the randomness of single irradiation and the severity of SEB, the safety of the LDMOS circuit is greatly improved under the safety BV.
Drawings
Fig. 1 is a cross-sectional view of a conventional LDMOS device;
FIG. 2 is a schematic view of the interior of a single particle driver device;
FIG. 3 is a schematic illustration of single particle burn-out;
FIG. 4 is a schematic diagram of single particle irradiation and heavy ion beam parameters;
FIG. 5 is a graph showing the drain current response of whether SEB occurs or not after a heavy ion beam is incident from a conventional LDMOS drift region;
FIG. 6 is a cross-sectional view of an SEB-harded LDMOS device of the present invention;
fig. 7 is a graph of the drain current response of whether or not SEB occurs after a heavy ion beam is incident from the SEB-harded LDMOS device drift region.
Wherein 1 is a P-type substrate, 2 is a deep N-type well region, 3 is a P-type buried layer, 4 is an N-type drift region, 5 is a P-type well region, 6 is a local buried oxide layer, 7 is a source region p+ implant, 8 is a source region n+ implant, 9 is a gate oxide layer, 10 is a source region Ptop implant, 11 is a local field oxide layer, 12 is a drain n+ implant, 13 is polysilicon, and 14 is a drain N-implant.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As shown in fig. 6, this embodiment provides a high-voltage single-particle reinforced LDMOS device, which includes a P-type substrate 1 at the bottom, a deep N-type well region 2 at the upper right of the P-type substrate 1, a P-type buried layer 3 at the upper left of the P-type substrate 1, an N-type drift region 4 at the right side of the P-type buried layer 3, a P-type well region 5 above the P-type buried layer 3, a source region p+ implant 7 at the upper left inside of the P-type well region 5, a source region n+ implant 8 at the right side of the p+ implant 7 inside the P-type well region 5, a depth of the deep N-type well region 2 is greater than a depth of the source region n+ implant 8, and further includes a gate oxide 9 at the upper right side of the P-type well region 5, a source region Ptop implant 10 at the upper inner side of the N-type drift region 4, a local field oxide 11 at the upper right side of the source region otop implant 10, a drain N-implant 14 at the upper right side of the ptn-type well region 2, a drain N-implant 14 at the upper right side of the N-type drift region 4, and a polysilicon layer 9 at the upper side of the gate oxide layer 13.
The depth of the drain n+ implant 12 is shallower than the drain N-implant 14, the length of the drain n+ implant 12 in the horizontal direction is smaller than the drain N-implant 14, the horizontal direction is the direction parallel to the surface of the device, the N-type drift region 4-drain N-implant 14-N-type drift region 4 forms two diodes, the 2 diodes have two positive poles connected, at the same time, the drain N-implant 14 and the drain n+ implant 12+ also form a new reverse diode from the N-type drift region 4 to the channel, thereby reducing the possibility of avalanche breakdown, and the drain N-implant 14 is located in the drain region and does not affect the channel, thus having no effect on the threshold voltage of the LDMOS.
With the addition of N-doping, the threshold Vth-SEB for single particle reinforcement increases with increasing N-doping concentration, but when N-doping concentration exceeds 1.17cm -3 When the concentration of the single particle reinforced threshold Vth-SEB increases, the threshold Vth-SEB is reduced; due to the introduction of N-doping, the original surface field structure is damaged, so that the breakdown voltage BV in the LDMOS is reduced along with the increase of N-concentration, the single-particle reinforced threshold Vth-SEB can be improved under the condition that the breakdown voltage BV of the LDMOS device in the working state is ensured, and the safety of the device is ensured.
Compared with the LDMOS with the conventional structure shown in fig. 1, the width of the original N+ doped transverse drain region is shortened, and one N-doping is added, so that the pn junction (Ndrift-N+) of the LDMOS is changed into two diodes (Ndrift-N-Ndrift), the two positive electrodes are connected, and meanwhile, the N-N+ can form a new reverse diode from the drift region to the drain region, so that the possibility of avalanche breakdown is reduced.
The conventional structure pn junction (Ndrift-N+) is changed into two diodes (Ndrift-N-Ndrift) by shortening the transverse width of the conventional structure drain region original N+ doping and adding N-doping, so that two positive poles are connected, and meanwhile, the N-N+ can form a new reverse diode which drifts to a sewer, thereby reducing the possibility of avalanche breakdown. Meanwhile, N-doping is located in the drain region and does not affect the channel, so that the threshold voltage of the LDMOS is not affected.
The Vth-SEB increases with increasing N-doping concentration as N-doping is added, but decreases with increasing concentration when N-doping concentration exceeds 1.17 cm-3. This is because it is difficult to form two reverse diodes between N-drift and N-drift when the concentration is too low and not much different from the doping concentration of the drift region, and it is also difficult to form a reverse diode between N-and n+ when the N-doping concentration is too high and not much different from the n+ doping concentration in the drain. In addition, due to the introduction of the N-doping, the original surface field structure is destroyed, resulting in a decrease in BV (breakdown voltage) in the LDMOS with an increase in the N-concentration. Therefore, it is necessary to find a balance point between BV and Vth-SEB.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims of this invention, which are within the skill of those skilled in the art, can be made without departing from the spirit and scope of the invention disclosed herein.
Claims (2)
1. The utility model provides a high-voltage single particle consolidates LDMOS device which characterized in that: the deep N-type well region (2) is positioned at the right upper part of the P-type substrate (1), the P-type buried layer (3) is positioned at the left upper part of the P-type substrate (1), the N-type drift region (4) is positioned at the right side of the P-type buried layer (3), the P-type well region (5) is positioned above the P-type buried layer (3), the source region P+ injection (7) is positioned at the left upper part inside the P-type well region (5), the source region N+ injection (8) is positioned at the right upper part inside the P-type well region (5), the depth of the deep N-type well region (2) is larger than the depth of the source region N+ injection (8), the deep N-type well region (2) is larger than the depth of the gate oxide layer (9) positioned at the right upper part of the P-type well region, the source region Ptop injection (10) is positioned at the inner upper part of the N-type drift region (4), the local field oxide layer (11) is positioned above the source region Ptop injection (10), the drain electrode N-injection (14) is positioned at the inner upper right upper part inside the P-type well region (5), the drain electrode N-injection (14) is positioned at the right upper part of the deep N-type well region (14) is positioned at the right upper part of the N-drain electrode (12), the drain electrode injection (12) is positioned at the right upper part of the drain electrode injection (12), the drain N-implant (14) is not directly below the drain N + implant (12).
2. The high voltage single-particle reinforced LDMOS device of claim 1, wherein: with the addition of N-doping, single particle additionThe fixed threshold Vth-SEB increases with increasing N-doping concentration, but when the N-doping concentration exceeds 1.17cm -3 When the concentration of the single particle reinforced threshold Vth-SEB increases, the threshold Vth-SEB is reduced; due to the introduction of N-doping, the original surface field structure is damaged, so that the breakdown voltage BV in the LDMOS is reduced along with the increase of N-concentration, the single-particle reinforced threshold Vth-SEB can be improved under the condition that the breakdown voltage BV of the LDMOS device in the working state is ensured, and the safety of the device is ensured.
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| JP4117385B2 (en) * | 2002-05-21 | 2008-07-16 | 独立行政法人 宇宙航空研究開発機構 | Semiconductor device having cosmic ray breakdown tolerance |
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