CN104078509A - Power MOS device with single-particle burnout resistance - Google Patents
Power MOS device with single-particle burnout resistance Download PDFInfo
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- 239000002245 particle Substances 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims description 11
- 229910044991 metal oxide Inorganic materials 0.000 claims description 10
- 150000004706 metal oxides Chemical class 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000001465 metallisation Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 13
- 230000003071 parasitic effect Effects 0.000 abstract description 13
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 230000005855 radiation Effects 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000000306 component Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000000191 radiation effect Effects 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000005260 alpha ray Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000005441 aurora Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005250 beta ray Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005025 nuclear technology Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to the technical field of power semiconductor devices, in particular to a power MOS device with the single-particle burnout resistance. According to the power MOS device with the single-particle burnout resistance, the current path of the device at normal work is avoided through a silicon dioxide dielectric layer located under a heavily-doped N-type source area, and therefore turn-on resistance of the device is not affected, and silicon dioxide does not affect the breakdown voltage of the device as the insulating dielectric layer in a P-type semiconductor base area. The power MOS device with the single-particle burnout resistance has the advantages that the peak value of instantaneous current generated in the high-energy particle bombardment process is greatly reduced; the irradiation current is effectively reduced; the lateral voltage generated in a Pbody area at high current density cannot turn on a parasitic bipolar transistor due to isolation of the silicon dioxide dielectric layer, and thus the current positive feedback effect is prevented from being formed to burn out the device.
Description
Technical field
The present invention relates to power semiconductor technical field, relate in particular to a kind of power MOS (Metal Oxide Semiconductor) device that anti-single particle burns ability that has.
Background technology
Power electronic system is the heart of space electronic system and nuclear electron system, and power electronic technology is the basis of all power electronic systems.VDMOS is the Important Components of power electronic system, and it provides the power supply of desired form and provide driving for motor device for electronic equipment.Almost all electronic equipments and motor device all need to use power VDMOSFET device.VDMOS device has can not be by the alternative premium properties of transverse conductance device, comprises high withstand voltage, low on-resistance, high-power, reliability etc.
Along with the fast development of aeronautical and space technology and nuclear technology, increasing electronic equipment will be applied in various radiation environments.These radiation environments sum up and can be divided into space radiation environment and the large class of man-made radiation environment two.Space radiation environment is mainly from cosmic ray, solar flare radiation, circumterrestrial inside and outside Van Allen belt, in addition also have solar wind, aurora, solar X-ray and the wider electromagnetic radiation of spectral range, mainly by high energy proton, high energy electron, X ray etc., formed.The radiation that man-made radiation environment mainly produces from nuclear power station, nuclear reactor, accelerator, nuclear weapon blast etc., is mainly comprised of alpha ray, β ray, neutron, gamma-rays, X ray, nuclear electromagnetic pulse etc.Microelectronic component is the elementary cell that forms electronic equipment at present, and even be core component, and semiconductor and microelectronic component are very responsive to these radiation, radiation effects is in electronic equipment, on its performance and function, can produce impact in various degree, even make its inefficacy.
In general, space radiation environment shows as three kinds of fundamental radiation effects to the impact of electronic devices and components function and performance: 1 total dose effect is to have an effect due to radiation ion and device material, produces electric charge and charge-site, affects device; 2 single particle effects are single particles while passing device, the impact of the High Density Charge producing on its track on device; 3 displacement damage effect are the effects due to particle, make atom in material structure or crystal lattice produce displacement, depart from its normal position, form defect center, and the secondary electron exciting with phonon that material effects produces, thereby affect device performance.
In space radiation environment, when high energy particle incident VDMOS device, can produce electronic stopping and core and stop.Core prevention causes by the lattice damage of irradiation material, and electronic stopping causes and is ionized by the composed atom of irradiation material, generation has hundreds of million-electron-volts or more high-octane secondary electron, and the track along secondary electron can produce a large amount of electron hole pairs again, under the double action of drift field and carrier diffusion, move to source electrode in the hole of these electron hole centerings, electronics is to drain electrode motion, form wink generating stream, if it is enough large to cross this electric current, can make the Pbody district generation of below, VDMOS device N+ source region is that parasitic bipolar transistor is opened and makes it work in magnifying state over the transverse electric pressure drop about 0.7V, if drain-source voltage reaches the puncture voltage BV of parasitic bipolar transistor
cEO, will there is avalanche multiplication effect in the collector electrode of parasitic bipolar transistor, and electric current sharply increases, and forms positive feedback, finally causes burning of VDMOS.Thereby reduce the resistance below VDMOS device N+ source region, increasing Pbody district concentration is to improve the effective ways that device anti-single particle burns.Traditional structure as shown in Figure 1, is considered the impact on device threshold, and Pbody district concentration can not be too large, and to the resistance that reduces below, VDMOS device N+ source region, without obvious effect, traditional structure does not substantially possess anti-single particle and burns ability.For the structure that has P+ to inject, as shown in Figure 2, add especially P+ inject to be exactly for reducing the resistance below VDMOS device N+ source region, but this needs the extra mask plate that increases, increased cost, and need the careful knot temperature and time of controlling, in case affect the doping content of channel region, cause the drift of threshold voltage.
Summary of the invention
Object of the present invention, it is exactly the problem existing for above-mentioned traditional devices structure, propose a kind of mask plate that neither additionally increases and increase cost, can not affect device electric property yet, and can eliminate the resistance of below, VDMOS device N+ source region, improve VDMOS device anti-single particle and burn the power MOS (Metal Oxide Semiconductor) device of ability.
Technical scheme of the present invention is, a kind of have a power MOS (Metal Oxide Semiconductor) device that anti-single particle burns ability, comprises N-type substrate 2, is positioned at the N-type epitaxial loayer 3 on N-type substrate 2 upper stratas; Described N-type substrate lower surface is provided with metallization drain electrode 1; The both sides on described N-type epitaxial loayer 3 upper stratas are respectively arranged with P type base 4; In described P type base 4, be provided with separate N-type source region 5 and P type tagma 6; P type base 4 upper surfaces between described N-type source region 5 and N-type epitaxial loayer 3, N-type epitaxial loayer 3 upper surfaces between P type base 4 are provided with gate oxide 7; Gate oxide 7 upper surfaces are provided with polysilicon gate 8; P type tagma 6 upper surfaces at two ends connect by metallizing source 10; Between metallizing source 10 and polysilicon gate 8, be provided with field oxide 9; It is characterized in that, described N-type source region 5 lower surfaces are provided with silica dioxide medium layer 12.
Concrete, described silica dioxide medium layer 12 is positioned at N-type source region 5 and is connected with P type tagma 6 lower surfaces and with metallizing source 10.
Beneficial effect of the present invention is, the electron hole pair number that high energy particle inspires in silica dioxide medium is far below the electron hole pair number inspiring in silicon, and this has just greatly reduced the transient current peak value that high-energy particle bombardment produces; Silica dioxide medium layer, for the electron hole pair that irradiation produces provides larger recombination probability, effectively reduces irradiation electric current; The impact of parasitic bipolar transistor in VDMOS device has been eliminated in the introducing of silica dioxide medium layer, the lateral voltage producing in Pbody district when high current density is not opened because the isolation of silica dioxide medium floor can not make parasitic bipolar transistor, prevents from forming positive current feedback effect and burns device.
Accompanying drawing explanation
Fig. 1 is the structural representation of traditional VDMOS device.
Fig. 2 is the VDMOS device architecture schematic diagram that has P+ (or N+) to inject;
Fig. 3 is the structural representation of embodiment 1;
Fig. 4 is the structural representation of embodiment 2;
Fig. 5 is puncture voltage traditional VDMOS device of being 100V level, have the parasitic bipolar transistor opening point of power MOS (Metal Oxide Semiconductor) device of VDMOS device that P+ (or N+) injects and embodiment 1, the simulation result figure of second breakdown point.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described
In the power MOS (Metal Oxide Semiconductor) device that the anti-single particle that the present invention proposes burns, by being positioned at the silica dioxide medium layer under heavy doping N-type source region, avoided current path when device is normally worked, therefore do not affect the conducting resistance of device, silicon dioxide does not affect the puncture voltage of device in P type semiconductor base yet as insulating medium layer simultaneously.
As shown in Figure 1, be the structural representation of traditional VDMOS device.Comprise the field oxide 9 between metallization drain electrode 1, heavy doping N (or P) type substrate 2, light dope extension N-(or P-) layer 3, P (or N) type semiconductor base 4, heavy doping N (or P) type source region 5, heavy doping P (or N) type tagma 6, gate oxide 7, polysilicon gate 8, metallizing source 10, polysilicon gate 8 and metallizing source 10.Traditional VDMOS device does not have the ability that anti-single particle burns.
As shown in Figure 2, be the VDMOS device architecture schematic diagram that has P+ (or N+) to inject.Comprise the field oxide 9 between metallization drain electrode 1, heavy doping N (or P) type substrate 2, light dope extension N-(or P-) layer 3, P (or N) type semiconductor base 4, heavy doping N (or P) type source region 5, heavy doping P (or N) type tagma 6, gate oxide 7, polysilicon gate 8, metallizing source 10, polysilicon gate 8 and metallizing source 10, be arranged in P (or N) type semiconductor base 4 and surround heavy doping N (or P) type source region 5 and heavy doping P (or N) type tagma 6 and from P (or N) type semiconductor base 4 lower surfaces, prolong heavily doped P (or N) the type semiconductor region 11 of bearing.Wherein the effect of heavy doping P (or N) type semiconductor region 11 is the resistance reducing under heavy doping N (or P) type source region, prevents that parasitic bipolar transistor from opening, and therefore, this structure has certain anti-single particle and burns ability.
Embodiment 1:
As shown in Figure 3, this example comprises heavy doping N type semiconductor substrate 2, be positioned at the metallization drain electrode 1 at heavy doping N type semiconductor substrate 2 back sides, be positioned at the light dope semiconductor epitaxial N-layer 3 in heavy doping N type semiconductor substrate 2 fronts, light dope semiconductor epitaxial N-layer 3 both sides, top have respectively a P type semiconductor base 4, in each P type semiconductor base 4, there is respectively a heavy doping N type semiconductor source region 5 and a heavy doping P type semiconductor tagma 6, the two contacts N-type heavily-doped semiconductor source region 5 and P type heavily-doped semiconductor tagma 6 with metallizing source 10, gate oxide 7 is covered in the surface of two P type semiconductor bases 4 and light dope extension N-layer 3, gate oxide upper surface is polysilicon gate 8, between polysilicon gate 8 and metallizing source 10, it is field oxide 9.In P type semiconductor base 4, under heavy doping N-type source region 5, be provided with silica dioxide medium layer 12.
This routine operation principle is:
In traditional VDMOS structure, under heavy doping N-type source region 5, introduce layer of silicon dioxide dielectric layer 12, this dielectric layer can play many-sided effect: (1) high energy particle inspires electron hole pair number far below the electron hole pair number inspiring in silicon in silica dioxide medium.Research shows, the combination of the electron hole pair of Si can be 3.6eV, SiO
2the combination of electron hole pair can be 17.0eV, 1rad (Si) dosage irradiation produces 4.0-4.2 * 10 in every cubic centimetre of Si
13to electron hole pair, 1rad (SiO
2) dosage irradiation is at every cubic centimetre of SiO
2middle generation 8.0-8.2 * 10
12to electron hole pair.Therefore, high energy particle in silica dioxide medium layer, inspire that electron hole pair number inspires in only having silicon 1/5th.(2) in silica dioxide medium layer, and there is the huge complex centre of quantity in the interface of silicon dioxide and silicon, can provide larger recombination probability and compound cross-section for the electron hole pair that irradiation produces, and effectively reduces irradiation electric current.SiO
2oxygen atom in Si, have three impurity energy levels: two acceptor levels, lay respectively at above valence band 0.38eV place below 0.35eV and conduction band, these two energy levels are near the deep energy levels that are positioned at the central authorities of Si forbidden band, are effective complex centre; A donor level, is positioned at 0.16eV place below conduction band.The huge complex centre of a large amount of impurity energy level quantity of formations, makes the electron hole pair producing at SiO
2in compound very fast.(3) impact of parasitic bipolar transistor has been eliminated in the introducing of silica dioxide medium layer to a great extent.In conventional VDMOS device due to the existence of resistance in Pbody district, the lateral voltage producing when high current density can make the PN junction conducting between P type semiconductor base and heavy doping N-type source region, simultaneously in the situation due to drain terminal high pressure, parasitic bipolar transistor is operated in amplification region, when drain terminal voltage reaches parasitic bipolar transistor puncture voltage BV
cEOtime, will there is avalanche multiplication effect in the collector electrode of parasitic bipolar transistor, and electric current sharply increases, and forms positive feedback, finally causes burning of VDMOS.And the resistance of below, heavy doping N-type source region has been eliminated in the introducing of silica dioxide medium layer, make this place's PN junction be difficult for conducting and finally cause device to burn.Therefore, the VDMOS structure with silica dioxide medium layer of this example has the anti-single particle higher than conventional structure and burns ability.As shown in Figure 5, puncture voltage is traditional VDMOS device of 100V level, the VDMOS device that has P+ (or N+) injection and the parasitic bipolar transistor opening point of this routine power MOS (Metal Oxide Semiconductor) device, the simulation result figure of second breakdown point, in figure, square is conventional structure, the circular structure for there being P+ to inject, triangle is this routine new construction.Can be with respect to traditional structure and the structure that has P+ to inject, this routine structure has obviously reduced irradiation electric current.
Embodiment 2:
As shown in Figure 4, this routine difference from Example 1 is, the metallizing source 10 that is covered in device upper surface is filled metal by cutting in silicon makes metallizing source contact with silica dioxide medium layer 12, heavy doping P type semiconductor tagma 6 and heavy doping N-type source region 5.This routine operation principle is identical with embodiment 1, but have more electric current when large electric current, from metallizing source 10, flows out, and has further improved the burn-out resistance of device.
The solution of the present invention is applicable to P raceway groove VDMOS device simultaneously, makes it have anti-single particle and burns ability.Described semiconductor adopts body silicon, carborundum, GaAs, indium phosphide or germanium silicon.
The present invention proposes has the power MOS (Metal Oxide Semiconductor) device that anti-single particle burns, and its implementation and conventional VDMOS device are similar, just need to increase the preparation process of silica dioxide medium layer 12.Wherein the preparation process of silica dioxide medium layer 12 is increased in after P (or N) type semiconductor base Implantation and high temperature pushes away trap, and Implantation carries out before forming heavy doping N (or P) type source region.Concrete mode can adopt O +ion implanted, and the mode that suitably pushes away trap forms and buries oxide layer in P (or N) type semiconductor base 4, under heavy doping N (or P) type source region 5, and silica dioxide medium layer 12.
Claims (2)
1. there is the power MOS (Metal Oxide Semiconductor) device that anti-single particle burns ability, comprise N-type substrate (2), be positioned at the N-type epitaxial loayer (3) on N-type substrate (2) upper strata; Described N-type substrate lower surface is provided with metallization drain electrode (1); The both sides on described N-type epitaxial loayer (3) upper strata are respectively arranged with P type base (4); In described P type base (4), be provided with separate N-type source region (5) and P type tagma (6); P type base (4) upper surface between described N-type source region (5) and N-type epitaxial loayer (3), N-type epitaxial loayer (3) upper surface between P type base (4) are provided with gate oxide (7); Gate oxide (7) upper surface is provided with polysilicon gate (8); P type tagma (6) upper surface at two ends connects by metallizing source (10); Between metallizing source (10) and polysilicon gate (8), be provided with field oxide (9); It is characterized in that, described N-type source region (5) lower surface is provided with silica dioxide medium layer (12).
2. a kind of power MOS (Metal Oxide Semiconductor) device that anti-single particle burns ability that has according to claim 1, it is characterized in that, described silica dioxide medium layer (12) is positioned at N-type source region (5) and is connected with P type tagma (6) lower surface and with metallizing source (10).
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111129119A (en) * | 2019-12-30 | 2020-05-08 | 北京工业大学 | Single-particle reinforced device structure of silicon carbide MOS and preparation method thereof |
| CN113471293A (en) * | 2021-07-19 | 2021-10-01 | 北京工业大学 | Super junction MOS device structure capable of resisting single event burnout |
| CN113497112A (en) * | 2020-03-19 | 2021-10-12 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor, intelligent power device and electronic product |
| CN114005813A (en) * | 2021-11-15 | 2022-02-01 | 中国电子科技集团公司第五十八研究所 | Radiation-resistant reinforced high-voltage MOSFET device |
| CN114551601A (en) * | 2022-04-26 | 2022-05-27 | 成都蓉矽半导体有限公司 | Silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) of integrated grid-controlled diode with high surge current resistance |
| WO2023071108A1 (en) * | 2021-11-01 | 2023-05-04 | 无锡华润上华科技有限公司 | Laterally diffused metal oxide semiconductor device and fabrication method therefor |
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| CN102969316A (en) * | 2012-11-20 | 2013-03-13 | 电子科技大学 | Single-particle radiation resistant MOSFET device and preparation method thereof |
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| US5268586A (en) * | 1992-02-25 | 1993-12-07 | North American Philips Corporation | Vertical power MOS device with increased ruggedness and method of fabrication |
| CN102097478A (en) * | 2010-12-19 | 2011-06-15 | 电子科技大学 | Extremely-low on resistance shallow slot buried channel VDMOS (vertical double diffusion metal oxide semiconductor) device |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111129119A (en) * | 2019-12-30 | 2020-05-08 | 北京工业大学 | Single-particle reinforced device structure of silicon carbide MOS and preparation method thereof |
| CN111129119B (en) * | 2019-12-30 | 2023-04-21 | 北京工业大学 | Single particle reinforcement device structure of silicon carbide MOS and preparation method thereof |
| CN113497112A (en) * | 2020-03-19 | 2021-10-12 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor, intelligent power device and electronic product |
| CN113471293A (en) * | 2021-07-19 | 2021-10-01 | 北京工业大学 | Super junction MOS device structure capable of resisting single event burnout |
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Application publication date: 20141001 |