CN114005813A - Radiation-resistant reinforced high-voltage MOSFET device - Google Patents
Radiation-resistant reinforced high-voltage MOSFET device Download PDFInfo
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- CN114005813A CN114005813A CN202111349127.0A CN202111349127A CN114005813A CN 114005813 A CN114005813 A CN 114005813A CN 202111349127 A CN202111349127 A CN 202111349127A CN 114005813 A CN114005813 A CN 114005813A
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- 230000005855 radiation Effects 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 239000007943 implant Substances 0.000 claims 1
- 239000002245 particle Substances 0.000 abstract description 31
- 230000003071 parasitic effect Effects 0.000 abstract description 17
- 230000000694 effects Effects 0.000 abstract description 13
- 230000001976 improved effect Effects 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 9
- 238000000605 extraction Methods 0.000 abstract description 4
- 238000009826 distribution Methods 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000001052 transient effect Effects 0.000 description 7
- 230000003471 anti-radiation Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000004088 simulation Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 238000005510 radiation hardening Methods 0.000 description 3
- 230000001960 triggered effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention discloses a radiation-resistant reinforced high-voltage MOSFET device, which belongs to the field of semiconductors.A P-type second heavily doped region is arranged below a P-type well region, and the P-type second heavily doped region is arranged at the upper interface of a buried oxide layer and does not influence the concentration distribution of an N-type drift region and a P-type well region nearby the N-type drift region, so that the device has the same voltage resistance with other NMOS devices in process integration, and can meet the application requirements of circuits. The base resistance of the parasitic NPN triode is reduced by the P-type second heavily doped region and the P-type third heavily doped region below the source electrode of the device, the starting threshold of the parasitic triode of the device in a single-particle radiation environment is improved, and the single-particle burnout effect of the device is avoided. The P-type first heavily doped region and the source N-type heavily doped region which are in body contact with the device adopt a short-circuit structure, so that the extraction path of hole current generated by single particles is shortened, and the single particle burnout resistance of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a radiation-resistant reinforced high-voltage MOSFET device.
Background
In a radiation environment, compared with a low-voltage integrated circuit, a high-voltage MOSFET device of the high-voltage integrated circuit is easier to generate a single event effect due to higher working voltage and larger inductive and capacitive loads. In a gate driver, a high voltage MOSFET device is used to provide an output current. For high voltage devices, the single event effects of most concern are single event burnout and single event gate-through effects. When the MOSFET is biased in the off state, heavy ions can induce a destructive single-particle burnout effect through impact on the MOSFET. When ions are incident into a MOSFET device, a large number of electron-hole pairs are generated and a transient current is formed under the dual action of drift and diffusion. When the voltage drop of the transient current across the well resistor increases to a certain value, the parasitic bipolar transistor inherent in the MOSFET structure turns on and positive feedback occurs and is maintained, eventually resulting in device damage.
Avalanche generated holes returning from the base/collector region are critical to maintaining a positive feedback process that can result in high current and high voltage. Therefore, in order to make the chip work normally in a severe irradiation environment, the integrated circuit must be reinforced against single particles.
Disclosure of Invention
The invention aims to provide an anti-radiation reinforced high-voltage MOSFET device to solve the problem that a traditional high-voltage device is easy to generate a single-event burnout effect.
In order to solve the technical problem, the invention provides a radiation-resistant reinforced high-voltage MOSFET device which comprises a P-type substrate, a P-type well region, a P-type first heavily doped region, a P-type third heavily doped region, an N-type drift region, an N-type heavily doped region, a gate oxide layer and grid polysilicon;
the P-type well region is positioned above the P-type substrate, and a buried oxide layer and/or a P-type second heavily doped region are/is arranged between the P-type well region and the P-type substrate;
the P-type first heavily doped region is positioned above the P-type well region, and the P-type third heavily doped region is positioned above the inner part of the P-type well region;
the N-type drift region is arranged on the surface of the drain end of the P-type well region, and the N-type heavily doped region is respectively arranged on the upper surfaces of the P-type well region and the N-type drift region;
the gate oxide layer is located on the upper interface of the P-type trap area, and the gate polycrystalline silicon is arranged on the top of the gate oxide layer.
Optionally, the P-type first heavily doped region and the N-type heavily doped region are shorted, and are overlapped on the upper surface of the P-type well region.
Optionally, the P-type first heavily doped region is disposed perpendicular to the gate polysilicon.
Optionally, when a buried oxide layer and a P-type second heavily doped region are disposed between the P-type well region and the P-type substrate, the buried oxide layer is located above the P-type substrate, the P-type second heavily doped region is located above the buried oxide layer, and the P-type well region is located above the P-type second heavily doped region.
Optionally, the implantation dose range of the P-type second heavily doped region and the P-type third heavily doped region is 1E12cm-2~1E16cm-2。
In the radiation-resistant reinforced high-voltage MOSFET device provided by the invention, the P-type second heavily-doped region is arranged below the P-type well region, and the concentration distribution of the N-type drift region and the P-type well region nearby the N-type drift region is not influenced by the P-type second heavily-doped region at the upper interface of the buried oxide layer, so that the device has the same voltage resistance with other NMOS devices in process integration, and the application requirement of a circuit can be met. The base resistance of the parasitic NPN triode is reduced by the P-type second heavily doped region and the P-type third heavily doped region below the source electrode of the device, the starting threshold of the parasitic triode of the device in a single-particle radiation environment is improved, and the single-particle burnout effect of the device is avoided. The P-type first heavily doped region and the source N-type heavily doped region which are in body contact with the device adopt a short-circuit structure, so that the extraction path of hole current generated by single particles is shortened, and the single particle burnout resistance of the device is improved. The reinforcement technology provided by the invention can also be applied to a bulk silicon high-voltage process and a PMOS device, and the single-particle burnout resistance of the anti-radiation device is improved through a p-type ion implantation process and layout design.
Drawings
FIG. 1 is a schematic structural diagram of a radiation-hardened high-voltage MOSFET device provided by the present invention;
FIG. 2 is a schematic structural diagram of a second embodiment of a radiation-hardened high-voltage MOSFET device provided in accordance with the present invention;
FIG. 3 is a schematic structural diagram of a third embodiment of a radiation-hardened high-voltage MOSFET device provided in accordance with the present invention;
FIG. 4 is a schematic structural diagram of a fourth embodiment of a radiation-hardened high-voltage MOSFET device provided in accordance with the present invention;
FIG. 5 is a schematic diagram showing the simulation results of the leakage current and the lattice temperature generated by the single particle radiation in the off-state condition of the conventional high-voltage device and the anti-radiation reinforced high-voltage MOSFET device provided by the present invention;
fig. 6 is a schematic diagram of a simulation result of a single-event burnout threshold voltage of a conventional high-voltage device and an anti-radiation hardened high-voltage MOSFET device provided by the present invention in an off state.
Detailed Description
The present invention provides a radiation hardened high voltage MOSFET device, which is described in further detail below with reference to the accompanying drawings and embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a radiation-resistant reinforced high-voltage MOSFET device, the structure of which is shown in figure 1, and the device comprises a P-type substrate 11, a buried oxide layer 21, a P-type well region 31, a P-type first heavily doped region 32, a P-type second heavily doped region 33, a P-type third heavily doped region 34, an N-type drift region 41, an N-type heavily doped region 42, a gate oxide layer 22 and gate polysilicon 52.
The buried oxide layer 21 is located above the P-type substrate 11, the P-type second heavily doped region 33 is located above the buried oxide layer 21, and the P-type well region 31 is located above the P-type second heavily doped region 33; the P-type third heavily doped region 34 is located above the inside of the P-type well region 31; the N-type drift region 41 is arranged on the surface of the drain end of the P-type well region 31, and the N-type heavily doped region 42 is respectively arranged on the upper surfaces of the P-type well region 31 and the inside of the N-type drift region 41; the P-type first heavily doped region 32 is located above the P-type well region 31 and in the N-type heavily doped region 42; the gate oxide layer 22 is located at the upper interface of the P-type well region 31, and the gate polysilicon 52 is arranged on the top of the gate oxide layer 22.
The working principle of the invention is as follows: when the high-voltage device is in a single-particle irradiation environment, the P-type second heavily doped region 33 and the P-type third heavily doped region 34 increase the base region concentration of a parasitic NPN triode of the NMOS device, reduce the base region resistance of the parasitic NPN triode of the NMOS device, and reduce the emitter junction voltage drop of the parasitic NPN triode for given single-particle radiation generated current, so that the starting threshold of the parasitic triode is improved, and the single-particle burnout effect of the device is avoided. The P-type first heavily doped region 32 is in short circuit with the N-type heavily doped region 42, so that the holes generated in a single-particle radiation environment are accelerated to be quickly extracted, the parasitic triodes are prevented from being triggered and burnt in advance due to overhigh bias voltage, and the single-particle burning resistance of the device is improved.
As shown in fig. 2, it is a second embodiment of the radiation hardening high voltage device, wherein the P-type first heavily doped region 32 is disposed perpendicular to the gate polysilicon 52, parallel to the channel and current direction, and shorted to the N-type heavily doped region 42. Under the single-particle irradiation environment, the hole current generated is extracted, and the single-particle burning effect of the device in advance is avoided.
As shown in fig. 3, the third embodiment of the radiation hardening high voltage device is provided, wherein the P-type second heavily doped region 33 is not formed in the P-type well region 31, so as to reduce the manufacturing cost of the device. The radiation-resistant reinforced high-voltage MOSFET device comprises a P-type substrate 11, a buried oxide layer 21, a P-type well region 31, a P-type first heavily doped region 32, a P-type third heavily doped region 34, an N-type drift region 41, an N-type heavily doped region 42, a gate oxide layer 22 and gate polysilicon 52. Aiming at different single-particle radiation capability requirements, the P-type second heavily doped region 33 is not selected, so that the photoetching is reduced, and an epitaxial process is not needed, thereby reducing the process manufacturing cost.
As shown in fig. 4, it is a fourth embodiment of the radiation hardening high voltage device, in which the P-type second heavily doped region 33 and the P-type well region 31 are sequentially disposed directly on the P-type substrate 11. The radiation-resistant reinforced high-voltage MOSFET device comprises a P-type substrate 11, a P-type well region 31, a P-type first heavily doped region 32, a P-type second heavily doped region 33, a P-type third heavily doped region 34, an N-type drift region 41, an N-type heavily doped region 42, a gate oxide layer 22 and gate polysilicon 52. Under the single-particle irradiation environment, the base resistance of a parasitic triode of the high-voltage device is reduced by the P-type second heavily doped region 33 and the P-type third heavily doped region 34, and meanwhile, the hole current extraction generated by single-particle radiation is accelerated by the P-type first heavily doped region 32, so that the single-particle burnout resistance of the device is improved.
As shown in fig. 5, in the case of the conventional high-voltage device and the anti-radiation hardened high-voltage device provided by the present invention, the leakage current and the lattice temperature simulation result generated by the single-particle radiation are obtained. The device is shown biased in the off state in fig. 5, with the drain voltage Vds = 20V. When LET =100 MeV ∙ cm2The high-energy ions of/mg are incident into the device, and a large amount of transient current is generated inside the device. Parasitic bipolar transistors may be triggered if a transient current passes through the sensitive region. For the traditional structure, the leakage current is kept at 6.44mA, and the temperature of the crystal lattice is continuously increased to 1600K in the transient process, which indicates that the traditional device has a single-particle burning effect. However, the ruggedized device produced a transient leakage current of up to 1.76mA and a lattice temperature of up to 337K, both returning to their original states as the transient time increased, and no burn-out effect occurred in the device. Therefore, the reinforced device has better single event burnout resistance.
FIG. 6 shows the single-event burnout threshold for the conventional high-voltage device and the anti-radiation hardened high-voltage device provided by the present invention in the off stateAnd (5) voltage simulation results. In fig. 6, the conventional device is shown at LET =100 MeV ∙ cm2At/mg, the single particle burnout resistance is poor, and the working voltage is only 15V. In contrast, when the LET value is from 30MeV ∙ cm2Increase in mg to 100MeV ∙ cm2And in the case of/mg, the single-particle burning threshold of the reinforced device exceeds 25V. Therefore, the reinforcing device has a higher single-particle burnout threshold value, and compared with the traditional device, the single-particle burnout resistance of the reinforcing device is greatly improved.
According to the radiation-resistant reinforced high-voltage device, the P-type second heavily doped region 33 is introduced into the upper interface of the buried oxide layer 21 and below the P-type well region 31, the P-type third heavily doped region 34 is introduced into the lower side of the N heavily doped region 42, the base region concentration of a parasitic NPN triode of an NMOS device is increased, the parasitic resistance of the NMOS device is reduced, and higher base current bias is required for starting the parasitic NPN triode, so that the starting threshold of the parasitic triode is improved, and the single-event burnout effect of the device is avoided. The P-type first heavily doped region 32 is in short circuit with the N-type heavily doped region 42, under the action of bias voltage, electrons generated by single-particle radiation are quickly extracted, meanwhile, the extraction of hole current is accelerated, the parasitic triode is prevented from being triggered in advance due to overhigh bias voltage, and the single-particle burnout resistance of the device is improved. For integrated circuits with different working voltages, the P-type second heavily doped region 33 and the P-type third heavily doped region 34 can adopt different process injection conditions to prevent the device from generating single event burnout effect.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (5)
1. The radiation-resistant reinforced high-voltage MOSFET device is characterized by comprising a P-type substrate (11), a P-type well region (31), a P-type first heavily doped region (32), a P-type third heavily doped region (34), an N-type drift region (41), an N-type heavily doped region (42), a gate oxide layer (22) and gate polysilicon (52);
the P-type well region (31) is positioned above the P-type substrate (11), and a buried oxide layer (21) and/or a P-type second heavily doped region (33) are/is arranged between the P-type well region (31) and the P-type substrate (11);
the P-type first heavily doped region (32) is positioned above the P-type well region (31), and the P-type third heavily doped region (34) is positioned above the inner part of the P-type well region (31);
the N-type drift region (41) is arranged on the surface of the drain end of the P-type well region (31), and the N-type heavily doped region (42) is respectively arranged on the upper surfaces of the P-type well region (31) and the N-type drift region (41);
the gate oxide layer (22) is located on the upper interface of the P-type well region (31), and the gate polycrystalline silicon (52) is arranged on the top of the gate oxide layer (22).
2. The radiation-hardened high-voltage MOSFET device as claimed in claim 1, wherein the first heavily doped P-type region (32) and the heavily doped N-type region (42) are shorted and overlap at the upper surface of the P-type well region (31).
3. The radiation-hardened high-voltage MOSFET device as claimed in claim 1, wherein the first heavily doped region (32) of P-type is arranged perpendicular to the gate polysilicon (52).
4. The radiation-hardened high-voltage MOSFET device according to claim 1, wherein the buried oxide layer (21) is located above the P-type substrate (11), the P-type second heavily doped region (33) is located above the buried oxide layer (21), and the P-type well region (31) is located above the P-type second heavily doped region (33) when the buried oxide layer (21) and the P-type second heavily doped region (33) are located between the P-type well region (31) and the P-type substrate (11).
5. Radiation hardened high voltage MOSFET device according to claim 4 characterized in that the second heavily doped region (33) of P type and the third heavily doped region of P typeThe implant dose range of region (34) is 1E12cm-2~1E16cm-2。
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111349127.0A CN114005813A (en) | 2021-11-15 | 2021-11-15 | Radiation-resistant reinforced high-voltage MOSFET device |
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| CN202111349127.0A CN114005813A (en) | 2021-11-15 | 2021-11-15 | Radiation-resistant reinforced high-voltage MOSFET device |
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