CN113471293A - Super junction MOS device structure capable of resisting single event burnout - Google Patents
Super junction MOS device structure capable of resisting single event burnout Download PDFInfo
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 53
- 238000002955 isolation Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000002245 particle Substances 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims 2
- 238000007254 oxidation reaction Methods 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000008901 benefit Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000002035 prolonged effect Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000001808 coupling effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The invention relates to the field of power semiconductors, in particular to a single-particle burnout resistant super-junction MOS device structure which comprises source metal, drain metal, a substrate, a buffer layer, N columns, P columns, a connecting block group, a gate group, an isolation oxide layer and a gate oxide layer, wherein one end of the substrate is in contact with the drain metal, the other end of the substrate is in contact with the buffer layer, two P columns are arranged between the two P columns and are respectively in contact with the two P columns, one ends of the two P columns and the N columns are respectively in contact with the buffer layer, the connecting block group is symmetrically arranged, one connecting block is respectively in contact with the source metal, the isolation oxide layer and the other end of one P column, the other connecting block is respectively in contact with the source metal, the isolation oxide layer and the other end of the other P column, the other end of the N column is respectively in contact with the two connecting block groups and the isolation oxide layer, the gate group and the gate oxide layer are arranged between the source metal and the isolation oxide layer.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the field of power semiconductors, in particular to a super junction MOS device structure capable of resisting single event burnout.
[ background of the invention ]
A power MOSFET is a unipolar semiconductor device for energy processing. The circuit has the advantages of high input impedance, low loss, high switching speed, good frequency characteristic and the like. The power supply management system is widely applied to power supply management of aerospace power supply systems such as spacecrafts, space stations and satellite navigation. As an electronic switching device, the high-voltage power supply has wide application prospect in a power system. Power devices typically require higher breakdown voltages and lower conduction resistances, but power MOSFETs suffer from a "silicon limit" problem of Ron, sp ∞ VB 2.5. Thus as the breakdown voltage of the device increases, the conduction loss increases accordingly. The appearance of the super junction structure breaks through the traditional silicon limit and limits the application of the power MOSFET in the high-voltage high-power field. That is, as the breakdown voltage increases, the conduction resistance is greatly reduced, greatly reducing the power loss of the device. The super junction MOS has excellent electrical characteristics and is an ideal power switch device in a high-power system.
In recent years, space radiation environments are complicated and device lifetimes are severely affected due to the presence of a variety of heavy ions and rays. The power device is widely applied to the field of space military, which puts higher requirements on the reliability of the power device in special environments. The Single Event Effect (SEE) is one of permanent failure mechanisms of the MOS device under the space irradiation environment, and the Single Event Burnout (SEB) is one of main types causing permanent damage of the device in the single event effect, and is caused by heavy ion impact on the device in a blocking state. Electron-hole pairs are generated along the incident path of the heavy ions. The parasitic bipolar transistor is formed by the n-source, p-body and n-drift regions inherent to a VDMOS power transistor. If the resulting carrier current causes a voltage drop and turns on a parasitic Bipolar Junction Transistor (BJT), which is inherent in field effect transistor structures, carrier multiplication occurs, resulting in excessive current flow and thus thermal damage.
Therefore, the prior art is not sufficient and needs to be improved.
[ summary of the invention ]
In order to overcome the technical problem, the invention provides a super junction MOS device structure capable of resisting single event burnout.
The invention provides a super-junction MOS device structure capable of resisting single-particle burnout, which comprises source metal, drain metal, a substrate, a buffer layer, N columns, P columns, a connecting block group, a gate group, an isolation oxide layer and a gate oxide layer, wherein one end of the substrate is contacted with the drain metal, the other end of the substrate is contacted with the buffer layer, the number of the P columns is two, the N columns are arranged between the two P columns and are respectively contacted with the two P columns, one ends of the two P columns and the N columns are respectively contacted with the buffer layer, the connecting block group is provided with two and are symmetrically arranged, one connecting block is respectively contacted with the source metal, the isolation oxide layer and the other end of one P column, the other connecting block is respectively contacted with the source metal, the isolation oxide layer and the other end of the other P column, the other end of the N column is respectively contacted with the two connecting block groups and the isolation oxide layer, the gate group and the gate oxide layer are arranged between the source metal and the isolation oxide layer, the gate group is respectively contacted with the gate oxide layer and the isolation oxide layer, the gate oxide layer is also respectively contacted with the isolation oxide layer and the source metal, and the isolation oxide layer is contacted with the source metal.
Preferably, the gate group includes a first gate and a second gate, the first gate and the second gate are arranged at an interval, the first gate is respectively in contact with the gate oxide and the isolation oxide, and the second gate is respectively in contact with the gate oxide and the isolation oxide.
Preferably, the connection region group includes a P well region, a P + well region and an N + active region, the P well region is in contact with the P + well region, the N + active region, the P pillar, the N pillar and the isolation oxide layer, the P + well region is in contact with the source metal and the N + active region, and the N + active region is in contact with the source metal and the isolation oxide layer.
Preferably, the source metal comprises a connecting portion and two protruding portions, the two protruding portions are respectively connected to two ends of the connecting portion, the protruding direction faces the drain metal, one side, close to the drain metal, of each protruding portion is in contact with the connecting block, and the inner sides of the protruding portions are in contact with the gate oxide layer and the isolation oxide layer respectively.
Preferably, the buffer layer is doped in an N type, the doping element is a P element, and the doping concentration is 1 × 1016～5×1016/cm-3The thickness is 5-50 μm.
Preferably, the distance between the first grid and the second grid is 0.5-2 μm.
Preferably, the source metal and the drain metal are both aluminum.
Preferably, the gate oxide layer and the isolation oxide layer are both made of silicon dioxide.
Preferably, the thickness of the gate oxide layer is 50-150nm, and the thickness of the isolation oxide layer is 50-150 nm.
Compared with the prior art, the super junction MOS device structure resisting single event burnout has the following advantages:
by additionally arranging the buffer layer, high-low junction avalanche on the back surface is effectively inhibited, the single-event burnout resistance is improved, the permanent failure probability of the super-junction MOS device structure resisting the single-event burnout due to the single-event burnout effect is favorably reduced, the service life of the device is favorably prolonged, the enterprise cost expenditure is favorably saved, and further the production benefit of an enterprise is favorably enlarged.
By adopting the grid group, wherein the grid group is the first grid and the second grid which are arranged at intervals, the thickness of the grid oxide layer between the first grid and the second grid is increased, the possibility that a large number of cavities are accumulated on the lower surface of the grid oxide layer due to the incidence of heavy particles so that the grid oxide layer is easily broken down is effectively reduced, the single-particle-penetration-resisting capability of the super-junction MOS device structure resisting the single-particle burning is improved, and the service life of the device is further prolonged; meanwhile, due to the adoption of the structure of the first grid electrode and the second grid electrode which are arranged at intervals, the coupling effect of the grid electrode and the drain electrode is reduced, the Miller capacitance Cgd is greatly reduced, the switching of the device is effectively reduced, and the switching speed of the device is increased.
[ description of the drawings ]
Fig. 1 is a specific structural diagram of the super junction MOS device structure resistant to single event burnout according to the present invention.
Description of reference numerals:
10. the super junction MOS device structure is resistant to single event burnout; 11. a source metal; 12. a drain metal; 13. a substrate; 14. a buffer layer; 15. an N column; 16. a P column; 17. connecting the block groups; 18. a gate group; 19. isolating the oxide layer; 20. a gate oxide layer; 181. a first gate electrode; 182. a second gate electrode; 111. a connecting portion; 112. a boss portion; 171. a P well region; 172. a P + well region; 173. an N + active region.
[ detailed description ] embodiments
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, the present invention provides a single-particle burnout resistant super junction MOS device structure 10, which includes a source metal 11, a drain metal 12, a substrate 13, a buffer layer 14, N pillars 15, P pillars 16, a connection block 17, a gate block 18, an isolation oxide layer 19, and a gate oxide layer 20, one end of the substrate 13 is in contact with the drain metal 12, the other end is in contact with the buffer layer 14, two P pillars 16 are provided, the N pillar 15 is disposed between the two P pillars 16 and is in contact with the two P pillars 16, one end of each of the two P pillars 16 and the N pillar 15 is in contact with the buffer layer 14, the connection block 17 is symmetrically provided, one connection region is in contact with the source metal 11, the isolation oxide layer 19, and the other end of each of the two P pillars 16, the other connection region is in contact with the source metal 11, the isolation oxide layer 19, and the other end of each of the other P pillar 16, the other end of the N pillar 15 is in contact with the two connection block 17 and the isolation oxide layer 19, the gate group 18 and the gate oxide layer 20 are arranged between the source metal 11 and the isolation oxide layer 19, the gate group 18 is respectively contacted with the gate oxide layer 20 and the isolation oxide layer 19, the gate oxide layer 20 is also respectively contacted with the isolation oxide layer 19 and the source metal 11, and the isolation oxide layer 19 is contacted with the source metal 11.
Preferably, the gate oxide layer 20 is made of silicon dioxide with a thickness of 50-150nm, and the isolation oxide layer 19 is made of silicon dioxide with a thickness of 50-150 nm.
Preferably, the buffer layer 14 is doped N-type, the doping element is P-type, and the doping concentration is 1 × 1016～5×1016/cm-3The thickness is 5-50 μm.
Further, the gate group 18 includes a first gate 181 and a second gate 182, the first gate 181 and the second gate 182 are disposed at an interval, the first gate 181 is in contact with the gate oxide 20 and the isolation oxide 19, respectively, and the second gate 182 is in contact with the gate oxide 20 and the isolation oxide 19, respectively.
Preferably, the spacing between the first gate 181 and the second gate 182 is 0.5-2 μm.
Preferably, the first gate 181 and the second gate 182 are both made of polysilicon and doped N-type, the doping element is P element, and the doping concentration is 1 × 1019～1×1020 /cm-3。
Further, the source metal 11 includes a connection portion 111 and two protruding portions 112, the two protruding portions 112 are respectively connected to two ends of the connection portion 111, the protruding direction of the two protruding portions 112 faces the drain metal 12, one side of the protruding portion 112 close to the drain metal 12 is in contact with the connection area group 17, and the inner side of the protruding portion 112 is in contact with the gate oxide 20 and the isolation oxide 19.
Preferably, the material of the source metal 11 and the drain metal 12 is aluminum.
Preferably, the P-pillar 16 has a doping concentration of 1 × 1014～1×1016/cm-3The thickness is 10-150 μm; doping concentration of N column 15Is 1 × 1014～1×1016/cm-3The thickness is 10-150 μm.
Further, the connection region group 17 includes a P well region 171, a P + well region 172, and an N + active region 173, the P well region 171 is in contact with the P + well region 172, the N + active region 173, the P pillar 16, the N pillar 16, and the isolation oxide layer 19, the P + well region 172 is in contact with the source metal 11 and the N + active region 173, and the N + active region 173 is in contact with the source metal 11 and the isolation oxide layer 19.
Preferably, the P-well region 171 is P-type doped with B element as doping element and has a doping concentration of 1 × 1017～5×1017/cm-3The thickness of the film is 2-4 mu m; the doping concentration of the P + well region 172 is 1 × 1018～5×1020/cm-3The thickness is 10-150 μm.
Preferably, the N + active region 173 is doped N-type, the doping element is As element, and the doping concentration is 1 × 1019～1×1020/cm-3The thickness is 2-6 μm.
Compared with the prior art, the super junction MOS device structure resisting single event burnout has the following advantages:
by additionally arranging the buffer layer, high-low junction avalanche on the back surface is effectively inhibited, the single-event burnout resistance is improved, the permanent failure probability of the super-junction MOS device structure resisting the single-event burnout due to the single-event burnout effect is favorably reduced, the service life of the device is favorably prolonged, the enterprise cost expenditure is favorably saved, and further the production benefit of an enterprise is favorably enlarged.
By adopting the grid group, wherein the grid group is the first grid and the second grid which are arranged at intervals, the thickness of the grid oxide layer between the first grid and the second grid is increased, the possibility that a large number of cavities are accumulated on the lower surface of the grid oxide layer due to the incidence of heavy particles so that the grid oxide layer is easily broken down is effectively reduced, the single-particle-penetration-resisting capability of the super-junction MOS device structure resisting the single-particle burning is improved, and the service life of the device is further prolonged; meanwhile, due to the adoption of the structure of the first grid electrode and the second grid electrode which are arranged at intervals, the coupling effect of the grid electrode and the drain electrode is reduced, the Miller capacitance Cgd is greatly reduced, the switching of the device is effectively reduced, and the switching speed of the device is increased.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and any modifications, equivalents, improvements, etc. made within the spirit of the present invention should be included in the scope of the present invention.
Claims (9)
1. The utility model provides a super junction MOS device structure that anti single event burns out which characterized in that: the super-junction MOS device structure resistant to single-particle burnout comprises source metal, drain metal, a substrate, a buffer layer, N columns, P columns, a connecting area group, a grid group, an isolation oxide layer and a grid oxide layer, wherein one end of the substrate is contacted with the drain metal, the other end of the substrate is contacted with the buffer layer, the number of the P columns is two, the N columns are arranged between the two P columns and are respectively contacted with the two P columns, one ends of the two P columns and one end of the N column are respectively contacted with the buffer layer, the two connecting area groups are symmetrically arranged, one connecting area is respectively contacted with the source metal, the isolation oxide layer and the other end of one P column, the other connecting area is respectively contacted with the source metal, the isolation oxide layer and the other end of the other P column, the other end of the N column is respectively contacted with the two connecting area groups and the isolation oxide layer, the grid group and the grid oxide layer are arranged between the source metal and the isolation oxide layer, the grid electrode group is respectively contacted with the grid oxide layer and the isolation oxide layer, the grid oxide layer is also respectively contacted with the isolation oxide layer and the source electrode metal, and the isolation oxide layer is contacted with the source electrode metal.
2. The single event burnout resistant superjunction MOS device structure of claim 1, wherein: the grid electrode group comprises a first grid electrode and a second grid electrode, the first grid electrode and the second grid electrode are arranged at intervals, the first grid electrode is respectively contacted with the grid oxide layer and the isolation oxide layer, and the second grid electrode is respectively contacted with the grid oxide layer and the isolation oxide layer.
3. The single event burnout resistant superjunction MOS device structure of claim 1, wherein: the connecting region group comprises a P well region, a P + well region and an N + active region, wherein the P well region is respectively contacted with the P + well region, the N + active region, a P column, an N column and an isolation oxidation layer, the P + well region is respectively contacted with the source metal and the N + active region, and the N + active region is respectively contacted with the source metal and the isolation oxidation layer.
4. The single event burnout resistant superjunction MOS device structure of claim 1, wherein: the source electrode metal comprises a connecting portion and two protruding portions, the protruding portions are connected to the two ends of the connecting portion respectively, the protruding portions face the drain electrode metal in the protruding direction, one side, close to the drain electrode metal, of each protruding portion is in contact with the connecting block group, and the inner sides of the protruding portions are in contact with the gate oxide layer and the isolation oxide layer respectively.
5. The single event burnout resistant superjunction MOS device structure of claim 1, wherein: the buffer layer is doped in N type, the doping element is P element, and the doping concentration is 1 multiplied by 1016～5×1016/cm-3The thickness is 5-50 μm.
6. The single event burnout resistant superjunction MOS device structure of claim 2, wherein: the distance between the first grid and the second grid is 0.5-2 μm.
7. The single event burnout resistant superjunction MOS device structure of claim 1, wherein: the source metal and the drain metal are both made of aluminum.
8. The single event burnout resistant superjunction MOS device structure of claim 1, wherein: the gate oxide layer and the isolation oxide layer are made of silicon dioxide.
9. The single event burnout resistant superjunction MOS device structure of claim 1, wherein: the thickness of the gate oxide layer is 50-150nm, and the thickness of the isolation oxide layer is 50-150 nm.
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| CN102760770A (en) * | 2012-06-11 | 2012-10-31 | 电子科技大学 | Single particle irradiation-resistant super junction VDMOS device |
| CN102810567A (en) * | 2012-06-08 | 2012-12-05 | 电子科技大学 | Super-junction vertical double-diffusion metal-oxide-semiconductor (VDMOS) device with dynamic charge balance |
| CN103515444A (en) * | 2013-09-24 | 2014-01-15 | 哈尔滨工程大学 | Groove gate power MOS device |
| CN104078509A (en) * | 2014-07-08 | 2014-10-01 | 电子科技大学 | Power MOS device with single-particle burnout resistance |
| CN105118862A (en) * | 2015-08-24 | 2015-12-02 | 电子科技大学 | VDMOS device with anti-SEU effect |
| US10186574B2 (en) * | 2015-10-29 | 2019-01-22 | Fuji Electric Co., Ltd. | Super junction MOSFET device and semiconductor chip |
| CN208489200U (en) * | 2018-06-12 | 2019-02-12 | 南京晟芯半导体有限公司 | Super-junction metal oxide semiconductor field effect transistor |
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2021
- 2021-07-19 CN CN202110814800.7A patent/CN113471293B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102810567A (en) * | 2012-06-08 | 2012-12-05 | 电子科技大学 | Super-junction vertical double-diffusion metal-oxide-semiconductor (VDMOS) device with dynamic charge balance |
| CN102760770A (en) * | 2012-06-11 | 2012-10-31 | 电子科技大学 | Single particle irradiation-resistant super junction VDMOS device |
| CN103515444A (en) * | 2013-09-24 | 2014-01-15 | 哈尔滨工程大学 | Groove gate power MOS device |
| CN104078509A (en) * | 2014-07-08 | 2014-10-01 | 电子科技大学 | Power MOS device with single-particle burnout resistance |
| CN105118862A (en) * | 2015-08-24 | 2015-12-02 | 电子科技大学 | VDMOS device with anti-SEU effect |
| US10186574B2 (en) * | 2015-10-29 | 2019-01-22 | Fuji Electric Co., Ltd. | Super junction MOSFET device and semiconductor chip |
| CN208489200U (en) * | 2018-06-12 | 2019-02-12 | 南京晟芯半导体有限公司 | Super-junction metal oxide semiconductor field effect transistor |
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