CN113871482B - LDMOS device for improving single particle burning resistance effect - Google Patents
LDMOS device for improving single particle burning resistance effect Download PDFInfo
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- CN113871482B CN113871482B CN202111147936.3A CN202111147936A CN113871482B CN 113871482 B CN113871482 B CN 113871482B CN 202111147936 A CN202111147936 A CN 202111147936A CN 113871482 B CN113871482 B CN 113871482B
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- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000007769 metal material Substances 0.000 claims description 4
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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Abstract
The invention discloses an LDMOS device for improving the single particle burning effect, which belongs to the field of power semiconductor devices, and comprises a substrate, wherein a first silicon carbide buried layer is formed on the substrate, and the first silicon carbide buried layer is an N-type silicon carbide buried layer; an active top layer formed on the first buried silicon carbide layer, wherein the active top layer comprises a source region, a well region, a drain buffer region, a drain region and a drift region; the device top layer is formed on the surface of the active top layer and comprises a source electrode, a drain electrode, a gate oxide layer, a grid electrode, a field oxide layer and a field plate; the invention effectively reduces the collection of drain electrons, reduces the drain buffer current and prevents the device from generating a single particle burning effect; meanwhile, the surface electric field of the top silicon layer can be regulated by adding the P-type silicon carbide buried layer, the electric field peak value of the drift region is reduced, the electron hole pairs generated by the drift region are relatively reduced, the collection amount of the drain electrode and the source electrode is reduced, and the probability of single particle burning of the device is reduced.
Description
Technical Field
The application relates to the field of power semiconductor devices, in particular to an LDMOS device for improving the effect of resisting single particle burnout.
Background
The LDMOS device is a power device with a double-diffusion structure. This technique is to implant arsenic (As) with a larger concentration (typically, 1015 cm-2) and boron (B) with a smaller concentration (typically, 1013 cm-2) into the same source/drain region twice. After implantation, a high temperature drive-in process is performed, and boron diffuses more rapidly than arsenic, so that a channel with a concentration gradient is formed under the boundary of the grid and the channel length is determined by the difference between the two lateral diffusion distances. In order to increase the breakdown voltage, a drift region is provided between the active region and the drain region. The drift region in the LDMOS is the key of the design of the device, and the impurity concentration of the drift region is relatively low, so that when the LDMOS is connected with high voltage, the drift region can bear higher voltage due to high resistance. The polycrystal of the LDMOS is expanded to the upper surface of the field oxide of the drift region and serves as a field plate, so that the surface electric field of the drift region can be weakened, and the breakdown voltage can be improved. The size of the field plate is closely related to the length of the field plate. The field plate can fully play a role, and the thickness of the SiO2 layer and the length of the field plate are designed.
The LDMOS fabrication process combines BPT and gallium arsenide processes. Unlike standard MOS process, LDMOS is not one BeO beryllium oxide isolating layer but one substrate, and has improved heat conducting performance, raised high temperature resistance and long service life. Because of the negative temperature effect of the LDMOS tube, the leakage current automatically equalizes when being heated, and hot spots are not formed on the local part of the collector current like the positive temperature effect of the bipolar tube, so that the tube is not easy to damage. The LDMOS tube greatly enhances the load mismatch and overdrive withstand capability. Also, due to the automatic current equalizing function of the LDMOS tube, the input-output characteristic curve of the LDMOS tube is slowly bent at a 1dB compression point (a saturation section for large signal application), so that the dynamic range is widened, and the amplification of the analog and digital television radio frequency signals is facilitated. The LDMOS is approximately linear in small signal amplification, has almost no intermodulation distortion, and greatly simplifies a correction circuit. The direct-current grid current of the MOS device is almost zero, the bias circuit is simple, and a complex active low-impedance bias circuit with positive temperature compensation is not needed.
For LDMOS, the thickness of the epitaxial layer, the doping concentration, and the length of the drift region are the most important characteristic parameters. The breakdown voltage can be increased by increasing the length of the drift region, but this increases the chip area and on-resistance. The withstand voltage and on-resistance of the high-voltage DMOS device depend on the concentration of the epitaxial layer, the thickness and the trade-off of the drift region length. Since the withstand voltage and on-resistance are contradictory to the requirements of the concentration and thickness of the epitaxial layer. A high breakdown voltage requires a thick lightly doped epitaxial layer and a long drift region, while a low on-resistance requires a thin heavily doped epitaxial layer and a short drift region, so that the optimal epitaxial parameters and drift region length must be chosen to obtain the minimum on-resistance while meeting a certain source-drain breakdown voltage.
However, when the LDMOS device is in an irradiation environment, electron hole pairs generated in the substrate are collected by the drain and the source, so that the drain buffer current of the device is increased, and the single-particle burning effect of the device is easier to occur, so that the single-particle burning effect of the traditional LDMOS device is improved to be a hot problem in the research field. Therefore, further research on the conventional LDMOS is necessary, and the structure is improved so as to improve the single particle burning resistance of the device.
Disclosure of Invention
The invention aims to provide an LDMOS device capable of effectively improving the single particle burnout resistance effect, and the integral performance of the device is optimized for improving the single particle burnout resistance effect of the device.
In order to achieve the above technical object, the present application provides an LDMOS device for improving the effect of anti-single particle burn-out, comprising:
a substrate, on which a first silicon carbide buried layer is formed, wherein the first silicon carbide buried layer is an N-type silicon carbide buried layer;
an active top layer formed on the first buried silicon carbide layer, wherein the active top layer comprises a source region, a well region, a drain buffer region, a drain region and a drift region;
and the device top layer is formed on the surface of the active top layer, wherein the device top layer comprises a source electrode, a drain electrode, a gate oxide layer, a grid electrode, a field oxide layer and a field plate.
Preferably, the first silicon carbide buried layer further comprises at least three second silicon carbide buried layers disposed in the N-type silicon carbide buried layer, wherein the second silicon carbide buried layers are disposed on the same horizontal plane.
Preferably, the second silicon carbide buried layer is arranged in the middle of the N-type silicon carbide buried layer;
the second silicon carbide buried layer comprises a P1 silicon carbide buried layer, a P2 silicon carbide buried layer and a P3 silicon carbide buried layer.
Preferably, the source regions include a p+ source region, an n+ source region;
the well region comprises a P-well region and a P+ well region;
the drain buffer area is an N-drain buffer area;
the drain region is an N+ drain region;
the drift region is an N-type drift region.
Preferably, the P+ well region is formed on the first silicon carbide buried layer;
the P+ source region, the N+ source region and the P-well region are sequentially formed on the upper surface of the P+ well region.
Preferably, the drift region is formed at one side of the P-well region and the P+ well region;
and one end of the drift region, which is far away from the P-well region, the P+ well region and the first silicon carbide buried layer, is provided with an N-drain buffer region and an N+ drain region, wherein the N+ drain region is connected with the drift region through the N-drain buffer region.
Preferably, the upper surface of the N+ drain region is provided with a drain electrode;
the upper surfaces of the P+ source region and the N+ source region are provided with source electrodes;
the upper surfaces of the drift region and the N-drain buffer region are provided with field oxide layers;
one end of the field oxide layer is provided with a grid electrode and a grid oxide layer, wherein the grid electrode is arranged on the upper surface of the grid oxide layer.
Preferably, the lower surface of the gate oxide layer is connected with the P-well region and the drift region respectively.
Preferably, the upper surfaces of the gate and the field oxide layer are on the same horizontal plane;
the upper surfaces of the grid electrode and the field oxide layer are also provided with a field plate.
Preferably, the source electrode, the grid electrode and the grid oxide layer are provided with an opening and a first width of the opening;
the source electrode and the N+ source region comprise a non-overlapping region and a second width of the non-overlapping region, wherein the upper surface of the non-overlapping region is also provided with a metal material which is the same as the material of the source electrode;
the first width is the same as the second width.
The structure of the invention has the following beneficial effects:
according to the LDMOS device capable of effectively improving the single particle burning effect, the silicon carbide buried layer is added between the substrate and the silicon on the active top layer, the wide forbidden band characteristic of the silicon carbide material is utilized, in the single particle impact process, the P-type silicon carbide can deplete the N-type silicon carbide, electrons generated in the substrate need to pass through the silicon carbide buried layer to reach the drain electrode, higher energy is needed, the collection of drain electrode electrons can be effectively reduced by adding the silicon carbide buried layer, the drain electrode buffer current is reduced, and the single particle burning effect of the device is prevented; meanwhile, the surface electric field of the top silicon layer can be regulated by adding the P-type silicon carbide buried layer, the electric field peak value of the drift region is reduced, the electron hole pairs generated by the drift region are relatively reduced, the collection amount of the drain electrode and the source electrode is reduced, and the probability of single particle burning of the device is further reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an LDMOS device designed based on the present invention to effectively improve the resistance to single particle burn-out;
fig. 2 is a schematic diagram of a conventional LDMOS device;
FIG. 3 is a graph of drain transient current versus time for two devices;
wherein 1 is a substrate, 2 is an N-type silicon carbide buried layer, 3 is a P1 silicon carbide buried layer, 4 is a P2 silicon carbide buried layer, 5 is a P3 silicon carbide buried layer, 6 is a P+ source region, 7 is an N+ source region, 8 is a P-well region, 9 is a P+ well region, 10 is an N-type drift region, 11 is an N-drain buffer region, 12 is an N+ drain region, 13 is a source electrode, 14 is a grid electrode, 15 is a grid oxide layer, 16 is a field plate, 17 is a field oxide layer, and 18 is a drain electrode.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
As shown in fig. 1-3, the present invention provides an LDMOS device for improving the resistance to the single particle burn-out effect, comprising:
a substrate 1, wherein a first silicon carbide buried layer is formed on the substrate 1, and the first silicon carbide buried layer is an N-type silicon carbide buried layer 2;
an active top layer formed on the first buried silicon carbide layer, wherein the active top layer comprises a source region, a well region, a drain buffer region, a drain region and a drift region;
and a device top layer formed on the surface of the active top layer, wherein the device top layer comprises a source electrode 13, a drain electrode 18, a gate oxide layer 15, a gate electrode 14, a field oxide layer 17 and a field plate 16.
Further, the first silicon carbide buried layer further comprises at least three second silicon carbide buried layers arranged in the N-type silicon carbide buried layer 2, wherein the second silicon carbide buried layers are arranged on the same horizontal plane.
Further, the second silicon carbide buried layer is arranged in the middle of the N-type silicon carbide buried layer 2;
the second silicon carbide buried layer comprises a P1 silicon carbide buried layer 3, a P2 silicon carbide buried layer 4 and a P3 silicon carbide buried layer 5.
Further, the source regions include a p+ source region 6, an n+ source region 7;
the well region comprises a P-well region 8 and a P+ well region 9;
the drain buffer is an N-drain buffer 11;
the drain region is an N+ drain region 12;
the drift region is an N-type drift region 10.
Further, a p+ well region 9 is formed on the first buried silicon carbide layer;
the P+ source region 6, the N+ source region 7 and the P-well region 8 are sequentially formed on the upper surface of the P+ well region 9.
Further, an N-type drift region 10 is formed on one side of the P-well region 8, the p+ well region 9;
an N-drain buffer region 11 and an N+ drain region 12 are arranged at one end of the drift region far away from the P-well region 8, the P+ well region 9 and the first silicon carbide buried layer, wherein the N+ drain region 12 is connected with an N-type drift region 10 through the N-drain buffer region 11.
Further, the upper surface of the n+ drain region 12 is provided with a drain electrode 18;
the upper surfaces of the p+ source region 6 and the n+ source region 7 are provided with source electrodes 13;
the upper surfaces of the N-type drift region 10 and the N-drain buffer region 11 are provided with a field oxide layer 17;
one end of the field oxide layer 17 is provided with a gate electrode 14, a gate oxide layer 15, wherein the gate electrode 14 is provided on the upper surface of the gate oxide layer 15.
Further, the lower surface of the gate oxide layer 15 is connected to the P-well region 8 and the N-type drift region 10, respectively.
Further, the upper surface of the gate 14 and the upper surface of the field oxide layer 17 are on the same horizontal plane;
the upper surface of the gate 14 and the upper surface of the field oxide layer 17 are also provided with a field plate 16.
Further, the source electrode 13, the gate electrode 14 and the gate oxide layer 15 have a first width of the opening;
the source electrode 13 and the N+ source region 7 comprise a non-overlapping region and a second width of the non-overlapping region, wherein the upper surface of the non-overlapping region is also provided with a metal material which is the same as the material of the source electrode 13;
the first width is the same as the second width.
Example 1: as shown in fig. 1, the LDMOS device of the present invention for effectively improving the single particle burn-out resistance comprises: substrate 1, N-type silicon carbide buried layer 2, P1 silicon carbide buried layer 3, P2 silicon carbide buried layer 4, P3 silicon carbide buried layer 5, P+ source region 6, N+ source region 7, P-well region 8, P+ well region 9, N-type drift region 10, N-drain buffer region 11, N+ drain region 12, source 13, gate 14, gate oxide layer 15, field plate 16, field oxide layer 17, drain 18. The P-type silicon carbide buried layer is positioned in the middle of the N-type silicon carbide buried layer 2.
As shown in fig. 2, the conventional LDMOS device includes: substrate 1, P+ source region 6, N+ source region 7, P-well region 8, P+ well region 9, N-type drift region 10, N-drain buffer region 11, N+ drain region 12, source 13, gate 14, gate oxide 15, field plate 16, field oxide 17, drain 18.
According to the simulation result shown in fig. 3, it can be obtained that under the conditions of let=5pc/μm and vd=15v, the single-particle burning effect is compared with that of the conventional LDMOS device, and because the wide bandgap semiconductor material silicon carbide is added in the structure, electron hole pairs in the substrate cannot be collected by the drain and the source, and the drain buffer current gradually increases along with the time of single-particle incidence and finally returns to zero, so that the single-particle burning effect does not occur. For the conventional LDMOS device, electrons generated in the substrate are collected by the drain, and the drain buffer current gradually increases, so that the parasitic transistor is turned on, and the device is burned out. The structure provided by the invention has good single particle burning resistance.
The device structure provided by the invention comprises the following components from bottom to top: a substrate silicon layer, a silicon carbide buried layer, an active top layer silicon and a device top layer. The silicon carbide buried layer comprises an N-type buried layer, and a P1 silicon carbide buried layer, a P2 silicon carbide buried layer and a P3 silicon carbide buried layer are formed in the N-type silicon carbide buried layer through ion implantation. The P-type silicon carbide is utilized to realize the depletion of the N-type silicon carbide, in the single particle burning effect, electron hole pairs are generated in the device by single particle impact, and the electron hole pairs generated in the substrate need to cross the silicon carbide layer by utilizing the wide forbidden band characteristic of the silicon carbide material, so that the collection amount of drain terminal electrons can be effectively reduced; meanwhile, the electric field of the drift region can be effectively regulated by adding the P-type silicon carbide buried layer, the electric field peak value of the drift region is reduced, the electron hole pairs generated in the drift region are relatively reduced, and the collection amount of the drain electrode and the source electrode is reduced. In summary, the structure provided by the invention can effectively improve the single particle burning resistance of the device.
It should be noted that: like reference numerals and letters in the following figures denote like items, and thus once an item is defined in one figure, no further definition or explanation of it is required in the following figures, and furthermore, the terms "first," "second," "third," etc. are used merely to distinguish one description from another and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above examples are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, but it should be understood by those skilled in the art that the present invention is not limited thereto, and that the present invention is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the corresponding technical solutions. Are intended to be encompassed within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. An LDMOS device for improving the resistance to single particle burn-out, comprising:
a substrate, on which a first silicon carbide buried layer is formed, wherein the first silicon carbide buried layer comprises an N-type silicon carbide buried layer;
an active top layer formed on the first buried silicon carbide layer, wherein the active top layer comprises a source region, a well region, a drain buffer region, a drain region and a drift region;
the device top layer is formed on the surface of the active top layer, wherein the device top layer comprises a source electrode, a drain electrode, a gate oxide layer, a gate electrode, a field oxide layer and a field plate;
the first silicon carbide buried layer further comprises at least three second silicon carbide buried layers arranged in the N-type silicon carbide buried layer, wherein the second silicon carbide buried layers are arranged on the same horizontal plane;
the second silicon carbide buried layer is arranged in the middle of the N-type silicon carbide buried layer;
the second silicon carbide buried layer comprises a P1 silicon carbide buried layer, a P2 silicon carbide buried layer and a P3 silicon carbide buried layer.
2. An LDMOS device for enhancing resistance to single particle burn-in as recited in claim 1, wherein:
the source region comprises a P+ source region and an N+ source region;
the well region comprises a P-well region and a P+ well region;
the drain electrode buffer area is an N-drain electrode buffer area;
the drain region is an N+ drain region;
the drift region is an N-type drift region.
3. An LDMOS device for enhancing resistance to single particle burn-in as recited in claim 2, wherein:
the P+ well region is formed on the first silicon carbide buried layer;
the P+ source region, the N+ source region and the P-well region are sequentially formed on the upper surface of the P+ well region.
4. An LDMOS device for enhancing resistance to single particle burn-in as recited in claim 3, wherein:
the drift region is formed on one side of the P-well region and one side of the P+ well region;
the drift region is far away from the P-well region, the P+ well region and the N+ drain region, and the N+ drain region is connected with the drift region through the N-drain buffer region.
5. An LDMOS device for enhancing resistance to single particle burn-in as recited in claim 4, wherein:
the drain electrode is arranged on the upper surface of the N+ drain region;
the upper surfaces of the P+ source region and the N+ source region are provided with the source electrodes;
the upper surfaces of the drift region and the N-drain buffer region are provided with the field oxide layer;
one end of the field oxide layer is provided with the grid electrode and the grid oxide layer, wherein the grid electrode is arranged on the upper surface of the grid oxide layer.
6. An LDMOS device for enhancing resistance to single particle burn-in as recited in claim 5, wherein:
the lower surface of the gate oxide layer is respectively connected with the P-well region and the drift region.
7. An LDMOS device for enhancing resistance to single particle burn-in as recited in claim 6, wherein:
the upper surfaces of the grid electrode and the field oxide layer are on the same horizontal plane;
the upper surfaces of the gate electrode and the field oxide layer are also provided with the field plate.
8. An LDMOS device for enhancing resistance to single particle burn-in as recited in claim 7, wherein:
an opening is formed between the source electrode and the grid electrode as well as between the source electrode and the grid electrode and between the source electrode and the grid oxide layer;
the source electrode and the N+ source region comprise a non-overlapping region and a second width of the non-overlapping region, wherein a metal material is further arranged on the upper surface of the non-overlapping region, and the metal material is the same as the source electrode;
the first width is the same as the second width.
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| CN104681621A (en) * | 2015-02-15 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | High-voltage LDMOS for source electrode rising voltage use and manufacturing method for high-voltage LDMOS |
| CN108511528A (en) * | 2018-04-11 | 2018-09-07 | 西安电子科技大学 | Lateral double diffusion metal oxide composite semiconductor field-effect tube with deep drain region and preparation method thereof |
| CN110112217A (en) * | 2019-04-15 | 2019-08-09 | 杭州电子科技大学 | Anti-single particle burns LDMOS device |
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| CN113782610A (en) * | 2021-09-14 | 2021-12-10 | 江苏芯唐微电子有限公司 | SOI LDMOS device for improving self-heating effect |
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| CN108511528A (en) * | 2018-04-11 | 2018-09-07 | 西安电子科技大学 | Lateral double diffusion metal oxide composite semiconductor field-effect tube with deep drain region and preparation method thereof |
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