CN108878533A - LDMOS device and its manufacturing method - Google Patents

LDMOS device and its manufacturing method Download PDF

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Publication number
CN108878533A
CN108878533A CN201810695463.2A CN201810695463A CN108878533A CN 108878533 A CN108878533 A CN 108878533A CN 201810695463 A CN201810695463 A CN 201810695463A CN 108878533 A CN108878533 A CN 108878533A
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CN
China
Prior art keywords
drift region
ldmos
region
area
oxygen
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CN201810695463.2A
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Chinese (zh)
Inventor
钱文生
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上海华虹宏力半导体制造有限公司
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Priority to CN201810695463.2A priority Critical patent/CN108878533A/en
Publication of CN108878533A publication Critical patent/CN108878533A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The invention discloses a kind of LDMOS devices, including drift region and body area;Gate dielectric layer and polysilicon gate;It is formed in the drift region oxygen on the drift region surface, the second side of polysilicon gate extends on the oxygen of drift region;Source region is formed in body surface, and drain region is formed in drift region surface;It is formed on the surface of drift region and adulterates opposite interpolation doped layer, be used for assisted depletion drift region;On lateral position, interpolation doped layer is located at the overlay area of drift region oxygen;In lengthwise position, interpolation doped layer is located at the bottom of drift region oxygen;Surface current channel region is formed between interpolation doped layer and the bottom of drift region oxygen;The impurity of surface current channel region is formed by stacking by the bulk doped impurity of drift region and the first ion implanted layer impurity of the first conduction type.The invention also discloses a kind of manufacturing methods of LDMOS device.The present invention can improve breakdown voltage while reduce the conducting resistance of device, to improve the performance of device.

Description

LDMOS device and its manufacturing method

Technical field

The present invention relates to semiconductor integrated circuit manufacturing fields, partly lead more particularly to a kind of lateral diffused metal oxide Body (LDMOS) device;The invention further relates to a kind of manufacturing methods of LDMOS device.

Background technique

Super-pressure LDMOS device needs longer drift region to undertake superelevation breakdown voltage, but drain terminal voltage gradually During increased, often there is drift region and do not exhaust all also, peak value electric field has reached critical electric field, causes hitting for device Wear low voltage.Therefore industry is typically employed in the intermediate of drift region and is inserted into one layer of doping opposite with drift region conduction type Layer, to help drift region to exhaust as early as possible in drain terminal voltage is incremented by, exhausting for drift region becomes two by original one-dimensional exhaust Dimension exhausts.

Due to the limitation of ion implantation energy and considering for assisted depletion effect, the doped layer of drift region insertion is closer Drift region surface is horizontally located at the bottom drift region Chang Yang.

When drain terminal plus low pressure, pinch off, current transfer are mainly drift of the carrier on drift region surface far away for drift region Electric current.But the depletion region broadening of drift region insert layer has the gesture of pinch off to the current channel of device, so that the conducting resistance of device Higher, saturation current is relatively low.

Summary of the invention

Technical problem to be solved by the invention is to provide a kind of LDMOS devices, can improve breakdown voltage while reduce device The conducting resistance of part, to improve the performance of device.For this purpose, the present invention also provides a kind of manufacturing methods of LDMOS device.

In order to solve the above technical problems, LDMOS device provided by the invention includes:

Drift region with the doping of the first conduction type.

Body area with the doping of the second conduction type, the body area and drift region side contact.

The gate structure being formed by stacking by gate dielectric layer and polysilicon gate, the polysilicon gate are covered on the body surface And extend on the drift region, the body area covered by the polysilicon gate is used to form channel.

Drift region oxygen is formed in the drift region surface, has interval between the drift region oxygen and the body area;Institute The first side for stating polysilicon gate is located in the body area, and the second side of the polysilicon gate extends to the drift region oxygen On.

The source region of first conduction type heavy doping is formed in the body surface and the first side with the polysilicon gate Autoregistration.

The drain region of first conduction type heavy doping be formed in the drift region surface and with the drift region oxygen second Side autoregistration.

It is formed with the interpolation doped layer of the second conduction type doping on the surface of the drift region, is born in LDMOS device When reverse biased, the doping concentration of the interpolation doped layer, which meets, to be carried out assisted depletion to the drift region and makes the drift region Electric field strength in completely depleted foregoing description drift region is below critical electric field.

On lateral position, the interpolation doped layer is located at the overlay area of the drift region oxygen;In lengthwise position, The interpolation doped layer is located at the bottom of the drift region oxygen;In the bottom of the interpolation doped layer and the drift region oxygen Between be formed with surface current channel region.

The impurity of the surface current channel region by the drift region bulk doped impurity and the first conduction type The first ion implanted layer impurity be formed by stacking, first ion implanted layer makes the doping concentration of the surface current channel region Increase and reduce the interpolation doped layer in the LDMOS device forward conduction and the surface current channel region is exhausted Width is to make the conducting width of the surface current channel region increase, to reduce the forward conduction electricity of the LDMOS device Resistance.

A further improvement is that the interpolation doped layer and first ion implanted layer all use ion implantation technology shape At and interpolation doped layer light shield corresponding with first ion implanted layer it is identical, first ion implanted layer and described The lateral dimension of interpolation doped layer is identical.

A further improvement is that the interpolation doped layer and first ion implanted layer are under the definition of identical light shield It sequentially forms.

A further improvement is that the drift region is by the first conductive type of trap district's groups at the body area is formed in the drift It moves in the selection area in area.

A further improvement is that the first conduction type well region of the drift region is formed in the second conductive type semiconductor lining Bottom surface.

A further improvement is that the semiconductor substrate is silicon substrate.

A further improvement is that the gate dielectric layer is gate oxide.

A further improvement is that the drift region oxygen is shallow trench field oxygen or local field oxygen.

A further improvement is that the doping concentration of the surface current channel region is dense for the doping of the ontology of the drift region 2 times~3 times of degree.

In order to solve the above technical problems, the manufacturing method of LDMOS device provided by the invention includes the following steps:

Step 1: forming the drift region of the first conduction type doping in semiconductor substrate surface.

Step 2: the body area of the second conduction type doping is formed, the body area and drift region side contact.

Step 3: forming drift region oxygen, the drift region oxygen is located at the drift region surface, the drift region oxygen There is interval between the body area.

Step 4: lithographic definition goes out the forming region of interpolation doped layer, the second conductive type ion of progress is infused in described The surface of drift region forms the interpolation doped layer, when LDMOS device bears reverse biased, the doping of the interpolation doped layer Concentration meets the electric field for carrying out assisted depletion to the drift region and making in the completely depleted foregoing description drift region in the drift region Intensity is below critical electric field.

On lateral position, the interpolation doped layer is located at the overlay area of the drift region oxygen;In lengthwise position, The interpolation doped layer is located at the bottom of the drift region oxygen;In the bottom of the interpolation doped layer and the drift region oxygen Between be formed with surface current channel region.

Step 5: then carrying out the first conductive type ion using the lithographic definition in step 4 is infused in the surface electricity The first ion implanted layer is formed in circulation road area, the impurity of the surface current channel region is mixed by the ontology of the drift region First ion implanted layer impurity of impurity and the first conduction type is formed by stacking, and first ion implanted layer makes the surface The doping concentration in current channel area increases and reduces the interpolation doped layer in the LDMOS device forward conduction to described The depletion widths of surface current channel region are to make the conducting width of the surface current channel region increase, thus described in reducing The forward conduction resistance of LDMOS device.

Step 6: forming the gate structure being formed by stacking by gate dielectric layer and polysilicon gate, the polysilicon gate is covered on The body surface simultaneously extends on the drift region, and the body area covered by the polysilicon gate is used to form channel;Institute The first side for stating polysilicon gate is located in the body area, and the second side of the polysilicon gate extends to the drift region oxygen On.

Step 7: the source and drain ion implanting for carrying out the first conduction type heavy doping is formed simultaneously source region and drain region, the source Area is formed in the body surface and the first side autoregistration with the polysilicon gate;The drain region is formed in the drift region Surface and second side autoregistration with the drift region oxygen.

A further improvement is that drift region described in step 1 by the first conductive type of trap district's groups at and use well region technique It is formed;The semiconductor substrate is the doping of the second conduction type, and the first conduction type well region of the drift region is formed in second Conductive type semiconductor substrate surface;The body area is formed in the selection area of the drift region.

A further improvement is that the gate dielectric layer is gate oxide.

A further improvement is that the drift region oxygen is formed or is used office using shallow trench field oxygen technique in step 3 Portion oxygen technique is formed.

A further improvement is that the doping concentration of the surface current channel region is dense for the doping of the ontology of the drift region 2 times~3 times of degree.

A further improvement is that the LDMOS device is N-type LDMOS device, the first conduction type is N-type, and second is conductive Type is p-type.

A further improvement is that the drift region formed in step 1 is Uniform Doped and doping concentration is 1e15cm-3 ~1e16cm-3

The impurity of the corresponding ion implanting of interpolation doped layer described in step 4 is boron, implantation dosage 2e12cm-2~ 5e12cm-2, Implantation Energy is 1000kev~2000kev.

The impurity of the corresponding ion implanting of first ion implanted layer described in step 5 is arsenic or phosphorus, and implantation dosage is 1e12cm-2~5e12cm-2, Implantation Energy is determining according to the thickness of the drift region oxygen and requires to guarantee first ion The peak value of the corresponding ion implanting of implanted layer is located in the surface current channel region of the bottom the drift region Chang Yang.

A further improvement is that the LDMOS device is p-type LDMOS device, the first conduction type is p-type, and second is conductive Type is N-type.

The present invention the drift region surface of drift region oxygen introduce realize to the interpolation doped layer of drift region assisted depletion from And drift region, that is, surface electricity under conditions of improving the breakdown voltage of device, between interpolation doped layer and drift region oxygen The first ion implanted layer is introduced in circulation road area, the master of channel current when due to surface current channel region being device forward conduction Channel is wanted, introducing the first ion implanted layer can increase the doping concentration of surface current channel region not only later to reduce electric conduction Resistance;And during can be reduced after the doping concentration increase of surface current channel region in forward conduction interpolation doped layer to surface Current lead-through area exhausts, so as to improve the conducting width of surface current channel region, the conducting width of surface current channel region Increase can also reduce the forward conduction resistance of device, so present invention combination interpolation doped layer and in surface current channel region The structure design for introducing the first ion implanted layer, can realize in raising breakdown voltage well while reduce the electric conduction of device Resistance, to improve the performance of device.

Detailed description of the invention

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

Fig. 1 is the structural schematic diagram of LDMOS device of the embodiment of the present invention;

Fig. 2 is the simulation curve of the doping concentration on the drift region surface of LDMOS device of the embodiment of the present invention and existing device Compare figure;

Fig. 3 A is device simulation figure of the existing device in linear zone work;

Fig. 3 B is device simulation figure of the device of the embodiment of the present invention in linear zone work;

Fig. 4 A is device simulation figure of the existing device in saturation region operation;

Fig. 4 B is device simulation figure of the device of the embodiment of the present invention in saturation region operation;

Fig. 5 is the simulation curve ratio of the current line on the drift region surface of LDMOS device of the embodiment of the present invention and existing device Compared with figure;

Fig. 6 is the simulation curve of the electric field strength on the drift region surface of LDMOS device of the embodiment of the present invention and existing device Compare figure;

Fig. 7 is that the curve of the Id-Vg of the linear zone of LDMOS device of the embodiment of the present invention and existing device compares figure;

Fig. 8 is that the curve of the Id-Vd of LDMOS device of the embodiment of the present invention and existing device compares figure;

Fig. 9 is the structural schematic diagram of existing LDMOS device.

Specific embodiment

Existing device:

For the ease of comparing, existing device is first introduced before introducing device of the embodiment of the present invention, as shown in figure 9, It is the structural schematic diagram of existing LDMOS device;Existing LDMOS device includes:

Drift region 2 with the doping of the first conduction type.

Body area 3 with the doping of the second conduction type, the body area 3 and the contact of 2 side of the drift region.

The gate structure being formed by stacking by gate dielectric layer 5 and polysilicon gate 6, the polysilicon gate 6 are covered on the body area 3 Surface simultaneously extends on the drift region 2, and the body area 3 covered by the polysilicon gate 6 is used to form channel.

Drift region oxygen 4 is formed in 2 surface of drift region, between having between the drift region oxygen 4 and the body area 3 Every;The first side of the polysilicon gate 6 is located in the body area 3, and the second side of the polysilicon gate 6 extends to the drift It moves on area oxygen 4.

The source region 7 of first conduction type heavy doping is formed in 3 surface of body area and the first side with the polysilicon gate 6 Face autoregistration.

The drain region 8 of first conduction type heavy doping be formed in 2 surface of drift region and with the drift region oxygen 4 the Two side faces autoregistration.

The body draw-out area 9 of the second conduction type heavy doping is also formed on the surface in the body area 3.

The top of source region 7 and body draw-out area 9 can be connected to the source electrode being made of front metal layer by contact hole;Drain region 8 Top can be connected to the drain electrode being made of front metal layer by contact hole, polysilicon gate 6 can be connected to by contact hole by The grid of front metal layer composition.

It is formed with the interpolation doped layer 10 of the second conduction type doping on the surface of the drift region 2, is held in LDMOS device When being reverse biased, the doping concentration of the interpolation doped layer 10, which meets, to be carried out assisted depletion to the drift region 2 and makes described Electric field strength in the completely depleted foregoing description drift region 2 in drift region 2 is below critical electric field.

On lateral position, the interpolation doped layer 10 is located at the overlay area of the drift region oxygen 4;In lengthwise position On, the interpolation doped layer 10 is located at the bottom of the drift region oxygen 4.

In existing device, the region between the interpolation doped layer 10 and the bottom of the drift region oxygen 4 is still protected It holds as the doped structure of the drift region 2.Due between the interpolation doped layer 10 and the bottom of the drift region oxygen 4 Region is surface current channel region, and in device forward conduction, surface current channel region is the main thoroughfare of drift region electric current.But It is that after the interpolation doped layer 10 introduces, the surface current channel region generation of the meeting pair of interpolation doped layer 10 is certain to be exhausted, Under the alive adjusting that drains, the depletion widths of the surface current channel region of the meeting pair of interpolation doped layer 10 be will increase, and be made The conducting sector width for obtaining surface current channel region reduces, and will increase the forward conduction resistance of device in this way.

In general, the drift region 2 is by the first conductive type of trap district's groups at the body area 3 is formed in the drift region 2 In selection area.

First conduction type well region of the drift region 2 is formed in 1 surface of the second conductive type semiconductor substrate.Described half Conductor substrate 1 is silicon substrate.The gate dielectric layer 5 is gate oxide.The drift region oxygen 4 is shallow trench field oxygen or local field Oxygen.

In description of the invention, it is compared so that existing LDMOS device is N-type LDMOS device as an example, the first conduction type For N-type, the second conduction type is p-type.

Device of the embodiment of the present invention:

As shown in Figure 1, being the structural schematic diagram of LDMOS device of the embodiment of the present invention;LDMOS device packet of the embodiment of the present invention It includes:

Drift region 2 with the doping of the first conduction type.

Body area 3 with the doping of the second conduction type, the body area 3 and the contact of 2 side of the drift region.

The gate structure being formed by stacking by gate dielectric layer 5 and polysilicon gate 6, the polysilicon gate 6 are covered on the body area 3 Surface simultaneously extends on the drift region 2, and the body area 3 covered by the polysilicon gate 6 is used to form channel.

Drift region oxygen 4 is formed in 2 surface of drift region, between having between the drift region oxygen 4 and the body area 3 Every;The first side of the polysilicon gate 6 is located in the body area 3, and the second side of the polysilicon gate 6 extends to the drift It moves on area oxygen 4.

The source region 7 of first conduction type heavy doping is formed in 3 surface of body area and the first side with the polysilicon gate 6 Face autoregistration.

The drain region 8 of first conduction type heavy doping be formed in 2 surface of drift region and with the drift region oxygen 4 the Two side faces autoregistration.

The body draw-out area 9 of the second conduction type heavy doping is also formed on the surface in the body area 3.

The top of source region 7 and body draw-out area 9 can be connected to the source electrode being made of front metal layer by contact hole;Drain region 8 Top can be connected to the drain electrode being made of front metal layer by contact hole, polysilicon gate 6 can be connected to by contact hole by The grid of front metal layer composition.

It is formed with the interpolation doped layer 10 of the second conduction type doping on the surface of the drift region 2, is held in LDMOS device When being reverse biased, the doping concentration of the interpolation doped layer 10, which meets, to be carried out assisted depletion to the drift region 2 and makes described Electric field strength in the completely depleted foregoing description drift region 2 in drift region 2 is below critical electric field.

On lateral position, the interpolation doped layer 10 is located at the overlay area of the drift region oxygen 4;In lengthwise position On, the interpolation doped layer 10 is located at the bottom of the drift region oxygen 4;In the interpolation doped layer 10 and the drift region Surface current channel region 11 is formed between the bottom of oxygen 4.

The impurity of the surface current channel region 11 by the drift region 2 bulk doped impurity and the first conductive-type First ion implanted layer impurity of type is formed by stacking, and first ion implanted layer makes mixing for the surface current channel region 11 Miscellaneous concentration increases and reduces the interpolation doped layer 10 in the LDMOS device forward conduction to the surface current channel The depletion widths in area 11 are to make the conducting width of the surface current channel region 11 increase, to reduce the LDMOS device Forward conduction resistance.

In the embodiment of the present invention, the doping concentration of the surface current channel region is that the doping of the ontology of the drift region is dense 2 times~3 times of degree.

In the embodiment of the present invention, the interpolation doped layer 10 and first ion implanted layer all use ion implantation technology Formed and the interpolation doped layer 10 light shield corresponding with first ion implanted layer it is identical, first ion implanted layer and The lateral dimension of the interpolation doped layer 10 is identical.

The interpolation doped layer 10 and first ion implanted layer are sequentially formed under the definition of identical light shield.

The drift region 2 is by the first conductive type of trap district's groups at the body area 3 is formed in the selected area of the drift region 2 In domain.

First conduction type well region of the drift region 2 is formed in 1 surface of the second conductive type semiconductor substrate.Described half Conductor substrate 1 is silicon substrate.The gate dielectric layer 5 is gate oxide.The drift region oxygen 4 is shallow trench field oxygen or local field Oxygen.

LDMOS device described in the embodiment of the present invention is N-type LDMOS device, and the first conduction type is N-type, the second conductive-type Type is p-type.The drift region 2 is Uniform Doped and doping concentration is 1e15cm-3~1e16cm-3.The interpolation doped layer 10 is right The impurity for the ion implanting answered is boron, implantation dosage 2e12cm-2~5e12cm-2, Implantation Energy be 1000kev~ 2000kev.The impurity of the corresponding ion implanting of first ion implanted layer is arsenic or phosphorus, implantation dosage 1e12cm-2~ 5e12cm-2

Also can be in other embodiments:The LDMOS device is p-type LDMOS device, and the first conduction type is P type, Second conduction type is N-type.

The embodiment of the present invention introduces the interpolation realized to 2 assisted depletion of drift region on 2 surface of drift region of drift region oxygen 4 Drift under conditions of breakdown voltage of the doped layer 10 to improve device, between interpolation doped layer 10 and drift region oxygen 4 Introduce the first ion implanted layer in 2 regions of area, that is, surface current channel region 11, due to surface current channel region 11 be device just To the main thoroughfare of channel current when conducting, introduce the first ion implanted layer not only can increase surface current channel region 11 later Doping concentration is to reduce conducting resistance;And it can be reduced after the doping concentration increase of surface current channel region 11 in positive guide Interpolation doped layer 10 exhausts surface current conducting area during logical, wide so as to the conducting that improves surface current channel region 11 Degree, the increase of the conducting width of surface current channel region 11 can also reduce the forward conduction resistance of device, so the present invention is implemented Example combines interpolation doped layer 10 and introduces the structure design of the first ion implanted layer in surface current channel region 11, can be well It realizes and is improving breakdown voltage while reducing the conducting resistance of device, to improve the performance of device.

The advantages of in order to illustrate the embodiment of the present invention, has carried out following emulation and has compared:

1, as shown in Fig. 2, being the doping concentration on the drift region surface of LDMOS device of the embodiment of the present invention and existing device Simulation curve compares figure;In Fig. 2, the lateral position on the drift region surface of emulation corresponds to the surface current channel region 11 of Fig. 1 Surface, curve 101 correspond to the doping concentration curve of existing device, and curve 102 corresponds to the doping of device of the embodiment of the present invention Concentration curve;As can be seen that the doping concentration of the surface current channel region 11 of LDMOS device of the embodiment of the present invention is improved.

It 2, as shown in Figure 3A, is device simulation figure of the existing device in linear zone work;It as shown in Figure 3B, is the present invention Device simulation figure of the embodiment device when linear zone works;D101 in Fig. 3 A represents the surface current channel in existing device The conducting width in area, the d1 in Fig. 3 B represent the conducting width of the surface current channel region in device of the embodiment of the present invention.Emulation As a result it is greater than d101 for d1, this increases the conducting width of the surface current channel region 11 of the embodiment of the present invention, therefore can reduce The conducting resistance in device linearity area.

It 3, is as shown in Figure 4 A, device simulation figure of the existing device in saturation region operation;It as shown in Figure 4 B, is the present invention Device simulation figure of the embodiment device in saturation region operation;Simulation result is equally available, and in saturation region, the present invention is implemented The conducting width of the surface current channel region 11 of example increases, therefore can reduce the conducting resistance of device saturation region.

4, as shown in figure 5, being the imitative of the current line on the drift region surface of LDMOS device of the embodiment of the present invention and existing device True curve compares figure;Curve 103 corresponds to the current line curve on the drift region surface of existing device, and curve 104 corresponds to this hair The current line on the drift region surface of bright embodiment device;As can be seen that the electric current on the drift region surface of device of the embodiment of the present invention Line increases, therefore can reduce the conducting resistance of device.

5, as shown in fig. 6, being the electric field strength on the drift region surface of LDMOS device of the embodiment of the present invention and existing device Simulation curve compares figure;Curve 105 corresponds to the electric field strength profile on the drift region surface of existing device, and curve 106 corresponds to The electric field strength profile on the drift region surface of device of the embodiment of the present invention;As can be seen that the drift of device of the embodiment of the present invention The electric field strength for moving area surface increases, and is conducive to the increase of driving current.

6, as shown in fig. 7, being the curve ratio of the Id-Vg of the linear zone of LDMOS device of the embodiment of the present invention and existing device Compared with figure;Curve 107 corresponds to the Id-Vg curve of the linear zone of existing device, and curve 108 corresponds to device of the embodiment of the present invention Linear zone Id-Vg curve;Id is drain current, and Vg is grid voltage, it can be seen that device of the embodiment of the present invention it is linear Electric current increases considerably, conducting resistance decline.

7, as shown in figure 8, being that the curve of the Id-Vd of LDMOS device of the embodiment of the present invention and existing device compares figure;Due to There is an Id-Vd curve that a plurality of Vg is different, shows respectively the embodiment of the present invention and existing device with different figures in Fig. 8 Id-Vd curve, Vd are drain voltage, it can be seen that the driving current of device of the embodiment of the present invention is significantly promoted.

The manufacturing method of LDMOS device of the embodiment of the present invention includes the following steps:

Step 1: forming the drift region 2 of the first conduction type doping on 1 surface of semiconductor substrate.

In present invention method, the drift region 2 by the first conductive type of trap district's groups at and use well region technique shape At;The semiconductor substrate 1 is the doping of the second conduction type, and the first conduction type well region of the drift region 2 is formed in second Conductive type semiconductor substrate such as 1 surface of silicon substrate;The body area 3 is formed in the selection area of the drift region 2.

Step 2: the body area 3 of the second conduction type doping is formed, the body area 3 and the contact of 2 side of the drift region.

Step 3: forming drift region oxygen 4, the drift region oxygen 4 is located at 2 surface of drift region, the drift region There is interval between field oxygen 4 and the body area 3.

The drift region oxygen 4 is formed using shallow trench field oxygen technique or is formed using local field oxygen technique.

Step 4: lithographic definition goes out the forming region of interpolation doped layer 10, carries out the second conductive type ion and be infused in institute The surface for stating drift region 2 forms the interpolation doped layer 10, when LDMOS device bears reverse biased, the interpolation doped layer 10 doping concentration, which meets, to be carried out assisted depletion to the drift region 2 and the completely depleted foregoing description in the drift region 2 is made to drift about Electric field strength in area 2 is below critical electric field.

On lateral position, the interpolation doped layer 10 is located at the overlay area of the drift region oxygen 4;In lengthwise position On, the interpolation doped layer 10 is located at the bottom of the drift region oxygen 4;In the interpolation doped layer 10 and the drift region Surface current channel region 11 is formed between the bottom of oxygen 4.

Step 5: then carrying out the first conductive type ion using the lithographic definition in step 4 is infused in the surface electricity The first ion implanted layer is formed in circulation road area 11, the impurity of the surface current channel region 11 is by the drift region 2 First ion implanted layer impurity of bulk doped impurity and the first conduction type is formed by stacking, and first ion implanted layer makes institute The doping concentration for stating surface current channel region 11 increases and reduces in the LDMOS device forward conduction interpolation doping The depletion widths of 10 pairs of surface current channel region 11 of layer to making the conducting width of the surface current channel region 11 increase, To reduce the forward conduction resistance of the LDMOS device.

Step 6: forming the gate structure being formed by stacking by gate dielectric layer 5 and polysilicon gate 6, the polysilicon gate 6 covers It covers on 3 surface of body area and extends on the drift region 2, the body area 3 covered by the polysilicon gate 6 is used for shape At channel;The first side of the polysilicon gate 6 is located in the body area 3, and the second side of the polysilicon gate 6 extends to institute It states on the oxygen 4 of drift region.

The gate dielectric layer 5 is gate oxide, is formed using thermal oxidation technology.

Step 7: the source and drain ion implanting for carrying out the first conduction type heavy doping is formed simultaneously source region 7 and drain region 8, it is described Source region 7 is formed in 3 surface of body area and the first side autoregistration with the polysilicon gate 6;The drain region 8 is formed in institute State 2 surface of drift region and the second side autoregistration with the drift region oxygen 4.

In present invention method, the LDMOS device be N-type LDMOS device, the first conduction type be N-type, second Conduction type is p-type.The drift region 2 formed in step 1 is Uniform Doped and doping concentration is 1e15cm-3~ 1e16cm-3

The impurity of the corresponding ion implanting of interpolation doped layer described in step 4 10 is boron, implantation dosage 2e12cm-2~ 5e12cm-2, Implantation Energy is 1000kev~2000kev.

The impurity of the corresponding ion implanting of first ion implanted layer described in step 5 is arsenic or phosphorus, and implantation dosage is 1e12cm-2~5e12cm-2, Implantation Energy is determining according to the thickness of the drift region oxygen 4 and requires to guarantee first ion The peak value of the corresponding ion implanting of implanted layer is located in the surface current channel region 11 of drift region 4 bottom of oxygen.

Also can be in other embodiments method:The LDMOS device is p-type LDMOS device, and the first conduction type is P Type, the second conduction type are N-type.

The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered It is considered as protection scope of the present invention.

Claims (15)

1. a kind of LDMOS device, which is characterized in that including:
Drift region with the doping of the first conduction type;
Body area with the doping of the second conduction type, the body area and drift region side contact;
The gate structure being formed by stacking by gate dielectric layer and polysilicon gate, the polysilicon gate are covered on the body surface and prolong It reaches on the drift region, the body area covered by the polysilicon gate is used to form channel;
Drift region oxygen is formed in the drift region surface, has interval between the drift region oxygen and the body area;It is described more The first side of crystal silicon grid is located in the body area, and the second side of the polysilicon gate extends on the drift region oxygen;
The source region of first conduction type heavy doping is formed in the body surface and with the first side of the polysilicon gate from right It is quasi-;
The drain region of first conduction type heavy doping is formed in the drift region surface and the second side with the drift region oxygen Autoregistration;
It is formed with the interpolation doped layer of the second conduction type doping on the surface of the drift region, is born in LDMOS device reversed When bias, the doping concentration of the interpolation doped layer, which meets, to be carried out assisted depletion to the drift region and keeps the drift region complete The electric field strength exhausted in foregoing description drift region is below critical electric field;
On lateral position, the interpolation doped layer is located at the overlay area of the drift region oxygen;It is described in lengthwise position Interpolation doped layer is located at the bottom of the drift region oxygen;Between the interpolation doped layer and the bottom of the drift region oxygen It is formed with surface current channel region;
The impurity of the surface current channel region by the drift region bulk doped impurity and the first conduction type One ion implanted layer impurity is formed by stacking, and first ion implanted layer increases the doping concentration of the surface current channel region And the interpolation doped layer is reduced in the LDMOS device forward conduction to the depletion widths of the surface current channel region To make the conducting width of the surface current channel region increase, to reduce the forward conduction resistance of the LDMOS device.
2. LDMOS device as described in claim 1, it is characterised in that:The interpolation doped layer and first ion implanting Layer is all formed using ion implantation technology and interpolation doped layer light shield corresponding with first ion implanted layer is identical, institute It is identical with the lateral dimension of the interpolation doped layer to state the first ion implanted layer.
3. LDMOS device as claimed in claim 2, it is characterised in that:The interpolation doped layer and first ion implanting Layer is sequentially formed under the definition of identical light shield.
4. LDMOS device as described in claim 1, it is characterised in that:The drift region by the first conductive type of trap district's groups at, The body area is formed in the selection area of the drift region.
5. LDMOS device as claimed in claim 4, it is characterised in that:First conduction type well region of the drift region is formed In the second conductive type semiconductor substrate surface.
6. LDMOS device as claimed in claim 5, it is characterised in that:The semiconductor substrate is silicon substrate.
7. LDMOS device as described in claim 1, it is characterised in that:The gate dielectric layer is gate oxide.
8. LDMOS device as described in claim 1, it is characterised in that:The doping concentration of the surface current channel region is institute 2 times~3 times for stating the doping concentration of the ontology of drift region.
9. a kind of manufacturing method of LDMOS device, which is characterized in that include the following steps:
Step 1: forming the drift region of the first conduction type doping in semiconductor substrate surface;
Step 2: the body area of the second conduction type doping is formed, the body area and drift region side contact;
Step 3: forming drift region oxygen, the drift region oxygen is located at the drift region surface, the drift region oxygen and institute Shu Ti has interval between area;
Step 4: lithographic definition goes out the forming region of interpolation doped layer, carries out the second conductive type ion and be infused in the drift The surface in area forms the interpolation doped layer, when LDMOS device bears reverse biased, the doping concentration of the interpolation doped layer Meet the electric field strength that assisted depletion is carried out to the drift region and is made in the completely depleted foregoing description drift region in the drift region Below critical electric field;
On lateral position, the interpolation doped layer is located at the overlay area of the drift region oxygen;It is described in lengthwise position Interpolation doped layer is located at the bottom of the drift region oxygen;Between the interpolation doped layer and the bottom of the drift region oxygen It is formed with surface current channel region;
Lead to Step 5: then carrying out the first conductive type ion using the lithographic definition in step 4 and being infused in the surface current The first ion implanted layer is formed in road area, the impurity of the surface current channel region is miscellaneous by the bulk doped of the drift region First ion implanted layer impurity of matter and the first conduction type is formed by stacking, and first ion implanted layer makes the surface current The doping concentration of channel region increases and reduces the interpolation doped layer in the LDMOS device forward conduction to the surface The depletion widths in current channel area are to make the conducting width of the surface current channel region increase, to reduce the LDMOS The forward conduction resistance of device;
Step 6: forming the gate structure being formed by stacking by gate dielectric layer and polysilicon gate, the polysilicon gate is covered on described Body surface simultaneously extends on the drift region, and the body area covered by the polysilicon gate is used to form channel;It is described more The first side of crystal silicon grid is located in the body area, and the second side of the polysilicon gate extends on the drift region oxygen;
Step 7: the source and drain ion implanting for carrying out the first conduction type heavy doping is formed simultaneously source region and drain region, the source region shape Body surface described in Cheng Yu and the first side autoregistration with the polysilicon gate;The drain region is formed in the drift region surface And the second side autoregistration with the drift region oxygen.
10. the manufacturing method of LDMOS device as claimed in claim 9, it is characterised in that:Drift region described in step 1 is by One conductive type of trap district's groups are formed at and using well region technique;The semiconductor substrate is the doping of the second conduction type, the drift The the first conduction type well region for moving area is formed in the second conductive type semiconductor substrate surface;The body area is formed in the drift In the selection area in area.
11. the manufacturing method of LDMOS device as claimed in claim 9, it is characterised in that:The gate dielectric layer is gate oxidation Layer.
12. the manufacturing method of LDMOS device as claimed in claim 9, it is characterised in that:The surface current channel region is mixed Miscellaneous concentration is 2 times~3 times of the doping concentration of the ontology of the drift region.
13. the manufacturing method of LDMOS device as claimed in claim 9, it is characterised in that:The LDMOS device is N-type LDMOS device, the first conduction type are N-type, and the second conduction type is p-type.
14. the manufacturing method of LDMOS device as claimed in claim 13, it is characterised in that:The drift formed in step 1 Shifting area is Uniform Doped and doping concentration is 1e15cm-3~1e16cm-3
The impurity of the corresponding ion implanting of interpolation doped layer described in step 4 is boron, implantation dosage 2e12cm-2~5e12cm-2, Implantation Energy is 1000kev~2000kev;
The impurity of the corresponding ion implanting of first ion implanted layer described in step 5 is arsenic or phosphorus, implantation dosage 1e12cm-2 ~5e12cm-2, Implantation Energy is determining according to the thickness of the drift region oxygen and requires to guarantee first ion implanted layer pair The peak value for the ion implanting answered is located in the surface current channel region of the bottom the drift region Chang Yang.
15. the manufacturing method of LDMOS device as claimed in claim 9, it is characterised in that:The LDMOS device is p-type LDMOS device, the first conduction type are p-type, and the second conduction type is N-type.
CN201810695463.2A 2018-06-29 2018-06-29 LDMOS device and its manufacturing method CN108878533A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105428415A (en) * 2015-11-16 2016-03-23 上海华虹宏力半导体制造有限公司 NLDMOS device and manufacturing method therefor
US20170194475A1 (en) * 2013-07-18 2017-07-06 Sensor Electronic Technology, Inc. Lateral/Vertical Semiconductor Device with Embedded Isolator
CN107644817A (en) * 2016-07-22 2018-01-30 北大方正集团有限公司 LDMOS and preparation method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170194475A1 (en) * 2013-07-18 2017-07-06 Sensor Electronic Technology, Inc. Lateral/Vertical Semiconductor Device with Embedded Isolator
CN105428415A (en) * 2015-11-16 2016-03-23 上海华虹宏力半导体制造有限公司 NLDMOS device and manufacturing method therefor
CN107644817A (en) * 2016-07-22 2018-01-30 北大方正集团有限公司 LDMOS and preparation method thereof

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