CN107644817A - LDMOS and preparation method thereof - Google Patents
LDMOS and preparation method thereof Download PDFInfo
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- CN107644817A CN107644817A CN201610585260.9A CN201610585260A CN107644817A CN 107644817 A CN107644817 A CN 107644817A CN 201610585260 A CN201610585260 A CN 201610585260A CN 107644817 A CN107644817 A CN 107644817A
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Abstract
The invention provides a kind of LDMOS and preparation method thereof, wherein, the preparation method of LDMOS includes：P type trap zone and N-type well region are sequentially formed in P type substrate；P-type buried district is formed in the specified junction depth position of N-type well region；N-type ion doped region is formed in the N-type well region above p-type buried district；Oxide layer is formed above N-type ion doped region, oxide layer does not cover the calmodulin binding domain CaM of N-type well region and P type trap zone；Grid structure is formed above calmodulin binding domain CaM；Drain electrode structure is formed in N-type well region；Source configuration is formed in the P type trap zone in the outside of grid structure；Block contact is formed in the N-type well region in the outside of source configuration, to complete the preparation of LDMOS.By technical scheme, while device voltage endurance is ensured, device low on-resistance and power consumption penalty are reduced.
Description
Technical field
The present invention relates to field of terminal technology, in particular to a kind of system of LDMOS
Preparation Method and a kind of LDMOS.
Background technology
In the related art, super-pressure LDMOS (UHVLDMOS, Ultra High
Voltage Laterally Diffused Metal Oxide Semiconductor) it is special with its high withstand voltage characteristic and low conducting
Property be widely used in integrated circuit, wherein, voltage endurance ensure that device reliability height, and low on state characteristic is related to device
Power consumption, by reducing the conducting resistance of device, the working temperature of power device on the one hand can be reduced, improve power chip integrated
Compatibility in circuit, on the other hand, the response time of device can be shortened by reducing the conducting resistance of device.
Therefore, how further to reduce the conducting resistance of LDMOS turns into urgently to be resolved hurrily
Technical problem.
The content of the invention
The present invention is based at least one above-mentioned technical problem, it is proposed that a kind of new lateral diffused metal oxide half
The preparation scheme of conductor, N-type ion doping is formed by the surface of the N-type well region in LDMOS
Area, the ion concentration of the surface texture of LDMOS is improved, led so as to reduce the transverse direction of device
The resistivity of circulation passage, the response characteristic of device is improved, further, since N-type ion doped region is not in PN junction interface area
Domain, therefore, the formation of N-type ion doped region have no effect on the voltage endurance of device.
In view of this, a kind of embodiment according to the first aspect of the invention, it is proposed that lateral diffused metal oxide half
The preparation method of conductor, including：P type trap zone and N-type well region are sequentially formed in P type substrate；In the specified junction depth position of N-type well region
Put to form p-type buried district；N-type ion doped region is formed in the N-type well region above p-type buried district；It is square on N-type ion doped region
Into oxide layer, oxide layer does not cover the calmodulin binding domain CaM of N-type well region and P type trap zone；Grid structure is formed above calmodulin binding domain CaM；
Drain electrode structure is formed in N-type well region；Source configuration is formed in the P type trap zone in the outside of grid structure；In the outer of source configuration
Block contact is formed in the N-type well region of side, to complete the preparation of LDMOS.
In the technical scheme, by the surface of the N-type well region in LDMOS formed N-type from
Sub- doped region, the ion concentration of the surface texture of LDMOS is improved, so as to reduce device
The resistivity of horizontal conductive channel, the response characteristic of device is improved, further, since N-type ion doped region is not in PN junction
Interface zone, therefore, the formation of N-type ion doped region have no effect on the voltage endurance of device.
Wherein, P type substrate can be the silicon substrate of p-type doping, and crystal orientation 100, sheet resistance is 100 /cm2, P type trap zone and
N-type well region forms PN junction, and N-type well region diffusion depth in the presence of high temperature pushes away trap is generally 8 microns, pushes away trap temperature and be generally
1100 degrees Celsius, pushing away the trap time is generally 6 hours, to form N-type deep-well region, meanwhile, the horizontal conductive channel of device is also served as,
After p-type buried district is formed (general depth is 2 microns), the ion concentration of the N-type well region above p-type buried district still than relatively low, because
This in the region, it is necessary to form the N-type ion doped region of high concentration, common Implantation Energy such as 100Kev, implantation dosage can
Use 1E12/cm2, this dosage can be with tolerance ± 5%, and then forms the N-type passage of rather high concentration on silicon chip substrate surface,
Reduce device on-resistance.
In addition, the preparation of field oxide can pass through thermal oxidation technology, chemical vapor deposition method or LOCOS techniques
(Local Oxidation of Silicon, local oxidation) is realized.
In the above-mentioned technical solutions, it is preferable that P type trap zone and N-type well region are sequentially formed in P type substrate, is specifically included
Following steps：First time p-type ion implanting is carried out to the designated area of P type substrate, the element of first time p-type ion implanting is boron
Series elements, the energy range of first time p-type ion implanting is 45~55KeV, and the first time dosage range of p-type ion implanting is
8.9E12~9.1E12/cm2；First time N-type ion implanting, first time N-type ion are carried out to the P type substrate beyond designated area
The element of injection is phosphorus series elements, and the energy range of first time p-type ion implanting is 90~110KeV, and first time p-type ion is noted
The dosage range entered is 1.9E12~2.1E12/cm2。
In the technical scheme, by carrying out first time p-type ion implanting, first time p-type to the designated area of P type substrate
The element of ion implanting is boron series elements, and the energy range of first time p-type ion implanting is 45~55KeV, first time p-type ion
The dosage range of injection is 8.9E12~9.1E12/cm2, and to beyond designated area P type substrate carry out first time N-type from
Son injection, the element of first time N-type ion implanting be phosphorus series elements, the energy range of first time p-type ion implanting is 90~
110KeV, the dosage range of first time p-type ion implanting is 1.9E12~2.1E12/cm2, form the oxidation of horizontal proliferation metal
The PN junction of thing semiconductor.
In any of the above-described technical scheme, it is preferable that the energy of first time p-type ion implanting is 50KeV, first time P
The dosage of type ion implanting is 9E12/cm2。
In any of the above-described technical scheme, it is preferable that the energy of first time N-type ion implanting is 100KeV, first time N
The dosage of type ion implanting is 2E12/cm2。
In any of the above-described technical scheme, it is preferable that also include：After first time N-type ion implanting is completed, 1000
P type substrate is carried out under~1200 DEG C of temperature range to push away trap processing, the time range for pushing away hydrazine processing is 5~7 hours.
In the technical scheme, by after first time N-type ion implanting is completed, in 1000~1200 DEG C of temperature range
Under to P type substrate push away trap processing, the time range for pushing away hydrazine processing is 5~7 hours, have activated the N-type ion of injection.
It is 100KeV in the energy of first time N-type ion implanting, the dosage of first time N-type ion implanting is 2E12/cm2
Afterwards, trap is pushed away at 1100 DEG C 6 hours, the diffusion depth for obtaining N-type well region is 8 microns.
In any of the above-described technical scheme, it is preferable that form p-type buried district in the specified junction depth position of N-type well region, specifically
Comprise the following steps：Second of p-type ion implanting is carried out to N-type well region, the element of second of p-type ion implanting is boron element,
The Implantation Energy scope of second of p-type ion implanting is 2.375~2.625MeV, and the dosage of second of p-type ion implanting is
4.95~5.05E12/cm2。
In the technical scheme, by carrying out second of p-type ion implanting to N-type well region, second p-type ion implanting
Element is boron element, and the Implantation Energy scope of second of p-type ion implanting is 2.375~2.625MeV, and second of p-type ion is noted
The dosage entered is 4.95~5.05E12/cm2, the p-type buried district that junction depth is 2 microns is formd, improves the reliability of device.
In any of the above-described technical scheme, it is preferable that the Implantation Energy of second of p-type ion implanting is 2.5MeV, the
The dosage of secondary p-type ion implanting is 5E12/cm2。
In any of the above-described technical scheme, it is preferable that N-type ion doping is formed in the N-type well region above p-type buried district
Area, specifically include following steps：N-type well region above p-type buried district carries out second of N-type ion implanting, second of N-type ion
The element of injection is phosphorus series elements, and the energy range of second of N-type ion implanting is 95~105KeV, and second of N-type ion is noted
The dosage range entered is 0.95E12~1.05E12/cm2。
In the technical scheme, second of N-type ion implanting is carried out by the N-type well region above p-type buried district, for the second time
The element of N-type ion implanting is phosphorus series elements, and the energy range of second of N-type ion implanting is 95~105KeV, second of N-type
The dosage range of ion implanting is 0.95E12~1.05E12/cm2, form the Ntop regions above p-type buried district, i.e., N-type from
Sub- doped region, the surface ion doping concentration of device is improved, the conducting resistance of the surface channel of device is reduced, improves device
The speed of response of part.
In any of the above-described technical scheme, it is preferable that the energy range of second of N-type ion implanting is 100KeV, the
The dosage range of secondary N-type ion implanting is 1E12/cm2, after second of N-type ion implanting is completed, to N-type ion doped region
Made annealing treatment with p-type buried district, wherein, the temperature range of annealing is 950~1050 DEG C, the time range of annealing
For 15~25 minutes.
In the technical scheme, by using rapid thermal anneal process (RTA, Rapid Thermal Anneal) to N-type
Ion doped region and p-type buried district are handled, and lattice damage caused by the one hand having repaired ion implanting, on the other hand have activated
The foreign ion of injection.
Embodiment according to the second aspect of the invention, it is proposed that a kind of LDMOS, use
The preparation method of LDMOS described in any of the above-described technical scheme is prepared.
In the technical scheme, by the surface of the N-type well region in LDMOS formed N-type from
Sub- doped region, the ion concentration of the surface texture of LDMOS is improved, so as to reduce device
The resistivity of horizontal conductive channel, the response characteristic of device is improved, further, since N-type ion doped region is not in PN junction
Interface zone, therefore, the formation of N-type ion doped region have no effect on the voltage endurance of device.
Brief description of the drawings
Fig. 1 shows the signal of the preparation method of LDMOS according to an embodiment of the invention
Flow chart；
Fig. 2 to Figure 10 shows the preparation process of LDMOS according to an embodiment of the invention
Partial cutaway schematic.
Embodiment
It is below in conjunction with the accompanying drawings and specific real in order to be more clearly understood that the above objects, features and advantages of the present invention
Mode is applied the present invention is further described in detail.It should be noted that in the case where not conflicting, the implementation of the application
Feature in example and embodiment can be mutually combined.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still, the present invention may be used also
To be different from other modes described here using other to implement, therefore, protection scope of the present invention is not by described below
Specific embodiment limitation.
Fig. 1 shows the preparation method of LDMOS according to an embodiment of the invention
Schematic flow diagram.
As shown in figure 1, the preparation method of LDMOS according to an embodiment of the invention,
Including：Step 102, P type trap zone and N-type well region are sequentially formed in P type substrate；Step 104, in the specified junction depth of N-type well region
Position forms p-type buried district；Step 106, N-type ion doped region is formed in the N-type well region above p-type buried district；Step 108, in N
Oxide layer is formed above type ion doped region, oxide layer does not cover the calmodulin binding domain CaM of N-type well region and P type trap zone；In calmodulin binding domain CaM
Top forms grid structure；Step 110, drain electrode structure is formed in N-type well region；Step 112, in the P in the outside of grid structure
Source configuration is formed in type well region；Step 114, block contact is formed in the N-type well region in the outside of source configuration, step 116, with
Complete the preparation of LDMOS.
In the technical scheme, by the surface of the N-type well region in LDMOS formed N-type from
Sub- doped region, the ion concentration of the surface texture of LDMOS is improved, so as to reduce device
The resistivity of horizontal conductive channel, the response characteristic of device is improved, further, since N-type ion doped region is not in PN junction
Interface zone, therefore, the formation of N-type ion doped region have no effect on the voltage endurance of device.
Wherein, P type substrate can be the silicon substrate of p-type doping, and crystal orientation 100, sheet resistance is 100 /cm2, P type trap zone and
N-type well region forms PN junction, and N-type well region diffusion depth in the presence of high temperature pushes away trap is generally 8 microns, pushes away trap temperature and be generally
1100 degrees Celsius, pushing away the trap time is generally 6 hours, to form N-type deep-well region, meanwhile, the horizontal conductive channel of device is also served as,
After p-type buried district is formed (general depth is 2 microns), the ion concentration of the N-type well region above p-type buried district still than relatively low, because
This in the region, it is necessary to form the N-type ion doped region of high concentration, common Implantation Energy such as 100Kev, implantation dosage can
Use 1E12/cm2, this dosage can be with tolerance ± 5%, and then forms the N-type passage of rather high concentration on silicon chip substrate surface,
Reduce device on-resistance.
In addition, the preparation of field oxide can pass through thermal oxidation technology, chemical vapor deposition method or LOCOS techniques
(Local Oxidation of Silicon, local oxidation) is realized.
In the above-mentioned technical solutions, it is preferable that P type trap zone and N-type well region are sequentially formed in P type substrate, is specifically included
Following steps：First time p-type ion implanting is carried out to the designated area of P type substrate, the element of first time p-type ion implanting is boron
Series elements, the energy range of first time p-type ion implanting is 45~55KeV, and the first time dosage range of p-type ion implanting is
8.9E12~9.1E12/cm2；First time N-type ion implanting, first time N-type ion are carried out to the P type substrate beyond designated area
The element of injection is phosphorus series elements, and the energy range of first time p-type ion implanting is 90~110KeV, and first time p-type ion is noted
The dosage range entered is 1.9E12~2.1E12/cm2。
In the technical scheme, by carrying out first time p-type ion implanting, first time p-type to the designated area of P type substrate
The element of ion implanting is boron series elements, and the energy range of first time p-type ion implanting is 45~55KeV, first time p-type ion
The dosage range of injection is 8.9E12~9.1E12/cm2, and to beyond designated area P type substrate carry out first time N-type from
Son injection, the element of first time N-type ion implanting be phosphorus series elements, the energy range of first time p-type ion implanting is 90~
110KeV, the dosage range of first time p-type ion implanting is 1.9E12~2.1E12/cm2, form the oxidation of horizontal proliferation metal
The PN junction of thing semiconductor.
In any of the above-described technical scheme, it is preferable that the energy of first time p-type ion implanting is 50KeV, first time P
The dosage of type ion implanting is 9E12/cm2。
In any of the above-described technical scheme, it is preferable that the energy of first time N-type ion implanting is 100KeV, first time N
The dosage of type ion implanting is 2E12/cm2。
In any of the above-described technical scheme, it is preferable that also include：After first time N-type ion implanting is completed, 1000
P type substrate is carried out under~1200 DEG C of temperature range to push away trap processing, the time range for pushing away hydrazine processing is 5~7 hours.
In the technical scheme, by after first time N-type ion implanting is completed, in 1000~1200 DEG C of temperature range
Under to P type substrate push away trap processing, the time range for pushing away hydrazine processing is 5~7 hours, have activated the N-type ion of injection.
After first time N-type ion implanting is carried out (energy of first time N-type ion implanting is 100KeV, first time N-type from
The dosage of son injection is 2E12/cm2), trap is pushed away at 1100 DEG C 6 hours, the diffusion depth for obtaining N-type well region is 8 microns.
In any of the above-described technical scheme, it is preferable that form p-type buried district in the specified junction depth position of N-type well region, specifically
Comprise the following steps：Second of p-type ion implanting is carried out to N-type well region, the element of second of p-type ion implanting is boron element,
The Implantation Energy scope of second of p-type ion implanting is 2.375~2.625MeV, and the dosage of second of p-type ion implanting is
4.95~5.05E12/cm2。
In the technical scheme, by carrying out second of p-type ion implanting to N-type well region, second p-type ion implanting
Element is boron element, and the Implantation Energy scope of second of p-type ion implanting is 2.375~2.625MeV, and second of p-type ion is noted
The dosage entered is 4.95~5.05E12/cm2, the p-type buried district that junction depth is 2 microns is formd, improves the reliability of device.
In any of the above-described technical scheme, it is preferable that the Implantation Energy of second of p-type ion implanting is 2.5MeV, the
The dosage of secondary p-type ion implanting is 5E12/cm2。
In any of the above-described technical scheme, it is preferable that N-type ion doping is formed in the N-type well region above p-type buried district
Area, specifically include following steps：N-type well region above p-type buried district carries out second of N-type ion implanting, second of N-type ion
The element of injection is phosphorus series elements, and the energy range of second of N-type ion implanting is 95~105KeV, and second of N-type ion is noted
The dosage range entered is 0.95E12~1.05E12/cm2。
In the technical scheme, second of N-type ion implanting is carried out by the N-type well region above p-type buried district, for the second time
The element of N-type ion implanting is phosphorus series elements, and the energy range of second of N-type ion implanting is 95~105KeV, second of N-type
The dosage range of ion implanting is 0.95E12~1.05E12/cm2, form the Ntop regions above p-type buried district, i.e., N-type from
Sub- doped region, the surface ion doping concentration of device is improved, the conducting resistance of the surface channel of device is reduced, improves device
The speed of response of part.
In any of the above-described technical scheme, it is preferable that the energy range of second of N-type ion implanting is 100KeV, the
The dosage range of secondary N-type ion implanting is 1E12/cm2, after second of N-type ion implanting is completed, to N-type ion doped region
Made annealing treatment with p-type buried district, wherein, the temperature range of annealing is 950~1050 DEG C, the time range of annealing
For 15~25 minutes.
In the technical scheme, by using rapid thermal anneal process (RTA, Rapid Thermal Anneal) to N-type
Ion doped region and p-type buried district are handled, and lattice damage caused by the one hand having repaired ion implanting, on the other hand have activated
The foreign ion of injection.
With reference to preparations of the Fig. 2 to Figure 10 to LDMOS according to an embodiment of the invention
Scheme is specifically described.
As shown in Fig. 2 prepared substrate material is p-type, 100 crystal orientation, sheet resistance is 100 /cm2, carry out first Zero photoetching,
Etching, but be to be subsequently lithographically formed alignment mark, specifically including the purpose of this step：P-type trap is sequentially formed in P type substrate
Area 202 and N-type well region 204；P-type buried district 206 is formed in the specified junction depth position of N-type well region 204；Above p-type buried district 206
N-type ion doped region 208 is formed in N-type well region 204；Oxide layer 210, oxide layer are formed above N-type ion doped region 208
210 do not cover the calmodulin binding domain CaM of N-type well region 204 and P type trap zone 202；Grid structure 212 is formed above calmodulin binding domain CaM；In N-type
Drain electrode structure 216 is formed in well region 204；Source configuration 214 is formed in the P type trap zone 202 in the outside of grid structure 212；
Block contact 218 is formed in the N-type well region 204 in the outside of source configuration 214, to complete LDMOS
Prepare.
In the technical scheme, N is formed by the surface of the N-type well region 204 in LDMOS
Type ion doped region 208, the ion concentration of the surface texture of LDMOS is improved, so as to reduce
The resistivity of the horizontal conductive channel of device, the response characteristic of device is improved, further, since N-type ion doped region 208 is not
In PN junction interface zone, therefore, the formation of N-type ion doped region 208 has no effect on the voltage endurance of device.
Wherein, P type substrate can be the silicon substrate of p-type doping, and crystal orientation 100, sheet resistance is 100 /cm2, P type trap zone
202 and N-type well region 204 form PN junction, the diffusion depth in the presence of high temperature pushes away trap of N-type well region 204 is generally 8 microns, pushes away trap
Temperature is generally 1100 degrees Celsius, pushes away the trap time and is generally 6 hours, to form N-type deep-well region, meanwhile, also serve as the horizontal stroke of device
To conductive channel, after p-type buried district 206 is formed (general depth is 2 microns), the N-type well region 204 of the top of p-type buried district 206 from
Sub- concentration, it is necessary to forms the N-type ion doped region 208 of high concentration, common Implantation Energy still than relatively low in the region
Such as 100Kev, implantation dosage can use 1E12, this dosage can be with tolerance ± 5%, and then forms phase on silicon chip substrate surface
To the N-type passage of high concentration, device on-resistance is reduced.
In addition, the preparation of field oxide 210 can pass through thermal oxidation technology, chemical vapor deposition method or LOCOS techniques
(Local Oxidation of Silicon, local oxidation) is realized.
As shown in Figures 2 and 3, P type trap zone 202 (i.e. P well, hereinafter PW) injection is carried out with N-type well region 204 (i.e.
N well, hereinafter NW) injection, PW is same type impurity with Psub, does not have junction interface, therefore figure below does not also indicate PW
Border, but PW now is present in silicon chip substrate surface more, specifically includes following steps：The designated area of P type substrate is entered
Row first time p-type ion implanting, the element of first time p-type ion implanting are boron series elements, the energy of first time p-type ion implanting
Scope is 45~55KeV, and the dosage range of first time p-type ion implanting is 8.9E12~9.1E12/cm2；To designated area with
Outer P type substrate carries out first time N-type ion implanting, and the element of first time N-type ion implanting is phosphorus series elements, first time p-type
The energy range of ion implanting is 90~110KeV, and the dosage range of first time p-type ion implanting is 1.9E12~2.1E12/
cm2。
In the technical scheme, by carrying out first time p-type ion implanting, first time p-type to the designated area of P type substrate
The element of ion implanting is boron series elements, and the energy range of first time p-type ion implanting is 45~55KeV, first time p-type ion
The dosage range of injection is 8.9E12~9.1E12/cm2, and to beyond designated area P type substrate carry out first time N-type from
Son injection, the element of first time N-type ion implanting be phosphorus series elements, the energy range of first time p-type ion implanting is 90~
110KeV, the dosage range of first time p-type ion implanting is 1.9E12~2.1E12/cm2, form the oxidation of horizontal proliferation metal
The PN junction of thing semiconductor.
In any of the above-described technical scheme, it is preferable that the energy of first time p-type ion implanting is 50KeV, first time P
The dosage of type ion implanting is 9E12/cm2。
In any of the above-described technical scheme, it is preferable that the energy of first time N-type ion implanting is 100KeV, first time N
The dosage of type ion implanting is 2E12/cm2。
As shown in figure 3, after first time N-type ion implanting is completed, p-type is served as a contrast under 1000~1200 DEG C of temperature range
Bottom carries out pushing away trap processing, and the time range for pushing away hydrazine processing is 5~7 hours.
In the technical scheme, by after first time N-type ion implanting is completed, in 1000~1200 DEG C of temperature range
Under to P type substrate push away trap processing, the time range for pushing away hydrazine processing is 5~7 hours, have activated the N-type ion of injection, and NW expands
Dissipate and form DNW (Deep N Well, N-type deep-well region), DNW now is simply present in the surface of silicon chip substrate as PW.
After first time N-type ion implanting is carried out (energy of first time N-type ion implanting is 100KeV, first time N-type from
The dosage of son injection is 2E12/cm2), trap is pushed away at 1100 DEG C 6 hours, the diffusion depth for obtaining N-type well region 204 is 8 microns.
As shown in figure 4, forming p-type buried district 206 in the specified junction depth position of N-type well region 204, following steps are specifically included：
After mask (mask layers) is formed, second of p-type ion implanting, the member of second of p-type ion implanting are carried out to N-type well region 204
Element is boron element, and the Implantation Energy scope of second of p-type ion implanting is 2.375~2.625MeV, second of p-type ion implanting
Dosage be 4.95~5.05E12/cm2。
In the technical scheme, by carrying out second of p-type ion implanting, second of p-type ion note to N-type well region 204
The element entered is boron element, and the Implantation Energy scope of second of p-type ion implanting is 2.375~2.625MeV, second of p-type from
The dosage of son injection is 4.95~5.05E12/cm2, it is 2 microns of p-type buried district 206 to form junction depth, and improve device can
By property.
In any of the above-described technical scheme, it is preferable that the Implantation Energy of second of p-type ion implanting is 2.5MeV, the
The dosage of secondary p-type ion implanting is 5E12/cm2。
As shown in figure 5, forming N-type ion doped region 208 in N-type well region 204 above p-type buried district 206, specifically include
Following steps：Retain Fig. 4 in mask (mask layers), to p-type buried district 206 above N-type well region 204 progress second of N-type from
Son injection, the element of second of N-type ion implanting be phosphorus series elements, the energy range of second of N-type ion implanting is 95~
105KeV, the dosage range of second of N-type ion implanting is 0.95E12~1.05E12/cm2。
In the technical scheme, second of N-type ion implanting is carried out by the N-type well region 204 above p-type buried district 206,
The element of second of N-type ion implanting is phosphorus series elements, and the energy range of second of N-type ion implanting is 95~105KeV, the
The dosage range of secondary N-type ion implanting is 0.95E12~1.05E12/cm2, form the Ntop areas above p-type buried district 206
Domain, i.e. N-type ion doped region 208, the surface ion doping concentration of device is improved, reduces the conducting of the surface channel of device
Resistance, improve the speed of response of device.
As shown in fig. 6, the energy range of second of N-type ion implanting is 100KeV, the dosage of second of N-type ion implanting
Scope is 1E12/cm2, after second of N-type ion implanting is completed, N-type ion doped region 208 and p-type buried district 206 are moved back
Fire processing, wherein, the temperature range of annealing is 950~1050 DEG C, and the time range of annealing is 15~25 minutes.
Wherein, a kind of embodiment of annealing includes：Design temperature is 1000 degrees Celsius, and the time is 20 minutes, p-type
There is slight diffusion buried district 206 and N-type ion doped region 208.
In the technical scheme, by using rapid thermal anneal process (RTA, Rapid Thermal Anneal) to N-type
Ion doped region 208 and p-type buried district 206 are handled, and have on the one hand repaired lattice damage caused by ion implanting, on the other hand
It has activated the foreign ion of injection.
As shown in fig. 6, aoxidized to form field oxide 210 with LOCOS process selectivities.
As shown in fig. 7, polysilicon layer is formed using chemical vapor deposition method, for forming grid structure 212, located at PN
The juncture area of knot, cover a lateral boundaries of field oxide 210.
As shown in figure 8, etching is patterned for polysilicon layer, to form grid structure 212.
As shown in figure 9, source configuration 214 (N-type heavy doping) and drain electrode structure 216 are formed using ion implantation technology simultaneously
(N-type heavy doping), wherein, source configuration 214 connects low potential when device works, in the PW in the outside of grid structure 212, leakage
Pole structure 216 connects high potential when device works, in the NW of the unlapped lateral boundaries of field oxide 210.
As shown in Figure 10, after source configuration 214 and drain electrode structure 216 is formed, ion implanting is carried out again to form block
218 (p-type heavy doping) are contacted, to reduce the contact resistance of device, are easy to implement the integrated welding of device.
In view of the conducting for how further reducing LDMOS proposed in correlation technique
The technical problem of resistance, the present invention propose a kind of preparation scheme of new LDMOS, by
The surface of the N-type well region of LDMOS forms N-type ion doped region, improves horizontal proliferation metal oxygen
The ion concentration of the surface texture of compound semiconductor, so as to reduce the resistivity of the horizontal conductive channel of device, improve device
The response characteristic of part, further, since N-type ion doped region is not in PN junction interface zone, therefore, N-type ion doped region
Form the voltage endurance for having no effect on device.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should be included in the scope of the protection.
Claims (10)
1. a kind of preparation method of LDMOS, it is characterised in that also include：
P type trap zone and N-type well region are sequentially formed in P type substrate；
P-type buried district is formed in the specified junction depth position of the N-type well region；
N-type ion doped region is formed in the N-type well region above the p-type buried district；
Oxide layer is formed above the N-type ion doped region, the oxide layer does not cover the N-type well region and the p-type trap
The calmodulin binding domain CaM in area；
Grid structure is formed above the calmodulin binding domain CaM；
Drain electrode structure is formed in the N-type well region；
Source configuration is formed in the P type trap zone in the outside of the grid structure；
Block contact is formed in the N-type well region in the outside of the source configuration, to complete the lateral diffused metal oxide half
The preparation of conductor.
2. the preparation method of LDMOS according to claim 1, it is characterised in that in p-type
P type trap zone and N-type well region are sequentially formed on substrate, specifically includes following steps：
First time p-type ion implanting, the element of the first time p-type ion implanting are carried out to the designated area of the P type substrate
For boron series elements, the energy range of the first time p-type ion implanting is 45~55KeV, the first time p-type ion implanting
Dosage range is 8.9E12~9.1E12/cm2；
First time N-type ion implanting is carried out to the P type substrate beyond the designated area, the first time N-type ion implanting
Element is phosphorus series elements, and the energy range of the first time p-type ion implanting is 90~110KeV, the first time p-type ion
The dosage range of injection is 1.9E12~2.1E12/cm2。
3. the preparation method of LDMOS according to claim 2, it is characterised in that
The energy of the first time p-type ion implanting is 50KeV, and the dosage of the first time p-type ion implanting is 9E12/cm2。
4. the preparation method of LDMOS according to claim 2, it is characterised in that
The energy of the first time N-type ion implanting is 100KeV, and the dosage of the first time N-type ion implanting is 2E12/cm2。
5. the preparation method of the LDMOS according to claim 3 or 4, it is characterised in that also
Including：
After the first time N-type ion implanting is completed, the P type substrate is carried out under 1000~1200 DEG C of temperature range
Trap processing is pushed away, the time range for pushing away hydrazine processing is 5~7 hours.
6. the preparation method of LDMOS according to claim 1, it is characterised in that described
The specified junction depth position of N-type well region forms p-type buried district, specifically includes following steps：
Carry out second of p-type ion implanting to the N-type well region, the element of second of p-type ion implanting is boron element, institute
The Implantation Energy scope for stating second of p-type ion implanting is 2.375~2.625MeV, the agent of second of p-type ion implanting
Measure as 4.95~5.05E12/cm2。
7. the preparation method of LDMOS according to claim 6, it is characterised in that
The Implantation Energy of second of p-type ion implanting is 2.5MeV, and the dosage of second of p-type ion implanting is
5E12/cm2。
8. the preparation method of LDMOS according to claim 1, it is characterised in that described
N-type ion doped region is formed in N-type well region above p-type buried district, specifically includes following steps：
N-type well region above the p-type buried district carries out second of N-type ion implanting, the member of second of N-type ion implanting
Element is phosphorus series elements, and the energy range of second of N-type ion implanting is 95~105KeV, second of N-type ion note
The dosage range entered is 0.95E12~1.05E12/cm2。
9. the preparation method of LDMOS according to claim 8, it is characterised in that
The energy range of second of N-type ion implanting is 100KeV, and the dosage range of second of N-type ion implanting is
1E12/cm2,
After second of N-type ion implanting is completed, the N-type ion doped region and p-type buried district are made annealing treatment,
Wherein, the temperature range of the annealing is 950~1050 DEG C, and the time range of the annealing is 15~25 points
Clock.
10. a kind of LDMOS, it is characterised in that using as any one of claim 1 to 9
The preparation method of LDMOS be prepared.
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| CN108878533A (en) * | 2018-06-29 | 2018-11-23 | 上海华虹宏力半导体制造有限公司 | LDMOS device and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110140201A1 (en) * | 2009-12-16 | 2011-06-16 | Cheng-Chi Lin | Lateral power mosfet structure and method of manufacture |
| CN104600111A (en) * | 2013-10-31 | 2015-05-06 | 上海华虹宏力半导体制造有限公司 | Ldmos device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110140201A1 (en) * | 2009-12-16 | 2011-06-16 | Cheng-Chi Lin | Lateral power mosfet structure and method of manufacture |
| CN104600111A (en) * | 2013-10-31 | 2015-05-06 | 上海华虹宏力半导体制造有限公司 | Ldmos device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878533A (en) * | 2018-06-29 | 2018-11-23 | 上海华虹宏力半导体制造有限公司 | LDMOS device and its manufacturing method |
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