CN102723354A - High voltage power LDMOS device and manufacture method thereof - Google Patents
High voltage power LDMOS device and manufacture method thereof Download PDFInfo
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- CN102723354A CN102723354A CN2011100786909A CN201110078690A CN102723354A CN 102723354 A CN102723354 A CN 102723354A CN 2011100786909 A CN2011100786909 A CN 2011100786909A CN 201110078690 A CN201110078690 A CN 201110078690A CN 102723354 A CN102723354 A CN 102723354A
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Abstract
The invention discloses a high voltage power LDMOS (Lateral Double-diffuse MOS)device and a manufacture method thereof. The high voltage power LDMOS device includes: a substrate, and a buried layer zone and a drift layer zone both located within the substrate. The said buried layer zone comprises a main buried layer zone and a vice buried layer zone, and the said vice buried layer zone is located in the drift region and near to the bottom of a source end, communicating with the said drift region. The high voltage power LDMOS device provided by the invention has the vice buried layer zone which is in the drift region near the bottom of the source end and communicated with the drift region, and the vice buried layer zone has an opposite doping type with that of the drift region, so that the vice buried layer zone is beneficial for realizing the balance between Qn and Qp charges and improving the stability of the device breakdown voltage.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly, relate to a kind of high-voltage power LDMOS device and manufacturing approach thereof.
Background technology
LDMOS (lateral double diffusion metal oxide semiconductor FET; Lateral Double-diffuseMOS) manufacturing of device mainly is to utilize double diffusion technique; Carry out twice boron phosphorous diffusion in succession at identical source/drain region, come the accurately length of control raceway groove by the difference of the horizontal junction depth of twice boron phosphorous diffusion.In the LDMOS device, between source region and drain region, resistive formation is arranged, be called drift region (drift).The existence of drift region has improved the puncture voltage of device, and has reduced the parasitic capacitance between source, leakage the two poles of the earth, helps improving frequency characteristic.Simultaneously, cushioning effect is played at raceway groove with between leaking in the drift region, has weakened the short-channel effect of LDMOS device.
High-voltage power LDMOS device is normal and low voltage power devices (or circuit) is integrated, realizes that the monolithic of high-voltage power integrated circuit (HVIC) is integrated.Traditional high-voltage power LDMOS device generally presents multi-finger (a plurality of finger) shape, and with reference to figure 1, Fig. 1 is the vertical view of the multi-finger shape and structure of prior art mesohigh power LDMOS device.This high-voltage power LDMOS device with multi-finger shape can be divided three classes according to the difference of its local shape: the first, and like frame of broken lines 1 indicated part among the figure, this part-structure is called the straight way part of multi-finger; The second, like frame of broken lines 2 indicated parts among the figure, this part-structure is called the multi-finger bend near end portion; The 3rd, like frame of broken lines 3 indicated parts among the figure, this part-structure is called the multi-finger bend near root portion.The multi-finger bend is referred to as multi-finger bend part near end portion and multi-finger bend near root portion, and different is to see that from the device vertical view the former is that drain terminal surrounds the source end for source end encirclement drain terminal, the latter.
In the traditional handicraft; No matter to form any class formation in above-mentioned three types; Generally all can form darker drift region; And adopt ion implantation technology to form the p-top layer opposite (for N type high-voltage power LDMOS device, be P type top layer, be called for short the p-top layer) at the top of said drift region with N type drift region doping type.This drift region structure with p-top layer; Be easy to partly realize the balance (balance of N type charge Q n and P type charge Q p) of electric charge at the straight way of multi-finger; Yet bend part for multi-finger; Especially the multi-finger bend is near the part of root, and the imbalance of Qn and Qp electric charge appears in regular meeting, relies on the drift region structure that has the p-top layer in the existing technology that is:; Can not realize the Qn and the Qp charge balance of multi-finger bend part drift region and substrate well, the imbalance of said multi-finger bend part Qn and Qp electric charge will directly influence the stability of LDMOS device electric breakdown strength.
Summary of the invention
In view of this, the present invention provides a kind of high-voltage power LDMOS device and manufacturing approach thereof, and this method can improve the stability of device electric breakdown strength.
For realizing above-mentioned purpose, the present invention provides following technical scheme:
A kind of high-voltage power LDMOS device, this device comprises:
Substrate;
Be positioned at intrabasement buried regions district and drift region, said buried regions district comprises main buried regions district and secondary buried regions district, and said secondary buried regions district is positioned at the drift region and is connected near bottom, source portion and with said drift region.
Preferably, in the above-mentioned high-voltage power LDMOS device, the degree of depth of an end that links to each other with main buried regions district in the said secondary buried regions district makes said secondary buried regions district become taper greater than the degree of depth of its other end.
Preferably, in the above-mentioned high-voltage power LDMOS device, the doping type of said buried regions district and drift region is opposite.
Preferably, in the above-mentioned high-voltage power LDMOS device, said drift region comprises source end well region and the drain terminal well region that is connected, and the degree of depth of said source end well region is less than the degree of depth of drain terminal well region; Said secondary buried regions district is positioned at end well region bottom, source and is connected with said source end well region.
Preferably, in the above-mentioned high-voltage power LDMOS device, the length of said drain terminal well region and the length ratio of drift region are: 1: 4～3: 4.
Preferably, in the above-mentioned high-voltage power LDMOS device, said substrate is the substrate that the multi-finger bend partly belongs to.
The present invention also provides a kind of high-voltage power LDMOS device making method, and this method comprises:
Substrate is provided, and said substrate comprises body layer;
In said substrate, form buried regions district and drift region, said buried regions district comprises main buried regions district and secondary buried regions district, and said secondary buried regions district is positioned at the drift region and is connected near bottom, source portion and with said drift region.
Preferably, in the above-mentioned high-voltage power LDMOS device making method, in said substrate, form the buried regions district, specifically comprise:
Spin coating photoresist layer on the body layer of said substrate;
With the mask with main buried regions district and secondary buried regions district pattern is that mask forms the photoresist layer with main buried regions district and secondary buried regions district pattern on said body layer;
With said photoresist layer with main buried regions district and secondary buried regions district pattern is that mask forms main buried regions district and secondary buried regions district in said body layer.
Preferably; In the above-mentioned high-voltage power LDMOS device making method; Secondary buried regions district pattern in the said mask comprises the Kong Qun that is formed by a plurality of holes, and the area in the near hole of crowd's middle distance master buried regions district, said hole pattern is greater than the area in the main buried regions of distance district pattern hole far away.
Preferably, in the above-mentioned high-voltage power LDMOS device making method, the secondary buried regions district pattern mesopore crowd's in the said mask the area sum and the percentage of the secondary buried regions district pattern gross area are: 10%～50%.
Can find out that from technique scheme high-voltage power LDMOS device provided by the present invention comprises: substrate; Be positioned at intrabasement buried regions district and drift region, said buried regions district comprises main buried regions district and secondary buried regions district, and said secondary buried regions district is positioned at the drift region and is connected near bottom, source portion and with said drift region.High-voltage power LDMOS device provided by the present invention; There is the secondary buried regions district that is connected with the drift region in the drift region near bottom, source portion; And the doping type of secondary buried regions district and drift region is opposite; So the existence in said secondary buried regions district can help to realize the balance of Qn and Qp electric charge, thereby be beneficial to the stability that improves device electric breakdown strength.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the vertical view of the multi-finger shape and structure of prior art mesohigh power LDMOS device;
Fig. 2 is the cross-sectional view of a kind of high-voltage power LDMOS device that the embodiment of the invention provided;
Fig. 3 is the cross-sectional view of the another kind of high-voltage power LDMOS device that the embodiment of the invention provided;
Fig. 4 is the cross-sectional view of another high-voltage power LDMOS device that the embodiment of the invention provided;
Fig. 5 is the manufacturing approach schematic flow sheet of a kind of high-voltage power LDMOS device that the embodiment of the invention provided;
Fig. 6 is the structural representation of a kind of mask that the embodiment of the invention provided;
Fig. 7 is the structural representation of the another kind of mask that the embodiment of the invention provided;
Fig. 8 is the structural representation of another mask that the embodiment of the invention provided;
Fig. 9～Figure 17 is the cross-sectional view in the high-voltage power LDMOS device manufacturing processes that the embodiment of the invention provided.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
Embodiment one
With reference to figure 2, Fig. 2 is the cross-sectional view of a kind of high-voltage power LDMOS device that the embodiment of the invention provided, and said high-voltage power LDMOS device (with N type high-voltage power LDMOS device is that example describes, down together) comprising: substrate 100; Be positioned at the buried regions district and the drift region 203 of substrate 100, said buried regions district comprises main buried regions district 103 and secondary buried regions district 104, and said secondary buried regions district 104 is positioned at drift region 203 and is connected near bottom, source portion and with drift region 203.
In addition, said high-voltage power LDMOS device also comprises: be positioned at the p-top layer 204 of drift region 203 near the top, said p-top layer 204 is opposite with the doping type of drift region 203; Be positioned at the field oxide 108 on the drift region 203; Be positioned at the drain region 114 of drift region 203; Be positioned in the main buried regions district 103 and the active well region 105 that links to each other with drift region 203; Be positioned at the source region 113 of active well region 105; Be positioned at the grid 109 on the active well region 105, the part that said grid 109 extends on the field oxide 108 is called source end grid field plate.
The doping type in the doping type of said drift region 203 and buried regions district is opposite; Main buried regions district 103 is identical with the doping type in secondary buried regions district 104 in the buried regions district, and said main buried regions district 103 forms with secondary buried regions district 104 simultaneously.
Said main buried regions district 103 demonstrates all identical rectangular-shaped structure of each position degree of depth (being vertical degree of depth); And said secondary buried regions district 104 demonstrates each position degree of depth cone structure all inequality; And the degree of depth of an end that links to each other with main buried regions district 103 in the said secondary buried regions district 104 is greater than the degree of depth of its other end, that is: in said secondary buried regions district 104, when its cross direction profiles during more and more away from main buried regions district 103; The pairing vertical degree of depth of its transverse area is more and more littler; Macroscopic view, vertical degree of depth in said secondary buried regions district 104 are gradual change, so said secondary buried regions district 104 also can be described as gradual change buried regions district.
By on can know; High-voltage power LDMOS device provided by the present invention, because said buried regions district comprises main buried regions district and secondary buried regions district, and said secondary buried regions district is positioned at the bottom, drift region and is connected with said drift region; And the doping type of secondary buried regions district and drift region is opposite; Therefore, the existence in secondary buried regions district can slow down the imbalance of drift region and buried regions district overlapping position Qn and Qp electric charge effectively, thereby makes the puncture voltage of high-voltage power LDMOS device can keep stability preferably.
Embodiment two
Different is with embodiment one, the high-voltage power LDMOS device that is provided in the present embodiment, and its drift region no longer is the common all identical well region of each position degree of depth, but comprises two well regions that the degree of depth is inequality.Drift region in the present embodiment is called graded drift regions, and in having the high-voltage power LDMOS device of graded drift regions, has removed the p-top layer, and is specific as follows:
With reference to figure 3, Fig. 3 is the cross-sectional view of the another kind of high-voltage power LDMOS device that the embodiment of the invention provided, and said high-voltage power LDMOS device comprises: substrate 100; Be positioned at the buried regions district and the graded drift regions of substrate 100; Wherein, said buried regions district comprises main buried regions district 103 and secondary buried regions district 104; Said graded drift regions comprises the drain terminal well region 202 and source end well region 201 that is connected, and the degree of depth of said drain terminal well region 202 is greater than the degree of depth of said source end well region 201; Said secondary buried regions district 104 is positioned at end well region 201 bottoms, said source and is connected with said source end well region 201.
Said high-voltage power LDMOS device also comprises: be positioned at the field oxide 108 on the graded drift regions; Be positioned at the drain region 114 of drain terminal well region 202; Be positioned in the main buried regions district 103 and the active well region 105 that links to each other with source end well region 201; Be positioned at the source region 113 of active well region 105; Be positioned at the grid 109 on the active well region 105, the part that said grid extends on the field oxide 108 is called source end grid field plate.
The doping type of said buried regions district and graded drift regions is opposite, but main buried regions district 103 is identical with the doping type in secondary buried regions district 104 in the said buried regions district, and drain terminal well region 202 is identical with the doping type of source end well region 201 in the said graded drift regions.
Drain terminal well region 202 is the well region near drain region 114 in the said graded drift regions; Said source end well region 201 is the well region near source region 113; And vertical degree of depth of each zone (transverse area) is all identical in the said drain terminal well region 202; Vertical degree of depth in each zone is also identical in the said source end well region 201, but the degree of depth of drain terminal well region 202 is greater than the degree of depth of source end well region 201, therefore; There is a degree of depth ledge structure inequality, gradual change in intersection at drain terminal well region 202 and source end well region 201, so the drift region of being made up of drain terminal well region 202 and source end well region 201 is called " graded drift regions ".
The length of graded drift regions described in the embodiment of the invention is the length sum of drain terminal well region 202 and source end well region 201, and the length ratio of the length of said drain terminal well region 202 and graded drift regions is: 1: 4～3: 4.
In said graded drift regions; Because the degree of depth of drain terminal well region 202 is greater than the degree of depth of source end well region 201; So charge carrier is easy in source end well region 201, exhaust with respect to drain terminal well region 202, thereby makes drain terminal well region 202 can bear higher voltage, therefore; In the high-voltage power LDMOS device provided by the present invention, removed p-top layer (referring to Fig. 1).Remove said p-top layer, make technical process oversimplify on the one hand, avoided on the other hand Qn and Qp charge balance being impacted, and then can make the puncture voltage of device more stable because of the fluctuation of p-top layer concentration.
And in the said graded drift regions; Can suitably improve its dopant dose; Make said high-voltage power LDMOS device have higher, stablize puncture voltage in, also have lower conducting resistance, alleviated common high-breakdown-voltage and the contradiction between the low on-resistance.
The high-voltage power LDMOS device that present embodiment provided; Said buried regions district comprises main buried regions district and secondary buried regions district; And said secondary buried regions district is arranged in the bottom of said graded drift regions source end well region and is connected with said source end well region, and the doping type of secondary buried regions district and source end well region is opposite, therefore; The existence in said secondary buried regions district can make Qn and Qp electric charge tend to balance, and then can improve the stability of device electric breakdown strength.
Below in conjunction with Fig. 4 embodiment two described high-voltage power LDMOS devices are described in more detail.
With reference to figure 4, Fig. 4 is the cross-sectional view of another high-voltage power LDMOS device that the embodiment of the invention provided, and said high-voltage power LDMOS device comprises: substrate 100; Be positioned at intrabasement buried regions district and graded drift regions; Wherein, said buried regions district comprises main buried regions district 103 and secondary buried regions district 104; Said graded drift regions comprises the source end well region 201 and drain terminal well region 202 that is connected, and the degree of depth of said drain terminal well region 202 is greater than the degree of depth of source end well region 201; Said secondary buried regions district 104 is positioned at end well region 201 bottoms, source and is connected with said source end well region 201.
Said high-voltage power LDMOS device also comprises: be positioned at the field oxide 108 on the graded drift regions; Be arranged in the low pressure well region 107 of graded drift regions drain terminal well region 202, the existence of said low pressure well region 107 mainly is the metal-oxide-semiconductor that in technology, forms mesolow, and said low pressure well region 107 can improve the high pressure dynamic I-V characteristic of high-voltage power LDMOS device again; Be positioned at the drain region 114 of said low pressure well region 107.
Said high-voltage power LDMOS device also comprises: be arranged in said substrate 100 and be positioned at the active well region 105 in the main buried regions district, buried regions district 103, said active well region 105 links to each other with source end well region 201; Be formed with body contact zone 112 and source region 113 in the said active well region 105, be formed with grid 109 on the said active well region 105, the part that grid 109 extends on the field oxide 108 is called source end grid field plate; Be positioned on the said field oxide 108 and be provided with drain terminal grid field plate 110 near the position in drain region 114, said drain terminal grid field plate 110 forms with grid 109 simultaneously.Acting as of said drain terminal grid field plate 110 and source end grid field plate: be beneficial to charge carrier exhausting in graded drift regions, bear high puncture voltage thereby be beneficial to device.
Said drain region 114 links to each other with drain terminal the first metal layer 120 with 118 through the metal 117 in the contact hole respectively with drain terminal grid field plate 110, and drain terminal the first metal layer 120 links to each other with drain terminal second metal level 128 with 125 through the tungsten plug 124 in the through hole again.In like manner, said body contact zone 112 links to each other with source end the first metal layer 119 with 116 through the metal 115 in the contact hole respectively with source region 113, and source end the first metal layer 119 links to each other with source end second metal level 126 with 123 through the tungsten plug 122 in the through hole again.Between the tungsten plug between each metal level, in each through hole and all isolated through intermetallic dielectric layer 127 between the tungsten plug in metal level and the through hole, it is isolated to pass through inter-level dielectric 121 between source end the first metal layer 119, drain terminal the first metal layer 120 and grid 109, the drain terminal grid field plate 110 etc.
The part that each metal level extends on field oxide 108 vertical directions forms metal field plate (comprising drain terminal metal field plate and source end metal field plate); The existence of said metal field plate also is beneficial to charge carrier exhausting in graded drift regions, and then contributes for the high-breakdown-voltage of device.
Need to prove; High-voltage power LDMOS device provided by the present invention; Its graded drift regions has comprised degree of depth drain terminal well region inequality 202 and source end well region 201, and does not have the p-top layer on the graded drift regions, and this also makes each field plate (comprising grid field plate and metal field plate) in the contribution of aspect carrier depletion, being done; Than prior art, be greatly improved.
The foregoing description one and the high-voltage power LDMOS device that embodiment two is provided both can be the pairing structure of straight way part of multi-finger, also can be the pairing structure of bend part of multi-finger.But, owing to adopt the formed high-voltage power LDMOS of prior art device, it generally is easier to realize the balance of Qn and Qp electric charge in the straight way part of multi-finger, so the straight way of said multi-finger partly still can form by prior art; And for the bend part of multi-finger; Especially the multi-finger bend is near the part of root; Then should form the structure of high-voltage power LDMOS device provided by the present invention, only in this way could alleviate the imbalance of Qn and Qp electric charge, and then the puncture voltage of stabilizing device.
More than describe high-voltage power LDMOS device provided by the present invention in detail, introduce the manufacturing approach of high-voltage power LDMOS device below.
Embodiment three
With reference to figure 5, Fig. 5 is the manufacturing approach schematic flow sheet of high-voltage power LDMOS device provided by the present invention.This method specifically comprises:
Step S1: substrate is provided, and said substrate comprises body layer.
The substrate that is provided in this step comprises body layer (also can claim substrate), follow-uply need on said body layer, form epitaxial loayer, and said body layer and epitaxial loayer are referred to as substrate.Will be referred to " in the substrate " and related notions such as " in the substrates " in the subsequent step, said " in the substrate " is meant that by the zone of substrate surface to the certain depth that extends below this zone belongs to the part of substrate; Said " in the substrate " is meant the zone that is made progress by substrate surface, and this zone does not belong to substrate itself.Among this paper other represented meaning is described also can be by that analogy.
Step S2: in said substrate, form buried regions district and drift region, said buried regions district comprises main buried regions district and secondary buried regions district, and said secondary buried regions district is positioned at the drift region and is connected near bottom, source portion and with said drift region.
In said substrate, form the buried regions district, concrete steps are following:
Spin coating photoresist layer on the body layer of said substrate; Utilization has the mask of main buried regions district and secondary buried regions district pattern and for mask said photoresist layer is made public, and develops afterwards, thereby on said body layer, forms the photoresist layer with main buried regions district and secondary buried regions district pattern; With said photoresist layer with main buried regions district and secondary buried regions district pattern is mask, adopts ion implantation technology in said body layer, to form the buried regions district, and said buried regions district comprises main buried regions district and secondary buried regions district.
Variation has taken place in used mask when in the embodiment of the invention said photoresist layer being made public relative to existing technologies.In the prior art,, generally has rectangular patterns on the used mask for multi-finger straight way part; And, generally have rectangular patterns and the semi-circular pattern that links to each other with this rectangular patterns on the used mask for multi-finger bend part.In the embodiment of the invention, comprise main buried regions district's pattern and secondary buried regions district pattern on the said mask.Wherein, said main buried regions district pattern is pairing pattern in the prior art; Said secondary buried regions district pattern comprises the Kong Qun that is formed by a plurality of apertures (also can be described as " island "), and the distance between each adjacent aperture of said Kong Qunzhong can equate also can not wait.In the more excellent scheme, when the distance between the said adjacent aperture equated, the area of the aperture that the main buried regions of operated by rotary motion distance district pattern is near was bigger; The area of the aperture that the main buried regions of distance district pattern is far away is less; This dosage with regard to the ion that the zone that makes away from main buried regions district pattern is injected into is less, thereby makes that its corresponding vertical degree of depth is more shallow, finally makes vertical degree of depth in the secondary buried regions district be taper and distributes; And more away from the position in main buried regions district, its degree of depth is more little in the secondary buried regions district; When the distance between the said adjacent aperture does not wait; Operated by rotary motion away from the spacing between the aperture of main buried regions district pattern greater than apart from the spacing between the nearer aperture of main buried regions district pattern; At this moment, the area of each aperture can be identical, also can be different; When the area of said each aperture not simultaneously, also should design and make area and each aperture of each aperture apart from the distance relation of being inversely proportional to of main buried regions district pattern.In any case design secondary buried regions district pattern, all should make vertical degree of depth in secondary buried regions district of final formation become the cone structure of gradual change, and in said secondary buried regions district more away from the position in main buried regions district, its corresponding vertical degree of depth is more little.
With reference to figure 6, Fig. 6 is the structural representation of a kind of mask that the embodiment of the invention provided, and this schemes the mask used version of corresponding multi-finger straight way part.Rectangular patterns 300 and a plurality of little square pattern 301 have been shown among the figure, and said rectangular patterns 300 is main buried regions district pattern, and said a plurality of little square pattern 301 have constituted secondary buried regions district pattern, and a plurality of little foursquare area is inequality.In said a plurality of little square pattern 301; Far away more apart from rectangular patterns 300; Its area is more little, and performance is in the drawings: c＜b＜a, wherein; A, b, c are respectively three little foursquare length of sides, and length of side a, b, pairing three the little squares of c are more and more far away apart from the distance of rectangular patterns 300.
With reference to figure 7, mask shown in Fig. 7 is used when making multi-finger bend part.Rectangular patterns in the main buried regions district pattern is not shown among the figure; Only show the semi-circular pattern in the main buried regions district pattern; A plurality of little squares constitute secondary buried regions district pattern shown in the figure; And said a plurality of little foursquare area is unequal, along with little square away from semi-circular pattern (promptly main buried regions district pattern), its area reduces gradually.The percentage of a plurality of little foursquare area sums and the secondary buried regions district pattern gross area in the secondary buried regions district pattern in the said mask (being the ratio of glazed area and the gross area in the secondary buried regions district pattern) is: 10%～50%; Preferably, the above-mentioned percentage of may command is 30%.
Semi-circular pattern and a plurality of little square pattern are the light-permeable zone among the figure; That is: when using mask shown in Figure 7 that photoresist layer on the body layer is made public; Develop afterwards; Then on said body layer, forming the photoresist layer with pattern shown in Figure 7, is mask with the photoresist layer with pattern shown in Figure 7 then, adopts ion implantation technology in said body layer, to inject ion.Because main buried regions district pattern comprised rectangle and semicircular area, thus ion can be injected in the body layer through said rectangle and semicircular area, thereby in said body layer all identical main buried regions district of each position degree of depth of formation; Because secondary buried regions district pattern comprises a plurality of little squares; And each little foursquare area is inversely proportional to the distance of the pattern apart from main buried regions district; So when ion after little square is injected in the body layer through each; In said body layer, form the secondary buried regions district of the taper of degree of depth gradual change, and the degree of depth of an end that links to each other with main buried regions district in the said secondary buried regions district is greater than the degree of depth of its other end.
With reference to figure 8, Fig. 8 is the structural representation of another mask that the embodiment of the invention provided.This mask is used when making multi-finger bend part equally; Fig. 8 is with the distinctive points of Fig. 7: each little foursquare arrangement mode is different; Each little square proper alignment among Fig. 8, the spacing between adjacent each row, each row all equate, among Fig. 7 in the formed row and column of each little square; Do not align between adjacent row and the row (or row be listed as); Arrange mutually but intersect, arrange thereby make each odd-numbered line (or each odd column) become equidistantly, each even number line (or each even column) becomes another kind of and equidistantly arranges.
Though each little foursquare arrangement mode is different among above-mentioned two figure; But both common ground are: the main buried regions of distance district pattern is far away more; Little foursquare area is more little, thereby vertical degree of depth in secondary buried regions district that can make final formation is along with reducing gradually away from main buried regions district.
Because in the row and column that each little square is formed among Fig. 7; Adjacent row and row, be listed as and be listed as into cross arrangement; This just makes that the ion concentration in the final formed secondary buried regions district is more even; And adopting the formed secondary buried regions of mask shown in Figure 8 district, the ion concentration in it is even not as the former comparatively speaking.
Need to prove; Aperture in the secondary buried regions district pattern can be square shape; Can be shapes such as circle or rhombus, to this, the present invention does not have special restriction yet; And the present invention is also unrestricted to the arrangement mode of each aperture, as long as the scope that all embodiment that those skilled in the art are obtained under the prerequisite of not making creative work all belong to the present invention to be protected.
After in the body layer of substrate, forming the buried regions district,, in said substrate, form and the opposite drift region of doping type, buried regions district through photoetching, etching, ion implantation technology then then at said body layer growing epitaxial layers with buried regions district.Said drift region is between source end and drain terminal, and the bottom of said drift region extend in the body layer.In addition, overlap mutually in body layer near the position of source end and the secondary buried regions district in the buried regions district said drift region, that is: said drift region is positioned at upper end, secondary buried regions district near the position of source end and is connected with said secondary buried regions district.Again because the doping type in drift region and secondary buried regions district is opposite, therefore, the position of overlapping mutually in drift region and secondary buried regions district makes Qn and Qp electric charge realization balance easily, and the balance of said Qn and Qp electric charge then can improve the stability of device electric breakdown strength.
In the technical process subsequently, need on said drift region, form field oxide, form grid on the surface of substrate, and in substrate, form corresponding source region and drain region etc., these technical processs no longer are described in detail here.
By on can know; High-voltage power LDMOS device making method provided by the present invention; Through changing the pattern of the mask that when forming the buried regions district, is adopted in the existing technology; And then in the body layer of substrate, form the buried regions district comprise main buried regions district and secondary buried regions district, and said secondary buried regions district is positioned at the bottom of the drift region of follow-up formation near the source end, and the doping type in drift region and buried regions district is opposite; This just makes the overlapping place of secondary buried regions district and drift region be easy to realize the balance of Qn and Qp electric charge, and the balance of said Qn and Qp electric charge helps to improve the stability of high-voltage power LDMOS device electric breakdown strength.
Embodiment four
Different is with embodiment three; The high-voltage power LDMOS device making method that is provided in the present embodiment; Not to adopt common processing step when forming the drift region, the drift region that formed drift region neither be common, but formed by two " graded drift regions " that well region constituted that the degree of depth is inequality; And removed the top layer in the said graded drift regions, concrete technical process is following:
Substrate is provided, and said substrate comprises body layer.Substrate described in the present embodiment be the multi-finger bend near the pairing substrate of root, said body layer is a P type silicon substrate.
In the substrate body layer, form deep-well region and buried regions district.
With reference to figure 9, in the body layer 101 of substrate, adopt ion implantation technology to form deep-well region 102, the position of said deep-well region 102 is near the follow-up drain region that will form, and formed deep-well region 102 is a N type doping deep-well region 102 in the present embodiment; Then in said body layer 101, adopt ion implantation technology to form the buried regions district; Mask used version is shown in Fig. 7 when forming the buried regions district; So formed buried regions district comprises main buried regions district 103 and secondary buried regions district 104; And said main buried regions district 103 is positioned at the below of the follow-up active well region that will form, and between said secondary buried regions district 104 and the deep-well region 102 certain distance is arranged, and the district of buried regions described in the present embodiment is P type buried dopant layer district.
After the ion in buried regions district injects completion, push away trap technology through high temperature and realize the diffusion of dopant ion in deep-well region 102 and buried regions district, the temperature that high temperature pushes away trap is about about 1100 ℃, and the time is about about 5h.
On the body layer of substrate, form epitaxial loayer.
With reference to Figure 10, through on said P type silicon substrate 101, the grow P type silicon epitaxy layer 200 of low concentration of growth technology, the thickness of formed epitaxial loayer 104 is about 3～6 μ m in the present embodiment.In the forming process of epitaxial loayer 200; The back-diffusion phenomenon can take place in the dopant ion in deep-well region 102 and the buried regions district; Be that said dopant ion can spread in epitaxial loayer 200, thereby make said deep-well region 102, main buried regions district 103 and secondary buried regions district 104 extend in the epitaxial loayer 200.
In said epitaxial loayer, form shallow well district, low pressure well region and active well region.
With reference to Figure 11; At first adopt ion implantation technology in said epitaxial loayer, to form the shallow well district 106 identical with deep-well region 102 doping types; Said shallow well district 106 is between the source region and drain region of follow-up formation; The degree of depth in said shallow well district 106 is approximately identical with the degree of depth of epitaxial loayer, and generally speaking, the ion dose that the dosage of the ion that is injected when forming shallow well district 106 is injected when forming deep-well region 102.Because when forming epitaxial loayer; All there is the back-diffusion part in said deep-well region 102, main buried regions district 103 and secondary buried regions district 104 in epitaxial loayer; So the time said shallow well district 106 overlap mutually near position, end, source and secondary buried regions district 104, overlap mutually near drain terminal position and deep-well region 102 in shallow well district 106.The position that overlap mutually in said shallow well district 106 and secondary buried regions district 104 is beneficial to the balance that realizes Qn and Qp electric charge, and said shallow well district 106 and deep-well region 102 overlap mutually and constituted graded drift regions.
In said graded drift regions; Be called drain terminal well region (can referring to part shown in Fig. 4 202) near the part (comprise deep-well region 102 and be arranged in the part shallow well district on deep-well region 102 vertical directions) of drain terminal, be called source end well region (can referring to part shown in Fig. 4 201) near the part (removing the subregion that is arranged on deep-well region 102 vertical directions in the shallow well district 106) of source end.The degree of depth of the well region of drain terminal described in the present embodiment is 6～12 μ m, and the ratio of the lateral length of said drain terminal well region and the lateral length of graded drift regions is: 1: 4～3: 4.
After shallow well district 106 forms, adopt ion implantation technology position near the drain region in said shallow well district 106 to form low pressure well region 107, the doping type of said low pressure well region 107 is identical with shallow well district 106.Being formed with of this low pressure well region 107 is beneficial to the high pressure dynamic I-V characteristic that improves high-voltage power LDMOS device.
After low pressure well region 107 forms, adopt ion implantation technology in said epitaxial loayer, to form active well region 105, said active well region 105 is positioned at the top in main buried regions district 103, and active well region 105 is a P type well region described in the present embodiment.Said active well region 105 is connected with shallow well district 106, thereby makes the zone that is dopant ion in the said epitaxial loayer.
After the ion of active well region 105 injects completion, push away trap technology through high temperature and realize the diffusion of dopant ion in shallow well district 106, low pressure well region 107 and active well region 105, the temperature that high temperature pushes away trap is about about 1100 ℃, and the time is about about 5h.
With reference to Figure 12, adopt LOCOS technology in said shallow well district 106, to form field oxide 108, the effect of said field oxide 108 is to isolate active device.
Form grid at substrate surface.
With reference to Figure 13; At first on the epitaxial loayer of substrate, form gate dielectric layer; Then on said gate dielectric layer, form grid material; On said active well region 105, form grid 109 through photoetching, etching technics then, simultaneously, on said field oxide 108, form drain terminal grid field plate 110 near the drain region.The part that extends in the said grid 109 on the field oxide 108 is called source end grid field plate.Being formed with of source end grid field plate and drain terminal grid field plate 110 is beneficial to and makes charge carrier exhausting in graded drift regions, thereby is beneficial to the puncture voltage that improves device.
Gate dielectric layer described in the present embodiment is a silicon dioxide, and said grid material is a polysilicon.
In the epitaxial loayer of substrate, be formed with the source region.
With reference to Figure 14; In said low pressure well region 107 and active well region 105, form heavily doped N type drain region 114 and N type source region 113 respectively through ion implantation technology, and in said active well region 105, form heavily doped P type body contact zone 112 through ion implantation technology.
With reference to Figure 15, after forming source region and drain region, form inter-level dielectric 121 at said substrate surface, inter-level dielectric described in the present embodiment 121 is a silicon dioxide.In said inter-level dielectric 121, form contact hole 115,116,117 and 118 through photoetching, etching technics subsequently, these four contact holes link to each other with drain region 114 with body contact zone 112, source region 113, drain terminal grid field plate 110 respectively.
With reference to Figure 16, on said inter-level dielectric 121, form the first metal layer, on said inter-level dielectric 121, form source end the first metal layer 119 and drain terminal the first metal layer 120 through photoetching, etching technics afterwards.When said the first metal layer forms; Also can be filled with metal in the contact hole 115,116,117 and 118; And then body contact zone 112 is linked to each other with source end the first metal layer 119 with 116 interior metals through contact hole 115 respectively with source region 113, drain terminal grid field plate 110 is linked to each other with drain terminal the first metal layer 120 with 118 interior metals through contact hole 117 respectively with drain region 114.
The part that said source end the first metal layer 119 extends on the field oxide 108 is a source end the first metal layer field plate; The part that said drain terminal the first metal layer 120 extends on the field oxide 108 is a drain terminal the first metal layer field plate; Having of these two field plates is beneficial to charge carrier exhausting in graded drift regions, thereby is beneficial to the puncture voltage that improves device.
With reference to figure 4; On said the first metal layer, form intermetallic dielectric layer 127; In said intermetallic dielectric layer 127, form through hole through photoetching, etching technics then, and in each through hole, fill the tungsten plug, the through hole of having filled the tungsten plug has 122,123,124 and 125 respectively.On intermetallic dielectric layer 127, form second metal level, on said intermetallic dielectric layer 127, form source end second metal level 126 and drain terminal second metal level 128 through photoetching, etching technics afterwards.Source end the first metal layer 119 can link to each other with source end second metal level 126 through the tungsten plug in through hole 122 and 123, and is same, and drain terminal the first metal layer 120 can link to each other with drain terminal second metal level 128 through the tungsten plug in through hole 124 and 125.The part that said drain terminal second metal level 128 extends on the field oxide 108 is the drain terminal second metal level field plate, and the existence of this field plate is beneficial to the puncture voltage that improves device equally.
Describe the manufacture process of high-voltage power LDMOS device above in detail; And the LDMOS of high-voltage power shown in Fig. 4 device architecture corresponding to the multi-finger bend near root portion; The profile that is device shown in Figure 4 can cut open down and get by BB ' arrow indication among Fig. 1; Different is, structure shown in Fig. 4 is for to form according to manufacturing approach of the present invention, but not forms by existing technology.
Near end portion, its forming process and said process are similar for the multi-finger bend, and the buried regions district also comprises main buried regions district and secondary buried regions district in its structure, so cross-section structure and Fig. 4 of the device that forms are similar.
For multi-finger straight way part, its buried regions district can make by existing technology, and the mask that when forming the buried regions district, is adopted in the existing technology only comprises main buried regions district pattern; Therefore; Do not have secondary buried regions district in the buried regions district of follow-up formation, with reference to Figure 17, Figure 17 shows the sectional structure chart of the corresponding multi-finger straight way part of high-voltage power LDMOS device; This figure can cut open down and get by AA ' arrow indication among Fig. 1; Different is, the forming process of its drift region of structure shown in Figure 17 (comprising drain terminal well region 202 and source end well region 201) forms by described in the present embodiment, and the forming process in buried regions district 103 still forms by existing technology.
The embodiment of the invention is described the manufacturing approach of high-voltage power LDMOS device in detail, by the produced high-voltage power LDMOS of this method device, can bear the different puncture voltage between 200V～1600V according to actual needs; And the high-voltage power LDMOS device that manufacturing is come out; Especially for multi-finger bend part; The pattern of mask used version when forming the buried regions district through changing; Can change the structure in the buried regions district of final formation, and then can make that Qn and Qp electric charge reach balance in the device, the balance of said Qn and Qp electric charge can improve the stability of device electric breakdown strength.
In addition; Formed drift region is for to have formed graded drift regions by two degree of depth well regions inequality in the embodiment of the invention, and the forming process of this graded drift regions and common CMOS technical process are similar, so this manufacturing approach can combine with common CMOS technology; Need not form the p-top layer in this manufacture process in addition; Therefore, technical process is simple, and cost is lower.And the graded drift regions of this kind structure can suitably improve dopant dose, is easy to the low on-resistance of control device; There has not been the p-top layer owing to designs again, thus can not break the balance of due Qn and Qp electric charge because of the fluctuation of p-top layer concentration, and then can improve the stability of device electric breakdown strength.
Each embodiment adopts the mode of going forward one by one to describe in this specification, and each embodiment stresses all is the difference with other embodiment, the reference mutually of relevant part.
Need to prove; In this article; Relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint relation or the order that has any this reality between these entities or the operation.And; Term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability; Thereby make and comprise that process, method, article or the equipment of a series of key elements not only comprise those key elements; But also comprise other key elements of clearly not listing, or also be included as this process, method, article or equipment intrinsic key element.Under the situation that do not having much more more restrictions, the key element that limits by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises said key element and also have other identical element.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments among this paper.Therefore, the present invention will can not be restricted to these embodiment shown in this paper, but will meet and principle disclosed herein and features of novelty the wideest corresponding to scope.
Claims (10)
1. a high-voltage power LDMOS device is characterized in that, comprising:
Substrate;
Be positioned at intrabasement buried regions district and drift region, said buried regions district comprises main buried regions district and secondary buried regions district, and said secondary buried regions district is positioned at the drift region and is connected near bottom, source portion and with said drift region.
2. high-voltage power LDMOS device according to claim 1 is characterized in that, the degree of depth of an end that links to each other with main buried regions district in the said secondary buried regions district makes said secondary buried regions district become taper greater than the degree of depth of its other end.
3. high-voltage power LDMOS device according to claim 2 is characterized in that the doping type of said buried regions district and drift region is opposite.
4. high-voltage power LDMOS device according to claim 3 is characterized in that, said drift region comprises source end well region and the drain terminal well region that is connected, and the degree of depth of said source end well region is less than the degree of depth of drain terminal well region; Said secondary buried regions district is positioned at end well region bottom, source and is connected with said source end well region.
5. high-voltage power LDMOS device according to claim 4 is characterized in that the length of said drain terminal well region and the length ratio of drift region are: 1: 4～3: 4.
6. high-voltage power LDMOS device according to claim 5 is characterized in that said substrate is the substrate that the multi-finger bend partly belongs to.
7. a high-voltage power LDMOS device making method is characterized in that, comprising:
Substrate is provided, and said substrate comprises body layer;
In said substrate, form buried regions district and drift region, said buried regions district comprises main buried regions district and secondary buried regions district, and said secondary buried regions district is positioned at the drift region and is connected near bottom, source portion and with said drift region.
8. method according to claim 7 is characterized in that, in said substrate, forms the buried regions district, specifically comprises:
Spin coating photoresist layer on the body layer of said substrate;
With the mask with main buried regions district and secondary buried regions district pattern is that mask forms the photoresist layer with main buried regions district and secondary buried regions district pattern on said body layer;
With said photoresist layer with main buried regions district and secondary buried regions district pattern is that mask forms main buried regions district and secondary buried regions district in said body layer.
9. method according to claim 8; It is characterized in that; Secondary buried regions district pattern in the said mask comprises the Kong Qun that is formed by a plurality of holes, and the area in the near hole of crowd's middle distance master buried regions district, said hole pattern is greater than the area in the main buried regions of distance district pattern hole far away.
10. method according to claim 9 is characterized in that, the secondary buried regions district pattern mesopore crowd's in the said mask the area sum and the percentage of the secondary buried regions district pattern gross area are: 10%～50%.
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| CN107403836A (en) * | 2016-05-20 | 2017-11-28 | 北大方正集团有限公司 | A kind of LDMOS LDMOS device and domain |
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| CN109300988A (en) * | 2018-10-08 | 2019-02-01 | 深圳市南硕明泰科技有限公司 | A kind of LDMOS and its manufacturing method |
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| CN111162124B (en) * | 2018-11-08 | 2023-10-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111180515A (en) * | 2018-11-12 | 2020-05-19 | 新唐科技股份有限公司 | Transistor structure and manufacturing method thereof |
| CN111180515B (en) * | 2018-11-12 | 2023-04-07 | 新唐科技股份有限公司 | Transistor structure and manufacturing method thereof |
| CN110112217A (en) * | 2019-04-15 | 2019-08-09 | 杭州电子科技大学 | Anti-single particle burns LDMOS device |
| CN113782609A (en) * | 2021-09-09 | 2021-12-10 | 东南大学 | 1200V bulk silicon LDMOS with substrate charge coupled and preparation method thereof |
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Application publication date: 20121010 |