CN103050528A - LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor and manufacturing method thereof - Google Patents
LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor and a manufacturing method thereof. A plurality of STI (Shallow Trench Isolation) structures are arranged between a source region and a drain region, so that the breakdown voltage of the transistor is improved, and the problem that the central region of the bottom of the STI structure protrudes when the width of the STI structure broadens; based on the existing manufacturing process of the LDMOS transistor, the additional manufacturing process of the LDMOS transistor provided by the invention is not added, so that the degree of complexity of manufacturing is reduced; after the plurality of STI structures are formed, the subsequent manufacturing process does not need to be changed, so that the possibility of impact on certain characteristics of other devices positioned on the same semiconductor substrate is avoided; and the impact on some characteristics of the transistor itself is also avoided.
Description
Technical field
The present invention relates to double-diffused metal oxide semiconductor field (DMOS), especially relate to a kind of LDOMS transistor and preparation method thereof.
Background technology
In power application, because DMOS (double-diffused metal-oxide-semiconductor) technology adopts vertical device structure (such as the vertical NPN bipolar transistor), therefore has lot of advantages, comprise high current driving ability, low on-resistance and high-breakdown-voltage etc., the patent No. is that 200810103337 file discloses a kind of high voltage bearing DMOS transistor.The DMOS transistor mainly contains two types, vertical DMOS field-effect transistor VDMOSFET (vertical double-diffused MOSFET) and lateral double diffusion metal oxide semiconductor field-effect transistor LDMOSFET (lateral double-dif fused MOSFET).Compare with common field-effect transistor, ldmos transistor has obvious advantage such as aspects such as gain, the linearity, switch performance, heat dispersion and minimizing progression aspect the device property of key, therefore be widely applied.Wherein, puncture voltage be of ldmos transistor important consider parameter.A kind of common N-type LDMOS (lateral double diffusion metal oxide semiconductor) structure is as shown in Figure 1 in the prior art:
Be provided with P type trap 1, the N-type drift region 2 that is separated from each other at the P type semiconductor substrate.Wherein, be provided with transistorized source region 3 in the P type trap 1, source region 3 is to be formed by twice Implantation, it is the higher arsenic of implantation concentration (As) that primary ions is injected, it is the lower boron of ion concentration (B) that another secondary ion injects, Implantation carries out a high temperature progradation later again, because boron is faster than arsenic diffusion speed, the lightly doped region in the source region 3 in the horizontal direction (direction as shown) upward spreads fartherly than heavily doped region.As the end that picks out of P type semiconductor substrate, the side away from N-type drift region 2 in source region 3 is provided with P type heavy doping active area 4.
The doping content of N-type drift region 2 is lower, therefore, can bear higher voltage when ldmos transistor connects high pressure.Be provided with transistorized drain region 5 in the N-type drift region 2, drain region 5 can be to be formed by twice N-type Implantation (a low concentration Implantation, a high concentration ion inject) or a N-type Implantation (high concentration ion injection).N-type drift region 2 interior sides near source region 3 are provided with a STI (Shallow Trench Isolation, shallow channel isolation area) structure 6.
The P type semiconductor substrate is provided with transistorized grid, and grid comprises the gate oxide 8 that is formed on the P type semiconductor substrate, the polysilicon gate 9 on the gate oxide 8, and the both sides of grid are formed with side wall 10.Grid is between transistorized source region 3, drain region 5, and grid extends to the top in sti structure 6, source region 3 in the horizontal direction on (direction as shown), and described grid in the horizontal direction (direction as shown) exists overlapping with source region 3, sti structure 6.Compare with source region 3, drain region 5 is further from grid, so drain region 5 ends have higher puncture voltage.
In order to increase the puncture voltage of above-mentioned ldmos transistor, one of thinkable way of those skilled in the art is to increase the in the horizontal direction width dimensions on (direction as shown) of sti structure, so that this structure can be shared more voltage in the high-tension circuit, thereby increase the puncture voltage of ldmos transistor.But can find that in actual production process such way can not improve the puncture voltage of ldmos transistor, even such way can reduce the puncture voltage of ldmos transistor in some cases.
Summary of the invention
The problem to be solved in the present invention provides a kind of ldmos transistor that can have larger puncture voltage, and the formation method of described ldmos transistor is compatible with existing transistorized processing procedure, need not increase extra manufacture craft.
For addressing the above problem, the invention provides a kind of ldmos transistor, comprising:
Semiconductor substrate is provided with the drift region, has the well region of spacing with described drift region in the described Semiconductor substrate;
Be positioned at the source region of described well region;
Be positioned at the drain region of described drift region, at least two sti structures, described sti structure all between described drain region and described source region, the described drain region of distance farthest sti structure and the side away from described drain region of described drift region have spacing;
Be positioned at the grid on the described Semiconductor substrate, a side of described grid extends to top, described source region, and opposite side extends to the top near the sti structure in described source region.
Optionally, be provided with the doped region that contacts with described source region in the described well region, described doped region is located at the side away from described grid in described source region.
Optionally, described source region comprises lightly doped region, heavily doped region, and described lightly doped region is positioned at described heavily doped region top, and there is spacing in a side of the close described drift region of described lightly doped region and described well region.
Optionally, described drain region only comprises heavily doped region.
Optionally, the quantity of described sti structure is two.
Optionally, there is spacing between the adjacent described sti structure.
Optionally, the doping type of described drift region is opposite with the doping type of described Semiconductor substrate.
Optionally, the doping type of described well region is identical with the doping type of described Semiconductor substrate.
Optionally, the doping type of described doped region is identical with the doping type of described Semiconductor substrate.
For addressing the above problem, the present invention also provides a kind of manufacture method of ldmos transistor, comprises following making step:
In Semiconductor substrate, form at least two sti structures, have spacing between the adjacent described sti structure;
Form graphical photoresist in described Semiconductor substrate, carry out first time Implantation to form the drift region, described sti structure all is located in the described drift region, and wherein there are spacing in the sti structure of a side and a wherein side of described drift region near described drift region;
Form graphical photoresist in described Semiconductor substrate, carry out second time Implantation with the formation well region, have spacing between described well region and the described drift region;
Form grid in described Semiconductor substrate, a side of described grid extends to the top near the sti structure of described grid, and opposite side extends to the top of described well region;
Form graphical photoresist in described Semiconductor substrate, carry out for the third time Implantation to form the lightly doped region in described source region or described drain region;
Both sides at described grid form side wall;
Form graphical photoresist in described Semiconductor substrate, carry out the 4th secondary ion and inject to form the heavily doped region in source region, the heavily doped region in drain region.
Optionally, what carry out forming in the Implantation step for the third time is the lightly doped region in described source region described.
Optionally, above-mentioned manufacture method comprises in addition: form graphical photoresist in described Semiconductor substrate, carry out the 5th secondary ion and inject with the side formation doped region away from described grid in described source region, described doped region contacts with described source region.
Optionally, described first time Implantation, the doping type that injects of Implantation, the 4th secondary ion is opposite with the doping type of described Semiconductor substrate for the third time, the doping type of described second time Implantation, injection of the 5th secondary ion is identical with the doping type of described Semiconductor substrate.
Compared with prior art, the present invention has the following advantages:
A plurality of sti structures are set in the ldmos transistor, Effective Raise puncture voltage, its bottom center zone projection when having avoided the sti structure width dimensions to enlarge; On the basis of existing ldmos transistor manufacture craft, the making of ldmos transistor does not increase extra manufacturing process among the present invention, has reduced the complexity of making; Form after a plurality of sti structures, follow-up manufacture craft need not change, and has avoided affecting the possibility that is positioned at other some characteristics of device on the semi-conductive substrate; Also can avoid affecting some characteristics of this transistor itself.
Description of drawings
Fig. 1 is the structural representation of a kind of common N-type ldmos transistor in the prior art.
Fig. 2 is the shape appearance figure of sti structure when the sti structure width dimensions in the ldmos transistor enlarges.
Fig. 3 is the structural representation of ldmos transistor among the ldmos transistor embodiment of the present invention.
Fig. 4 is the making flow chart of ldmos transistor in the manufacture method of ldmos transistor of the present invention.
Fig. 5 to Figure 11 is the structural representation of ldmos transistor in the manufacturing process of ldmos transistor shown in Figure 4.
Embodiment
In order to improve the puncture voltage of ldmos transistor, one of thinkable way of those skilled in the art is the width dimensions that increases the sti structure between transistor source region, the drain region, but can find the purpose that this way can not reach increases breakdown voltage transistor in the transistor fabrication process of reality.On the contrary, this way even can reduce transistorized puncture voltage in some cases.Thereby the technical staff has to from other angle, improves the puncture voltage of ldmos transistor such as the material of changing the filling sti structure, the size of increase device integral body.
The inventor finds to produce this phenomenon in practice (increases the transistor source region, the width dimensions of the sti structure between the drain region can not increase breakdown voltage transistor) reason be: the shallow trench in the sti structure is to form through plasma etch process, in the process of plasma etching, the sidewall that plasma runs into inclination can rebound and the bottom of shallow trench is produced for the second time Ions Bombardment, because the width dimensions of sti structure is larger, the plasma great majority of bounce-back only can fall into the zone of the close described sidewall of shallow trench bottom, the middle section of shallow trench bottom can not fall into the plasma of bounce-back, so that the regional etching of the close sidewall of shallow trench bottom is darker, thereby cause zone and the middle section etching of the close sidewall bottom the shallow trench inhomogeneous, the middle section projection that shows as the shallow trench bottom that this consequence is concrete.As shown in Figure 2, the height value in the bottom center zone 141 of sti structure 14 is less, and is highly larger near the zone 142 of sidewall, and both differences in height are very large.Because sti structure is located in the drift region of ldmos transistor, the ion concentration that concentrates on sti structure bottom center zone is larger, causes this regional puncture voltage less, so that the puncture voltage of whole ldmos transistor reduces.
For the problems referred to above, if take some processing technology to remove the jut of sti structure bottom, not only can increase extra manufacturing process, fabrication cycle is prolonged, and can add the difficulty of the ldmos transistor of producing extensively; Often on a Semiconductor substrate, make simultaneously ldmos transistor and some other semiconductor device in the actual production process, when in whole processing procedure, having increased extra manufacturing process, can make follow-up manufacture craft with changing, and can be because of some characteristic of other devices of various factors in the process of removing jut; On the other hand, even removed the jut of sti structure bottom, improved puncture voltage, but some other characteristic of ldmos transistor can not be guaranteed, such as the isolation effect of sti structure.
For this reason, the purpose of this invention is to provide a kind of ldmos transistor, be provided with the less sti structure of a plurality of width dimensions between the source region of described ldmos transistor, the drain region, described ldmos transistor is when improving puncture voltage, its processing procedure and existing transistor processing procedure are compatible, and need not increase extra manufacture craft.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization in the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public embodiment.
As shown in Figure 3, ldmos transistor provided by the invention comprises P type semiconductor substrate 11, is provided with N-type drift region 12 in the P type semiconductor substrate 11, and is low concentration ion doping zone, and this zone is high resistance area, can bear higher voltage.
Be provided with drain region 13, at least two sti structures 14 in the N-type drift region 12, there is a default spacing between the adjacent sti structure 14, all sti structures 14 are arranged in a side (figure left side) in drain region 13, apart from a side away from drain region 13 (in figure left side) the existence one default spacing L1 of drain region 13 sti structure 14 (left side among the figure) farthest with N-type drift region 12, this spacing can be as required with adjusting in the actual fabrication process, the doping type in drain region 13 is N-type, and is the high concentration ion doped region.
Be provided with well region 15 in the P type semiconductor substrate 11, have a default spacing L2 between well region 15 and the N-type drift region 12.This spacing L2 can be as required with adjusting in the actual fabrication process, and the effect of well region 15 is to adjust transistorized cut-in voltage.Be provided with source region 16 in well region 15, the doping type of well region 15 is the P type, and is the ion doping zone of intermediate concentration, and the doping type in source region 16 is N-type.
P type semiconductor substrate 11 is provided with grid, one side of grid (left side among the figure) extends to the top in source region 16, the opposite side of grid (right side among the figure) extends to the top near the sti structure 14 in source region 16 (left side among the figure), described grid in the horizontal direction on (direction as shown) respectively with source region 16, exist overlapping near the sti structure 14 in source region 16.
Wherein, drain region 13 can form through twice Implantation (carry out first the low concentration Implantation, carry out high concentration ion again inject), the lightly doped region, the heavily doped region that namely comprise the drain region, drain region 13 also can only be injected (high concentration ion injection) through primary ions and form, namely only comprise the heavily doped region in drain region, drain region 13 only comprises heavily doped region in the present embodiment; Source region 16 can form through twice Implantation (carry out first the low concentration Implantation, carry out high concentration ion again inject), the lightly doped region, the heavily doped region that namely comprise the source region, lightly doped region is positioned at the top of heavily doped region, there is a default spacing L3 in one side of the close grid of lightly doped region and well region 15 (right side among the figure), and such double doped structure can increase the in the horizontal direction puncture voltage of (direction as shown) of this transistor; Grid comprises the gate oxide 19 that is positioned at P type semiconductor substrate 11 tops, the polysilicon gate 20 that is positioned at gate oxide 19 tops.
Above-mentioned transistorized well region 15 is interior can also to be provided with the doped region 18 that contacts with source region 16, and doped region 18 is located at the side away from grid (left side among the figure) in source region 16, and its effect is the end that picks out as P type semiconductor substrate 11.The doping type of doped region 18 is the P type, and is the high concentration ion doped region.
As from the foregoing, by between the source region of ldmos transistor, drain region, a plurality of sti structures being set, make described sti structure can share more voltage, thereby improve the puncture voltage of whole ldmos transistor.
Need to prove; the quantity of sti structure 14 can be for two or more; its quantity can be a plurality of in the situation that device size allows; to improve its puncture voltage; its concrete quantity can be according to the actual requirements with adjusting; this quantity is not subjected to the restriction of accompanying drawing, can not be construed as limiting protection scope of the present invention with this.
Need to prove that in addition above-described embodiment is take the N-type ldmos transistor as example, can change transistorized doping type to obtain having the P type ldmos transistor of same structure.
Fig. 4 is the making flow chart of introducing ldmos transistor among the present invention, and Fig. 5 to Figure 11 and Fig. 3 are the structural section figure of ldmos transistor ldmos transistor in forming process.The below combines the manufacture method that further specifies ldmos transistor with Fig. 4 respectively with Fig. 5 to Figure 11 and Fig. 3, take the N-type ldmos transistor as example, also can slightly do corresponding the adjustment to obtain P type ldmos transistor to it in actual application.
Need to prove that the purpose that these accompanying drawings are provided is to help to understand embodiments of the invention, and should not be construed as improperly restriction of the present invention.For the purpose of clearer, size shown in the figure and not drawn on scale may be done to amplify, dwindle or other changes.
S1, in Semiconductor substrate, form at least two sti structures.Deposit one deck nitride on P type semiconductor substrate 11, form graphical photoresist at nitride, dry etching falls nitride and silicon with at Semiconductor substrate 11 interior formation shallow trenchs, remove photoresist, form silicon oxide layer to fill described shallow trench with chemical vapour deposition (CVD), adopt the described silicon oxide layer of chemico-mechanical polishing planarization until expose described nitride layer, at this moment nitride serves as polish stop; Remove nitride, form a plurality of sti structures 14, the transistor arrangement of formation as shown in Figure 5.Here to make two sti structures as example, its width dimensions is not more than the width dimensions of sti structure in the prior art, there is a default spacing between the adjacent sti structure 14, in order to make the ldmos transistor size as far as possible little, the puncture voltage required according to ldmos transistor can adjust the spacing between the adjacent S TI structure.
S2, form graphical photoresist in Semiconductor substrate, carry out first time Implantation to form the drift region, sti structure all is located in the drift region, close drift region wherein the sti structure of a side and described drift region wherein a side have spacing.Form graphical photoresist at P type semiconductor substrate 11, make sti structure be arranged on not having in the zone covered by photoresist of P type semiconductor substrate 11, carry out for the first time Implantation with formation N-type drift region 12 in having zone covered by photoresist, and make near drift region 12 wherein a side (among the figure left side) sti structure 14 and described drift region 12 wherein a side (left side among the figure) have a default spacing L1, remove photoresist, the transistor arrangement of formation as shown in Figure 6.The doping type of Implantation is that N-type is mixed for the first time, and is the low concentration Implantation.
S3, form graphical photoresist in Semiconductor substrate, carry out second time Implantation to form well region, exist one to preset spacing between well region and the drift region.Form graphical photoresist at P type semiconductor substrate 11, make the top of N-type drift region 12 covered by photoresist, carry out for the second time Implantation there not to be zone covered by photoresist to form well region 15, make and have a default spacing L2 between well region 15 and the N-type drift region 12, remove photoresist, the transistor arrangement of formation as shown in Figure 7.The doping type of Implantation is that the P type mixes for the second time.
Need to prove that two steps of S2, S3 can be exchanged in the actual fabrication process.
S4, form grid in Semiconductor substrate, a side of grid extends to the top near the sti structure of grid, and opposite side extends to the top of well region.Thermal oxide growth one deck gate oxide 19 on P type semiconductor substrate 11, deposit one deck polysilicon 20 on gate oxide 19, form one deck antireflecting coating (ARC) at polysilicon 20, form graphical photoresist in antireflecting coating, dry etching polysilicon 20 is to form polysilicon gate.Grid comprises gate oxide 19, polysilicon 20, grid one side (right side among the figure) that forms extends to the top near the sti structure 14 (right side among the figure) of grid, opposite side (left side among the figure) extends to the top of well region 15, remove the antireflecting coating of photoresist and below, the transistor arrangement of formation as shown in Figure 8.
S5, form graphical photoresist in Semiconductor substrate, carry out for the third time Implantation to form the lightly doped region in source region or drain region.Form graphical photoresist at P type semiconductor substrate 11, make the top, subregion of well region 15 not have covered by photoresist, carry out Implantation for the third time there not to be zone covered by photoresist to form the lightly doped region in source region 16, also can make simultaneously the regional area of N-type drift region 12 covered by photoresist, make the lightly doped region that does not have zone covered by photoresist to form drain region 13 (in conjunction with Figure 11), remove photoresist.In the present embodiment, what described for the third time Implantation formed is the lightly doped region in source region 16, and the transistor arrangement of formation as shown in Figure 9.The element of Implantation is boron (B) for the third time, and is the low concentration Implantation.
S6, form side wall in the both sides of grid.Form one deck silica 21 at P type semiconductor substrate 11, dry etching silica 21, remaining silica 21 forms side wall 21 in the both sides of polysilicon gate 20, and the transistor arrangement of formation is as shown in figure 10.
S7, form graphical photoresist in Semiconductor substrate, carry out the 4th secondary ion and inject to form the heavily doped region in source region, the heavily doped region in drain region.Form graphical photoresist at P type semiconductor substrate 11, make the top, subregion of well region 15 and N-type drift region 12 covered by photoresist, as carrying out the 4th secondary ion, mask injects do not having zone covered by photoresist to form the heavily doped region in source region 16, the heavily doped region in drain region 13 take grid and apart from well region 15 sti structure 14 (right side among the figure) farthest, remove photoresist, the transistor arrangement of formation as shown in figure 11.The element that the 4th secondary ion injects is arsenic (As), and is the high concentration ion injection.
In manufacturing process, can make a side (right side among the figure) of the close grid of the lightly doped region in source region of formation and well region 15 have a default spacing L3.
S8, form graphical photoresist in Semiconductor substrate, carry out the 5th secondary ion and inject with the side away from grid in the source region and form doped region, doped region contacts with the source region.Form graphical photoresist at P type semiconductor substrate 11, make the top, subregion of well region 15 covered by photoresist, carry out the 5th secondary ion and inject do not having zone covered by photoresist to form doped region 18, doped region 18 contacts with source region 16, remove photoresist, the transistor arrangement of formation as shown in Figure 3.The doping type that the 5th secondary ion injects is that the P type mixes, and is the high concentration ion injection.
The inventor of this case has carried out l-G simulation test to multiple ldmos transistor structure, to verify effect of the present invention.Situation one, when the sti structure width dimensions enlarges to improve its puncture voltage in to ldmos transistor, and in the sti structure absolute ideal situation of (there is not rough phenomenon in the bottom), this transistorized puncture voltage is 42.2V.Situation two, when the sti structure width dimensions in the ldmos transistor being enlarged and makes its width dimensions and width dimensions in the situation one equates, when making the jut height that is positioned at middle section of sti structure bottom be 500 dust, this transistorized puncture voltage is 35.6V.Situation three, when two sti structures are set in ldmos transistor, and the gap sum between the width dimensions that makes two sti structures and two sti structures equates with width dimensions in the situation one, this transistorized puncture voltage is 41.5V, these data approximate the data in the situation one, can find out that thus the present invention has feasibility.
In sum, compared with prior art, the present invention has the following advantages:
At least two sti structures of ldmos transistor setting, Effective Raise puncture voltage, its bottom center zone projection when having avoided the sti structure width dimensions to enlarge; On the basis of existing ldmos transistor manufacture craft, the making of ldmos transistor does not increase extra manufacturing process among the present invention, has reduced the complexity of making; Form after a plurality of sti structures, follow-up manufacture craft need not change, and has avoided affecting the possibility that is positioned at other some characteristics of device on the semi-conductive substrate; Also can avoid affecting some characteristics of this transistor itself.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (13)
1. a ldmos transistor is characterized in that, comprising:
Semiconductor substrate is provided with the drift region, has the well region of spacing with described drift region in the described Semiconductor substrate;
Be positioned at the source region of described well region;
Be positioned at the drain region of described drift region, at least two sti structures, described sti structure all between described drain region and described source region, the described drain region of distance farthest sti structure and the side away from described drain region of described drift region have spacing;
Be positioned at the grid on the described Semiconductor substrate, a side of described grid extends to top, described source region, and opposite side extends to the top near the sti structure in described source region.
2. ldmos transistor according to claim 1 is characterized in that, is provided with the doped region that contacts with described source region in the described well region, and described doped region is located at the side away from described grid in described source region.
3. ldmos transistor according to claim 1, it is characterized in that, described source region comprises lightly doped region, heavily doped region, and described lightly doped region is positioned at described heavily doped region top, and there is spacing in a side of the close described drift region of described lightly doped region and described well region.
4. ldmos transistor according to claim 1 is characterized in that, described drain region only comprises heavily doped region.
5. ldmos transistor according to claim 1 is characterized in that, the quantity of described sti structure is two.
6. ldmos transistor according to claim 1 is characterized in that, has spacing between the adjacent described sti structure.
7. ldmos transistor according to claim 1 is characterized in that, the doping type of described drift region is opposite with the doping type of described Semiconductor substrate.
8. ldmos transistor according to claim 1 is characterized in that, the doping type of described well region is identical with the doping type of described Semiconductor substrate.
9. ldmos transistor according to claim 2 is characterized in that, the doping type of described doped region is identical with the doping type of described Semiconductor substrate.
10. the manufacture method of a ldmos transistor is characterized in that, comprises following making step:
In Semiconductor substrate, form at least two sti structures, have spacing between the adjacent described sti structure;
Form graphical photoresist in described Semiconductor substrate, carry out first time Implantation to form the drift region, described sti structure all is located in the described drift region, close described drift region wherein the sti structure of a side and described drift region wherein a side have spacing;
Form graphical photoresist in described Semiconductor substrate, carry out second time Implantation with the formation well region, have spacing between described well region and the described drift region;
Form grid in described Semiconductor substrate, a side of described grid extends to the top near the sti structure of described grid, and opposite side extends to the top of described well region;
Form graphical photoresist in described Semiconductor substrate, carry out for the third time Implantation to form the lightly doped region in described source region or described drain region;
Both sides at described grid form side wall;
Form graphical photoresist in described Semiconductor substrate, carry out the 4th secondary ion and inject to form the heavily doped region in source region, the heavily doped region in drain region.
11. manufacture method according to claim 10 is characterized in that, what carry out forming in the Implantation step for the third time is the lightly doped region in described source region described.
12. manufacture method according to claim 10, it is characterized in that, other comprises: form graphical photoresist in described Semiconductor substrate, carry out the 5th secondary ion and inject with the side formation doped region away from described grid in described source region, described doped region contacts with described source region.
13. manufacture method according to claim 10, it is characterized in that, described first time Implantation, the doping type that injects of Implantation, the 4th secondary ion is opposite with the doping type of described Semiconductor substrate for the third time, the doping type of described second time Implantation, injection of the 5th secondary ion is identical with the doping type of described Semiconductor substrate.
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| CN104282667A (en) * | 2014-09-30 | 2015-01-14 | 中航（重庆）微电子有限公司 | MOS electrostatic protection structure and protection method |
| CN104377243A (en) * | 2013-08-13 | 2015-02-25 | 无锡华润上华半导体有限公司 | LDMOS capable of lowering LDMOS on resistance and increasing breakdown voltage in on state |
| CN104900694A (en) * | 2014-03-03 | 2015-09-09 | 无锡华润上华半导体有限公司 | Laterally diffused metal oxide semiconductor device and manufacturing method thereof |
| CN105448990A (en) * | 2014-08-26 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Ldmos transistor and forming method thereof |
| CN107346788A (en) * | 2016-05-06 | 2017-11-14 | 中航（重庆）微电子有限公司 | Resurf semiconductor devices and preparation method thereof |
| CN108630745A (en) * | 2018-04-13 | 2018-10-09 | 上海华力集成电路制造有限公司 | Semiconductor devices |
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| CN104377243A (en) * | 2013-08-13 | 2015-02-25 | 无锡华润上华半导体有限公司 | LDMOS capable of lowering LDMOS on resistance and increasing breakdown voltage in on state |
| CN104900694A (en) * | 2014-03-03 | 2015-09-09 | 无锡华润上华半导体有限公司 | Laterally diffused metal oxide semiconductor device and manufacturing method thereof |
| CN105448990A (en) * | 2014-08-26 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Ldmos transistor and forming method thereof |
| CN105448990B (en) * | 2014-08-26 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | Ldmos transistor and forming method thereof |
| CN104282667A (en) * | 2014-09-30 | 2015-01-14 | 中航（重庆）微电子有限公司 | MOS electrostatic protection structure and protection method |
| CN104282667B (en) * | 2014-09-30 | 2017-11-10 | 中航（重庆）微电子有限公司 | A kind of MOS electrostatic preventing structures and guard method |
| CN107346788A (en) * | 2016-05-06 | 2017-11-14 | 中航（重庆）微电子有限公司 | Resurf semiconductor devices and preparation method thereof |
| CN107346788B (en) * | 2016-05-06 | 2020-04-28 | 华润微电子（重庆）有限公司 | Resurf semiconductor device and manufacturing method thereof |
| CN108630745A (en) * | 2018-04-13 | 2018-10-09 | 上海华力集成电路制造有限公司 | Semiconductor devices |
| CN112331652A (en) * | 2020-10-23 | 2021-02-05 | 长江存储科技有限责任公司 | Bit line driving structure and three-dimensional memory structure |
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