CN104900646A - Compound semiconductor device and manufacturing method thereof - Google Patents
Compound semiconductor device and manufacturing method thereof Download PDFInfo
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- CN104900646A CN104900646A CN201510306198.0A CN201510306198A CN104900646A CN 104900646 A CN104900646 A CN 104900646A CN 201510306198 A CN201510306198 A CN 201510306198A CN 104900646 A CN104900646 A CN 104900646A
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Abstract
The invention provides a compound semiconductor device and a manufacturing method thereof. The device comprises a semiconductor substrate of a first doping type, an epitaxial layer of a second doping type which is disposed on the semiconductor substrate, a high-voltage well of the second doping type which is disposed in the epitaxial layer, a deep well of the second doping type which is disposed in the high-voltage well, a first well of the first doping type which is disposed side by side with the high-voltage well in the epitaxial layer, a source ohmic contact area of the second doping type which is disposed in the first well, a drain ohmic contact area which is disposed in the deep well, a pinched resistor ohm contact area which is disposed in the epitaxial layer, and a gate which is near the source ohmic contact area and at least covers the epitaxial layer between the source ohmic contact area and the high-voltage well. The device of the invention can be used to start a circuit, and is conductive to saving the layout area and reducing the cost.
Description
Technical field
The present invention relates to semiconductor device and manufacturing process, particularly relate to a kind of composite high pressure semiconductor device and manufacture method thereof.
Background technology
High pressure BCD (Bipolar-CMOS-DMOS) technology generally refers to the BCD technology of device withstand voltage at more than 100V, is widely used in the field such as AC-DC power supply, LED driving at present.Usually, what require power device does not withstand voltagely reach 500V to 800V not etc.
LDMOS (lateral double diffusion MOS) transistor device is a kind of lateral high-voltage device, the driving element generally as module below in AC AC applications.Usually, all electrodes of ldmos transistor device, all at device surface, are convenient to the partly integrated design with low-voltage circuit.
In AC AC applications, drive circuit needs start-up circuit usually.In start-up circuit, conventional process mode is, start-up circuit directly connects large resistance as starting resistance from rectification bridge output end, and rectifier bridge is charged to shunt capacitance, until start-up circuit is started working by this large resistance.The shortcoming of this mode is, after drive circuit normally works, starting resistance still will waste certain power consumption, and needs increase resistive element in peripheral scheme, the cost of the complete machine of increase.Another implementation utilizes the integrated high voltage device of start-up circuit own to complete the function of startup, is then enclosed in same packaging body by the mode of closing envelope with VDMOS driving element.Usually, the high tension apparatus in start-up circuit is fabricated to a large ball, and low-voltage driving circuit is integrated.But this mode improves the cost of encapsulation in small-power power, and the large ball in start-up circuit accounts for the very large area ratio of chip.
Therefore, a kind of novel high tension apparatus is needed, to solve the problem.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of multiple-unit semiconductor device and manufacture method thereof, and this device may be used for start-up circuit, and is conducive to saving chip area, reduces costs.
For solving the problems of the technologies described above, the invention provides a kind of multiple-unit semiconductor device, comprising:
The Semiconductor substrate of the first doping type;
The epitaxial loayer of the second doping type, is positioned in described Semiconductor substrate, and described second doping type is contrary with the first doping type;
The high pressure trap of the second doping type, is positioned at described epitaxial loayer;
The deep trap of the second doping type, is positioned at described high pressure trap;
First trap of the first doping type, is positioned at described epitaxial loayer side by side with described high pressure trap;
The source electrode ohmic contact regions of the second doping type, is positioned at described first trap;
Drain ohmic contact district, is positioned at described deep trap;
Pinched resistor ohmic contact regions, is positioned at described epitaxial loayer;
Near the grid of described source electrode ohmic contact regions, at least cover the epitaxial loayer between described source electrode ohmic contact regions and described high pressure trap;
Wherein, described source electrode ohmic contact regions, drain ohmic contact district and the grid near described source electrode ohmic contact regions form transistor at least partially, and described drain ohmic contact district and pinched resistor ohmic contact regions form pinched resistor at least partially.
According to one embodiment of present invention, described device also comprises: the first doping type field layer falls, be positioned at described high pressure trap side by side with described drain ohmic contact district.
According to one embodiment of present invention, described device also comprises: the buried regions of the first doping type, is positioned at described Semiconductor substrate, and described epitaxial loayer covers described buried regions.
According to one embodiment of present invention, described device also comprises:
Field oxide, at least covers the epitaxial loayer between the border of described high pressure trap and drain ohmic contact district;
Near the grid in described drain ohmic contact district, cover a part for described field oxide.
According to one embodiment of present invention, described device also comprises:
The shading ring of the first doping type, is positioned at described epitaxial loayer side by side with described high pressure trap;
Earth potential contact zone, is positioned at described shading ring.
According to one embodiment of present invention, described device also comprises: body contact zone, is positioned at described first trap side by side with described source electrode ohmic contact regions.
According to one embodiment of present invention, the epitaxial loayer between described shading ring and first trap of next-door neighbour is coated with field oxide, described field oxide has high value resistor, described body contact zone is electrically connected with described earth potential contact zone.
According to one embodiment of present invention, on the domain of described multiple-unit semiconductor device, described high value resistor is distributed in the outermost of described multiple-unit semiconductor device.
According to one embodiment of present invention, described drain ohmic contact district has the second doping type, and described transistor is ldmos transistor.
According to one embodiment of present invention, described drain ohmic contact district has the first doping type, and described transistor is LIGBT transistor.
According to one embodiment of present invention, described device also comprises: the second trap of the second doping type, is positioned at described epitaxial loayer side by side with described high pressure trap, and described pinched resistor ohmic contact regions is positioned at described second trap.
In order to solve the problems of the technologies described above, present invention also offers a kind of manufacture method of multiple-unit semiconductor device, comprising:
The Semiconductor substrate of the first doping type is provided;
Form the epitaxial loayer of the second doping type on the semiconductor substrate, described second doping type is contrary with the first doping type;
The high pressure trap of the second doping type is formed in described epitaxial loayer;
The deep trap of the second doping type is formed in described high pressure trap;
In described epitaxial loayer, form first trap arranged side by side with described high pressure trap, described first trap has the first doping type;
In described first trap, form source electrode ohmic contact regions, in described epitaxial loayer, form pinched resistor ohmic contact regions, in described deep trap, form drain ohmic contact district;
Form the grid near described source electrode ohmic contact regions, the grid near described source electrode ohmic contact regions at least covers the epitaxial loayer between described source electrode ohmic contact regions and described high pressure trap;
Wherein, described source electrode ohmic contact regions, drain ohmic contact district and grid form transistor at least partially, and described drain ohmic contact district and pinched resistor ohmic contact regions form pinched resistor at least partially.
According to one embodiment of present invention, also comprise after the described deep trap of formation: what in described high pressure trap, form the first doping type falls field layer, described in field floor falls and described drain ohmic contact district is positioned at described high pressure trap side by side.
According to one embodiment of present invention, also comprised before the described epitaxial loayer of formation: the buried regions forming the first doping type in described Semiconductor substrate, wherein, described epitaxial loayer covers described buried regions.
According to one embodiment of present invention, also comprised before the grid forming close described source electrode ohmic contact regions:
Form field oxide, described field oxide at least covers the epitaxial loayer between the border of described high pressure trap and drain ohmic contact district;
When forming the grid near described source electrode ohmic contact regions, also form the grid near described drain ohmic contact district in the lump, the grid near described drain ohmic contact district covers a part for described field oxide.
According to one embodiment of present invention, described method also comprises:
In described epitaxial loayer, form the shading ring arranged side by side with described high pressure trap, described shading ring has the first doping type;
Earth potential contact zone is formed in described shading ring.
According to one embodiment of present invention, described method also comprises: in described first trap, form the body contact zone arranged side by side with described source electrode ohmic contact regions.
According to one embodiment of present invention, described method also comprises:
Epitaxial loayer between described shading ring and first trap of next-door neighbour forms field oxide;
Described field oxide forms high value resistor, and described body contact zone is electrically connected with described earth potential contact zone.
According to one embodiment of present invention, on the domain of described multiple-unit semiconductor device, described high value resistor is distributed in the outermost of described multiple-unit semiconductor device.
According to one embodiment of present invention, described drain ohmic contact district has the second doping type, and described transistor is ldmos transistor.
According to one embodiment of present invention, described drain ohmic contact district has the first doping type, and described transistor is LIGBT transistor.
According to one embodiment of present invention, described method also comprises: the second trap forming the second doping type, and described second trap and described high pressure trap are positioned at described epitaxial loayer side by side, and described pinched resistor ohmic contact regions is positioned at described second trap.
Compared with prior art, the present invention has the following advantages:
The multiple-unit semiconductor device of the embodiment of the present invention is integrated with transistor and pinched resistor, may be used for the start-up circuit of drive circuit.This transistor and pinched resistor are compatible in manufacturing process, and form drain structure altogether, and this makes the domain structure of device more compact, is conducive to saving chip area, reduces costs.
In addition, the multiple-unit semiconductor device of the embodiment of the present invention is also integrated with high value resistor, and this high value resistor may be used for start-up circuit.This high value resistor can adopt and be formed with the technique of transistor, pinched resistor compatibility, is conducive to improving integrated level further, reduces costs.
Furthermore, in the multiple-unit semiconductor device of the embodiment of the present invention, high pressure trap in buried regions in Semiconductor substrate, the epitaxial loayer on buried regions, epitaxial loayer and the deep trap in high pressure trap and fall field layer and form two trap gradual change (Double-Resurf) structure, have following benefit for transistor:
(1) the charge sensitive sex chromosome mosaicism of conventional two trap gradual change transistor (as ldmos transistor) is alleviated, be conducive to increasing process window, because the Double-Resurf transistor of traditional handicraft is limited by the requirement restriction of N-type electric charge and P type charge matching, the non-equilibrium effect of performance parameter to electric charge of device is very sensitive, thus adds the difficulty of technology controlling and process; And the present invention's above-mentioned pair of trap grading structure introduces the line change Impurity Distribution structure that epitaxial loayer/high pressure trap/deep trap is formed, optimised devices breakdown voltage on the basis of Double-Resurf structure, alleviate the sensitiveness of electric charge;
(2) deep trap can introduce new surface peak electric field (knot also namely between deep trap and high pressure trap introduces new peak value electric field at device surface), thus it is withstand voltage to improve transversal device, make as far as possible few device drift region length (also namely little chip area) that higher voltage can be born, and do not increase conduction resistance; Due to the introducing of deep trap, the peak value electric field near transistor source and drain terminal is reduced, thus reduces the impact on device surface, be conducive to improving device reliability;
(3) deep trap of drain terminal can improve drain terminal concentration, is conducive to the on-state characteristic improving device, thus the safety operation area of extended device;
(4) the high pressure trap that doping type is contrary and epitaxial loayer combine formed structure, the control difficulty of simple epitaxy technique (namely drift region all realizes controlling with extension electric charge) can be reduced, also reduce the process time pushing away trap technique and the difficulty of high pressure trap simultaneously;
(4) introducing of buried regions can reduce the effect that thin epitaxy technique electric field is concentrated to source, thus reduces because integrity problems such as the excessive problems that runs off (walk-out) brought of beak partial electric-field.
Accompanying drawing explanation
Fig. 1 is the domain schematic diagram of multiple-unit semiconductor device according to a first embodiment of the present invention;
Fig. 2 is the cross-sectional view in region 104 in Fig. 1;
Fig. 3 is the drive circuit schematic diagram of band pinched resistor according to a second embodiment of the present invention;
Fig. 4 is the domain schematic diagram of multiple-unit semiconductor device according to a second embodiment of the present invention;
Fig. 5 is the cross-sectional view of multiple-unit semiconductor device according to a third embodiment of the present invention;
Fig. 6 is the cross-sectional view of multiple-unit semiconductor device according to a fourth embodiment of the present invention;
Fig. 7 is the schematic flow sheet of the manufacture method of multiple-unit semiconductor device according to a fifth embodiment of the present invention;
Fig. 8 A to Fig. 8 J is the cross-sectional view that in the manufacture method of multiple-unit semiconductor device according to a fifth embodiment of the present invention, each step is corresponding.
Embodiment
Below in conjunction with specific embodiments and the drawings, the invention will be further described, but should not limit the scope of the invention with this.
First embodiment
The complete domain of the multiple-unit semiconductor device according to the present embodiment is shown with reference to figure 1, Fig. 1.The element layout of the present embodiment is interdigitated domain, to obtain enough current capacities.As shown in Figure 1, in this domain, mainly comprise drain electrode part 102, source electrode portion 101, grid part 103, and grounded part 100.The straight flange region 104 that dotted line frame goes out is the part of actual conductive area, and other parts are in parallel with it.Be integrated with transistor (such as, being ldmos transistor in the present embodiment) and pinched resistor in this multiple-unit semiconductor device, transistor and pinched resistor have shared drain electrode, to form common drain structure.Drain structure can make product domain compacter altogether, thus saving chip area.
Show the section structural scheme of mechanism in region 104 in Fig. 1 with reference to figure 2, Fig. 2, Fig. 1 cuts the profile of the ldmos transistor part obtained on the left of Fig. 2 along OA ' direction, cuts the profile of the pinched resistor part shown in obtaining on the right side of Fig. 2 along OA direction.
With reference to figure 2, this multiple-unit semiconductor device comprises: the Semiconductor substrate 1 of P type doping; The buried regions 2 of P type doping, is positioned in the Semiconductor substrate 1 of P type doping; N-type doping epitaxial loayer 3, be positioned at P type doping buried regions 2 and Semiconductor substrate 1 on; The high pressure trap 4 of N-type doping and the shading ring 5 of P type doping, be positioned at the epitaxial loayer 3 of N-type doping side by side; What the deep trap 6 of N-type doping and P type adulterated falls field layer 7, is positioned at the high pressure trap 4 of N-type doping; First trap 8A of P type doping and the second trap 8B of N-type doping, is positioned at high pressure trap 4 epitaxial loayer 3 that N-type adulterates side by side; Field oxide 9, be positioned on the surface of epitaxial loayer 3, a part for field oxide 9 at least covers the epitaxial loayer 3 between the border of high pressure trap 4 and drain ohmic contact district 11C, and another part of field oxide 9 at least covers the epitaxial loayer 3 between shading ring 5 and the first trap 8A; Grid 10A, wherein, the epitaxial loayer 3 between source electrode ohmic contact regions 11A and high pressure trap 4 is at least covered near the grid 10A of source electrode ohmic contact regions 11A, a part for field oxide 9 is covered near the grid 10A of drain ohmic contact district 11C, the material of grid 10A can be such as polysilicon, wherein, form the gate electrode of device near the grid 10A of source electrode ohmic contact regions 11A, and the grid 10A on field oxide 9 forms the field plate of device; Be positioned at the source electrode ohmic contact regions 11A on epitaxial loayer 3 surface, body contact zone 11B, source electrode ohmic contact regions 11A and body contact zone 11B is positioned at the first trap 8A, more specifically, be positioned at the surface portion of the first trap 8A, source electrode ohmic contact regions 11A such as has N-type doping; Drain ohmic contact district 11C, is positioned at deep trap 6, more specifically, is positioned at the surface portion of deep trap 6, and drain ohmic contact district 11C such as has N-type doping; Earth potential contact zone 11D, is positioned at shading ring 5, more specifically, is positioned at the surface portion of shading ring 5; Pinched resistor ohmic contact regions 11E, is positioned at the second trap 8B, more specifically, is positioned at the surface portion of the second trap 8B; Interconnection line 12, is positioned at device surface, and interconnection line is used for electrical connection, such as, be electrically connected by earth potential contact zone 11D and body contact zone 11B, and be electrically connected being positioned at grid 10A field oxide 9 being used as field plate, the material of interconnection line 12 is such as aluminium.
In above-mentioned multiple-unit semiconductor device, the grid 10A of source electrode ohmic contact regions 11A, drain ohmic contact district 11C and close source electrode ohmic contact regions 11A forms ldmos transistor at least partially, and drain ohmic contact district 11C and pinched resistor ohmic contact regions 11E forms pinched resistor at least partially.Pinched resistor and ldmos transistor leak altogether, that is to say shared identical drain ohmic contact district 11C.In brief, ldmos transistor and pinched resistor have identical drain electrode structure, and the domain structure of the two also can be in parallel.
In addition, in ldmos transistor, the field oxide 9 between the shading ring 5 of P type doping and the first trap 8A of P type doping can also have high value resistor 10B.This high value resistor 10B can adopt the polysilicon of polysilicon or doping to be formed.This high value resistor 10B according to the needs of embody rule, can have default resistance value.
In Fig. 2, buried regions 2, first trap 8A and the second trap 8B part forms double-deck P type structure (i.e. the first trap 8A and buried regions 2), and such structure is " double-deck pinched resistor structure ": the buried regions 2 Semiconductor substrate 1 of P type doping being formed the doping of P type; The buried regions 2 of P type doping is formed the epitaxial loayer 3 of N-type doping; The first trap 8A of P type doping and the second trap 8B of N-type doping is formed in epitaxial loayer 3.Wherein, buried regions 2 and the first trap 8A form double-deck P type structure, epitaxial loayer 3 to the second trap 8B of drain ohmic contact district 11C between double-deck P type structure, then to pinched resistor ohmic contact regions 11E, this passage is the current channel of pinched resistor.
It should be noted that, the epitaxial loayer of N-type doping forms pinched resistor, in the processing mode that in prior art, conventional solution adopts usually, generally not there is buried regions 2 or the first trap 8A, in this case, the pressure-resistance structure of the pinched resistor in the pressure-resistance structure of the ldmos transistor in OA region in Fig. 1 and OA ' region can be caused different, thus cause the pinched resistor part of device electric fields on domain to be concentrated near source, make the entirety of multiple device withstand voltage on the low side.And in multiple-unit semiconductor device according to a first embodiment of the present invention, the pressure-resistance structure of pinched resistor part keeps the same with ldmos transistor, the reliability of integral device is guaranteed.In addition, for the multiple-unit semiconductor device according to the embodiment of the present invention, by controlling the spacing H between buried regions 2 and the first trap 8A, can effectively control the electric current I flowing through pinched resistor
oNand pinch-off voltage V
p, make the scope of application of multiple-unit semiconductor device wider.
Second embodiment
As shown in Figure 3, in the application of reality, as in power supply or AC-LED application, usually need start-up circuit 32.When circuit start, need pinched resistor 31 to open and charge to start-up circuit 32, after completing charging, circuit normally works.Now, the source electrode of pinched resistor 31 is lifted to more than 10V, and pinched resistor 31 is closed, and now only has very little electric current (such as 10 below the μ A) resistance 33 on the left of Fig. 3 to flow through, and so according to R=V/I estimation, this resistance 33 at least needs 1M ohm.At present, general technology is applied 2K resistance ratio more, and for ensureing the precision of resistance, general resistor width is more than 2 μm, so the resistance of 1M ohm needs the length of resistance very large (such as more than 2000 μm).
If so large resistance is arranged on separately beyond multiple device, the area of integral device can be wasted.And in the present embodiment, with reference to figure 2, the field oxide 9 between shading ring 5 and the first trap 8A arranges high value resistor 10B.Due to the first trap 8A and shading ring 5 equipotential (being such as electrically connected by interconnection line 12), so any ghost effect can not be produced.As shown in Figure 4, high value resistor can be arranged on product domain outermost part 400, and a circle of such as outermost so effectively can save the area of integral device.
3rd embodiment
Another multiple-unit semiconductor device provided according to the 3rd embodiment is provided with reference to figure 5, Fig. 5.The profile obtained shown in Fig. 5 is cut in the straight flange region 104 in the straight flange region 104, Fig. 1 that Fig. 5 corresponds in Fig. 1 open along AA '.The device architecture of the first embodiment shown in the 3rd embodiment with Fig. 2 is substantially identical, and difference is, the doping type of levels all in device architecture is contrary with the first embodiment, thus forms the ldmos transistor of P type.
4th embodiment
Another multiple-unit semiconductor device provided according to the 4th embodiment is provided with reference to figure 6, Fig. 6.The profile obtained shown in Fig. 6 is cut in the straight flange region 104 in the straight flange region 104, Fig. 1 that Fig. 6 corresponds in Fig. 1 open along AA '.The device architecture of the first embodiment shown in the 4th embodiment with Fig. 2 is substantially identical, and difference is, the doping type of drain ohmic contact district 11C is contrary with the first embodiment, namely has the doping of P type, thus forms LIGBT transistor.
5th embodiment
With reference to figure 7, the manufacture method of multiple-unit semiconductor device according to a fifth embodiment of the present invention comprises:
Step S11, provides the Semiconductor substrate of the first doping type;
Step S12, forms the epitaxial loayer of the second doping type on the semiconductor substrate, and described second doping type is contrary with the first doping type;
Step S13, forms the high pressure trap of the second doping type in described epitaxial loayer;
Step S14, forms the deep trap of the second doping type in described high pressure trap;
Step S15, in described epitaxial loayer, form first trap arranged side by side with described high pressure trap, described first trap has the first doping type;
Step S16, forms source electrode ohmic contact regions, forms pinched resistor ohmic contact regions in described epitaxial loayer, form drain ohmic contact district in described deep trap in described first trap;
Step S17, forms the grid near described source electrode ohmic contact regions, and the grid near described source electrode ohmic contact regions at least covers the epitaxial loayer between described source electrode ohmic contact regions and described high pressure trap.
Below in conjunction with Fig. 8 A to Fig. 8 J, above-mentioned manufacture method is described in detail.It should be noted that, manufacture method described below for be the first embodiment also i.e. device architecture shown in Fig. 2, for the device architecture of other embodiments, only need slightly to adjust corresponding step according to the difference of device architecture.
With reference to figure 8A, provide Semiconductor substrate 1.This Semiconductor substrate 1 can be such as the silicon substrate of P type doping.
With reference to figure 8B, in Semiconductor substrate 1, form the buried regions 2 of P type doping.Specifically, photoetching process can be used to define the figure of buried regions 2; Then buried regions 2 is formed by the mode of ion implantation.After ion implantation, annealing knot can also be carried out.
With reference to figure 8C, form the epitaxial loayer 3 of N-type doping, this epitaxial loayer 3 covers Semiconductor substrate 1 and buried regions 2.As a nonrestrictive example, the thickness of epitaxial loayer 3 can be such as 5 μm to 15 μm.
With reference to figure 8D, in epitaxial loayer 3, form the shading ring 5 of the high pressure trap 4 of N-type doping, the doping of P type.The manufacture method of high pressure trap 4 and shading ring 5 such as can comprise the conventional steps such as photoetching, ion implantation, annealing knot.Wherein, shading ring 5 and buried regions 2 can be formed logical isolation.
With reference to figure 8E, what the deep trap 6 of formation N-type doping in high pressure trap 4 and P type adulterated falls field layer 7.Deep trap 6 such as can comprise the conventional steps such as photoetching, ion implantation, annealing knot with the manufacture method of falling field layer 7.
With reference to figure 8F, in epitaxial loayer 3, form the first trap 8A of P type doping and the second trap 8B of N-type doping.The manufacture method of the first trap 8A and the second trap 8B such as can comprise the conventional steps such as photoetching, ion implantation, annealing knot.
With reference to figure 8G, the surface of epitaxial loayer 3 forms field oxide 9.The forming process of field oxide 9 can comprise: have source region window, carry out field cut-off injection and carry out field oxidation.
With reference to figure 8H, the field oxide 9 between shading ring 5 and the first trap 8A forms high value resistor 10B; Appropriate location on epitaxial loayer 3 and field oxide 9 forms grid 10A.The formation method of grid 10A and high value resistor 10B can comprise: growth grid oxic horizon, such as, by thermal oxidation method growth thickness be
extremely
grid oxic horizon; Chemical vapour deposition (CVD) (CVD) or other proper methods is adopted to form the polysilicon of undoped; High value resistor ion implantation and the injection of grid high concentration ion are carried out to polysilicon; Polysilicon is etched, forms grid 10A and high value resistor 10B.In addition, before formation high value resistor 10B and grid 10A, threshold value can also be carried out and regulate injection.
With reference to figure 8I, in the first trap 8A, form source electrode ohmic contact regions 11A and body contact zone 11B, in shading ring 5, form earth potential contact zone 11D, in the second trap 8B, form pinched resistor ohmic contact regions 11E.The formation method of each contact zone above-mentioned can comprise photoetching, ion implantation, annealing etc.
With reference to figure 8J, form the dielectric layer covering whole multiple-unit semiconductor device, the material of this dielectric layer is such as BPSG or other suitable insulating material.Afterwards, form ohmic contact hole in the appropriate location of dielectric layer, and deposits conductive material (such as aluminium), thus form interconnection line 12.
Afterwards, the passivation layer of blanket dielectric layer and interconnection line 12 can also be formed, and open pressure point window in the passivation layer, until form complete multiple-unit semiconductor device.
In above-mentioned manufacture method, adopt same group of processing step to define ldmos transistor and pinched resistor simultaneously, make technique simpler.
It should be noted that, by the suitable adjustment to processing step, the multiple-unit semiconductor device in other embodiments can also be formed.Such as, on the basis of above-described embodiment, by the doping type negate of whole doped region, the ldmos transistor of P type and the pinched resistor of P type just can be formed.Or, on the basis of above-described embodiment, the doping type of drain ohmic contact district 11C is revised as the doping of P type, the multiple-unit semiconductor device comprising LIGBT device and pinched resistor can be formed.
It is to be understood that above-described embodiment is just to explanation of the present invention; instead of limitation of the present invention; any innovation and creation do not exceeded in spirit of the present invention; include but not limited to the replacement of the change to local structure, the type to components and parts or model; and the replacement of other unsubstantialities or amendment, all fall within scope.
Claims (22)
1. a multiple-unit semiconductor device, is characterized in that, comprising:
The Semiconductor substrate of the first doping type;
The epitaxial loayer of the second doping type, is positioned in described Semiconductor substrate, and described second doping type is contrary with the first doping type;
The high pressure trap of the second doping type, is positioned at described epitaxial loayer;
The deep trap of the second doping type, is positioned at described high pressure trap;
First trap of the first doping type, is positioned at described epitaxial loayer side by side with described high pressure trap;
The source electrode ohmic contact regions of the second doping type, is positioned at described first trap;
Drain ohmic contact district, is positioned at described deep trap;
Pinched resistor ohmic contact regions, is positioned at described epitaxial loayer;
Near the grid of described source electrode ohmic contact regions, at least cover the epitaxial loayer between described source electrode ohmic contact regions and described high pressure trap;
Wherein, described source electrode ohmic contact regions, drain ohmic contact district and the grid near described source electrode ohmic contact regions form transistor at least partially, and described drain ohmic contact district and pinched resistor ohmic contact regions form pinched resistor at least partially.
2. multiple-unit semiconductor device according to claim 1, is characterized in that, also comprises:
First doping type field layer falls, be positioned at described high pressure trap side by side with described drain ohmic contact district.
3. multiple-unit semiconductor device according to claim 1, is characterized in that, also comprises:
The buried regions of the first doping type, is positioned at described Semiconductor substrate, and described epitaxial loayer covers described buried regions.
4. multiple-unit semiconductor device according to claim 1, is characterized in that, also comprises:
Field oxide, at least covers the epitaxial loayer between the border of described high pressure trap and drain ohmic contact district;
Near the grid in described drain ohmic contact district, cover a part for described field oxide.
5. multiple-unit semiconductor device according to claim 1, is characterized in that, also comprises:
The shading ring of the first doping type, is positioned at described epitaxial loayer side by side with described high pressure trap;
Earth potential contact zone, is positioned at described shading ring.
6. multiple-unit semiconductor device according to claim 5, is characterized in that, also comprises:
Body contact zone, is positioned at described first trap side by side with described source electrode ohmic contact regions.
7. multiple-unit semiconductor device according to claim 6, it is characterized in that, epitaxial loayer between described shading ring and first trap of next-door neighbour is coated with field oxide, described field oxide has high value resistor, described body contact zone is electrically connected with described earth potential contact zone.
8. multiple-unit semiconductor device according to claim 7, is characterized in that, on the domain of described multiple-unit semiconductor device, described high value resistor is distributed in the outermost of described multiple-unit semiconductor device.
9. multiple-unit semiconductor device according to claim 1, is characterized in that, described drain ohmic contact district has the second doping type, and described transistor is ldmos transistor.
10. multiple-unit semiconductor device according to claim 1, is characterized in that, described drain ohmic contact district has the first doping type, and described transistor is LIGBT transistor.
11. multiple-unit semiconductor devices according to claim 1, is characterized in that, also comprise:
Second trap of the second doping type, is positioned at described epitaxial loayer side by side with described high pressure trap, and described pinched resistor ohmic contact regions is positioned at described second trap.
The manufacture method of 12. 1 kinds of multiple-unit semiconductor devices, is characterized in that, comprising:
The Semiconductor substrate of the first doping type is provided;
Form the epitaxial loayer of the second doping type on the semiconductor substrate, described second doping type is contrary with the first doping type;
The high pressure trap of the second doping type is formed in described epitaxial loayer;
The deep trap of the second doping type is formed in described high pressure trap;
In described epitaxial loayer, form first trap arranged side by side with described high pressure trap, described first trap has the first doping type;
In described first trap, form source electrode ohmic contact regions, in described epitaxial loayer, form pinched resistor ohmic contact regions, in described deep trap, form drain ohmic contact district;
Form the grid near described source electrode ohmic contact regions, the grid near described source electrode ohmic contact regions at least covers the epitaxial loayer between described source electrode ohmic contact regions and described high pressure trap;
Wherein, described source electrode ohmic contact regions, drain ohmic contact district and grid form transistor at least partially, and described drain ohmic contact district and pinched resistor ohmic contact regions form pinched resistor at least partially.
13. manufacture methods according to claim 12, is characterized in that, also comprise after the described deep trap of formation:
What in described high pressure trap, form the first doping type falls field layer, described in field floor falls and described drain ohmic contact district is positioned at described high pressure trap side by side.
14. manufacture methods according to claim 12, is characterized in that, also comprise before the described epitaxial loayer of formation:
In described Semiconductor substrate, form the buried regions of the first doping type, wherein, described epitaxial loayer covers described buried regions.
15. manufacture methods according to claim 12, is characterized in that, also comprise before the grid forming close described source electrode ohmic contact regions:
Form field oxide, described field oxide at least covers the epitaxial loayer between the border of described high pressure trap and drain ohmic contact district;
When forming the grid near described source electrode ohmic contact regions, also form the grid near described drain ohmic contact district in the lump, the grid near described drain ohmic contact district covers a part for described field oxide.
16. manufacture methods according to claim 12, is characterized in that, also comprise:
In described epitaxial loayer, form the shading ring arranged side by side with described high pressure trap, described shading ring has the first doping type;
Earth potential contact zone is formed in described shading ring.
17. manufacture methods according to claim 16, is characterized in that, also comprise:
The body contact zone arranged side by side with described source electrode ohmic contact regions is formed in described first trap.
18. manufacture methods according to claim 17, is characterized in that, also comprise:
Epitaxial loayer between described shading ring and first trap of next-door neighbour forms field oxide;
Described field oxide forms high value resistor, and described body contact zone is electrically connected with described earth potential contact zone.
19. manufacture methods according to claim 18, is characterized in that, on the domain of described multiple-unit semiconductor device, described high value resistor is distributed in the outermost of described multiple-unit semiconductor device.
20. manufacture methods according to claim 12, is characterized in that, described drain ohmic contact district has the second doping type, and described transistor is ldmos transistor.
21. manufacture methods according to claim 12, is characterized in that, described drain ohmic contact district has the first doping type, and described transistor is LIGBT transistor.
22. manufacture methods according to claim 12, it is characterized in that, also comprise: the second trap forming the second doping type, described second trap and described high pressure trap are positioned at described epitaxial loayer side by side, and described pinched resistor ohmic contact regions is positioned at described second trap.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107403836A (en) * | 2016-05-20 | 2017-11-28 | 北大方正集团有限公司 | A kind of LDMOS LDMOS device and domain |
| CN107452794A (en) * | 2016-06-01 | 2017-12-08 | 北大方正集团有限公司 | A kind of high pressure LDMOS LDMOS |
| CN107546253A (en) * | 2016-06-27 | 2018-01-05 | 北大方正集团有限公司 | The preparation method and metal-oxide semiconductor (MOS) of metal-oxide semiconductor (MOS) |
| CN110190055A (en) * | 2019-04-09 | 2019-08-30 | 上海华虹宏力半导体制造有限公司 | A kind of self-shield of high-voltage structure of grid driving technique |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110057230A1 (en) * | 2009-09-09 | 2011-03-10 | Florin Udrea | Lateral Insulated Gate Bipolar Transistors (LIGBTS) |
| CN104347683A (en) * | 2013-08-09 | 2015-02-11 | 美格纳半导体有限公司 | Semiconductor device |
| CN204632758U (en) * | 2015-06-05 | 2015-09-09 | 杭州士兰微电子股份有限公司 | Multiple-unit semiconductor device |
-
2015
- 2015-06-05 CN CN201510306198.0A patent/CN104900646B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110057230A1 (en) * | 2009-09-09 | 2011-03-10 | Florin Udrea | Lateral Insulated Gate Bipolar Transistors (LIGBTS) |
| CN104347683A (en) * | 2013-08-09 | 2015-02-11 | 美格纳半导体有限公司 | Semiconductor device |
| CN204632758U (en) * | 2015-06-05 | 2015-09-09 | 杭州士兰微电子股份有限公司 | Multiple-unit semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107403836A (en) * | 2016-05-20 | 2017-11-28 | 北大方正集团有限公司 | A kind of LDMOS LDMOS device and domain |
| CN107403836B (en) * | 2016-05-20 | 2020-10-13 | 北大方正集团有限公司 | Laterally diffused metal oxide semiconductor LDMOS device and layout |
| CN107452794A (en) * | 2016-06-01 | 2017-12-08 | 北大方正集团有限公司 | A kind of high pressure LDMOS LDMOS |
| CN107546253A (en) * | 2016-06-27 | 2018-01-05 | 北大方正集团有限公司 | The preparation method and metal-oxide semiconductor (MOS) of metal-oxide semiconductor (MOS) |
| CN110190055A (en) * | 2019-04-09 | 2019-08-30 | 上海华虹宏力半导体制造有限公司 | A kind of self-shield of high-voltage structure of grid driving technique |
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| CN104900646B (en) | 2017-09-29 |
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