CN107887426B - P-type LDMOS structure with charge-adjustable field plate - Google Patents
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- 239000002184 metal Substances 0.000 claims abstract description 76
- 230000006698 induction Effects 0.000 claims abstract description 28
- 230000005684 electric field Effects 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 230000003071 parasitic effect Effects 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 5
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000006872 improvement Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000005457 optimization Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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Abstract
The invention discloses a P-type LDMOS structure with a charge-adjustable field plate, which comprises: the field oxide layer is provided with a plurality of charge adjustable field plates on the surface, each charge adjustable field plate is connected with a metal induction layer, the N-type contact region and the P-type source region are connected with source electrode metal, and the source electrode metal completely covers all the metal induction layers. The structure can enable the whole drift region of the device to obtain uniform surface transverse electric field distribution, has high transverse voltage resistance, and can improve the doping concentration of the drift region of the device under the condition of keeping high breakdown voltage, thereby obtaining low on-resistance.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a P-type LDMOS (laterally double-diffused metal oxide semiconductor field effect transistor) suitable for high-voltage application, and a driving chip suitable for high-voltage and low-current fields such as printers, motors, flat panel displays and the like.
Background
LDMOS (lateral double diffused metal oxide semiconductor transistor) is a lateral high voltage device of DMOS (double diffused metal oxide semiconductor transistor device). The method has the advantages of high withstand voltage, large gain, low distortion and the like, and is more compatible with a CMOS (complementary metal oxide semiconductor) process, so that the method is widely applied to an intelligent power integrated circuit. The P-type LDMOS can greatly simplify the circuit design, and thus has received much attention and research. The key point of the current P-type LDMOS design is how to reasonably alleviate the contradiction between breakdown voltage and on-resistance and ensure that the P-type LDMOS has higher stability. Currently, the focus of LDMOS research is mainly focused on the design of the concentration of the drift region, and the compromise between breakdown voltage and on-resistance is realized by reducing the surface electric Field strength (RESURF for short) of the device through a buried layer technology, and by using technologies such as a resistive Field plate, a Super Junction, and gradual doping of the drift region.
In order to make the device have better functions, it is an important research topic to improve the breakdown voltage of the device. The field plate technology is an effective and important technology for optimizing the surface electric field of the LDMOS device, and the uneven charge distribution on the conventional field plate makes the surface electric field distribution of the device not ideal, so the design method of the conventional field plate technology needs further improvement.
Disclosure of Invention
The invention provides a P-type LDMOS structure with a charge adjustable field plate, wherein charges on the field plate in the device can be adjusted through parameter design, and the P-type LDMOS structure has higher transverse voltage endurance capability and smaller on-resistance.
The technical scheme of the invention is as follows:
a P-type LDMOS structure with a charge-tunable field plate comprises: an N-type semiconductor substrate, on which a P-type drift region and an N-type well are arranged, a P-type source region and an N-type contact region are arranged on the N-type well, a P-type drain region and a field oxide layer are arranged on the P-type drift region, a gate oxide layer is arranged above part of the P-type drift region and part of the N-type well, one end of the gate oxide layer is abutted against the boundary of the P-type source region, the other end of the gate oxide layer is abutted against the boundary of the field oxide layer, a polysilicon gate is arranged on the surface of the gate oxide layer, the polysilicon gate extends above the field oxide layer, dielectric layers are arranged on the surfaces of part of the N-type well, the N-type contact region, the P-type source region, the polysilicon gate, the P-type drain region and part of the field oxide layer, and drain metal is connected on the P-type drain region, characterized in that a first charge adjustable field plate, the adjustable type field plate of first electric charge is connected with first metal induction layer, be connected with second metal induction layer on the adjustable type field plate of second electric charge, be connected with third metal induction layer on the adjustable type field plate of third electric charge, be connected with source electrode metal on N type contact region and P type source region, source electrode metal extends to field oxide's top, and source electrode metal covers third metal induction layer completely.
Based on the basic scheme, the invention further carries out the following optimization, limitation and improvement:
the lengths of the first charge adjustable field plate, the second charge adjustable field plate, the third charge adjustable field plate, the first metal induction layer, the second metal induction layer and the third metal induction layer are different from each other, and can be adjusted according to design requirements.
The first charge-adjustable field plate, the second charge-adjustable field plate, the third charge-adjustable field plate, the first metal induction layer, the second metal induction layer and the third metal induction layer can be made of metal or heavily doped polysilicon and other materials with good conductivity.
The invention further discloses a driving chip applied to a printer, a motor or a flat panel display, and the P-type LDMOS structure with the charge-adjustable field plate is adopted.
The invention has the beneficial effects that:
(1) the potential of the field plate in the traditional structure is fixed to be a low potential in a voltage-resistant state of the device, the induced charge quantity on the field plate is also a fixed value and cannot be adjusted according to the voltage-resistant requirement of the drift region of the device, and the potential and the induced charge quantity of each field plate in the structure can be designed and adjusted according to the requirement of charge balance design of the drift region. In the structure of the present invention, the first charge-tunable field plate 121 is connected to the first metal sensing layer 131, so that the parasitic capacitance between the first charge-tunable field plate 121 and the P-type drift region 2 and the parasitic capacitance between the first metal sensing layer 131 and the source metal 14 form a series relationship. When the device is in a voltage-resistant state, the P-type drift region 2 is at a low potential, the source metal 14 is at a high potential, and the induced potentials of the first charge-tunable field plate 121 and the first metal sensing layer 131 are affected by the parasitic capacitance between the first charge-tunable field plate 121 and the P-type drift region 2 and the parasitic capacitance between the first metal sensing layer 131 and the source metal 14. Therefore, the potential of the first charge-tunable field plate 121 and the induced charge on the first charge-tunable field plate 121 can be adjusted by adjusting the length of the first charge-tunable field plate 121 and the length of the first metal sensing layer 131. Similarly, the potential of the second charge-tunable field plate 122 and the induced charge on the second charge-tunable field plate 122 can be adjusted by the length of the second charge-tunable field plate 122 and the length of the second metal sensing layer 132, and the potential of the third charge-tunable field plate 123 and the induced charge on the third charge-tunable field plate 123 can be adjusted by the length of the third charge-tunable field plate 123 and the length of the third metal sensing layer 133.
(2) The device with the structure can obtain uniform electric field distribution in the whole drift region and has high transverse voltage resistance. For the device with the structure of the present invention, the induced charge quantity on the first charge-adjustable field plate 121 can be adjusted to make the induced positive charge on the first charge-adjustable field plate 121 and the negative space charge in the P-type drift region 2 counteract each other, so that the device surface lateral electric field under the first charge-adjustable field plate 121 is uniformly distributed.
(3) The structure device of the invention has low on-resistance. The induced charge amounts on the first charge-adjustable field plate 121, the second charge-adjustable field plate 122 and the third charge-adjustable field plate 123 in the structure of the invention can be adjusted, so that after the doping concentration of the P-type drift region 2 of the device is increased, the induced charges on the first charge-adjustable field plate 121, the second charge-adjustable field plate 122 and the third charge-adjustable field plate 123 can be adjusted to enable the device to obtain uniform surface transverse electric field distribution in the whole drift region, therefore, the structure of the invention can reduce the on-resistance of the device by increasing the doping concentration of the P-type drift region 2 on the premise of keeping high breakdown voltage.
(4) The first charge-tunable field plate 121, the second charge-tunable field plate 122, the third charge-tunable field plate 123, the first metal sensing layer 131, the second metal sensing layer 132, and the third metal sensing layer 133 in the structure of the present invention can be implemented by using a polysilicon gate or an interconnection metal in a conventional CMOS process, and do not require additional process steps, so that the structure of the present invention is completely compatible with the conventional CMOS process, and does not increase process cost.
Drawings
Fig. 1 is a schematic structural diagram of a P-type LDMOS with a charge-tunable field plate according to the present invention.
The specific implementation mode is as follows:
referring to fig. 1, a P-type LDMOS structure with a charge tunable field plate includes: an N-type semiconductor substrate 1, a P-type drift region 2 and an N-type trap 3 are arranged on the N-type semiconductor substrate 1, a P-type source region 4 and an N-type contact region 5 are arranged on the N-type trap 3, a P-type drain region 6 and a field oxide layer 7 are arranged on the P-type drift region 2, a gate oxide layer 8 is arranged above part of the P-type drift region 2 and part of the N-type trap 3, one end of the gate oxide layer 8 is abutted against the boundary of the P-type source region 4, the other end of the gate oxide layer 8 is abutted against the boundary of the field oxide layer 7, a polysilicon gate 9 is arranged on the surface of the gate oxide layer 8, the polysilicon gate 9 extends to the upper part of the field oxide layer 7, a dielectric layer 10 is arranged on the surfaces of part of the N-type trap 3, the N-type contact region 5, the P-type source region 4, the polysilicon gate 9, the P-type drain region 6 and part of the field oxide layer 7, a drain metal 11 is, A second charge-tunable field plate 122 and a third charge-tunable field plate 123, the first charge-tunable field plate 121 is connected with a first metal sensing layer 131, the second charge-tunable field plate 122 is connected with a second metal sensing layer 132, the third charge-tunable field plate 123 is connected with a third metal sensing layer 133, the N-type contact region 5 and the P-type source region 4 are connected with a source metal 14, the source metal 14 extends to the top of the field oxide layer 7, and the source metal 14 completely covers the third metal sensing layer 133.
The P-type LDMOS structure with the charge-tunable field plate is characterized in that the lengths of the first charge-tunable field plate 121, the second charge-tunable field plate 122, the third charge-tunable field plate 123, the first metal sensing layer 131, the second metal sensing layer 132 and the third metal sensing layer 133 are different and can be respectively adjusted according to design requirements.
The P-type LDMOS structure with the charge-adjustable field plate is characterized in that the first charge-adjustable field plate 121, the second charge-adjustable field plate 122, the third charge-adjustable field plate 123, the first metal induction layer 131, the second metal induction layer 132 and the third metal induction layer 133 are made of a material with good conductivity, such as metal or heavily doped polysilicon.
The invention further discloses a driving chip applied to a printer, a motor or a flat panel display, which is characterized in that the driving chip adopts the P-type LDMOS structure with the charge-adjustable field plate.
It should be noted that, for those skilled in the art, various modifications and substitutions can be made without departing from the technical principle of the present invention, and these should be also construed as the scope of the present invention.
Claims (4)
1. A P-type LDMOS structure with a charge-tunable field plate comprises: n type semiconductor substrate (1), be provided with P type drift region (2) and N type trap (3) on N type semiconductor substrate (1), be equipped with P type source region (4) and N type contact zone (5) on N type trap (3), be equipped with P type drain region (6) and field oxide (7) on P type drift region (2), be equipped with gate oxide (8) above partial P type drift region (2) and partial N type trap (3), and the one end of gate oxide (8) offsets with the boundary of P type source region (4), the other end of gate oxide (8) offsets with the boundary of field oxide (7), is equipped with polycrystalline silicon gate (9) on gate oxide (8) surface, and polycrystalline silicon gate (9) extend to the top of field oxide (7), at partial N type trap (3), N type contact zone (5), P type source region (4), polycrystalline silicon gate (9), A dielectric layer (10) is arranged on the surfaces of the P-type drain region (6) and a part of the field oxide layer (7), a drain metal (11) is connected on the P-type drain region (6), characterized in that a first charge adjustable field plate (121), a second charge adjustable field plate (122) and a third charge adjustable field plate (123) are arranged on the surface of the field oxide layer (7), the first charge adjustable field plate (121) is connected with a first metal induction layer (131), a second metal induction layer (132) is connected on the second charge-adjustable field plate (122), a third metal induction layer (133) is connected on the third charge-adjustable field plate (123), a source metal (14) is connected on the N-type contact region (5) and the P-type source region (4), the source metal (14) extends to the upper part of the field oxide layer (7), and the source metal (14) completely covers the third metal induction layer (133);
when the device is in a voltage-resistant state, the P-type drift region (2) is at a low potential, the source metal (14) is at a high potential, and the induced potentials of the first charge-adjustable field plate (121) and the first metal induction layer (131) are influenced by the magnitude of parasitic capacitance between the first charge-adjustable field plate (121) and the P-type drift region (2) and the magnitude of parasitic capacitance between the first metal induction layer (131) and the source metal (14), so that the potential of the first charge-adjustable field plate (121) and the induced charge on the first charge-adjustable field plate (121) can be adjusted by adjusting the length of the first charge-adjustable field plate (121) and the length of the first metal induction layer (131); the induced potentials of the second charge-tunable field plate (122) and the second metal induction layer (132) are influenced by the parasitic capacitance between the second charge-tunable field plate (122) and the P-type drift region (2) and the parasitic capacitance between the second metal induction layer (132) and the source metal (14), so that the potential of the second charge-tunable field plate (122) and the induced charge on the second charge-tunable field plate (122) can be adjusted by the length of the second charge-tunable field plate (122) and the length of the second metal induction layer (132); the induced potentials of the third charge-tunable field plate (123) and the third metal induction layer (133) are affected by the parasitic capacitance between the third charge-tunable field plate (123) and the P-type drift region (2) and the parasitic capacitance between the third metal induction layer (133) and the source metal (14), so that the potential of the third charge-tunable field plate (123) and the induced charge on the third charge-tunable field plate (123) can be adjusted by the length of the third charge-tunable field plate (123) and the length of the third metal induction layer (133);
adjusting the induced positive charge on the first adjustable field plate (121) to counteract the negative space charge in the P-type drift region (2), so that the lateral electric field of the device surface under the first charge adjustable field plate (121) is uniformly distributed; adjusting the induced positive charges on the second adjustable field plate (122) to counteract the negative space charge in the P-type drift region (2) so that the lateral electric field of the surface of the device below the second adjustable field plate (122) is uniformly distributed; and adjusting the induced positive charges on the third adjustable field plate (123) to counteract the negative space charge in the P-type drift region (2) so that the lateral electric field on the surface of the device below the third adjustable field plate (123) is uniformly distributed, thereby obtaining uniform lateral electric field distribution on the surface of the device in the whole drift region.
2. The P-type LDMOS structure with a charge modulated field plate of claim 1, wherein the lengths of the first charge modulated field plate (121), the second charge modulated field plate (122), the third charge modulated field plate (123), the first metal sensing layer (131), the second metal sensing layer (132) and the third metal sensing layer (133) are different and can be adjusted according to design requirements.
3. The P-type LDMOS structure with a charge modulated field plate of claim 1, wherein the material of the first charge modulated field plate (121), the second charge modulated field plate (122), the third charge modulated field plate (123), the first metal sensing layer (131), the second metal sensing layer (132) and the third metal sensing layer (133) is metal.
4. A driver chip for a printer, a motor or a flat panel display, wherein the P-type LDMOS structure with a charge tunable field plate as claimed in any one of claims 1 to 3 is used.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711034819.XA CN107887426B (en) | 2017-10-30 | 2017-10-30 | P-type LDMOS structure with charge-adjustable field plate |
| PCT/CN2018/112150 WO2019085835A1 (en) | 2017-10-30 | 2018-10-26 | Super field plate structure adapted for power semiconductor device, and application thereof |
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| CN201711034819.XA CN107887426B (en) | 2017-10-30 | 2017-10-30 | P-type LDMOS structure with charge-adjustable field plate |
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| WO2019085835A1 (en) * | 2017-10-30 | 2019-05-09 | 济南大学 | Super field plate structure adapted for power semiconductor device, and application thereof |
| CN116759455A (en) * | 2018-05-25 | 2023-09-15 | 矽力杰半导体技术(杭州)有限公司 | Laterally diffused metal oxide semiconductor device and method of manufacturing the same |
| CN110634948B (en) * | 2018-06-22 | 2023-03-24 | 中芯国际集成电路制造(上海)有限公司 | LDMOS device and forming method thereof |
| CN109300988A (en) * | 2018-10-08 | 2019-02-01 | 深圳市南硕明泰科技有限公司 | A kind of LDMOS and its manufacturing method |
| CN111200006B (en) * | 2018-11-19 | 2021-12-21 | 无锡华润上华科技有限公司 | Lateral double-diffusion metal oxide semiconductor field effect transistor and preparation method thereof |
| CN112750911B (en) * | 2021-02-03 | 2022-06-17 | 南京邮电大学 | LDMOS with controllable three-dimensional electric field and preparation method thereof |
| CN113270500B (en) * | 2021-05-17 | 2022-11-04 | 电子科技大学 | Power semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102867844A (en) * | 2012-09-27 | 2013-01-09 | 东南大学 | P-shaped longitudinal highly-pressure-resistant transverse double-diffusion metal oxide semiconductor transistor |
| CN106653830A (en) * | 2015-10-28 | 2017-05-10 | 无锡华润上华半导体有限公司 | Semiconductor device voltage-withstanding structure |
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| CN102867844A (en) * | 2012-09-27 | 2013-01-09 | 东南大学 | P-shaped longitudinal highly-pressure-resistant transverse double-diffusion metal oxide semiconductor transistor |
| CN106653830A (en) * | 2015-10-28 | 2017-05-10 | 无锡华润上华半导体有限公司 | Semiconductor device voltage-withstanding structure |
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