WO2019085835A1 - Super field plate structure adapted for power semiconductor device, and application thereof - Google Patents

Abstract

A super field plate structure adapted for a power semiconductor device, and an application thereof. The super field plate structure adapted for a power semiconductor device comprises: an adjustable field plate (131-133) and a regulating capacitor, wherein one electrode (141-143) of the regulating capacitor is connected to the adjustable field plate (131-133) or the adjustable field plate (131-133) is directly used as an electrode, the other electrode (151-153) of the regulating capacitor is connected with an electrode, having the lowest level, of the power semiconductor device through a metal interconnecting wire (16), and the adjustable field plate (131-133) is arranged on a surface of a dielectric layer (8) of the power semiconductor device; by arranging the size of the electrodes of the regulating capacitor, the amount of induced charges and an inductive level on the adjustable field plate (131-133) can be regulated, so that uniform lateral electric field distribution is obtained in a drift region (3) at a position corresponding to the super field plate structure. By the design of the size of a regulating capacitor in a super field plate, the inductive level and the amount of induced charges of an adjustable field plate (131-133) in the super field plate can be changed, and the function of the super field plate in adjusting an electric field of a drift region (3) of a power semiconductor device is further changed, so that the drift region (3) has uniform lateral electric field distribution.

Description

Super field plate structure suitable for power semiconductor devices and its application Technical field

The present disclosure relates to the field of power semiconductor devices and, more particularly, to a super field plate structure suitable for use in power semiconductor devices and applications thereof.

Background technique

Power semiconductor devices include lateral double-diffused metal oxide semiconductor field effect transistors (LDMOS), lateral insulated gate bipolar transistors (LIGBTs), high electron mobility transistors (HEMTs), and high voltage diodes. They are characterized by high breakdown voltage and high current capability, and are widely used in power management systems for electrical equipment such as mobile phones, computers and motors. Power management systems require power semiconductor devices to have as high a breakdown voltage as possible and as much current as possible, and there is a contradiction between the breakdown voltage and current capability of power semiconductor devices. Therefore, technicians in the field of power semiconductor devices are There is a conflict between efforts to address the breakdown voltage and current capability of power semiconductor devices.

Field plate technology is a technology that can effectively alleviate the contradiction between the breakdown voltage and current capability of power semiconductor devices. The traditional field plate structure mainly includes the source field plate and the floating field plate.

The source field plate structure is shown in Figure 1. The source field plate is connected to the source metal of the device and has a fixed potential. However, in the withstand voltage state, the surface potential of the drift region is continuously along the source to the drain. Therefore, the effect of the source field plate increases along the direction of the source and the drain, which results in a uniform lateral electric field distribution on the device surface, which is not conducive to the breakdown voltage optimization of the device, and at the same time, to avoid the source field. The plate is too strong, and its length cannot be too long. It can only be placed in a part of the drift region close to the source, and cannot cover the entire drift region. Therefore, the source field plate cannot act on the entire drift region of the device.

The structure of the floating field plate is shown in Figure 2. The potential of the floating field plate is obtained by the inductive coupling of the potential of the drift region of the device. The potential is the average potential of the drift surface below the field plate, and the induced potential cannot be adjusted according to the needs of the design personnel. Therefore, the potential of the floating field plate (reference numeral 17 in Fig. 2) is very close to the surface potential of the drift region, and the adjustment of the electric field on the surface of the drift region is very small, and only local electric field adjustment can be performed, and the entire device cannot be drifted. The zone obtains a uniform transverse electric field distribution.

Therefore, the conventional source field plate and the floating field plate cannot obtain a uniform lateral electric field distribution in the device drift region, and the device withstand voltage capability cannot be optimized.

Summary of the invention

The present disclosure proposes a super field plate structure suitable for a power semiconductor device and its application, which can improve the lateral electric field distribution of the surface of the power semiconductor device, improve the lateral withstand voltage capability of the power semiconductor device, and reduce the on-resistance of the device.

A super field plate structure suitable for a power semiconductor device disclosed in one or more embodiments, comprising: an adjustable field plate and an adjustment capacitor, one of the electrodes of the adjustment capacitor being connected to the adjustable field plate or The adjustable field plate is directly used as an electrode for adjusting the capacitance, which is called a positive electrode; the other electrode of the regulating capacitor is connected to the electrode which is always at the lowest potential in the power semiconductor device through a metal interconnection, which is called a negative electrode; The adjustable field plate is disposed on a surface of the dielectric layer of the power semiconductor device;

By setting the size of the adjustment capacitor electrode, the amount of induced charge and the induced potential on the adjustable field plate can be adjusted so that a uniform lateral electric field distribution is obtained in the drift region corresponding to the position of the super field plate structure.

Further, the super field plates are spaced apart in the longitudinal direction of the power semiconductor device such that the effect covers the entire drift region of the power semiconductor device, so that the entire drift region obtains a uniform lateral electric field distribution.

By designing the size of the regulating capacitor in the super field plate, the sensing potential of the adjustable field plate in the super field plate can be changed, thereby changing the adjustment effect of the super field plate on the electric field in the drift region of the power semiconductor device, and the drift under the super field plate A uniform transverse electric field distribution is obtained in the region, and a plurality of super field plates are laterally spaced apart on the surface of the dielectric layer of the power semiconductor device, so that the effect of the super field plate covers the entire drift region, so that a uniform lateral electric field can be obtained in the entire drift region of the power semiconductor device. distributed. Therefore, the super field plate can achieve the best lateral withstand voltage capability of the power semiconductor device.

Further, the adjustable field plate is intermittently disposed along the width direction of the power semiconductor device, and the adjustable field plate in the width direction is divided into a plurality of adjustable field plate units, and each adjustable field plate unit is connected correspondingly Adjust the capacitance.

Further, the metal interconnections for connecting the adjustment capacitors and the electrodes which are always at the lowest potential in the power semiconductor device are arranged in a misaligned manner in the length direction. In order to prevent the field plate effect brought by the metal interconnections from overlapping each other in the length direction, the metal interconnection line is prevented from lowering the lateral withstand voltage capability of the power semiconductor device.

Further, when the power semiconductor device has at least two dielectric layers, an adjustable field plate is disposed on at least two dielectric layers of the power semiconductor device, and each of the adjustable field plates is connected to one of the electrodes of the adjustment capacitor, and is adjusted. The other electrode of the capacitor is connected to an electrode that is always at the lowest potential in the power semiconductor device.

A lateral double-diffused metal oxide semiconductor field effect transistor disclosed in one or more embodiments, comprising: a source metal, a field oxide layer, and a drift region under the field oxide layer, further comprising: the above for power The super field plate structure of the semiconductor device; specifically: setting a plurality of adjustable field plates on the surface of the field oxide layer, and setting a distance between two adjacent adjustable field plates;

Each adjustable field plate is connected with an adjustment capacitor; the adjustable field plate is connected to the positive electrode of the adjustment capacitor, and the negative electrode of the adjustment capacitor is disposed above the positive electrode of the adjustment capacitor; the negative electrode of all the adjustment capacitors passes through the metal The interconnect is connected to the source metal;

By setting the size of the positive and negative electrodes of the adjustable field plate and adjusting the capacitance, the amount of induced charge and the induced potential on the adjustable field plate can be adjusted, so that a uniform surface transverse electric field distribution is obtained in the drift region.

Further, in the direction of the source metal to the drain metal, the areas covered by the positive and negative electrodes of the adjusting capacitor are successively decreased.

Further, a gap between the source metal and the drain metal is filled with an insulating dielectric layer.

A high voltage diode disclosed in one or more embodiments, comprising: a cathode metal, a field oxide layer and a drift region under the field oxide layer, further comprising: the above-described super field plate structure suitable for a power semiconductor device; a plurality of adjustable field plates are disposed on the surface of the field oxide layer, and a distance is set between two adjacent adjustable field plates;

Each adjustable field plate is connected with an adjustment capacitor; the adjustable field plate is connected to the positive electrode of the adjustment capacitor, and the negative electrode of the adjustment capacitor is disposed above the positive electrode of the adjustment capacitor; the negative electrode of all the adjustment capacitors passes through the metal The interconnect is connected to the cathode metal;

By setting the size of the positive and negative electrodes of the adjustable field plate and adjusting the capacitance, the induced potential and the amount of induced charge on the adjustable field plate can be adjusted, so that a uniform surface electric field distribution is obtained in the drift region.

Further, the gap of the surface of the device is filled with an insulating dielectric layer.

A high electron mobility transistor disclosed in one or more embodiments, comprising: a substrate; a buffer layer disposed above the substrate; a channel layer disposed above the buffer layer; a source metal and a drain layer disposed above the channel layer a metal and a barrier layer, and a source metal and a drain metal are located at both ends of the barrier layer; a dielectric layer and a gate electrode are disposed over the barrier layer; and the super field plate structure suitable for the power semiconductor device is further included Specifically, a plurality of adjustable field plates are disposed on a surface of the dielectric layer between the gate electrode and the drain metal, and a distance is set between two adjacent adjustable field plates; each adjustable field A coupling electrode is disposed above the board, and all the coupling electrodes are connected to the source metal through the metal interconnection;

The adjustable field plate is the coupled field plate, the coupling electrode is used as the negative electrode of the adjusting capacitor, and the adjustable field plate is used as the positive electrode of the adjusting capacitor, and can be changed by setting the coverage area between the coupling electrode and the corresponding adjustable field plate. The coupling effect of the coupling electrode on the corresponding coupling field plate changes the coupling potential of the corresponding coupling field plate, thereby adjusting the transverse electric field in the barrier layer below the corresponding coupling field plate, and finally optimizing the lateral direction between the gate electrode and the drain metal of the device. The electric field distribution increases the lateral withstand voltage capability of the device.

Further, in the direction of the source metal to the drain metal, the area covered by the coupling electrode and the corresponding adjustable field plate is successively decreased.

Further, the metal interconnection between the coupling electrodes and the metal interconnection between the coupling electrode and the source electrode are spaced apart from each other by a set distance in the width direction.

A potential floating type super field plate structure suitable for a power semiconductor device disclosed in one or more embodiments, comprising: an adjustment capacitor and an adjustable field plate; the adjustable field plate being disposed in a power semiconductor device medium The surface of the layer;

One of the electrodes of the adjustment capacitor is connected to the adjustable field plate, and the other electrode of the adjustment capacitor is used as a field plate potential adjustment electrode of the power semiconductor device, and the potential thereof is provided by an external circuit;

When the power semiconductor device is in a withstand voltage state, the external circuit supplies the field plate potential adjustment electrode with the same potential as the electrode having the lowest potential of the power semiconductor device;

The size of the regulating capacitor in the potential floating type super field plate can change the sensing potential of the adjustable field plate in the potential floating type super field plate, thereby changing the electric field adjustment of the potential floating type super field plate in the drift region of the power semiconductor device. The size of the action enables a uniform lateral electric field distribution in the drift region of the power semiconductor device, so that the power semiconductor device can obtain the best lateral withstand voltage capability;

When the power semiconductor device is in an on state, the external circuit provides a potential for the field plate potential adjustment electrode that is higher than the potential of the lowest potential electrode of the power semiconductor device.

At this time, the field plate potential adjusting electrode will make the adjustable field plate potential in the potential floating type super field plate higher than the potential of the drift region of the power semiconductor device through the coupling effect of the adjusting capacitor in the potential floating type super field plate, therefore, the potential The adjustable field plate in the floating super field plate will induce additional carriers on the surface of the drift region of the power semiconductor device to improve the current capability of the power semiconductor device.

Further, at least two potential floating type super field plate structures are disposed on the surface of the lateral double-diffused metal oxide semiconductor field effect transistor dielectric layer; the electrode of the adjusting capacitor as a power semiconductor device field plate potential adjusting electrode is completely covered with another One electrode.

A power management chip disclosed in one or more embodiments includes any of the above-described super field plate structures or any of the above-described potential floating type super field plate structures.

Advantages of the disclosure:

(1) When the super field plate structure proposed by the present disclosure is applied to a power semiconductor device, the size of the adjustment capacitor in the super field plate can adjust the sensing potential of the adjustable field plate in the super field plate under the withstand voltage state of the power semiconductor device, By adjusting the size of the capacitor in the super field plate, the sensing potential and the amount of induced charge of the adjustable field plate in the super field plate can be changed, thereby changing the electric field adjustment effect of the super field plate on the drift region of the power semiconductor device, so that the super field The drift region under the plate obtains a uniform transverse electric field distribution, and a plurality of super field plates are laterally spaced along the drift region of the power semiconductor device, so that the effect of the super field plate completely covers the entire drift region of the power semiconductor device, so that the entire power semiconductor device can be made. A uniform transverse electric field distribution is obtained in the drift region, so that the power semiconductor device can obtain the best lateral withstand voltage capability. Therefore, the super field plate structure proposed by the present disclosure can provide the power semiconductor device with an optimum lateral withstand voltage capability.

(2) The magnitude of the electric field adjustment effect of the super field plate structure proposed by the present disclosure on the drift region of the power semiconductor device can be adjusted by design. Therefore, by increasing the doping concentration of the drift region of the power semiconductor device, the design of the super field plate can still be adopted. The drift region of the power semiconductor device achieves a uniform transverse electric field distribution so as not to degrade the lateral withstand capability of the device. Therefore, the super field plate structure proposed by the present disclosure can enable the power semiconductor device to increase the drift region doping concentration, reduce the on-resistance, and increase the current capability without reducing the lateral withstand voltage capability.

(3) The adjustment capacitor in the super field plate proposed by the present invention can be realized by using parasitic capacitance between interconnect metals, parasitic capacitance between interconnect metal and polysilicon, or separately fabricated capacitors outside the device, and is compatible with conventional processes. Strong, will not increase the cost of the process;

When the adjustment capacitor is implemented with parasitic capacitance between the interconnect metals, the super field plate structure is fully compatible with conventional processes and does not increase the area of the power semiconductor device;

When the regulating capacitor is realized by the parasitic capacitance between the interconnect metal and the polysilicon, the super field plate does not increase the area of the power semiconductor device, and only needs to occupy one layer of interconnect metal;

When the adjustment capacitor is realized by a separately fabricated capacitor outside the device, the size of the adjustment capacitor is not limited by the size of the power semiconductor device, and the selectable range is large, and the selectable range of the electric field adjustment effect of the super field plate on the drift region of the power semiconductor device is correspondingly increased. Big.

(4) The adjustable field plate in the super field plate structure proposed by the present disclosure may be disposed on different dielectric layers, and the adjustable field plate may be disposed on different dielectric layers to change the adjustable field plate and the power semiconductor device. The size of the parasitic capacitance between the drift regions, in turn, changes the size of the super field plate adjustment, so that the super field plate can meet the needs of different situations and increase the application range of the super field plate.

(5) When the power semiconductor device drift region is laterally disposed with a plurality of super field plates, metal interconnection lines for connecting the super field plate and the lowest potential electrode of the power semiconductor device are misaligned in the length direction of the device, thereby preventing metal interconnection lines The additional field plate effects are superimposed on each other in the length direction, which effectively reduces the adverse effect of the metal interconnection on the lateral withstand voltage capability of the device.

(6) When the potential floating type super field plate is applied to a power semiconductor device, the field plate potential adjusting electrode of the potential floating type super field plate is applied with the same potential as the low potential electrode of the power semiconductor device under the withstand voltage state of the power semiconductor device. The time-potential floating type field plate has the same effect as the above-mentioned super field plate, and can obtain the optimum lateral withstand voltage capability of the power semiconductor device, and the field plate potential adjustment of the potential floating type super field plate under the conduction state of the power semiconductor device The potential applied by the electrode is higher than the potential of the lowest potential electrode of the power semiconductor device, so that the coupling potential of the adjustable field plate in the potential floating type super field plate is higher than the drift region potential of the power semiconductor device, and therefore, the potential floating field plate field plate Additional carriers will be induced in the drift region of the power semiconductor device, increasing the current capability of the power semiconductor device. Therefore, the potential floating type super field plate can achieve the best lateral voltage withstand capability and greater current capability of the power semiconductor device.

Instruction sheet

The accompanying drawings that form a part of this disclosure are used to provide a further understanding of the disclosure, and the description of the present disclosure and the description thereof are not intended to limit the disclosure.

1 is a schematic diagram of a three-dimensional structure of an LDMOS with a conventional source field plate;

2 is a schematic diagram of a three-dimensional structure of an LDMOS with a conventional floating field plate;

3(a) is a three-dimensional structural diagram of an LDMOS with a super field plate in Example 1;

Figure 3 (b) is a two-dimensional cross-sectional view of the LDMOS with the super field plate in the first embodiment along the length direction and the thickness direction;

3(c) is a top plan view of the LDMOS with the super field plate in the first example;

4 is a schematic view showing a three-dimensional structure of a high voltage diode with a super field plate in Example 2;

5 is a three-dimensional structural diagram of a high voltage diode terminal structure with a super field plate in Example 3;

6 is a schematic diagram of a three-dimensional structure of a HEMT with a super field plate in Example 4;

7 is a schematic structural view of an LIGBT with a super field plate in Example 5;

8 is a schematic structural view of an LDMOS with a potential floating type super field plate in Example 6;

Fig. 9 is a view showing the potential change of the field plate potential adjusting electrode and the gate electrode of the sixth embodiment with the potential floating type super field plate LDMOS.

Among them, 1.P type semiconductor substrate, 2. buried oxide layer, 3.N type drift region, 4.P type well, 5.P type contact region, 6.N type source region, 7. source metal, 8 Dielectric layer, 8-1. First dielectric layer, 8-2. Second dielectric layer, 9. N-type contact region, 10. Drain metal, 11. Gate oxide layer, 12. Gate electrode, 131. First Adjustable field plate, 132. second adjustable field plate, 133. third adjustable field plate, 134. fourth adjustable field plate, 141. first regulating capacitor positive electrode, 142. second adjustment Capacitor positive electrode, 143. Third regulating capacitor positive electrode, 144. Fourth regulating capacitor positive electrode, 151. First regulating capacitor negative electrode, 152. Second regulating capacitor negative electrode, 153. Third regulating capacitor negative electrode, 16 Metal interconnect, 17. floating field plate, 18. cathode metal, 19. anode metal, 20. substrate, 21. buffer layer, 22. channel layer, 23. barrier layer, 24. P-type anode Contact region, 25. third dielectric layer, 26. field plate potential adjustment electrode, 271. first metal sensing layer, 272. second metal sensing layer, 273. third metal sensing layer.

Detailed ways

It should be noted that the following detailed description is illustrative and is intended to provide a further description of the disclosure. All technical and scientific terms used in the present disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs, unless otherwise indicated.

It is to be noted that the terminology used herein is for the purpose of describing the particular embodiments, As used herein, the singular " " " " " " There are features, steps, operations, devices, components, and/or combinations thereof.

Embodiment 1

In one or more embodiments, a super field plate structure suitable for a power semiconductor device is disclosed, comprising: an adjustable field plate and an adjustment capacitor, one of the electrodes of the adjustment capacitor being connected to the adjustable field plate, adjusted The other electrode of the capacitor is connected to the electrode having the lowest potential in the power semiconductor device through the metal interconnection 16, and the adjustable field plate is disposed on the surface of the dielectric layer 8 of the power semiconductor device.

By designing the size of the regulating capacitor in the super field plate, the sensing potential of the adjustable field plate in the super field plate can be changed, thereby changing the adjustment effect of the super field plate on the electric field in the drift region of the power semiconductor device, and the drift under the super field plate The region obtains a uniform transverse electric field distribution;

By arranging a plurality of super field plate structures laterally spaced apart on the surface of the dielectric semiconductor device dielectric layer 8, a uniform lateral electric field distribution can be obtained throughout the drift region of the power semiconductor device, thereby obtaining an optimum lateral withstand voltage capability of the power semiconductor device.

It should be noted that the metal interconnections 16 for connecting the adjustment capacitor and the low potential electrode of the power semiconductor device may be arranged along the same line in the longitudinal direction or may be arranged in a misalignment; when the metal interconnections 16 are arranged in a misaligned manner, it can be prevented. The field plate effects brought about by the metal interconnections 16 are superimposed on each other in the length direction, thereby preventing the metal interconnections 16 from lowering the lateral withstand voltage capability of the power semiconductor device.

3(a)-(c) show an example of the structure in which the above super field plate structure is applied to a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS).

The lateral double-diffused metal oxide semiconductor field effect transistor includes: a P-type semiconductor substrate 1 on which a buried oxide layer 2 is provided, and an N-type drift region 3 and a P-type are provided on the buried oxide layer 2. The well 4 is provided with a P-type contact region 5 and an N-type source region 6 on the P-type well 4, and a source metal 7 is connected to the P-type contact region 5 and the N-type source region 6, on the N-type drift region 3. A field oxide layer and an N-type contact region 9 are provided, a drain metal 10 is connected to the N-type contact region 9, a gate oxide layer 11 is disposed over a portion of the N-type drift region 3 and a portion of the P-type well 4, and gate oxide is formed. One end of the layer 11 is opposite to the boundary of the N-type source region 6, the other end of the gate oxide layer 11 is opposite to the boundary of the field oxide layer, the gate electrode 12 is disposed above the gate oxide layer 11, and the gate electrode 12 is extended to the field oxide layer. Above.

It should be noted that, according to a conventional understanding by those skilled in the art, the field oxide layer of the lateral double-diffused metal oxide semiconductor field effect transistor is a dielectric layer, and therefore, the adjustable field plate in the super field plate can be set in the field. Oxide layer surface.

As shown in FIG. 3(a), a plurality of adjustable field plates are disposed on the surface of the field oxide layer, and a distance is set between two adjacent adjustable field plates; each adjustable field plate is connected with an adjustment capacitor; The adjustable field plate is connected to the positive electrode of the adjusting capacitor, and the adjusting capacitor negative electrode is arranged above the adjusting capacitor positive electrode; the source is the electrode with the lowest potential in the lateral double-diffused metal oxide semiconductor field effect transistor, and the negative electrode of all adjusting capacitors It is connected to the source metal 7 through a metal interconnection 16.

The number of adjustable field plates is set according to actual needs.

The number of adjustable field plates shown in Figures 3(a)-(c) is three, respectively: first adjustable field plate 131, second adjustable field plate 132, and third adjustable type Field plate 133;

A first adjustable capacitor positive electrode 141 is connected to the first adjustable field plate 131, a second adjustable capacitor positive electrode 142 is connected to the second adjustable field plate 132, and a third adjustable field plate 133 is connected to the first adjustable field plate 133. Three adjustment capacitor positive electrode 143;

A first adjustment capacitor negative electrode 151 is disposed above the first adjustment capacitor positive electrode 141, a second adjustment capacitor negative electrode 152 is disposed above the second adjustment capacitor positive electrode 142, and a third adjustment capacitor is disposed above the third adjustment capacitor positive electrode 143. The negative electrode 153, the first adjustment capacitor negative electrode 151, the second adjustment capacitor negative electrode 152, and the third adjustment capacitor negative electrode 153 are connected to the source metal 7 through the metal interconnection 16.

As shown in Fig. 3(c), the adjustment capacitor positive electrode and the adjustment capacitor negative electrode are equal in size and perfectly aligned. The area of the third adjustment capacitor negative electrode 153 and the third adjustment capacitor positive electrode 143 covering each other is smaller than the area covered by the second adjustment capacitor negative electrode 152 and the second adjustment capacitor positive electrode 142; the second adjustment capacitor negative electrode 152 and the second The area of the adjustment capacitor positive electrode 142 covering each other is smaller than the area covered by the first adjustment capacitor negative electrode 151 and the first adjustment capacitor positive electrode 141.

Or, adjust the coverage area of each adjustment capacitor according to actual needs.

In still other embodiments, the voids in the surface of the lateral double-diffused metal oxide semiconductor field effect device device may be filled with an insulating dielectric layer.

The positive and negative electrodes of the first regulating capacitor, the positive and negative electrodes of the second regulating capacitor, and the dimensions of the positive and negative electrodes of the third regulating capacitor in the length direction and the width direction can be designed according to the needs of the device. By setting the adjustable field plate and adjusting the size of the positive and negative electrodes of the capacitor, the amount of induced charge and the induced potential on the adjustable field plate can be adjusted, so that a uniform surface transverse electric field distribution is obtained in the drift region.

In one or more embodiments, the adjustable field plates are intermittently disposed in the width direction, and each of the segmented adjustable field plate units is connected to the positive plate of the regulating capacitor, and the regulating capacitors on the adjacent two segments are The positive plate of the capacitor is also disconnected, and the negative plate of the regulating capacitor can be disconnected or not. In the above manner, the size of the parasitic capacitance between the adjustable field plate and the drift region and the size of the parasitic capacitance between the positive and negative plates of the capacitor can be adjusted.

In this embodiment, the parasitic capacitance between the first adjustable field plate 131 and the N-type drift region 3 is named C131, and the parasitic capacitance between the first adjustment capacitor positive electrode 141 and the first adjustment capacitor negative electrode 151 is Named C141, since the first adjustable field plate 131 is connected to the first regulating capacitor positive electrode 141, the parasitic capacitances C131 and C141 form a series relationship, and when the device is in the off voltage withstand state, the first regulating capacitor negative electrode 151 is at Low potential, and the N-type drift region 3 is at a high potential, according to the voltage division relationship of the series capacitor, the potential of the first adjustable field plate 131 is between the potential of the N-type drift region 3 and the first adjustment capacitor negative electrode Between the potentials of 151, and the potential of the first tunable field plate 131 is affected by the magnitude of the parasitic capacitances C131 and C141.

Therefore, by designing the length and width of the first adjustable type field plate 131, the first adjustment capacitor positive electrode 141, and the first adjustment capacitance negative electrode 151, the size of the parasitic capacitances C131 and C141 can be adjusted, thereby adjusting the first adjustable type. The potential of the field plate 131 can adjust the amount of induced charge on the first adjustable field plate 131 by adjusting the potential of the first adjustable field plate 131, thereby adjusting the magnitude of the action of the first adjustable field plate 131. The N-type drift region 3 below the tunable field plate 131 achieves a uniform surface lateral (i.e., lengthwise) electric field distribution.

Similarly, the potential of the second adjustable field plate 132 can be adjusted by the length and width design of the second adjustable field plate 132, the second adjusting capacitor positive electrode 142 and the second adjusting electrode negative electrode, thereby making the second The N-type drift region 3 under the adjustable field plate 132 obtains a uniform surface transverse electric field distribution, and is designed by the length and width of the third adjustable field plate 133, the third regulating capacitor positive electrode 143, and the third regulating electrode negative electrode. The potential of the third adjustable field plate 133 can be adjusted such that the N-type drift region 3 under the third adjustable field plate 133 obtains a uniform surface transverse electric field distribution.

The super-field plate structure at different lateral positions has different potentials under the device understand voltage state, and the device can obtain uniform surface transverse electric field distribution throughout the drift region, so that the device has the best lateral withstand voltage capability.

Embodiment 2

In one or more embodiments, a structural example in which the super field plate structure in the first embodiment is applied to a high voltage diode is disclosed. As shown in FIG. 4, the structure of the high voltage diode includes: a P type semiconductor substrate 1, at P The semiconductor substrate 1 is provided with a buried oxide layer 2, and the buried oxide layer 2 is provided with an N-type drift region 3 and a P-type well 4, and a P-type contact region 5 is provided on the P-type well 4, in a P-type contact. A cathode metal 18 is connected to the region 5, a field oxide layer and an N-type contact region 9 are provided on the N-type drift region 3, and an anode metal 19 is connected to the N-type contact region 9.

It should be noted that, according to a conventional understanding by those skilled in the art, the field oxide layer of the high voltage diode is a dielectric layer, and therefore, the adjustable field plate in the super field plate can be disposed on the surface of the field oxide layer.

A plurality of adjustable field plates are arranged on the surface of the field oxide layer, and the distance between adjacent two adjustable field plates is set; each adjustable field plate is connected with an adjustment capacitor; the adjustable field plate and the adjustable capacitance are The positive electrodes are connected, and a negative electrode of the regulating capacitor is disposed above the positive electrode of the adjusting capacitor; the cathode is an electrode of the high voltage diode which is always at the lowest potential, and the negative electrodes of all the adjusting capacitors are connected to the cathode metal 18 through the metal interconnection 16.

The rest of the structure of the super field plate is the same as that in the first embodiment, and will not be described again.

In other embodiments, the voids in the surface of the high voltage diode device with the adjustable field plate may be filled with an insulating dielectric layer.

Embodiment 3

In one or more embodiments, a structural example of applying the super field plate structure of the first embodiment to a terminal structure of a high voltage diode is disclosed. As shown in FIG. 5, the structure of the high voltage diode includes: an anode metal 19, An anode contact region 9 is provided on the anode metal 19, an N-type drift region 3 and a P-type well 4 are provided on the N-type contact region 9, and a P-type contact region 5 is provided on the P-type well 4 in the P-type contact. A cathode metal 18 is connected to the region 5, and a field oxide layer is provided on the N-type drift region 3.

It should be noted that, according to a conventional understanding by those skilled in the art, the field oxide layer of the termination structure of the high voltage diode is a dielectric layer, and therefore, the adjustable field plate in the super field plate can be disposed on the surface of the field oxide layer.

A plurality of adjustable field plates are arranged on the surface of the field oxide layer, and the distance between adjacent two adjustable field plates is set; each adjustable field plate is connected with an adjustment capacitor; the adjustable field plate and the adjustable capacitance are The positive electrodes are connected, and a negative electrode of the regulating capacitor is disposed above the positive electrode of the adjusting capacitor; the cathode is an electrode having the lowest potential in the terminal structure of the high voltage diode, and the negative electrodes of all the adjusting capacitors are connected to the cathode metal 18 through the metal interconnection 16.

The rest of the structure of the super field plate is the same as that in the first embodiment, and will not be described again.

In still other embodiments, the voids in the surface of the termination structure of the high voltage diode with the adjustable field plate may be filled with an insulating dielectric layer.

It should be noted that, in addition to the power semiconductor devices given in Embodiment 1, Embodiment 2 and Embodiment 3, the above-mentioned super field plate structure is also applicable to other power semiconductor devices, such as: insulated gate bipolar transistors and High electron mobility transistors, etc.

Embodiment 4

A super field plate structure suitable for a power semiconductor device is disclosed in one or more embodiments, including: an adjustable field plate and an adjustment capacitor, wherein, as a conventional variation of the adjustment capacitor in the first embodiment, directly An adjustable field plate is used as one of the electrodes for adjusting the capacitance, and the other electrode of the adjustment capacitor is connected to the electrode having the lowest potential in the power semiconductor device through the metal interconnection 16 , and the adjustable field plate is disposed on the dielectric layer 8 of the power semiconductor device s surface.

By designing the size of the regulating capacitor in the super field plate, the sensing potential of the adjustable field plate in the super field plate can be changed, thereby changing the adjustment effect of the super field plate on the electric field in the drift region of the power semiconductor device, and the drift under the super field plate The region obtains a uniform transverse electric field distribution;

By arranging a plurality of super field plate structures laterally spaced apart on the surface of the dielectric semiconductor device dielectric layer 8, a uniform lateral electric field distribution can be obtained throughout the drift region of the power semiconductor device, thereby obtaining an optimum lateral withstand voltage capability of the power semiconductor device.

Fig. 6 shows an example of the structure in which the super field plate structure of the present embodiment is applied to a high electron mobility transistor.

The structure of the high electron mobility transistor includes: a substrate 20; a buffer layer 21 disposed above the substrate 20; a channel layer 22 disposed above the buffer layer 21; and a source metal 7 (source electrode) disposed above the channel layer 22, a drain metal 10 (drain electrode) and a barrier layer 23, and a source metal 7 and a drain metal 10 are located at both ends of the barrier layer 23, and a barrier layer 23 is located between the source metal 7 and the drain metal 10; A dielectric layer 8 and a gate electrode 12 are provided above the barrier layer 23.

It should be noted that the barrier layer of the high electron mobility transistor is also referred to as a drift region according to a conventional understanding by those skilled in the art.

As shown in FIG. 6, a plurality of coupled field plates (ie, adjustable field plates, the same below) are disposed on the surface of the dielectric layer 8, and a distance is set between adjacent two coupled field plates; each of the coupled field plates is disposed above There is a coupling electrode (ie, the negative electrode of the adjustment capacitor). In this embodiment, the coupling field plate simultaneously functions as a positive electrode for adjusting the capacitance in the super field plate, and forms an adjustment capacitor in the super field plate with the coupling electrode; the source metal 7 It is an electrode that is always at the lowest potential in the high electron mobility transistor. Therefore, all the coupling electrodes are connected to the source metal 7 through the metal interconnection 16; the coverage area between the coupling electrode and the corresponding coupling field plate can be changed. The coupling effect of the coupling electrode on the corresponding coupling field plate changes the coupling potential of the corresponding coupling field plate, thereby adjusting the transverse electric field in the barrier layer 23 under the corresponding coupling field plate, and finally optimizing the device gate electrode 12 and the drain metal 10 The transverse electric field distribution between the devices improves the lateral withstand voltage capability of the device.

It should be noted that the number of coupled field plates is set according to actual needs.

In the high electron mobility transistor with a super field plate structure shown in FIG. 6, the number of adjustable field plates is three, namely: a first adjustable field plate 131 and a second adjustable field plate 132. And a third adjustable field plate 133;

A first adjustable capacitor negative electrode 151 is disposed above the first adjustable field plate 131, a second adjustable capacitor negative electrode 152 is disposed above the second adjustable field plate 132, and a third adjustable field plate 133 is disposed above The three adjustment capacitor negative electrode 153, the first adjustment capacitor negative electrode 151, the second adjustment capacitor negative electrode 152, the third adjustment capacitor negative electrode 153 and the source metal 7 are connected by a metal interconnection 16; as can be seen from FIG. The metal interconnections 16 between the negative electrodes of the respective adjustment capacitors are offset in the length direction, so that the first metal interconnection 16, the second metal interconnection 16 and the third metal interconnection 16 can be avoided. The field plate effects appear at the same width position and overlap each other, thereby alleviating the influence of the introduction of the metal interconnection 16 on the lateral withstand voltage capability of the device.

In other embodiments, the voids in the surface of the high electron mobility transistor device with the tunable field plate may be filled with an insulating dielectric layer.

The parasitic capacitance between the first adjustable field plate 131 and the barrier layer 23 is named C91, and the parasitic capacitance between the first adjustment capacitor negative electrode 151 and the first adjustable field plate 131 is named C101 due to The parasitic capacitances C91 and C101 are in series relationship. When the device is in the off voltage withstand state, the potential of the first adjustable field plate 131 will be determined by the size of the parasitic capacitances C91 and C101.

Therefore, the design of the first adjustable type field plate 131 and the first adjusting capacitor negative electrode 151 can adjust the size of the parasitic capacitances C91 and C101, thereby adjusting the coupling potential of the first adjustable field plate 131, and changing the first adjustable The effect of the field plate 131 on the transverse electric field in the lower barrier layer 23 is such that the barrier layer 23 under the first adjustable field plate 131 has a uniform transverse electric field distribution.

Similarly, the second adjustable field plate 132 and the barrier layer 23 under the third adjustable field plate 133 also have a uniform transverse electric field distribution, so that the high electron mobility transistor has a near-ideal lateral withstand voltage capability.

It should be noted that the above super field plate structure is applicable to other power semiconductor devices, such as a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), in addition to the high electron mobility transistor given in this embodiment. , horizontal insulated gate bipolar transistor (LIGBT) and high voltage diode.

Embodiment 5

A super field plate structure suitable for a power semiconductor device disclosed in one or more embodiments, comprising: an adjustable field plate and an adjustment capacitor, wherein, as a conventional deformation of the adjustment capacitor in the first embodiment, adjustment One of the electrodes of the capacitor is connected to the adjustable field plate, the other electrode of the regulating capacitor is realized by the P-well 4, and the P-well 4 is connected to the electrode whose power semiconductor device is always at the lowest potential.

Fig. 7 shows an example of the structure in which the super field plate structure of the present embodiment is applied to a lateral insulated gate bipolar transistor. The structure of the lateral insulated gate bipolar transistor includes: a P-type semiconductor substrate 1 on which an N-type drift region 3 and a P-type well 4 are provided, and an N-type contact is provided on the P-type well 4 The region 9, the P-type contact region 5 and the first dielectric layer 8-1 are provided with a P-type anode contact region 24 and a second dielectric layer 8-2 on the N-type drift region 3, and are connected on the P-type anode contact region 24. There is an anode metal 19, a cathode metal 18 is connected to the N-type contact region 9 and the P-type contact region 5, and a gate oxide layer 11 is provided over a portion of the N-type drift region 3 and a portion of the P-type well 4, and the gate oxide layer 11 One end of the gate oxide layer 11 abuts against the boundary of the N-type contact region 9, and the other end of the gate oxide layer 11 abuts the boundary of the second dielectric layer 8-2 (ie, the second field oxide layer), and a gate is provided on the surface of the gate oxide layer 11. Electrode 12 (polysilicon gate), and gate electrode 12 extends above second dielectric layer, in first dielectric layer 8-1 (ie, first field oxide layer), P-type contact region 5, N-type contact region 9, gate A third dielectric layer 25 is disposed above the electrode 12, the second field oxide layer, and the P-type anode contact region 24.

At least one adjustable field plate is respectively disposed on the surfaces of the second dielectric layer 8-2 and the third dielectric layer 25, and the adjusting capacitance corresponding to the adjustable field plate is respectively disposed on the surface of the first dielectric layer 8-1. The positive electrode uses a P-well 4 as a negative electrode for adjusting the capacitance. Each of the tunable field plates is connected to a corresponding modulating positive electrode via a heavily doped polysilicon or metal interconnect.

The adjustable field plate and the adjusting capacitor are all adjustable in size, and the number of adjustable field plates can be set according to actual needs, and the number of positive electrodes of the adjusting capacitor is equal to the total number of adjustable field plates.

In FIG. 7, two adjustable field plates are respectively disposed on the surface of the second dielectric layer 8-2 and the surface of the third dielectric layer 25, respectively: a first adjustable field plate 131 and a second adjustable field plate 132. a third adjustable field plate 133 and a fourth adjustable field plate 134; four adjustable capacitor positive electrodes are disposed on the surface of the first dielectric layer 8-1, respectively: a first regulating capacitor positive electrode 141, and a second adjustment The capacitor positive electrode 142, the third adjustment capacitor positive electrode 143, and the fourth adjustment capacitor positive electrode 144.

There is a parasitic capacitance between the first adjustable field plate 131 and the N-type drift region 3, which is named C121; the parasitic capacitance between the first regulating capacitor positive plate and the P-well 4 is named C141; The field plate 131 is connected to the first adjusting capacitor positive plate, and the parasitic capacitances C121 and C141 form a series relationship. Under the condition that the device is under withstand voltage, the N-type drift region 3 is at a high potential, and the P-type well 4 is at a low potential, according to The voltage division relationship of the series capacitor, the potential of the first adjustable field plate 131 is between the potentials of the N-type drift region 3 and the P-type well 4, and the potential of the first adjustable field plate 131 is affected by the parasitic capacitance C121 and The size of the C141 is affected.

Therefore, the size of the parasitic capacitances C121 and C141 can be adjusted by adjusting the sizes of the first adjustable field plate 131 and the first adjustment capacitor positive electrode 141, thereby adjusting the induced potential and the induced charge of the first adjustable field plate 131. The induced charge on the first tunable field plate 131 is balanced with the positive space charge in the N-type drift region 3, thereby obtaining a uniform surface transverse electric field distribution in the drift region below the first tunable field plate 131.

Similarly, by adjusting the size of the second adjustable field plate 132 and the second adjusting capacitor positive electrode 142, the induced potential and the induced charge of the second adjustable field plate 132 can be adjusted to be below the second adjustable field plate 132. A uniform surface transverse electric field distribution is obtained in the drift region.

Similarly, a uniform surface transverse electric field distribution can be obtained in the drift region below the third adjustable field plate 133 and the fourth adjustable field plate 134.

Therefore, the device parameters are designed so that different adjustable field plates have different potentials under the withstand voltage state, so that a uniform surface lateral electric field distribution is obtained in the entire drift region, and the lateral withstand voltage capability of the device is improved.

In still other embodiments, the voids in the surface of the laterally insulated gate bipolar transistor device with the tunable field plate may be filled with an insulating dielectric layer.

It should be noted that the above super field plate structure is applicable to other power semiconductor devices, such as a lateral double-diffused metal oxide semiconductor field effect transistor, in addition to the lateral insulated gate bipolar transistor given in this embodiment. LDMOS), high electron mobility transistor (HEMT) and high voltage diodes.

Embodiment 6

A potential floating type super field plate structure suitable for a power semiconductor device is disclosed in one or more embodiments, comprising: an adjustment capacitor and an adjustable field plate; the adjustable field plate is disposed on the dielectric layer of the power semiconductor device 8 s surface;

One of the electrodes of the adjustment capacitor is connected to the adjustable field plate, and the other electrode of the adjustment capacitor is used as the field plate potential adjustment electrode 26 of the power semiconductor device, the potential of which is provided by an external circuit; the field plate potential adjustment electrode 26 is disposed in the third medium The surface of layer 25.

As shown in FIG. 9, when the power semiconductor device is in a withstand voltage state, the external circuit supplies the field plate potential adjustment electrode 26 with the same potential as the low potential electrode of the power semiconductor device;

The size of the regulating capacitor in the potential floating type super field plate can change the sensing potential of the adjustable field plate in the potential floating type super field plate, thereby changing the electric field adjustment of the potential floating type super field plate in the drift region of the power semiconductor device. The size of the action enables a uniform lateral electric field distribution in the drift region of the power semiconductor device, so that the power semiconductor device can obtain the best lateral withstand voltage capability.

When the power semiconductor device is in an on state, the external circuit supplies the potential of the field plate potential adjustment electrode 26 to be higher than the potential of the lowest potential electrode of the power semiconductor device;

At this time, the field plate potential adjusting electrode 26 causes the adjustable field plate potential in the potential floating type super field plate to be higher than the potential of the drift region of the power semiconductor device by the coupling effect of the adjusting capacitance in the potential floating type super field plate, thereby The adjustable field plate in the potential floating super field plate induces additional carriers on the surface of the drift region of the power semiconductor device to improve the current capability of the power semiconductor device.

Fig. 8 shows an example of the structure in which the potential floating type super field plate structure of the present embodiment is applied to a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS).

It should be noted that, according to a conventional understanding by those skilled in the art, the field oxide layer of the lateral double-diffused metal oxide semiconductor field effect transistor is a dielectric layer, and therefore, the adjustable field plate in the super field plate can be set in the field. Oxide layer surface.

The structure of the lateral double-diffused metal oxide semiconductor field effect transistor includes: a P-type semiconductor substrate 1 on which an N-type drift region 3 and a P-type well 4 are disposed, and a P-type well 4 is provided The N-type source region 6 and the P-type contact region 5 are provided with an N-type contact region 9 (N-type drain region) and a field oxide layer on the N-type drift region 3, and a portion of the N-type drift region 3 and a portion of the P-type well 4 A gate oxide layer 11 is disposed thereon, and one end of the gate oxide layer 11 and the boundary of the N-type source region 6 are offset, and the other end of the gate oxide layer 11 is opposite to the boundary of the field oxide layer, and a gate electrode is disposed on the surface of the gate oxide layer 11. 12, and the gate electrode 12 extends above the field oxide layer, and is disposed on a surface of a portion of the P-type well 4, the P-type contact region 5, the N-type source region 6, the gate electrode 12, the N-type contact region 9, and a portion of the field oxide layer a third dielectric layer 25, a drain metal 10 is connected to the N-type contact region 9, and a source metal 7 is connected to the P-type contact region 5 and the N-type source region 6;

The surface of the field oxide layer (ie, the dielectric layer) is provided with at least two adjustable field plates, each of which is connected to one of the electrodes of the regulating capacitor, and the surface of the third dielectric layer 25 is provided with a regulating capacitor. One electrode, that is, the field plate potential adjusting electrode 26; in FIG. 8, the first oxide field plate 131, the second adjustable field plate 132, and the third adjustable field plate 133 are respectively disposed on the surface of the field oxide layer; The field plate potential adjusting electrode 26 completely covers the first metal sensing layer 271 and the second metal sensing layer respectively connected to the first adjustable field plate 131, the second adjustable field plate 132 and the third adjustable field plate 133. 272 and a third metal sensing layer 273.

It should be noted that the first adjustable field plate 131, the second adjustable field plate 132, the third adjustable field plate 133, the first metal sensing layer 271, the second metal sensing layer 272, and the third metal sensing The size of layer 273 can be adjusted separately depending on the design needs.

In still other embodiments, the voids in the surface of the lateral double-diffused metal oxide semiconductor field effect transistor device with the tunable field plate may be filled with an insulating dielectric layer.

It should be noted that the above super field plate structure is applicable to other power semiconductor devices, such as a lateral insulated gate bipolar transistor, in addition to the lateral double-diffused metal oxide semiconductor field effect transistor given in this embodiment. LIGBT), high electron mobility transistor (HEMT) and high voltage diodes.

Example 7

In one or more embodiments, a super field plate structure and a power semiconductor with a super field plate structure in Embodiment 1, Embodiment 2, Embodiment 3, Embodiment 4, Embodiment 5 or Embodiment 6 are disclosed. The specific application of the device.

In some embodiments, the field plate structure disclosed in the above embodiments and the power semiconductor device with the super field plate structure may be applied to the driving chip;

In still other embodiments, the above-described driver chip is applied to a power management chip, or a device such as a printer, an electric motor, and a flat panel display.

The above description of the specific embodiments of the present disclosure is not limited to the scope of the disclosure, and those skilled in the art should understand that those skilled in the art do not need to work creatively on the basis of the technical solutions of the present disclosure. Various modifications or variations that can be made are still within the scope of the disclosure.

Claims (16)

1. A super field plate structure suitable for a power semiconductor device, comprising: an adjustable field plate and an adjustment capacitor, wherein one of the electrodes of the adjustment capacitor is connected to the adjustable field plate or directly adopts an adjustable field The plate serves as an electrode for adjusting the capacitance, which is called a positive electrode; the other electrode of the adjustment capacitor is connected to the electrode which is always at the lowest potential in the power semiconductor device through a metal interconnection, which is called a negative electrode; the adjustable field plate setting On the surface of the dielectric layer of the power semiconductor device;

   By setting the size of the adjusting capacitor electrode, the size of the adjusting capacitor can be set, thereby adjusting the amount of induced charge and the sensing potential on the adjustable field plate, so that a uniform lateral electric field distribution is obtained in the drift region corresponding to the position of the super field plate structure.
2. A super field plate structure suitable for a power semiconductor device according to claim 1, wherein said super field plate is provided with at least two super field plates spaced apart in a length direction of the power semiconductor device to make the entire drift The zone obtains a uniform transverse electric field distribution.
3. A super field plate structure suitable for a power semiconductor device according to claim 2, wherein said adjustable field plate is intermittently disposed along a width direction of the power semiconductor device, and an adjustable field plate in a width direction is provided. Divided into a number of adjustable field plate units, each adjustable field plate unit is connected to the corresponding adjustment capacitor.
4. A super field plate structure suitable for a power semiconductor device according to claim 2, wherein the metal interconnection for connecting the adjustment capacitor and the electrode which is always at the lowest potential in the power semiconductor device is misaligned in the length direction arrangement.
5. A super field plate structure suitable for a power semiconductor device according to claim 1, wherein when the power semiconductor device has at least two dielectric layers, the surface of at least two dielectric layers of the power semiconductor device is adjustable The field plate, each adjustable field plate is connected to one of the electrodes of the regulating capacitor, and the other electrode of the adjusting capacitor is connected to the electrode of the power semiconductor device which is always at the lowest potential.
6. A lateral double-diffused metal oxide semiconductor field effect transistor comprising: a source metal, a field oxide layer and a drift region under the field oxide layer, further comprising: the power semiconductor device according to claim 1 The super field plate structure; specifically: setting a plurality of adjustable field plates on the surface of the field oxide layer, and setting a distance between two adjacent adjustable field plates;

   Each adjustable field plate is connected with an adjustment capacitor; the adjustable field plate is connected to the positive electrode of the adjustment capacitor, and the negative electrode of the adjustment capacitor is disposed above the positive electrode of the adjustment capacitor; the negative electrode of all the adjustment capacitors passes through the metal The interconnect is connected to the source metal;

   By setting the size of the positive and negative electrodes of the adjustable field plate and adjusting the capacitance, the amount of induced charge and the induced potential on the adjustable field plate can be adjusted, so that a uniform surface transverse electric field distribution is obtained in the drift region.
7. The lateral double-diffused metal oxide semiconductor field effect transistor according to claim 6, wherein in the direction of the source metal to the drain metal, the area covered by the positive and negative electrodes of the adjusting capacitor is sequentially Decrement.
8. The lateral double-diffused metal oxide semiconductor field effect transistor according to claim 6, wherein the gap between the source metal and the drain metal is filled with an insulating dielectric layer.
9. A high voltage diode comprising: a cathode metal, a field oxide layer and a drift region under the field oxide layer, further comprising: the super field plate structure suitable for the power semiconductor device according to claim 1; specifically: Providing a plurality of adjustable field plates on the surface of the field oxide layer, and setting a distance between two adjacent adjustable field plates;

   Each adjustable field plate is connected with an adjustment capacitor; the adjustable field plate is connected to the positive electrode of the adjustment capacitor, and the negative electrode of the adjustment capacitor is disposed above the positive electrode of the adjustment capacitor; the negative electrode of all the adjustment capacitors passes through the metal The interconnect is connected to the cathode metal;

   By setting the size of the positive and negative electrodes of the adjustable field plate and adjusting the capacitance, the induced potential and the amount of induced charge on the adjustable field plate can be adjusted, so that a uniform surface electric field distribution is obtained in the drift region.
10. The high voltage diode of claim 9 wherein the voids in the surface of the device are filled with an insulating dielectric layer.
11. A high electron mobility transistor, comprising: a substrate; a buffer layer disposed above the substrate; a channel layer disposed above the buffer layer; and a source metal, a drain metal, and a barrier above the channel layer a layer, and the source metal and the drain metal are located at two ends of the barrier layer; the dielectric layer and the gate electrode are disposed above the barrier layer; and the method further includes: the super device for the power semiconductor device according to claim 1. a field plate structure; specifically: a plurality of adjustable field plates are disposed on a surface of the dielectric layer between the gate electrode and the drain metal, and a distance is set between adjacent two adjustable field plates; each of the A coupling electrode is disposed above the modulation field plate, and all the coupling electrodes are connected to the source metal through the metal interconnection;

    By setting the coverage area between the coupling electrode and the corresponding adjustable field plate, the coupling effect of the coupling electrode on the corresponding coupling field plate can be changed, thereby changing the coupling potential of the corresponding coupling field plate, thereby adjusting the lower barrier of the corresponding coupling field plate. The transverse electric field in the layer finally optimizes the transverse electric field distribution between the gate electrode and the drain metal of the device, and improves the lateral withstand voltage capability of the device.
12. The high electron mobility transistor of claim 11 wherein the area of the coupling electrode and the corresponding tunable field plate that overlap each other in the direction of the source metal to the drain metal is successively decreased.
13. The high electron mobility transistor according to claim 11, wherein the metal interconnection between the coupling electrodes and the metal interconnection between the coupling electrode and the source electrode are spaced apart from each other by a set distance in the width direction .
14. A potential floating type super field plate structure suitable for a power semiconductor device, comprising: an adjustment capacitor and an adjustable field plate; the adjustable field plate is disposed on a surface of the dielectric layer of the power semiconductor device;

    One of the electrodes of the adjustment capacitor is connected to the adjustable field plate, and the other electrode of the adjustment capacitor is used as a field plate potential adjustment electrode of the power semiconductor device, and the potential thereof is provided by an external circuit;

    When the power semiconductor device is in a withstand voltage state, the external circuit supplies the field plate potential adjustment electrode with the same potential as the electrode having the lowest potential of the power semiconductor device;

    When the power semiconductor device is in an on state, the external circuit provides a potential for the field plate potential adjustment electrode that is higher than the potential of the lowest potential electrode of the power semiconductor device.
15. A potential floating type super field plate structure suitable for a power semiconductor device according to claim 14, wherein three potential floating type super are disposed on a surface of the lateral double-diffused metal oxide semiconductor field effect transistor dielectric layer The field plate structure; the electrode of the regulating capacitor as the field plate potential adjusting electrode of the power semiconductor device completely covers the other electrode.
16. A power management chip, characterized in that it comprises the super field plate structure according to any one of claims 1 to 5 or the potential floating type super field plate structure according to any one of claims 14-15.

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