CN108550628B - Power device with surface charge area structure - Google Patents
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- CN108550628B CN108550628B CN201810399461.9A CN201810399461A CN108550628B CN 108550628 B CN108550628 B CN 108550628B CN 201810399461 A CN201810399461 A CN 201810399461A CN 108550628 B CN108550628 B CN 108550628B
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- 239000000758 substrate Substances 0.000 claims abstract description 35
- 229910052681 coesite Inorganic materials 0.000 claims description 10
- 229910052906 cristobalite Inorganic materials 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052682 stishovite Inorganic materials 0.000 claims description 10
- 229910052905 tridymite Inorganic materials 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 16
- 230000005684 electric field Effects 0.000 abstract description 14
- 230000008569 process Effects 0.000 abstract description 14
- 239000004065 semiconductor Substances 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 5
- 238000011161 development Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 230000006872 improvement Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
Abstract
The invention provides a power device with a surface charge region structure, which comprises a P substrate I (1), a floating equipotential layer (4), a P substrate II (2) and a drift region (5) which are sequentially arranged from bottom to top; an N + drain region, a drain electrode (10), a gate electrode (12), a source electrode (11), an N + contact region, a P well (7) and a P + source region are arranged on the drift region (5); the top of the drift region (5) is positioned in the drift region, and a series of N + charge regions (6) which are transversely and equidistantly distributed are arranged in the drift region to form a surface charge region. The invention arranges a series of N with equal spacing on the surface of the drift region+The surface charge area structure of the charge area generates interface charges, so that an electric field in the charge area is enhanced, and the transverse withstand voltage of the device is improved; the interface charges simultaneously enhance the longitudinal electric field and the longitudinal withstand voltage of the buried layer, reduce the electric field near the drain electrode and prevent the surface of the device from being broken down too early; due to the adoption of the surface charge region structure with equal spacing N +, the process is simple and feasible, the process tolerance is good, and the method is compatible with the conventional CMOS process.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a power device with a surface charge region structure.
Background
A power semiconductor device is a semiconductor device that performs power processing, and is a main subject of power electronics research. Power electronics is emerging under the push of the development of power semiconductor devices, and has gradually matured over several decades of development. Power semiconductor devices have a very wide range of applications such as weaponry, power electronics, aerospace, flat panel display drives and other high and new technology industries. However, the lateral power device has a lateral channel, and the drain, the source and the gate are on the surface of the chip, so that the lateral power device is easy to integrate with a low-voltage signal through internal connection, and is widely applied to a power integrated circuit. Therefore, experts and scholars at home and abroad have paid great attention and intensive research on the situation.
The power semiconductor device comprises a power diode, a power switch device and a power integrated circuit. The power semiconductor technology is the foundation and core of the power electronic technology, and is the combination of the microelectronic technology and the power electronic technology. With the development of polysilicon and planar processes, various options are provided for the development of power devices. The key of the design of the power semiconductor device is to optimize the compromise among key characteristic parameters such as voltage resistance, on-state voltage drop, fast switching and the like. The improvement of power density and the reduction of loss have been the development of power semiconductor devices, and the former is closely related to the improvement of withstand voltage of power devices. The traditional means for improving the withstand voltage is complex in process and high in cost price, adopts a surface charge region structure, is simple and feasible in process and good in process tolerance, and is compatible with the conventional CMOS process.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a power device having a surface charge region structure, which is capable of generating interface charges, enhancing an electric field in the surface charge region, and improving withstand voltage.
In order to achieve the above and other related objects, the present invention provides a power device having a surface charge region structure, which includes a P substrate I1, a floating equipotential layer 4, a P substrate II2, and a drift region 5, which are sequentially arranged from bottom to top; n is arranged on the drift region 5+Drain region, drain electrode 10, gate electrode 12, source electrode 11, N+Contact region, P well 7 and P+A source region; a series of N distributed along the transverse direction at equal intervals are arranged on the top of the drift region 5 and in the drift region+Charge regions 6 form surface charge regions.
Preferably, the surface of the surface charge region is provided with SiO2A buried layer 8.
Preferably, the power device further comprises a surface substrate 9, said surface substrate being embeddedTo SiO2Buried layer in the substrate to make the surface substrate and SiO2The buried layer is flush.
Preferably, two of said N are adjacent+The concentration, height and width of the charge regions 6 are the same.
Preferably, the surface substrate 9 is a polysilicon oxide layer structure or an isolated structure of polycide, metal or similar oxide layer with similar structure.
Preferably, both the gate electrode 12 and the source electrode 11 are below the top of the drift region 5.
As described above, the power device having the surface charge region structure according to the present invention has the following advantages:
firstly, due to the arrangement of equal spacing N in the high-power device+Thus, a higher and more stable breakdown voltage is advantageously obtained.
Secondly, since the surface of the drift region is provided with a series of equally spaced N+The surface charge area structure of the charge area generates interface charges, so that an electric field in the charge area is enhanced, and the transverse withstand voltage of the device is improved. The interface charges simultaneously enhance the longitudinal electric field and the longitudinal withstand voltage of the buried layer, reduce the electric field near the drain electrode and prevent the surface of the device from being broken down prematurely. Due to the adoption of the surface charge region structure with equal spacing N +, the process is simple and feasible, the process tolerance is good, and the method is compatible with the conventional CMOS process.
Finally, in the power device with the surface charge region structure, the depletion effect of the drift region is increased in the surface substrate structure, the concentration of the drift region is improved, and the specific on-resistance is reduced.
Drawings
To further illustrate the description of the present invention, the following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings. It is appreciated that these drawings are merely exemplary and are not to be considered limiting of the scope of the invention. In the drawings:
FIG. 1 is a schematic structural diagram of a power device having a surface charge region structure according to the present invention;
fig. 2 is an equipotential line distribution diagram for a power device having a surface charge region structure.
The following are marked in the figure: 1. substrate I, 2, substrate II, 3, P type buried layer, 4, floating equipotential layer, 5, drift region, 6, N+Charge region, 7, P-well, 8, SiO2Buried layer, 9, surface substrate, 10, drain electrode, 11, source electrode, 12, gate electrode.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment provides a power device having a surface charge region structure, which includes a drift region 5, a P substrate II2, a floating equipotential layer 4, and a P substrate I1, which are sequentially arranged from top to bottom;
the drift region 5 is provided with an N + drain region, a drain electrode 10, a gate electrode 12, a source electrode 11, an N + contact region, a P well 7 and a P + source region. In this embodiment, the upper left portion of the drift region is recessed downward to form a recess, and the source electrode and the gate electrode are disposed at the bottom of the recess; the gate electrode 12 and the source electrode 11 are positioned lower than the drift region 5, and the drain electrode 10 is arranged at the upper right part of the drift region.
A series of N distributed along the transverse direction at equal intervals are arranged on the top of the drift region 5 and in the drift region+Charge regions 6 form surface charge regions.
Due to the arrangement of a series of equal intervals N on the drift region 5+ Charge region 6, and thus the surface charge region, is adjacent to N+Interface charges are generated in the charge area, so that the surface transverse electric field is enhanced, and the surface transverse withstand voltage is improved.
In order to increase the concentration of the drift region 5, reduce the specific on-resistance, and simultaneously enhance the surface lateral electric field to the maximum extent through the charge region, and improve the surface lateral withstand voltage, further, the P-type buried layer 3 is arranged on the P-substrate II2 to optimize the lateral electric field and improve the lateral withstand voltage. The P-type buried layer is partially located in the drift region 5, and the other part of the P-type buried layer is located in the P substrate II 2.
As an improvement to this embodiment, the surface of the surface charge region is provided with SiO2A buried layer 8. Further, the power device also comprises a surface substrate 9, wherein the surface substrate 9 is embedded in SiO2Buried layer in the substrate to make the surface substrate and SiO2The buried layer is flush.
Further, the surface substrate 9 adopts a polysilicon oxide layer structure or an isolated structure of polycide, metal or similar oxide layer with similar structure. By adopting the structure, the depletion effect of the drift region is increased, the concentration of the drift region is improved, and the specific on-resistance is reduced.
In summary, the power device with the surface charge region structure according to the present invention has the following advantages over the existing power devices: firstly, due to the arrangement of equal spacing N in the high-power device+And a charge region, thereby facilitating a higher and more stable breakdown voltage.
Secondly, further, the surface substrate 9 adopts a polysilicon oxide layer structure or an isolated structure of polycide, metal or similar oxide layers with similar structures. Because the surface is provided with a series of equal intervals N+The charge area forms a surface charge area structure, and the surface charge area generates interface charges, so that an electric field in the charge area is enhanced, and the transverse withstand voltage of the device is improved. The interface charges simultaneously enhance the longitudinal electric field and the longitudinal withstand voltage of the buried layer, reduce the electric field near the drain electrode and prevent the surface of the device from being broken down prematurely. Because of adopting the surface charge area structure with equal spacing N +, the process is simple and feasible, the process tolerance is better,compatible with conventional CMOS processes.
Finally, in the power device with the surface charge region structure, the depletion effect of the drift region is increased in the surface substrate structure, the concentration of the drift region is improved, and the specific on-resistance is reduced.
Example 1:
the power device with the surface charge region structure shown in fig. 1 includes a drift region 5, a substrate II2, a floating equipotential layer 4, and a substrate I1, which are arranged in sequence from top to bottom; an N + drain region, a drain electrode 10, a gate electrode 12, a source electrode 11, an N + contact region, a P well 7 and a P + source region are arranged on the drift region 5; n is arranged above the drift region 5+ Charge region 6, N+A surface substrate 9 is arranged above the charge region 6; said N is+The charge regions 6 are uniformly distributed in the lateral direction. The gate electrode 12 and the source electrode 11 are positioned lower than the surface substrate 9.
Due to the arrangement of a series of equal intervals N on the drift region 5+ Charge region 6, and thus the surface charge region, is adjacent to N+Interface charges are generated in the charge area, so that the surface transverse electric field is enhanced, and the surface transverse withstand voltage is improved.
In the present embodiment, the concentration of the drift region 5 is set to 1.2e 15. The concentration of the P-well was set to 3e 17. The concentrations of the N + drain region, the N + contact region and the P + source region are all set to be 1e19, and the concentrations of the P type buried layer 3 are all 1.55e 16. N is a radical of+The height of charge region 6 is 0.5um and the width is 0.5um, the equal spacing is 2um, and the charge region concentration is 3e 18.
When a high voltage is applied to the drain electrode 10 and the gate electrode 12, the source electrode 11, the substrate I1 and the surface substrate 9 are grounded, the device is in a reverse blocking state.
The equipotential line distribution of a power device having a surface charge region structure shown in fig. 2. The breakdown voltage of the structure provided by the invention reaches 608V, the breakdown voltage of the traditional bulk silicon structure is 373V, which is increased by 63%, equipotential lines are uniformly distributed by adopting the structure, the depletion effect of a drift region is increased, the concentration of the drift region is increased, the resistance is reduced, and the breakdown voltage is increased.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (3)
1. A power device with a surface charge region structure comprises a P substrate I (1), a floating equipotential layer (4), a P substrate II (2) and a drift region (5) which are sequentially arranged from bottom to top; n is arranged on the drift region (5)+A drain region, a drain electrode (10), a gate electrode (12), a source electrode (11), and N+Contact region, P-well (7) and P+A source region;
characterized in that a series of N distributed along the transverse direction at equal intervals are arranged on the top of the drift region (5) and in the drift region+A charge region (6) forming a surface charge region; the surface of the surface charge region is provided with SiO2A buried layer (8), the power device further comprising a surface substrate (9) embedded in SiO2In the buried layer, the surface of the surface substrate and SiO2The buried layer is flush, and the surface substrate (9) adopts a polysilicon oxide layer structure.
2. The power device of claim 1, wherein two adjacent N of said N-type surface charge regions are adjacent to each other+The concentration, height and width of the charge regions (6) are the same.
3. A power device with a surface charge region structure according to claim 1, characterized in that the gate electrode (12) and the source electrode (11) are both below the top of the drift region (5).
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| CN201810399461.9A CN108550628B (en) | 2018-04-28 | 2018-04-28 | Power device with surface charge area structure |
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| CN201810399461.9A CN108550628B (en) | 2018-04-28 | 2018-04-28 | Power device with surface charge area structure |
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| CN108550628A CN108550628A (en) | 2018-09-18 |
| CN108550628B true CN108550628B (en) | 2021-10-22 |
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| CN107863379A (en) * | 2017-10-30 | 2018-03-30 | 济南大学 | A kind of N-type LDMOS structure with field plate supplementary doping area |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020070394A1 (en) * | 2000-12-08 | 2002-06-13 | John Lin | Using segmented N-type channel stop to enhance the SOA (safe-operating area) of LDMOS transistors |
| US9437693B2 (en) * | 2014-12-17 | 2016-09-06 | Freescale Semiconductor, Inc. | Device having a shield plate dopant region and method of manufacturing same |
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2018
- 2018-04-28 CN CN201810399461.9A patent/CN108550628B/en active Active
Patent Citations (8)
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| CN101375402A (en) * | 2005-12-21 | 2009-02-25 | 丰田自动车株式会社 | Transverse SOI semiconductor devices and manufacturing method thereof |
| CN101477999A (en) * | 2009-01-19 | 2009-07-08 | 电子科技大学 | SOI voltage resistant structure having interface charge island for power device |
| JP2011049457A (en) * | 2009-08-28 | 2011-03-10 | Tokai Rika Co Ltd | High breakdown-voltage semiconductor device and method of manufacturing the same |
| CN103413830A (en) * | 2013-08-16 | 2013-11-27 | 电子科技大学 | Laterally high-voltage MOSFET and manufacturing method thereof |
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