CN106057904B - A kind of germanium base SiGe drop field layer LDMOS device structure - Google Patents

A kind of germanium base SiGe drop field layer LDMOS device structure Download PDF

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CN106057904B
CN106057904B CN201610624781.0A CN201610624781A CN106057904B CN 106057904 B CN106057904 B CN 106057904B CN 201610624781 A CN201610624781 A CN 201610624781A CN 106057904 B CN106057904 B CN 106057904B
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layer
germanium
sige
type doping
drift
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CN106057904A (en
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王勇
王瑛
丁超
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Guangdong University of Technology
Dongguan South China Design and Innovation Institute
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Guangdong University of Technology
Dongguan South China Design and Innovation Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys

Abstract

The invention discloses a kind of germanium base SiGe drop field layer LDMOS device structure, structure is followed successively by：One p-type germanium channel layer；The germanium drift layer of one n-type doping；The germanium ohmic contact layer of one heavy N-type doping；The grown layer of one SiGe and sige spacer is as drift layer；The SiGe drift drop field layer of one p-type doping；One depth reaches the grid slot structure of p-type germanium channel layer；The one oxide isolation layer formed in grid slot；One barrier metal layer formed in grid slot；One source and drain metal electrodes formed in source and drain areas.

Description

A kind of germanium base SiGe drop field layer LDMOS device structure
Technical field
The invention belongs to microelectronic fields, and in particular to a kind of Ge-based semiconductor LDMOSFET device architecture.
Background technique
Integrated circuit based on silicon base CMOS technology is quickly grown, and silicon substrate LDMOSFET device is in high-frequency and high-voltage device sum aggregate It is also gradually expanded at the application of circuit field.But there is still a need for into one for the radio-frequency performance of silicon substrate LDMOSFET device, voltage endurance capability Step is promoted.Now with the continuous development of the Germanium semiconductor material gradually application in silicon base CMOS technology and epitaxy technology, germanium Base MOSFET element characteristic achieves major progress, inevitable if Germanium semiconductor material is introduced into silicon substrate LDMOSFET device There can be huge help to the radio-frequency performance and voltage endurance capability for improving device.Using germanium as channel material, using SiGe as drift The LDMOSFET device ratio for moving layer will bring huge performance boost to LDMOSFET device.
Summary of the invention
It is an object of the invention to propose a kind of device using silicon germanium material as germanium base LDMOSFET device drop field layer Structure, using the band offsets of SiGe and silicon materials come so that Potential Distributing of the device between drain-gate changes.To mention The breakdown voltage of high device, and improve the radiofrequency characteristics of device.
The present invention provides a kind of germanium base SiGe drop field layer LDMOS device structure, structure is followed successively by
One p-type germanium channel layer；
The germanium drift layer of one n-type doping；
The germanium ohmic contact layer of one heavy N-type doping；
The grown layer of one SiGe and sige spacer is as drift layer；
The SiGe drift drop field layer of one p-type doping；
One depth reaches the grid slot structure of p-type germanium channel layer；
The one oxide isolation layer formed in grid slot；
One barrier metal layer formed in grid slot；
One source and drain metal electrodes formed in source and drain areas.
A kind of germanium base SiGe drop field layer LDMOS device structure according to this programme, it is characterised in that LDMOSFET device The drift layer of part is spaced apart from each other the epitaxial film materials of growth using SiGe and germanium material.
A kind of germanium base SiGe drop field layer LDMOS device structure according to this programme, it is characterised in that LDMOSFET device Part uses the silicon germanium material of p-type doping as drop field layer.
A kind of germanium base SiGe drop field layer LDMOS device structure according to this programme, it is characterised in that the germanium of n-type doping Drift layer thickness is 20 nanometers.
A kind of germanium base SiGe drop field layer LDMOS device structure according to this programme, it is characterised in that field layer drops in SiGe It is 30 nanometers.
A kind of germanium base SiGe drop field layer LDMOS device structure according to this programme, it is characterised in that heavy N-type doping Germanium ohmic contact layer with a thickness of 50 nanometers, doping concentration is 5 × 1018cm-3。
Beneficial effect
The present invention, as drift layer and drop field layer, using concave grid groove structure, is reduced in device fabrication processes using SiGe To the dependence of epitaxial material.The LDMOSFET device of production, structure and process are simple.Convenient for manufacture.It is floated using SiGe bilayer The drift speed of electronics can effectively be increased by moving layer structure, and the channel layer using Germanium semiconductor material as device improves ditch Road mobility while improving the radiofrequency characteristics of device, improves the voltage endurance capability of device.
Detailed description of the invention
A kind of Fig. 1 germanium base SiGe drop field layer LDMOS device structure proposed by the present invention.
Specific embodiment
Below with reference to Fig. 1, the present invention is described in detail.
A kind of germanium base SiGe drop field layer LDMOS device structure that the present embodiment proposes, structure are followed successively by
One p-type germanium channel layer (101)；
The germanium drift layer (102) of one n-type doping；
The germanium ohmic contact layer (103) of one heavy N-type doping；
The grown layer of one SiGe and sige spacer is as drift layer (102-2)；
The SiGe drift drop field layer (104) of one p-type doping；
One depth reaches the grid slot structure of p-type germanium channel layer；
The one oxide isolation layer (105) formed in grid slot；
One barrier metal layer (106) formed in grid slot；
One source and drain metal electrodes (107) formed in source and drain areas.
In the present embodiment, the drift layer of LDMOSFET device is spaced apart from each other using SiGe (102-2) with germanium (102) material The epitaxial film materials of growth.
In the present embodiment, the silicon germanium material that LDMOSFET device uses p-type doping is used as drop field layer, and doping concentration is 5×1017cm-3。
In the present embodiment, the germanium drift layer (102-2) of n-type doping is with a thickness of 20 nanometers.
In the present embodiment, SiGe is by field layer (104) with a thickness of 30 nanometers.
In the present embodiment, the germanium ohmic contact layer (103) of heavy N-type doping with a thickness of 50 nanometers, doping concentration is 5 × 1018cm-3。

Claims (5)

1. a kind of germanium base SiGe drop field layer LDMOS device structure, structure are followed successively by
One p-type germanium channel layer；
The germanium drift layer of one n-type doping；
The germanium ohmic contact layer of one heavy N-type doping；
The grown layer of one SiGe and sige spacer is as drift layer；
The SiGe drift drop field layer of one p-type doping；
One depth reaches the grid slot structure of p-type germanium channel layer；
The one oxide isolation layer formed in grid slot；
One barrier metal layer formed in grid slot；
One source and drain metal electrodes formed in source and drain areas；The overhead surface of the p-type germanium channel layer connects the n-type doping Germanium drift layer, the overhead surface of the germanium drift layer of the n-type doping connects the germanium ohmic contact layer of the heavy N-type doping, described One end of the germanium ohmic contact layer of heavy N-type doping connects the SiGe drift drop field layer of the p-type doping.
2. a kind of germanium base SiGe drop field according to claim 1 layer LDMOS device structure, it is characterised in that LDMOSFET device The drift layer of part is spaced apart from each other the epitaxial film materials of growth using SiGe and germanium material.
3. a kind of germanium base SiGe drop field according to claim 1 layer LDMOS device structure, it is characterised in that n-type doping Germanium drift layer thickness is 20 nanometers.
4. a kind of germanium base SiGe drop field according to claim 1 layer LDMOS device structure, it is characterised in that field layer drops in SiGe It is 30 nanometers.
5. a kind of germanium base SiGe drop field according to claim 1 layer LDMOS device structure, it is characterised in that heavy N-type doping Germanium ohmic contact layer with a thickness of 50 nanometers, doping concentration is 5 × 1018cm-3。
CN201610624781.0A 2016-07-29 2016-07-29 A kind of germanium base SiGe drop field layer LDMOS device structure Active CN106057904B (en)

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Publication number Priority date Publication date Assignee Title
CN106783941A (en) * 2016-11-29 2017-05-31 东莞市广信知识产权服务有限公司 A kind of silicon substrate SiGe drift layer LDMOSFET device architectures
CN117153888B (en) * 2023-10-30 2024-02-02 粤芯半导体技术股份有限公司 Semiconductor device and method for manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6768180B2 (en) * 2002-04-04 2004-07-27 C. Andre T. Salama Superjunction LDMOST using an insulator substrate for power integrated circuits
CN102097389A (en) * 2011-01-12 2011-06-15 深圳市联德合微电子有限公司 LDMOS (laterally diffused metal oxide semiconductor), semiconductor device integrated with same and manufacturing method thereof
CN102522428A (en) * 2011-12-21 2012-06-27 成都成电硅海科技股份有限公司 High-voltage LDMOS (laterally diffused metal oxide semiconductor) structure
CN103094350A (en) * 2013-02-07 2013-05-08 南京邮电大学 High voltage lateral double diffused MOSFET (LDMOS) device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6768180B2 (en) * 2002-04-04 2004-07-27 C. Andre T. Salama Superjunction LDMOST using an insulator substrate for power integrated circuits
CN102097389A (en) * 2011-01-12 2011-06-15 深圳市联德合微电子有限公司 LDMOS (laterally diffused metal oxide semiconductor), semiconductor device integrated with same and manufacturing method thereof
CN102522428A (en) * 2011-12-21 2012-06-27 成都成电硅海科技股份有限公司 High-voltage LDMOS (laterally diffused metal oxide semiconductor) structure
CN103094350A (en) * 2013-02-07 2013-05-08 南京邮电大学 High voltage lateral double diffused MOSFET (LDMOS) device

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Denomination of invention: A germanium-based silicon germanium drop field layer LDMOS device structure

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