CN106783941A - A kind of silicon substrate SiGe drift layer LDMOSFET device architectures - Google Patents
A kind of silicon substrate SiGe drift layer LDMOSFET device architectures Download PDFInfo
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- CN106783941A CN106783941A CN201611076150.6A CN201611076150A CN106783941A CN 106783941 A CN106783941 A CN 106783941A CN 201611076150 A CN201611076150 A CN 201611076150A CN 106783941 A CN106783941 A CN 106783941A
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- silicon
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 43
- 239000010703 silicon Substances 0.000 title claims abstract description 43
- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 10
- 108091006146 Channels Proteins 0.000 claims abstract description 7
- 230000008021 deposition Effects 0.000 claims abstract description 6
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 150000002500 ions Chemical class 0.000 claims abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of silicon substrate SiGe drift layer LDMOSFET device architectures, it includes：One P-type silicon base semiconductor channel layer, the silicon-based semiconductor layer of one n-type doping, the silicon-based semiconductor contact layer of one heavy N-type doping, the silicon germanium semiconductor drift layer of one n-type doping, one depth to P-type channel layer 100 nanometers long of grid groove, a silicon oxide dielectric layer deposited in the grid groove, a grid metal deposited on the dielectric layer, the source and drain areas that two heavy N-types formed by ion implanting are adulterated, two source-drain electrodes in source and drain areas deposition.
Description
Technical field
The invention belongs to microelectronic, and in particular to a kind of silicon substrate SiGe drift layer LDMOSFET device architectures.
Background technology
Integrated circuit based on silicon base CMOS technology quickly grows, and silicon substrate LDMOSFET devices are in high-frequency and high-voltage device and collection
Application into circuit field is also progressively expanded.But the radio-frequency performance of silicon substrate LDMOSFET devices, voltage endurance capability are stilled need into one
Step lifting.Now with continuing to develop for the application gradually in silicon base CMOS technology of silicon germanium semiconductor material and epitaxy technology,
Silicon germanium semiconductor material is introduced into silicon substrate LDMOSFET devices, will necessarily be had to the radio-frequency performance and voltage endurance capability that improve device
Huge help.The LDMOSFET devices of SiGe drift layer are wherein important application directions.
The content of the invention
It is an object of the invention to propose a kind of device architecture of application silicon germanium material as LDMOSFET device drift layers.
The main drift layer for using silicon germanium material as device, improves drift layer electron mobility, improves the radiofrequency characteristicses of device.
Silicon substrate SiGe drift layer LDMOSFET device architectures proposed by the present invention, it includes：
One P-type silicon base semiconductor channel layer；
The silicon semiconductor drift layer of one n-type doping；
The silicon-based semiconductor contact layer of one heavy N-type doping；
The silicon germanium semiconductor drift layer of one n-type doping；
100 nanometer long of grid groove of one depth to P-type channel layer；
One silicon oxide dielectric layer deposited in the grid groove；
One grid metal deposited on the dielectric layer；
The source and drain areas that two heavy N-types formed by ion implanting are adulterated；
Two source-drain electrodes in source and drain areas deposition.
A kind of silicon substrate SiGe drift layer LDMOSFET device architectures according to this programme, it is characterised in that p-type is mixed
The doping concentration of miscellaneous semiconductor channel layer is 3 × 1017cm-3。
A kind of silicon substrate SiGe drift layer LDMOSFET device architectures according to this programme, it is characterised in that N-type is mixed
The thickness of miscellaneous silicon semiconductor drift layer is 20 nanometers, and doping concentration is 7 × 1017cm-3。
A kind of silicon substrate SiGe drift layer LDMOSFET device architectures according to this programme, it is characterised in that N-type is mixed
The thickness of miscellaneous silicon germanium semiconductor drift layer is 30 nanometers, and doping concentration is 3 × 1017cm-3。
A kind of silicon substrate SiGe drift layer LDMOSFET device architectures according to this programme, it is characterised in that grid metal
A part of silicon germanium semiconductor layer is covered, the length of covering is 50-100 nanometers.
A kind of silicon substrate SiGe drift layer LDMOSFET device architectures according to this programme, it is characterised in that grid metal
Cover the silicon-based semiconductor contact layer of a part of heavy N-type doping；, the length of covering is 30-50 nanometers.
Beneficial effect
The present invention, as drift layer, using concave grid groove structure, is reduced in device fabrication processes to extension material using SiGe
The dependence of material.The LDMOSFET devices of making, structure and operation are simple.It is easy to manufacture.Using silicon and SiGe bilayer drift layer
Structure can effectively increase the drift speed of electronics, while improving the radiofrequency characteristicses of device, improve the voltage endurance capability of device.
Brief description of the drawings
Fig. 1 SiGe drift layer LDMOSFET device architectures proposed by the present invention
Specific embodiment
With reference to Fig. 1, the present invention is described in detail.
The silicon substrate SiGe drift layer LDMOSFET device architectures that the present embodiment is proposed, it includes：
One P-type silicon base semiconductor channel layer (101)；
The silicon semiconductor drift layer (102) of one n-type doping；
The silicon-based semiconductor contact layer (103) of one heavy N-type doping；
The silicon germanium semiconductor drift layer (104) of one n-type doping；
100 nanometer long of grid groove of one depth to P-type channel layer；
One silicon oxide dielectric layer (105) deposited in the grid groove；
One grid metal (106) deposited on the dielectric layer；
The source and drain areas (107) that two heavy N-types formed by ion implanting are adulterated；
Two source-drain electrodes (108) in source and drain areas deposition.
In the present embodiment, epitaxial material all can be using the method for high vacuum chemical gas deposition be deposited on once
Cross on the silicon chip of comprehensive cleaning, be doped using doping pattern in situ.
In the present embodiment, the doping concentration of the semiconductor channel layer of p-type doping is 3 × 1017cm-3。
In the present embodiment, the thickness of the silicon semiconductor drift layer (102) of n-type doping be 20 nanometers, doping concentration be 7 ×
1017cm-3。
In the present embodiment, the thickness of the silicon germanium semiconductor drift layer (104) of n-type doping is 30 nanometers, and doping concentration is 3
×1017cm-3。
In the present embodiment, grid metal covers a part of silicon germanium semiconductor layer, and the length of covering is 50-100 nanometers.
In the present embodiment, grid metal covers the silicon-based semiconductor contact layer of a part of heavy N-type doping；, the length of covering
Spend is 30-50 nanometers.
In the present embodiment, the grid groove on silicon-based semiconductor is formed by the method for etching.
In the present embodiment, the deposition of gate medium (105) is deposited using the method for ald, it is ensured that dielectric material
Spreadability.
Claims (6)
1. a kind of silicon substrate SiGe drift layer LDMOSFET device architectures, it includes：
One P-type silicon base semiconductor channel layer；
The silicon semiconductor drift layer of one n-type doping；
The silicon-based semiconductor contact layer of one heavy N-type doping；
The silicon germanium semiconductor drift layer of one n-type doping；
100 nanometer long of grid groove of one depth to P-type channel layer；
One silicon oxide dielectric layer deposited in the grid groove；
One grid metal deposited on the dielectric layer；
The source and drain areas that two heavy N-types formed by ion implanting are adulterated；
Two source-drain electrodes in source and drain areas deposition.
2. a kind of silicon substrate SiGe drift layer LDMOSFET device architectures according to claim 1, it is characterised in that p-type is adulterated
Semiconductor channel layer doping concentration be 3 × 1017cm-3。
3. a kind of silicon substrate SiGe drift layer LDMOSFET device architectures according to claim 1, it is characterised in that n-type doping
Silicon semiconductor drift layer thickness be 20 nanometers, doping concentration be 7 × 1017cm-3。
4. a kind of silicon substrate SiGe drift layer LDMOSFET device architectures according to claim 1, it is characterised in that n-type doping
Silicon germanium semiconductor drift layer thickness be 30 nanometers, doping concentration be 3 × 1017cm-3。
5. a kind of silicon substrate SiGe drift layer LDMOSFET device architectures according to claim 1, it is characterised in that grid metal
A part of silicon germanium semiconductor layer is covered, the length of covering is 50-100 nanometers.
6. a kind of silicon substrate SiGe drift layer LDMOSFET device architectures according to claim 1, it is characterised in that grid metal
Cover the silicon-based semiconductor contact layer of a part of heavy N-type doping；, the length of covering is 30-50 nanometers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611076150.6A CN106783941A (en) | 2016-11-29 | 2016-11-29 | A kind of silicon substrate SiGe drift layer LDMOSFET device architectures |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611076150.6A CN106783941A (en) | 2016-11-29 | 2016-11-29 | A kind of silicon substrate SiGe drift layer LDMOSFET device architectures |
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| Publication Number | Publication Date |
|---|---|
| CN106783941A true CN106783941A (en) | 2017-05-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201611076150.6A Pending CN106783941A (en) | 2016-11-29 | 2016-11-29 | A kind of silicon substrate SiGe drift layer LDMOSFET device architectures |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446967A (en) * | 2010-09-30 | 2012-05-09 | 北京大学 | Silicon-on-insulator laterally diffused metal oxide semiconductor (SOI LDMOS) device containing composite drift region |
| US20120248528A1 (en) * | 2002-10-03 | 2012-10-04 | Wilson Peter H | Trench-gate ldmos structures |
| CN102903748A (en) * | 2011-07-25 | 2013-01-30 | 中芯国际集成电路制造(上海)有限公司 | Lateral double-diffused metal oxide semiconductor (DMOS) and manufacturing method thereof |
| CN104752500A (en) * | 2013-12-25 | 2015-07-01 | 上海华虹宏力半导体制造有限公司 | Radio-frequency LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and technological method |
| CN106033777A (en) * | 2015-03-20 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | LDMOS device and forming method thereof |
| CN106057904A (en) * | 2016-07-29 | 2016-10-26 | 东莞华南设计创新院 | Germanium-based silicon germanium reduced-field layer LDMOS device structure |
-
2016
- 2016-11-29 CN CN201611076150.6A patent/CN106783941A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120248528A1 (en) * | 2002-10-03 | 2012-10-04 | Wilson Peter H | Trench-gate ldmos structures |
| CN102446967A (en) * | 2010-09-30 | 2012-05-09 | 北京大学 | Silicon-on-insulator laterally diffused metal oxide semiconductor (SOI LDMOS) device containing composite drift region |
| CN102903748A (en) * | 2011-07-25 | 2013-01-30 | 中芯国际集成电路制造(上海)有限公司 | Lateral double-diffused metal oxide semiconductor (DMOS) and manufacturing method thereof |
| CN104752500A (en) * | 2013-12-25 | 2015-07-01 | 上海华虹宏力半导体制造有限公司 | Radio-frequency LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and technological method |
| CN106033777A (en) * | 2015-03-20 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | LDMOS device and forming method thereof |
| CN106057904A (en) * | 2016-07-29 | 2016-10-26 | 东莞华南设计创新院 | Germanium-based silicon germanium reduced-field layer LDMOS device structure |
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Application publication date: 20170531 |