CN102446967A - Silicon-on-insulator laterally diffused metal oxide semiconductor (SOI LDMOS) device containing composite drift region - Google Patents
Silicon-on-insulator laterally diffused metal oxide semiconductor (SOI LDMOS) device containing composite drift region Download PDFInfo
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- CN102446967A CN102446967A CN2010105040045A CN201010504004A CN102446967A CN 102446967 A CN102446967 A CN 102446967A CN 2010105040045 A CN2010105040045 A CN 2010105040045A CN 201010504004 A CN201010504004 A CN 201010504004A CN 102446967 A CN102446967 A CN 102446967A
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Abstract
The invention discloses a silicon-on-insulator laterally diffused metal oxide semiconductor (SOI LDMOS) device containing a composite drift region. The device sequentially comprises a grid oxide layer, a top silicon layer, a buried oxide layer and a bottom silicon layer from top to bottom, wherein the top silicon layer contains the composite drift region; and the composite drift region contains a first drift region and a second drift region, wherein the first drift region is adjacent to a channel region and is encircled by the second drift region. By adopting the composite drift region in the device, the maximum electric field value of the drift region close to one end of the channel, and the breakdown voltage value is improved; and because the first drift region is thinner than the top silicon layer, the additional value of the on resistance caused by the first drift region is reduced, and the on conduction property is improved.
Description
Technical field
The present invention relates to the high-voltage semi-conductor device field, particularly a kind of SOI LDMOS device that contains compound drift region.
Background technology
LDMOS (Laterally Diffused Metal Oxide Semiconductor; LDMOS) technology; It is a kind of high-voltage semi-conductor device that is widely used in fields such as RF base station, PDP (Plasma Display Panel, plasma panel) display driver and automotive electronics.With traditional I GBT (Insulated Gate BipolarTransistor; Insulated gate bipolar transistor) compares; It has higher response speed and lower leakage current, and it is integrated to help technology more as planar device, however the increase that also brings ON resistance simultaneously.
SOI (Silicon-On-Insulator; Silicon-on-insulator) technology and the isolation characteristic that combines to have improved greatly device of LDMOS; Greatly reduce low-voltage control circuit and the phase mutual interference between the high voltage integrated circuit in the high voltage integrated circuit; Reduce parasitic capacitance simultaneously, improved operating frequency and anti-irradiation ability.Traditional SOI LDMOS device architecture is as shown in Figure 1.Wherein, A1 is that raceway groove contact zone, A2 are that source contact area, A3 are drain contact region.Yet present SOI LDMOS device has following defective: if improve its puncture voltage, will certainly increase its ON state pressure drop greatly.
Summary of the invention
The technical problem that (one) will solve
The technical problem that the present invention will solve is: how a kind of SOI LDMOS device is provided, in the puncture voltage that improves device, to increase the ON state pressure drop of device less as far as possible.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of SOI LDMOS device that contains compound drift region, said device comprises grid oxide layer, top layer silicon, oxygen buried layer and bottom silicon from top to bottom successively.
Wherein, contain first drift region in the said top layer silicon, the thickness of said first drift region is less than the thickness of said top layer silicon.
Wherein, said top layer silicon comprises channel region and compound drift region, and said compound drift region comprises said first drift region and second drift region, and said first drift region surrounds in abutting connection with said channel region and by said second drift region.
Wherein, said first drift region is the intrinsic region.
Wherein, said bottom silicon is P substrate or N substrate.
Wherein, said channel region is the P channel region, and correspondingly, said second drift region is N type drift region; Perhaps, said channel region is the N channel region, and correspondingly, said second drift region is P type drift region.
(3) beneficial effect
The present invention has reduced the maximum field value of drift region near raceway groove one end through in device architecture, adopting compound drift region, has improved breakdown voltage value; And, improved the ON state on state characteristic because the thickness of first drift region (intrinsic region) has lowered ON resistance less than top layer silicon thickness.And simultaneously, there is identical puncture voltage lifting effect the first thin drift region with first drift region of the whole top layer silicon of break-through because the drift region near the maximum field value of raceway groove one end and breakdown point near the surface.
Description of drawings
Fig. 1 is a traditional SOI LDMOS device architecture sketch map;
Fig. 2 is the SOI LDMOS device architecture sketch map of the embodiment of the invention;
Fig. 3 is the OFF state breakdown characteristic figure of SOI LDMOS device of SOILDMOS device and the embodiment of the invention of traditional SOI LDMOS device, the whole top layer silicon of the first drift region break-through;
Fig. 4 is the ON state on state characteristic curve chart of SOI LDMOS device of SOILDMOS device and the embodiment of the invention of traditional SOI LDMOS device, the whole top layer silicon of the first drift region break-through.
Embodiment
For making the object of the invention, content and advantage clearer, will combine accompanying drawing that embodiment of the present invention is done to describe in detail further below.
As shown in Figure 2; The SOI LDMOS device that contains compound drift region of the embodiment of the invention; Comprise grid oxide layer, top layer silicon, oxygen buried layer and bottom silicon (being the substrate zone among Fig. 2) from top to bottom successively; Wherein said top layer silicon comprises channel region and compound drift region, and said compound drift region comprises first drift region and second drift region, and the thickness of first drift region wherein is less than the thickness of top layer silicon.
Said channel region is P channel region (being the channel region that the P type mixes); Correspondingly; Said second drift region is N type drift region (being the drift region that the N type mixes), and the doping of source contact area A2, drain contact region A3 and raceway groove contact zone A1 is respectively the heavy doping of N type, the heavy doping of N type and the heavy doping of P type; Perhaps, said channel region is the N channel region, and correspondingly, said second drift region is P type drift region, and the doping of source contact area A2, drain contact region A3 and raceway groove contact zone A1 is respectively the heavy doping of P type, the heavy doping of P type and the heavy doping of N type.
Above-mentioned first drift region is intrinsic region (intrinsic region), i.e. doped region not.Can know by Gauss theorem, because the intrinsic region does not have the existence of space charge, the increase that can not bring electric field strength, electric field strength is tending towards even distribution, has avoided the appearance of electric field kurtosis.Compare with traditional devices; The structure that the present invention proposes contains the compound drift region of first drift region (intrinsic region) through employing; Reduced the maximum field value of drift region near raceway groove one end; And the maximum field value in zone often is exactly the maximum field value of entire device, also be the factor of decision device electric breakdown strength, so this structure can improve the breakdown voltage value of device.And compare with the structure in the whole top layer silicon of intrinsic region break-through zone, the structure that the present invention proposes has realized lower ON resistance because the thickness of first drift region (intrinsic region) is less, has improved the ON state on state characteristic.And simultaneously; The thickness of intrinsic region does not influence the puncture voltage lifting effect that it brings; Because the drift region appears near the surface near the maximum field value of raceway groove one end, the structure that the present invention proposes is as far as comparing the inhibitory action that equivalence is arranged near the electric field value of surface and the SOI LDMOS device of the whole top layer silicon of intrinsic region break-through.
Above-mentioned advantage of the present invention can be found out through Fig. 3,4 result.Among Fig. 3; The solid line of band square is the OFF state breakdown characteristic of traditional SOI LDMOS device (structure 1); The solid line of band circle is the OFF state breakdown characteristic of SOI LDMOS device of the present invention (structure 2), and the solid line of band corner block is the OFF state breakdown characteristic of the SOI LDMOS device (structure 3) of the whole top layer silicon of intrinsic region break-through.Among Fig. 4; The solid line of band circle is the ON state on state characteristic curve of traditional SOI LDMOS device (structure 1); The ON state on state characteristic curve of the solid line SOI LDMOS of the present invention device (structure 2) of band corner block, the solid line of band square is the ON state on state characteristic curve of the SOI LDMOS device (structure 3) of the whole top layer silicon of intrinsic region break-through.
Above execution mode only is used to explain the present invention; And be not limitation of the present invention; The those of ordinary skill in relevant technologies field under the situation that does not break away from the spirit and scope of the present invention, can also be made various variations and modification; Therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (6)
1. a SOI LDMOS device that contains compound drift region is characterized in that said device comprises grid oxide layer, top layer silicon, oxygen buried layer and bottom silicon from top to bottom successively.
2. the SOI LDMOS device that contains compound drift region as claimed in claim 1 is characterized in that contain first drift region in the said top layer silicon, the thickness of said first drift region is less than the thickness of said top layer silicon.
3. the SOI LDMOS device that contains compound drift region as claimed in claim 2; It is characterized in that; Said top layer silicon comprises channel region and compound drift region; Said compound drift region comprises said first drift region and second drift region, and said first drift region surrounds in abutting connection with said channel region and by said second drift region.
4. the SOI LDMOS device that contains compound drift region as claimed in claim 3 is characterized in that said first drift region is the intrinsic region.
5. the SOI LDMOS device that contains compound drift region as claimed in claim 1 is characterized in that said bottom silicon is P substrate or N substrate.
6. like each described SOI LDMOS device that contains compound drift region of claim 1～5, it is characterized in that said channel region is the P channel region, correspondingly, said second drift region is N type drift region; Perhaps, said channel region is the N channel region, and correspondingly, said second drift region is P type drift region.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035731A (en) * | 2012-12-11 | 2013-04-10 | 上海华虹Nec电子有限公司 | Field effect transistor of radio frequency lateral double-diffusion and preparation method thereof |
| CN104538441A (en) * | 2014-07-03 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Radio-frequency LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
| CN104867979A (en) * | 2014-02-26 | 2015-08-26 | 丰田自动车株式会社 | Semiconductor device |
| CN106783941A (en) * | 2016-11-29 | 2017-05-31 | 东莞市广信知识产权服务有限公司 | A kind of silicon substrate SiGe drift layer LDMOSFET device architectures |
| CN110729354A (en) * | 2019-10-11 | 2020-01-24 | 深圳第三代半导体研究院 | Silicon carbide transverse MOSFET device and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101266930A (en) * | 2008-04-11 | 2008-09-17 | 北京大学 | A method for making horizontal dual pervasion field effect transistor |
| CN101515586A (en) * | 2008-02-21 | 2009-08-26 | 中国科学院微电子研究所 | Radio frequency SOI LDMOS device with close body contact |
-
2010
- 2010-09-30 CN CN2010105040045A patent/CN102446967A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101515586A (en) * | 2008-02-21 | 2009-08-26 | 中国科学院微电子研究所 | Radio frequency SOI LDMOS device with close body contact |
| CN101266930A (en) * | 2008-04-11 | 2008-09-17 | 北京大学 | A method for making horizontal dual pervasion field effect transistor |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035731A (en) * | 2012-12-11 | 2013-04-10 | 上海华虹Nec电子有限公司 | Field effect transistor of radio frequency lateral double-diffusion and preparation method thereof |
| CN103035731B (en) * | 2012-12-11 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | Radio frequency horizontal dual pervasion field effect transistor and manufacture method thereof |
| CN104867979A (en) * | 2014-02-26 | 2015-08-26 | 丰田自动车株式会社 | Semiconductor device |
| CN104867979B (en) * | 2014-02-26 | 2018-01-02 | 丰田自动车株式会社 | Semiconductor device |
| CN104538441A (en) * | 2014-07-03 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Radio-frequency LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
| CN104538441B (en) * | 2014-07-03 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | Radio frequency LDMOS device and its manufacture method |
| CN106783941A (en) * | 2016-11-29 | 2017-05-31 | 东莞市广信知识产权服务有限公司 | A kind of silicon substrate SiGe drift layer LDMOSFET device architectures |
| CN110729354A (en) * | 2019-10-11 | 2020-01-24 | 深圳第三代半导体研究院 | Silicon carbide transverse MOSFET device and preparation method thereof |
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Application publication date: 20120509 |