CN103383944A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN103383944A CN103383944A CN201310154687XA CN201310154687A CN103383944A CN 103383944 A CN103383944 A CN 103383944A CN 201310154687X A CN201310154687X A CN 201310154687XA CN 201310154687 A CN201310154687 A CN 201310154687A CN 103383944 A CN103383944 A CN 103383944A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 484
- 239000000758 substrate Substances 0.000 claims abstract description 98
- 238000007667 floating Methods 0.000 claims abstract description 41
- 230000005684 electric field Effects 0.000 claims description 159
- 239000003990 capacitor Substances 0.000 claims description 122
- 230000033228 biological regulation Effects 0.000 claims description 45
- 230000005611 electricity Effects 0.000 claims description 31
- 238000002955 isolation Methods 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 59
- 229910052710 silicon Inorganic materials 0.000 abstract description 59
- 239000010703 silicon Substances 0.000 abstract description 59
- 239000010410 layer Substances 0.000 description 245
- 239000012535 impurity Substances 0.000 description 52
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 39
- 229920005591 polysilicon Polymers 0.000 description 39
- 230000000052 comparative effect Effects 0.000 description 13
- 238000000034 method Methods 0.000 description 9
- 150000001875 compounds Chemical class 0.000 description 7
- 238000010276 construction Methods 0.000 description 7
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 238000005192 partition Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
- H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0676—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type comprising combinations of diodes, or capacitors or resistors
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L28/60—Electrodes
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
Abstract
The invention relates to a semiconductor device. In a region located between a collector electrode (18) and a semiconductor substrate (1), there are a portion where a hollow region is located and a portion where no hollow region is located. Between the collector electrode (18) and the portion where no hollow region is located in the semiconductor substrate (1), a floating silicon layer (21) electrically isolated by insulating films (17) is formed.
Description
Technical field
The present invention relates to semiconductor device, particularly used the semiconductor device of SOI substrate.
Background technology
At the inverter circuit that is used for making the work of induction motor even load, as switch element, for example use the insulated gate bipolar transistor (LIGBT:Lateral Insulated Gate Bipolar Transistor) of horizontal type.In this semiconductor device, as the substrate of the LIGBT that forms the n channel-type, use SOI(Silicon On Insulator: silicon-on-insulator) substrate.In the SOI substrate, be formed with N across dielectric film on the first type surface of Semiconductor substrate
-Semiconductor layer.
At N
-Semiconductor layer is formed with the first p type impurity from its surface to the degree of depth of regulation regional.Be formed with the first N-type extrinsic region in the mode of surrounding this first p type impurity zone with the below from the side.Be formed with collector electrode in the mode with the Surface Contact in the first p type impurity zone.Be positioned at collector electrode under N
-Part between semiconductor layer and Semiconductor substrate is formed with hole region.
With the N of the first N-type extrinsic region partition distance
-The regulation zone of semiconductor layer, the degree of depth from its surface to regulation is formed with the second N-type extrinsic region.Be formed with the second p type impurity zone in the mode of surrounding this second N-type extrinsic region with the below from the side.By the second N-type extrinsic region and N
-On the surface of the part in the second p type impurity zone that semiconductor layer clips, be formed with gate electrode across gate insulating film.In addition, be formed with emitter electrode in the mode with the Surface Contact of the surface in the second p type impurity zone and the second N-type extrinsic region.Consisted of each electrode of LIGBT by emitter electrode, collector electrode and gate electrode.
Be set at semiconductor device under the state of cut-off (OFF), depletion layer is mainly from the second p type impurity zone and N
-The interface of semiconductor layer is towards N
-Semiconductor layer enlarges.At this moment, by to N
-Impurity concentration and the thickness of semiconductor layer are adjusted, thereby can make N
-The integral body of semiconductor layer exhausts, and at N
-The electric field of the surface of semiconductor layer obtains the withstand voltage of maximum under state substantially uniformly.
Under this state, when the distance (interval) that makes emitter (electrode) with collector electrode (electrode) enlarges, finally due to the N under collector electrode (electrode)
-Concentrating of the electric field at the part place of semiconductor layer and whole withstand voltage of restriction.In addition, although make the first N-type extrinsic region and collector electrode extend in the groundwork of IGBT towards the side that emitter electrode is arranged to be unwanted, to have under cut-off state to be suppressed at N
-The effect that the depletion layer of the near surface of semiconductor layer extends.
At N
-The structure that part between semiconductor layer and Semiconductor substrate forms hole region is be used to improving withstand voltage structure, for example at No. 2739018 communique of patent documentation 1(patent), No. 148017 communiques of patent documentation 2(TOHKEMY 2006 –) and No. 173204 communiques of patent documentation 3(TOHKEMY 2006 –) in this structure has been proposed.In the stepped construction of Semiconductor substrate (silicon), dielectric film (silicon oxide layer) and hole region, the ratio of electric field strength is equivalent to the inverse of the ratio of dielectric constant.At this, because N
-The ratio of the dielectric constant of semiconductor layer (silicon), dielectric film (silicon oxide layer) and hole region is substantially 12 ︰ 4 ︰ 1, so can set the voltage drop at hole region place larger, correspondingly can make N
-The voltage drop at the part place of semiconductor layer diminishes.Thus, can make N
-The electric field at the part place of semiconductor layer relaxes to suppress the extension of depletion layer, consequently can make the withstand voltage lifting of semiconductor device.
Yet, such problem below existing in semiconductor device in the past.As mentioned above, hole region can in the situation that high withstand voltageization that electrical characteristics of the semiconductor elements such as LIGBT is not impacted semiconductor device contributes, make the mechanical strength of semiconductor device reduce on the other hand.Thereby, may be owing to destroying semiconductor device such as stress when the electrode as the encapsulation (package) of semiconductor device is carried out wire-bonded (wire bonding) or utilizes resin-sealed encapsulation the etc.
Summary of the invention
The present invention completes in such exploitation link, and its purpose is to provide a kind of semiconductor device that suppresses the reduction of mechanical strength when keeping height withstand voltage.
The invention provides a kind of semiconductor device, possess: the semiconductor layer of the conductivity type of Semiconductor substrate, the first dielectric film, regulation, the second dielectric film and the first electrode.Semiconductor substrate has first type surface and is applied in earthed voltage.The first dielectric film forms in the mode of the first type surface of covering Semiconductor substrate.Semiconductor layer forms in the mode that covers the first dielectric film.The second dielectric film forms in the mode that covers semiconductor layer.The first electrode forms and is applied in the voltage of the regulation higher than earthed voltage in the mode in the regulation zone that covers the second dielectric film.In the zone that is clipped by the first electrode and Semiconductor substrate, have in the zone that is being formed with the cavity between Semiconductor substrate and the first dielectric film and be not formed with empty zone between Semiconductor substrate and the first dielectric film.Be positioned at the zone that is formed with the cavity directly over the part of semiconductor layer be formed with the element-forming region that is electrically connected to and is formed with the semiconductor element of regulation with the first electrode.Be formed with the electric field relief areas between the part of Semiconductor substrate in the zone that be not formed with the cavity and the first electrode.In the electric field relief areas, be formed with at the voltage of the regulation that is applied to the first electrode and be applied to a plurality of capacitors that are connected in series between the earthed voltage of Semiconductor substrate.
According to semiconductor device of the present invention, can suppress the reduction of mechanical strength when keeping height withstand voltage.
The following detailed explanation relevant according to the present invention who understands explicitly to accompanying drawing, above-mentioned and other purpose, feature, aspect and advantage of the present invention become clear.
Description of drawings
Fig. 1 is the profile of the semiconductor device of embodiment of the present invention 1.
Fig. 2 is the profile of the semiconductor device of comparative example.
Fig. 3 is the fragmentary cross-sectional view that describes for the effect that the electric field in the semiconductor device of execution mode 1 is relaxed.
Fig. 4 is the fragmentary cross-sectional view of the semiconductor device of embodiment of the present invention 2.
Fig. 5 is the fragmentary cross-sectional view that describes for the effect that the electric field in the semiconductor device of execution mode 2 is relaxed.
Fig. 6 is the fragmentary cross-sectional view of the semiconductor device of embodiment of the present invention 3.
Fig. 7 is the fragmentary cross-sectional view that describes for the effect that the electric field in the semiconductor device of execution mode 3 is relaxed.
Fig. 8 is the fragmentary cross-sectional view of the semiconductor device of embodiment of the present invention 4.
Fig. 9 is the fragmentary cross-sectional view that describes for the effect that the electric field in the semiconductor device of execution mode 4 is relaxed.
Figure 10 is the fragmentary cross-sectional view of the semiconductor device of embodiment of the present invention 5.
Figure 11 is the fragmentary cross-sectional view that describes for the effect that the electric field in the semiconductor device of execution mode 5 is relaxed.
Figure 12 is the fragmentary cross-sectional view that the semiconductor device of the first case in the semiconductor device of embodiment of the present invention 6 is shown.
Figure 13 is the fragmentary cross-sectional view that the semiconductor device of the second case in execution mode 6 is shown.
Figure 14 is the fragmentary cross-sectional view that the semiconductor device of the 3rd example in execution mode 6 is shown.
Figure 15 is the fragmentary cross-sectional view that the semiconductor device of the 4th example in execution mode 6 is shown.
Figure 16 is the fragmentary cross-sectional view that the semiconductor device of the 5th example in execution mode 6 is shown.
Figure 17 is the fragmentary cross-sectional view that the semiconductor device of the first case in the semiconductor device of embodiment of the present invention 7 is shown.
Figure 18 is the fragmentary cross-sectional view that the semiconductor device of the second case in execution mode 7 is shown.
Figure 19 is the fragmentary cross-sectional view that the semiconductor device of the 3rd example in execution mode 7 is shown.
Figure 20 is the fragmentary cross-sectional view that the semiconductor device of the 4th example in execution mode 7 is shown.
Figure 21 is the fragmentary cross-sectional view that the semiconductor device of the 5th example in execution mode 7 is shown.
Figure 22 is the fragmentary cross-sectional view that the semiconductor device of the first case in the semiconductor device of embodiment of the present invention 8 is shown.
Figure 23 is the fragmentary cross-sectional view that the semiconductor device of the second case in execution mode 8 is shown.
Figure 24 is the fragmentary cross-sectional view that the semiconductor device of the 3rd example in execution mode 8 is shown.
Figure 25 is the fragmentary cross-sectional view that the semiconductor device of the 4th example in execution mode 8 is shown.
Figure 26 is the fragmentary cross-sectional view that the semiconductor device of the 5th example in execution mode 8 is shown.
Figure 27 is the fragmentary cross-sectional view that the semiconductor device of the first case in the semiconductor device of embodiment of the present invention 9 is shown.
Figure 28 is the fragmentary cross-sectional view that the semiconductor device of the second case in execution mode 9 is shown.
Figure 29 is the fragmentary cross-sectional view that the semiconductor device of the 3rd example in execution mode 9 is shown.
Figure 30 is the fragmentary cross-sectional view that the semiconductor device of the 4th example in execution mode 9 is shown.
Figure 31 is the fragmentary cross-sectional view that the semiconductor device of the 5th example in execution mode 9 is shown.
Figure 32 is first's profile that the configuration structure of the hole region in the embodiments of the present invention is shown.
Figure 33 is the second portion profile that the configuration structure of the hole region in the embodiments of the present invention is shown.
Figure 34 is the third part profile that the configuration structure of the hole region in the embodiments of the present invention is shown.
Embodiment
At this, as the semiconductor element SE1(that forms at the SOI substrate with reference to Fig. 1), enumerate the IGBT(LIGBT of the horizontal type of n channel-type) be example, its first case is described.
As shown in Figure 1, in semiconductor device SD, semiconductor element SE1 adopts the cross-section structure with respect to line segment S1 symmetry.At first, as the SOI substrate, use on the first type surface of Semiconductor substrate 1 across being called as BOX(Buried Oxide: buried oxide) dielectric film 2 of layer is formed with the N of specific thickness
-The SOI substrate S UB of semiconductor layer 3.At this, will be insulated that film 25 surrounds and be called N with the zone of other isolation
-Semiconductor layer 3a.In addition, Semiconductor substrate means silicon substrate, and unless otherwise specified, dielectric film means silicon oxide layer.
As hereinafter described, at Semiconductor substrate 1 and N
-Between semiconductor layer 3a, be formed with hole region 4 at assigned position.At N
-Regulation zone in semiconductor layer 3a is from N
-The surface of semiconductor layer 3a is formed with p type impurity zone 11 as collector electrode to the degree of depth of regulation.To surround from the side the mode in this p type impurity zone 11 with the below, from N
-The surface of semiconductor layer 3a is formed with the N-type extrinsic region 12 as the buffer area to the zone darker than p type impurity regional 11.
At the N from N-type extrinsic region 12 partition distance
-The part of semiconductor layer 3a is from N
-The surface of semiconductor layer 3a is formed with N-type extrinsic region 13 as emitter to the degree of depth of regulation.To surround from the side the mode of this N-type extrinsic region 13 with the below, from N
-The surface of semiconductor layer 3a is to the zone darker than N-type extrinsic region 13, is formed with the p type impurity zone 14 as main body (body) (base stage).At least by N-type extrinsic region 13 and N
-Semiconductor layer 3a clips is positioned on the surface of part in p type impurity zone 14 of collector electrode side, is formed with the gate electrode 16 that for example is made of polysilicon film across gate insulating film 15.
The N that comprises this gate electrode 16 with covering
-The mode on the surface of semiconductor layer 3a is formed with the dielectric film 17 as interlayer dielectric.Be formed with the collector electrode 18 that is consisted of by metal film that contacts with p type impurity zone 11 via the peristome that is formed at dielectric film 17 in the regulation zone on the surface of dielectric film 17.In addition, be formed with the emitter electrode 19 that is consisted of by metal film that contacts with p type impurity zone 14 via other peristome that is formed at dielectric film 17 and N-type extrinsic region 13 on the surface of dielectric film 17.
In this semiconductor device SD, in the zone that is clipped by collector electrode 18 and Semiconductor substrate 1, have the part of hole region 4 and there is no the part of hole region.Therefore, hole region 4 be not with the integral body of collector electrode 18 in opposite directions but with collector electrode 18 partly in opposite directions mode form.Specifically, be not formed with hole region under the central portion of collector electrode 18.In addition, be filled with atmosphere or for vacuum in hole region 4.
Between the part and collector electrode 18 of the Semiconductor substrate 1 that is not formed with hole region 4, be formed with by dielectric film 2, dielectric film 20 and dielectric film 17 by the silicon layer 21(N that floats of electricity isolation
-Semiconductor layer 3).Utilize dielectric film 2,20,17 and the silicon layer 21 of floating the part of the Semiconductor substrate 1 that is not formed with hole region and the electric field between collector electrode 18 are relaxed, thus, dielectric film 2,20,17 and the silicon layer 21 of floating as electric field relief areas performance function.Like this, this semiconductor device SD adopts the structure that does not configure hole region in the part in the zone that is clipped by collector electrode 18 and Semiconductor substrate 1.
Then, to the LIGBT of the semiconductor element SE1(n channel-type in above-mentioned semiconductor device SD) work describe.At first, gate electrode 16 is applied the high voltage of threshold voltage than regulation, thus, be positioned at gate electrode 16 under the surface portion in p type impurity zone 14 form the raceway groove of N-shaped.When raceway groove is formed, from emitter electrode 19 through N-type extrinsic region 13 and raceway groove to N
-Semiconductor layer 3a injects electronics, on the other hand, from collector electrode 18 through p type impurity zone 11 to N
-Semiconductor layer 3a injected hole (hole).Thus, N
-The resistance value of semiconductor layer 3a becomes from the state (conducting state) of collector electrode side towards the emitter side current flowing because conductivity modulation (conductivity modulation) descends.
On the other hand, when gate electrode 16 being applied than the low voltage of threshold voltage, the raceway groove that is formed at p type impurity zone 14 disappears.When raceway groove disappears, to N
-The electronic injection of semiconductor layer 3a stops, and accumulates in N
-The electronics of semiconductor layer 3a and hole disappear or by disappearing to emitter electrode 19 or collector electrode 18 discharges, finally become the cut state of electric current (cut-off state) by compound.
In above-mentioned semiconductor device SD, adopt the structure that does not configure hole region in the part in the zone that is clipped by collector electrode 18 and Semiconductor substrate 1.Thus, can suppress mechanical strength when guaranteeing semiconductor device SD withstand voltage reduces.About this, the comparative example that intersects describes.
In the semiconductor device of comparative example, except be formed with hole region in the zone that is clipped by collector electrode and Semiconductor substrate in the integral body mode in opposite directions with collector electrode and be not formed with the electric field relief areas aspect, the structure with semiconductor device shown in Figure 1 is identical in fact.As shown in Figure 2, make dielectric film 102 between Semiconductor substrate 101 and N
-SOI substrate S UB between semiconductor layer 103.At N
-Semiconductor layer 103 be formed be insulated that film 125 surrounds and with the N of other isolation
-Semiconductor layer 103a.At N
-Regulation zone in semiconductor layer 103a is from N
-The surface of semiconductor layer 103a is formed with p type impurity zone 111 to the degree of depth of regulation.To surround from the side the mode in this p type impurity zone 111 with the below, from N
-The surface of semiconductor layer 103a is to being formed with N-type extrinsic region 112 than 111 dark zones, p type impurity zone.
At the N from N-type extrinsic region 112 partition distance
-The part of semiconductor layer 103a is from N
-The surface of semiconductor layer 103a is formed with N-type extrinsic region 113 to the degree of depth of regulation.To surround from the side the mode of this N-type extrinsic region 113 with the below, from N
-The surface of semiconductor layer 103a is formed with p type impurity zone 114 to the zone darker than N-type extrinsic region 113.By N-type extrinsic region 113 and N
-On the surface of the part in semiconductor layer 103a clips p type impurity zone 114, be formed with gate electrode 116 across gate insulating film 115.
Be formed with dielectric film 117 in the mode that covers this gate electrode 116.Regulation zone on the surface of dielectric film 117 is formed with via regional 111 collector electrodes that contact 118 of the peristome that is formed at dielectric film 117 and p type impurity.In addition, be formed with on the surface of dielectric film 117 via other peristome that is formed at dielectric film 117 and regional 114 emitter electrodes that contact 119 of N-type extrinsic region 113 and p type impurity.
In the semiconductor device of comparative example, gate electrode 116 is applied than the high voltage of threshold voltage of stipulating, thus, to N
-Semiconductor layer 103a injects electronics and hole, N
-The resistance value of semiconductor layer 103a becomes from the state (conducting state) of collector electrode side towards the emitter side current flowing because conductivity modulation descends.
On the other hand, gate electrode 116 is applied the voltage lower than threshold voltage, thus, to N
-The electronic injection of semiconductor layer 103a stops, and accumulates in N
-The electronics of semiconductor layer 103a and hole disappear or by disappearing to emitter electrode 119 or collector electrode 118 discharges, become the cut state of electric current (cut-off state) by compound.
Under the state of semiconductor device (LIGBT) for cut-off, become emitter electrode 119 is applied earthing potential (0V) and collector electrode 118 for example applied the state of the voltage of about 1000V left and right, N
-The roughly whole zone of semiconductor layer 103a is depleted.Due to N
-Semiconductor layer 103a roughly depleted and cause particularly be positioned at collector electrode 118 under N
-The electric field grow at the interface of the part of semiconductor layer 103a and dielectric film 102.Therefore, withstand voltage in order to improve, based on following reason, adopt the structure that is provided with hole region 104 under collector electrode 118 as comparative example.
In the semiconductor device of comparative example, the zone being clipped by collector electrode 118 and Semiconductor substrate 101 is formed with hole region 104 in the integral body mode in opposite directions with collector electrode 118.N
-Semiconductor layer 103a(silicon), dielectric film 102(silicon oxide layer) and the ratio of the electric field strength in the stepped construction of hole region 104 be equivalent to the inverse of the ratio of dielectric constant.At this, N
-Semiconductor layer 103a(silicon), the ratio of the dielectric constant of dielectric film (silicon oxide layer) and hole region is substantially 12 ︰ 4 ︰ 1.Therefore, the ratio of electric field strength is 1 ︰ 3 ︰ 12, can become large amount with the voltage drop that can make hole region 104 places and correspondingly make N
-The voltage drop at the part place of semiconductor layer 103a diminishes.Thus, can make N
-The electric field at the part place of semiconductor layer 103a relaxes.
Yet, in the semiconductor device of comparative example, in order to be formed with hole region 104 in the integral body mode in opposite directions with collector electrode 118, the possibility that exists mechanical strength to reduce.Thereby, in wire-bonded, when resin-sealed etc., the possibility that exists semiconductor device to be destroyed by applied force.
With comparative example relatively, in above-mentioned semiconductor device SD, in the zone that is clipped by collector electrode 18 and Semiconductor substrate 1, with collector electrode 18 partly in opposite directions mode be formed with hole region 4.Be formed with electric field relief areas ER between the part of the Semiconductor substrate that is not formed with hole region 1 of locating under collector electrode 18 and collector electrode 18.
As shown in Figure 3, under cut-off state, in the high-tension collector electrode 18(that is applied in 1000V for example left and right or p type impurity zone 11) and be fixed in electric field between the Semiconductor substrate 1 of earthing potential, can with can utilize hole region 4 to make voltage drop (being equivalent to area DP1) fully become large amount correspondingly to make N
-The voltage drop at semiconductor layer 3a place (being equivalent to area DP2) diminishes.Thus, can make at roughly depleted N
-The electric field of the generation of interfaces of semiconductor layer 3a and dielectric film 2 relaxes.In addition, distribution map of the electric field shown in Figure 3 is along the desirable distribution map by near the vertical line segment (not shown) the substantial middle of hole region 4.
On the other hand, the zone between the Semiconductor substrate 1 that there is no hole region 4 and collector electrode 18, utilize dielectric film 2,20,17 and the silicon layer 21 of floating be formed with electric field relief areas ER.Floated silicon layer 21 between dielectric film 2 and dielectric film 17 by what electricity was isolated, thus, in the electric field relief areas, become following structure: capacitor C2V that silicon layer (electrode) 21, dielectric film (dielectric) 17 and collector electrode (electrode) 18 obtain is connected in series to utilize capacitor C1V that Semiconductor substrate (electrode) 1, dielectric film (dielectric) 2 and the silicon layer of floating (electrode) 21 obtain and utilization to float.
Thus, the high-tension collector voltage 18 that is applied in about 1000V is split into the voltage drop that is caused by capacitor C1V and the voltage drop that is caused by capacitor C2V with the voltage that is fixed in the Semiconductor substrate 1 of earthing potential, and electric field is relaxed longitudinally.
At this, in the high-tension situation that collector electrode 18 is applied the 1000V left and right, adjust by the electric capacity (dielectric constant, thickness etc.) to dielectric film 17 and dielectric film 2, thereby the voltage of the silicon layer 21 of floating becomes for example 500V.So, in usually using the dielectric film 2 of heat oxide film, as long as thickness is about 1.5 μ m left and right, just can guarantee that 500V's is withstand voltage.In addition, using CVD(Chemical Vapor Deposition: chemical vapour deposition (CVD)) in the dielectric film 17 of oxide-film, as long as thickness is about 5 μ m left and right, just can guarantee the withstand voltage of 500V, and, can be in the situation that can not improve production cost and form.Thus, be not formed with the part of Semiconductor substrate 1 of hole region and the electric field between collector electrode 18 and relaxed, guarantee withstand voltage.
Like this, in above-mentioned semiconductor device SD, in the zone that is clipped by collector electrode 18 and Semiconductor substrate 1, with with collector electrode 18 partly in opposite directions mode form hole region 4, on the other hand, do not form the zone of hole region with the mode setting of following electric field relief areas ER, thus, with comparing with the semiconductor device (comparative example) that the integral body mode in opposite directions of collector electrode is formed with hole region, can be in the reduction of guaranteeing to suppress in withstand voltage the mechanical strength of semiconductor device SD.Especially, in the situation that such to the direct bonding wire of collector electrode 18, can prevent that semiconductor device SD from sustaining damage.
At this, as the semiconductor element SE1(that forms at the SOI substrate with reference to Fig. 4), enumerate the IGBT(LIGBT of the horizontal type of n channel-type) be example, its second case is described.In addition, in each following execution mode, in order to simplify accompanying drawing, as the structure of semiconductor device, line segment S1(is shown with reference to the frame A of Fig. 1 according to the symmetry of semiconductor element) the zone of right half part.
In above-mentioned semiconductor device (with reference to Fig. 1), under the state of semiconductor element (LIGBT of n channel-type) SE1 for cut-off, N
-The part of dielectric film 20 sides at semiconductor layer 3a place is depleted.Thereby, can say N
-Semiconductor layer 3a and the electric field between silicon layer 21 floated than the electric field between collector electrode 18 and Semiconductor substrate 1 a little less than.Yet, though a little less than electric field, when making N
-During the thickness attenuation of semiconductor layer 3a and the dielectric film 20 of silicon layer 21 insulation of floating, need to guarantee N
-Semiconductor layer 3a and withstand voltage between silicon layer 21 of floating.Second case is an example of its countermeasure.
As shown in Figure 4, in the electric field relief areas ER of this semiconductor device SD, at N
-Semiconductor layer 3 is spaced from each other the compartment of terrain and is formed with from N
-The surface of semiconductor layer 3 arrives dielectric film 20a, 20b, the 20c of dielectric film 2.By N
-What the part of semiconductor layer 3 consisted of is floated silicon layer 21a between dielectric film 20a and dielectric film 20b by what electricity was isolated.In addition, by N
-What the part of semiconductor layer 3 consisted of is floated silicon layer 21b between dielectric film 20b and dielectric film 20c by what electricity was isolated.
In addition, about structure in addition, since identical with semiconductor device SD shown in Figure 1, so to the same Reference numeral of same member mark, no longer repeat its explanation.
The LIGBT of the semiconductor element SE1(n channel-type in above-mentioned semiconductor device SD) in, by gate electrode 16 is applied than the regulation the high voltage of threshold voltage, thereby to N
-Semiconductor layer 3a injects electronics and hole, N
-The resistance value of semiconductor layer 3a becomes from the state (conducting state) of collector electrode side towards the emitter side current flowing because conductivity modulation descends.
On the other hand, by gate electrode 16 being applied the voltage lower than threshold voltage, thereby to N
-The electronic injection of semiconductor layer 3a stops, and accumulates in N
-The electronics of semiconductor layer 3a and hole disappear or by disappearing to emitter electrode 19 or collector electrode 18 discharges, finally become the cut state of electric current (cut-off state) by compound.
In above-mentioned semiconductor device SD, at the LIGBT of semiconductor element SE1(n channel-type) under state for cut-off, become emitter electrode 19 is applied earthing potential and collector electrode 18 for example applied the state of the voltage of about 1000V left and right, N
-The roughly whole zone of semiconductor layer 3a is depleted.At this moment, as what illustrated, at roughly depleted N
-The electric field of the generation of interfaces of semiconductor layer 3a and dielectric film 2 is relaxed by hole region 4.
On the other hand, zone between the Semiconductor substrate 1 that there is no hole region 4 and collector electrode 18, except dielectric film 2,17 and the silicon layer 21 of floating, also utilize dielectric film 20a, 20b, 20c and float silicon layer 21a, 21b are formed with electric field relief areas ER.
Thereby, as shown in Figure 5, in electric field relief areas ER, except the structure that capacitor C1V and capacitor C2V are connected in series, also become following structure: utilize N
-The capacitor C1H that semiconductor layer (electrode) 3a, dielectric film (dielectric) 20a and the silicon layer of floating (electrode) 21a obtain, the utilization capacitor C2H that silicon layer (electrode) 21a, dielectric film (dielectric) 20b and the silicon layer of floating (electrode) 21b obtain that floats, the capacitor C3H that utilizes float silicon layer (electrode) 21b, dielectric film (dielectric) 20c and the silicon layer of floating (electrode) 21 to obtain is connected in series.
Thus, be applied in the high-tension collector electrode 18(N of 1000V left and right
-Semiconductor layer 3a) and the voltage of the silicon layer 21 of floating is split into the voltage drop that caused by capacitor C1H, the voltage drop that is caused by capacitor C2H and the voltage drop that is caused by capacitor C3H, horizontal electric field is relaxed.
At this, in the high-tension situation that collector electrode 18 is applied the 1000V left and right, adjust by the electric capacity (dielectric constant, thickness etc.) to dielectric film 17 and dielectric film 2, thereby the voltage of the silicon layer 21 of floating becomes for example 500V.As mentioned above, in the dielectric film of having used the CVD oxide-film, as long as its thickness is about 5 about μ m, just can guarantee that 500V's is withstand voltage.
So, in the structure that capacitor C1H, capacitor C2H, capacitor C3H are connected in series, utilize 1/3rd the thickness (approximately 1.7 μ m) of about 5 μ m as the thickness separately of dielectric film 20a, 20b, 20c, can guarantee that 500V's is withstand voltage.Thus, in the situation that guarantee identical withstand voltagely, can seek the reduction of production cost.That is, at N
-Semiconductor layer 3a devices spaced apart ground form three width that are equivalent to thickness approximately the peristome of 1.7 μ m and filling insulation film situation with form width approximately the peristome of 5 μ m and the situation of filling insulation film compare, the thickness of the dielectric film that should pile up is thinner.
In addition, in the situation that form respectively the dielectric film of identical thickness, the situation that forms three-layer insulated film 20a, 20b, 20c is compared with the situation that forms one deck dielectric film, withstand voltage lifting.In addition, as what illustrated, the capacitor C1V that is connected in series of electric field and capacitor C2V relax longitudinally.
Like this, in above-mentioned semiconductor device SD, in the zone that is clipped by collector electrode 18 and Semiconductor substrate 1, with with collector electrode 18 partly in opposite directions mode form hole region 4, the zone that does not form hole region is set on the other hand, thus, and comparing with the semiconductor device (comparative example) that the integral body mode in opposite directions of collector electrode is formed with hole region, can suppress the reduction of the mechanical strength of semiconductor device SD when guaranteeing vertical and horizontal withstand voltage.
At this, as the semiconductor element SE1(that forms at the SOI substrate with reference to Fig. 6), enumerate the IGBT(LIGBT of the horizontal type of n channel-type) be example, its 3rd example is described.The 3rd example is similarly to be used for guaranteeing N with above-mentioned example
-Semiconductor layer 3a and another example of the withstand voltage countermeasure between silicon layer 21 of floating.
In the electric field relief areas ER of this semiconductor device, utilize to be used for semiconductor element and electric groove (trench) isolation structures of isolating of other semiconductor element such as LIGBT.As shown in Figure 6, to cover from N
-The mode of the sidewall of the groove of the surface arrival dielectric film 2 of semiconductor layer 3 is formed with dielectric film 20a, 20b, and then, be formed with polysilicon film 22a, the 22b that is isolated by electricity respectively in the mode of filling this groove.
In addition, by N
-What the part of semiconductor layer 3 consisted of is floated silicon layer 21a between groove and groove by what electricity was isolated.In addition, about structure in addition, since identical with semiconductor device SD shown in Figure 1, so to the same Reference numeral of same member mark, no longer repeat its explanation.
The LIGBT of the semiconductor element SE1(n channel-type in above-mentioned semiconductor device SD) in, by gate electrode 16 is applied than the regulation the high voltage of threshold voltage, thereby to N
-Semiconductor layer 3a injects electronics and hole, N
-The resistance value of semiconductor layer 3a becomes from the state (conducting state) of collector electrode side towards the emitter side current flowing because conductivity modulation descends.
On the other hand, by gate electrode 16 being applied the voltage lower than threshold voltage, thereby to N
-The electronic injection of semiconductor layer 3a stops, and accumulates in N
-The electronics of semiconductor layer 3a and hole disappear or by disappearing to emitter electrode 19 or collector electrode 18 discharges, finally become the cut state of electric current (cut-off state) by compound.
In above-mentioned semiconductor device SD, at the LIGBT of semiconductor element SE1(n channel-type) under state for cut-off, become emitter electrode 19 is applied earthing potential and collector electrode 18 for example applied the state of the voltage of about 1000V left and right, N
-The roughly whole zone of semiconductor layer 3a is depleted.At this moment, as what illustrated, at roughly depleted N
-The electric field of the generation of interfaces of semiconductor layer 3a and dielectric film 2 is relaxed by hole region 4.
On the other hand, zone between the Semiconductor substrate 1 that there is no hole region 4 and collector electrode 18, except dielectric film 2,17 and the silicon layer 21 of floating, also utilize the dielectric film 20a(20b be filled into groove) and polysilicon film 22a(22b) be formed with electric field relief areas ER.
Thereby, as shown in Figure 7, in electric field relief areas ER, except the structure that capacitor C1V and capacitor C2V are connected in series, also become following structure: utilize N
-The capacitor C1H that semiconductor layer (electrode) 3a, dielectric film (dielectric) 20a and polysilicon film (electrode) 22a obtain, the capacitor C2H that utilizes polysilicon film (electrode) 22a, dielectric film (dielectric) 20a and the silicon layer of floating (electrode) 21a to obtain, the utilization capacitor C3H that silicon layer (electrode) 21a, dielectric film (dielectric) 20b and polysilicon film (electrode) 22b obtain that floats, the capacitor C4H that utilizes polysilicon film (electrode) 22b, dielectric film (dielectric) 20b and the silicon layer of floating (electrode) 21 to obtain is connected in series.
Thus, be applied in the high-tension collector electrode 18(N of 1000V left and right
-Semiconductor layer 3a) and the voltage of the silicon layer 21 of floating is split into the voltage drop that caused by capacitor C1H, the voltage drop that caused by capacitor C2H, the voltage drop that is caused by capacitor C3H and the voltage drop that is caused by capacitor C4H.Consequently, in semiconductor device SD, particularly horizontal electric field is relaxed.And, by forming simultaneously when the groove isolation construction that is formed for semiconductor element electricity isolation, thereby can form electric field relief areas ER in the situation that can not increase process number.
Like this, in above-mentioned semiconductor device SD, in the zone that is clipped by collector electrode 18 and Semiconductor substrate 1, with with collector electrode 18 partly in opposite directions mode form hole region 4, the zone that does not form hole region is set on the other hand, thus, and comparing with the semiconductor device (comparative example) that the integral body mode in opposite directions of collector electrode is formed with hole region, can suppress the reduction of the mechanical strength of semiconductor device SD when guaranteeing vertical and horizontal withstand voltage.
At this, as the semiconductor element SE1(that forms at the SOI substrate with reference to Fig. 8), enumerate the IGBT(LIGBT of the horizontal type of n channel-type) be example, its 4th example is described.
As shown in Figure 8, in this semiconductor device SD, be formed with the polysilicon film 22c that is isolated by electricity in dielectric film 17.In addition, about structure in addition, since identical with semiconductor device SD shown in Figure 1, so to the same Reference numeral of same member mark, no longer repeat its explanation.
The LIGBT of the semiconductor element SE1(n channel-type in above-mentioned semiconductor device SD) in, by gate electrode 16 is applied than the regulation the high voltage of threshold voltage, thereby to N
-Semiconductor layer 3a injects electronics and hole, N
-The resistance value of semiconductor layer 3a becomes from the state (conducting state) of collector electrode side towards the emitter side current flowing because conductivity modulation descends.
On the other hand, by gate electrode 16 being applied the voltage lower than threshold voltage, thereby to N
-The electronic injection of semiconductor layer 3a stops, and accumulates in N
-The electronics of semiconductor layer 3a and hole disappear or by disappearing to emitter electrode 19 or collector electrode 18 discharges, finally become the cut state of electric current (cut-off state) by compound.
In above-mentioned semiconductor device SD, at the LIGBT of semiconductor element SE1(n channel-type) under state for cut-off, become emitter electrode 19 is applied earthing potential and collector electrode 18 for example applied the state of the voltage of about 1000V left and right, N
-The roughly whole zone of semiconductor layer 3a is depleted.At this moment, as what illustrated, at roughly depleted N
-The electric field of the generation of interfaces of semiconductor layer 3a and dielectric film 2 is relaxed by hole region 4.
On the other hand, the zone between the Semiconductor substrate 1 that there is no hole region 4 and collector electrode 18, except dielectric film 2,20,17 and the silicon layer 21 of floating, also utilize the polysilicon film 22c be formed in dielectric film 17 to be formed with electric field relief areas ER.
Thereby, as shown in Figure 9, in electric field relief areas ER, become following structure: except capacitor C1V, utilize float silicon layer (electrode) 21, dielectric film (dielectric) 17 and polysilicon film (electrode) 22c the capacitor C2V that obtains and the capacitor C3V that utilizes polysilicon film (electrode) 22c, dielectric film (dielectric) 17 and collector electrode (electrode) 18 to obtain to be connected in series.
Thus, be applied in the high-tension collector electrode 18 of about 1000V and be not formed with that voltage between the part of Semiconductor substrate 1 of hole region is split into the voltage drop that caused by capacitor C1V, the voltage drop that is caused by capacitor C2V and the voltage drop that is caused by capacitor C3V.Consequently, in semiconductor device SD, particularly electric field is relaxed longitudinally.And, by forming simultaneously polysilicon film 22c when forming the gate electrode 16 of LIGBT, thereby can form electric field relief areas ER in the situation that can not increase process number.
Like this, in above-mentioned semiconductor device SD, in the zone that is clipped by collector electrode 18 and Semiconductor substrate 1, with with collector electrode 18 partly in opposite directions mode form hole region 4, the zone that does not form hole region is set on the other hand, thus, and to compare with the semiconductor device (comparative example) that the integral body mode in opposite directions of collector electrode is formed with hole region, particularly can be in the reduction of guaranteeing to suppress in withstand voltage longitudinally the mechanical strength of semiconductor device SD.
Execution mode 5
At this, as the semiconductor element SE1(that forms at the SOI substrate with reference to Figure 10), enumerate the IGBT(LIGBT of the horizontal type of n channel-type) be example, its 5th example is described.
As shown in figure 10, in this semiconductor device SD, be formed with the polysilicon film 22c that is isolated by electricity in dielectric film 17.And then, at dielectric film 17 and float and be formed with dielectric film 23 between silicon layer 21, be formed with the polysilicon film 22d that is isolated by electricity in this dielectric film 23.In addition, about structure in addition, since identical with semiconductor device SD shown in Figure 1, so to the same Reference numeral of same member mark, no longer repeat its explanation.
The LIGBT of the semiconductor element SE1(n channel-type in above-mentioned semiconductor device SD) in, by gate electrode 16 is applied than the regulation the high voltage of threshold voltage, thereby to N
-Semiconductor layer 3a injects electronics and hole, N
-The resistance value of semiconductor layer 3a becomes from the state (conducting state) of collector electrode side towards the emitter side current flowing because conductivity modulation descends.
On the other hand, by gate electrode 16 being applied the voltage lower than threshold voltage, thereby to N
-The electronic injection of semiconductor layer 3a stops, and accumulates in N
-The electronics of semiconductor layer 3a and hole disappear or by disappearing to emitter electrode 19 or collector electrode 18 discharges, finally become the cut state of electric current (cut-off state) by compound.
In above-mentioned semiconductor device SD, at the LIGBT of semiconductor element SE1(n channel-type) under state for cut-off, become emitter electrode 19 is applied earthing potential and collector electrode 18 for example applied the state of the voltage of about 1000V left and right, N
-The roughly whole zone of semiconductor layer 3a is depleted.At this moment, as what illustrated, at roughly depleted N
-The electric field of the generation of interfaces of semiconductor layer 3a and dielectric film 2 is relaxed by hole region 4.
On the other hand, zone between the Semiconductor substrate 1 that there is no hole region 4 and collector electrode 18, except dielectric film 2,20,17 and the silicon layer 21 of floating, also utilize the polysilicon film 22d be formed at polysilicon film 22c, the dielectric film 23 in dielectric film 17 and be formed in this dielectric film 23 to be formed with electric field relief areas ER.
Thereby, as shown in figure 11, in electric field relief areas ER, become following structure: except capacitor C1V, utilize capacitor C2V that float silicon layer (electrode) 21, dielectric film (dielectric) 23 and polysilicon film (electrode) 22d obtain, utilize capacitor C3V, the capacitor C4V that utilizes polysilicon film (electrode) 22c, dielectric film (dielectric) 17 and collector electrode (electrode) 18 to obtain that polysilicon film (electrode) 22d, dielectric film (dielectric) 23,17 and polysilicon film (electrode) 22c obtain to be connected in series.
Thus, be applied in the high-tension collector electrode 18 of about 1000V and be not formed with voltage drop that voltage between the part of Semiconductor substrate 1 of hole region is split into the voltage drop that caused by capacitor C1V, caused by capacitor C2V, the voltage drop that is caused by capacitor C3V and the voltage drop that is caused by capacitor C4V.Consequently, in semiconductor device SD, particularly electric field is relaxed longitudinally.
Like this, in above-mentioned semiconductor device SD, in the zone that is clipped by collector electrode 18 and Semiconductor substrate 1, with with collector electrode 18 partly in opposite directions mode form hole region 4, the zone that does not form hole region is set on the other hand, thus, and to compare with the semiconductor device (comparative example) that the integral body mode in opposite directions of collector electrode is formed with hole region, particularly can be in the reduction of guaranteeing to suppress in withstand voltage longitudinally the mechanical strength of semiconductor device SD.
Execution mode 6
At this, as the semiconductor element SE2(that forms at the SOI substrate with reference to Figure 12～Figure 16), enumerate the DMOS(LDMOS:Lateral Double diffused Metal Oxide Semiconductor of the horizontal type of n channel-type: lateral double diffusion metal oxide semiconductor) describe for example.
(first case)
As shown in figure 12, be positioned at N
-Part (the N in the regulation zone of semiconductor layer 3
- Semiconductor layer 3a) in, from N
-The surface of semiconductor layer 3a is formed with as the N-type extrinsic region 31 that drains to the degree of depth of regulation.At the N from N-type extrinsic region 31 partition distance
-The part of semiconductor layer 3a is from N
-The surface of semiconductor layer 3a is formed with N-type extrinsic region 32 as source electrode to the degree of depth of regulation.
To surround from the side the mode of this N-type extrinsic region 32 with the below, from N
-The surface of semiconductor layer 3a is to the zone darker than N-type extrinsic region 32, is formed with the p type impurity zone 33 as main body (base stage).By N-type extrinsic region 32 and N
-On the surface of the part in semiconductor layer 3a clips p type impurity zone 33, be formed with gate electrode 35 across gate insulating film 34.
Be formed with dielectric film 17 in the mode that covers this gate electrode 35.Regulation zone on the surface of dielectric film 17 is formed with the drain electrode 37 that contacts with N-type extrinsic region 31 via the peristome that is formed at dielectric film 17.In addition, be formed with on the surface of dielectric film 17 via other peristome that is formed at dielectric film 17 and regional 33 source electrodes that contact 38 of N-type extrinsic region 32 and p type impurity.
In addition, about the structure of in addition hole region 4 and electric field relief areas ER etc., since identical with semiconductor device SD shown in Figure 1, so to the same Reference numeral of same member mark, no longer repeat its explanation.
Then, to the LDMOS of the semiconductor element SE2(n channel-type in above-mentioned semiconductor device SD) work describe.At first, by gate electrode 35 being applied the high voltage of threshold voltage than regulation, thereby be positioned at gate electrode 35 under the part in p type impurity zone 33 form the raceway groove of N-shaped.When raceway groove is formed, from source electrode 38 through N-type extrinsic region 32 and raceway groove to N
-Semiconductor layer 3a injects electronics.Thus, become from the state (conducting state) of drain side towards the source side current flowing.
On the other hand, when gate electrode 35 being applied than the low voltage of threshold voltage, the raceway groove that is formed at p type impurity zone 33 disappears.When raceway groove disappeared, electronics was towards N
-The mobile of semiconductor layer 3a stops, and becomes the cut state of electric current (cut-off state).
In above-mentioned semiconductor device SD, at the LDMOS of semiconductor element SE2(n channel-type) under state for cut-off, become source electrode 38 is applied earthing potential and drain electrode 37 for example applied the state of the voltage of about 1000V left and right, N
-The roughly whole zone of semiconductor layer 3a is depleted.At this moment, as illustrated in execution mode 1, at roughly depleted N
-The electric field of the generation of interfaces of semiconductor layer 3a and dielectric film 2 is relaxed by hole region 4.
On the other hand, the zone between the Semiconductor substrate 1 that there is no hole region 4 and drain electrode 37 utilize dielectric film 2,20,17 and the silicon layer 21 of floating be formed with electric field relief areas ER.Thus, with identical in situation illustrated in fig. 3, the voltage that is applied in the high-tension drain electrode 37 of about 1000V and is fixed between the Semiconductor substrate 1 of earthing potential is split into the voltage drop that is caused by capacitor C1V and the voltage drop that is caused by capacitor C2V, and electric field is relaxed longitudinally.
(second case)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 4, this electric field relief areas ER is spaced from each other the compartment of terrain and is formed with from N as shown in figure 13
-The surface of semiconductor layer 3 arrives dielectric film 20a, 20b, the 20c of dielectric film 2.
In this case, identical with the situation that Fig. 5 is described, be applied in the high-tension drain electrode 37(N about 1000V
-Semiconductor layer 3a) and the voltage of the silicon layer 21 of floating is split into the voltage drop that caused by capacitor C1H, the voltage drop that is caused by capacitor C2H and the voltage drop that is caused by capacitor C3H, horizontal electric field is relaxed.
(the 3rd example)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 6, this electric field relief areas ER as shown in figure 14, to cover from N
-The mode of the sidewall of the groove of the surface arrival dielectric film 2 of semiconductor layer 3 is formed with dielectric film 20a, 20b, and then is formed with in the mode of filling this groove polysilicon film 22a, the 22b that is isolated by electricity respectively.
In this case, identical with the situation that Fig. 7 is described, be applied in the high-tension drain electrode 37(N about 1000V
-Semiconductor layer 3a) and the voltage of the silicon layer 21 of floating is split into the voltage drop that caused by capacitor C1H, the voltage drop that caused by capacitor C2H, the voltage drop that is caused by capacitor C3H and the voltage drop that is caused by capacitor C4H.Consequently, in semiconductor device SD, particularly horizontal electric field is relaxed.And, by forming simultaneously when the groove isolation construction that is formed for semiconductor element electricity isolation, thereby can form electric field relief areas ER in the situation that can not increase process number.
(the 4th example)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 8, this electric field relief areas ER is formed with the polysilicon film 22c that is isolated by electricity as shown in figure 15 in dielectric film 17.
In this case, identical with the situation that Fig. 9 is described, be applied in the high-tension drain electrode 37(N about 1000V
-Semiconductor layer 3a) and be fixed in that voltage between the Semiconductor substrate 1 of earthing potential is split into the voltage drop that caused by capacitor C1V, the voltage drop that is caused by capacitor C2V and the voltage drop that is caused by capacitor C3V.Consequently, in semiconductor device SD, particularly electric field is relaxed longitudinally.And, by forming simultaneously polysilicon film 22c when forming the gate electrode 35 of LDMOS, thereby can form electric field relief areas ER in the situation that can not increase process number.
(the 5th example)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 10, this electric field relief areas ER as shown in figure 16, except be formed with polysilicon film 22c in dielectric film 17, also at dielectric film 17 and float and be formed with dielectric film 23 between silicon layer 21, and be formed with the polysilicon film 22d that is isolated by electricity in this dielectric film 23.
In this case, identical with the situation that Figure 11 is described, be applied in the high-tension drain electrode 37(N about 1000V
-Semiconductor layer 3a) and be fixed in voltage drop that voltage between the Semiconductor substrate 1 of earthing potential is split into the voltage drop that caused by capacitor C1V, caused by capacitor C2V, the voltage drop that is caused by capacitor C3V and the voltage drop that is caused by capacitor C4V.Consequently, in semiconductor device SD, particularly electric field is relaxed longitudinally.
Like this, in this semiconductor device (first case～the 5th example), in the zone that is clipped by drain electrode 37 and Semiconductor substrate 1, with with drain electrode 37 partly in opposite directions mode form hole region 4, the zone that does not form hole region is set on the other hand, thus, and comparing with the semiconductor device that the integral body mode in opposite directions of drain electrode is formed with hole region, can suppress the reduction of the mechanical strength of semiconductor device SD when guaranteeing vertical and horizontal withstand voltage.
At this, as the semiconductor element SE3(that forms at the SOI substrate with reference to Figure 17～Figure 21), the LIGBT that enumerates the p channel-type is that example describes.
(first case)
As shown in figure 17, be positioned at N
-Part (the N in the regulation zone of semiconductor layer 3
- Semiconductor layer 3a) in, from N
-The surface of semiconductor layer 3a is formed with p type impurity zone 41 as emitter to the degree of depth of regulation.To surround from the side the mode in this p type impurity zone 41 with the below, from N
-The surface of semiconductor layer 3a is to the N-type extrinsic region 42 that is formed with than 41 dark zones, p type impurity zone as main body (base stage).
At the N from N-type extrinsic region 42 partition distance
-The part of semiconductor layer 3a is from N
-The surface of semiconductor layer 3a is formed with N-type extrinsic region 43 as collector electrode to the degree of depth of regulation.To surround from the side the mode of this N-type extrinsic region 43 with the below, from N
-The surface of semiconductor layer 3a is formed with the p type impurity zone 44 as drift region to the zone darker than N-type extrinsic region 43.At the N that is clipped by N-type extrinsic region 42 and p type impurity zone 44
-The part of semiconductor layer 3a is from N
-The surface of semiconductor layer 3a is formed with P as drift region to the degree of depth of regulation
-Extrinsic region 45.
By p type impurity zone 41 and P
-On the surface of the part of the N-type extrinsic region 42 that extrinsic region 45 clips, be formed with gate electrode 47 across gate insulating film 46.Be formed with dielectric film 17 in the mode that covers this gate electrode 47.Be formed with on the surface of dielectric film 17 via regional 41 emitter electrodes 48 that contact with N-type extrinsic region 42 of the peristome that is formed at dielectric film 17 and p type impurity.In addition, the regulation zone on the surface of dielectric film 17 is formed with the collector electrode 49 that contacts with N-type extrinsic region 43 via other peristome that is formed at dielectric film 17.
In addition, about the structure of in addition hole region 4 and electric field relief areas ER etc., since identical with semiconductor device SD shown in Figure 1, so to the same Reference numeral of same member mark, no longer repeat its explanation.
Then, to the LIGBT of the semiconductor element SE3(p channel-type in above-mentioned semiconductor device SD) work describe.At first, to gate electrode 47 apply threshold voltage than regulation (＜0V) low voltage, thus, be positioned at gate electrode 47 under the part of N-type extrinsic region 42 form the raceway groove of p-type.When raceway groove is formed, from emitter electrode 48 through the p type impurity zone 41, raceway groove and P
-Extrinsic region 45 is to N
-Semiconductor layer 3a injected hole (hole), on the other hand, from collector electrode 49 through N-type extrinsic region 43 to N
-Semiconductor layer 3a injects electronics.Thus, N
-The resistance value of semiconductor layer 3a becomes from the state (conducting state) of emitter side towards collector electrode effluent overcurrent because conductivity modulation descends.
On the other hand, when gate electrode 47 being applied than the high voltage of threshold voltage, the raceway groove that is formed at N-type extrinsic region 42 disappears.When raceway groove disappears, to N
-The hole of semiconductor layer 3a is injected and is stopped, and accumulates in N
-The electronics of semiconductor layer 3a and hole disappear or by disappearing to emitter electrode 48 or collector electrode 49 discharges, finally become the cut state of electric current (cut-off state) by compound.
In above-mentioned semiconductor device SD, at the LIGBT of semiconductor element SE3(p channel-type) under state for cut-off, become and apply the state of the voltage of high pressure to emitter electrode 48 with respect to collector electrode 49, N
-The roughly whole zone of semiconductor layer 3a is depleted.At this moment, as illustrated in execution mode 1, at roughly depleted N
-The electric field of the generation of interfaces of semiconductor layer 3a and dielectric film 2 is relaxed by hole region 4.
On the other hand, the zone between the Semiconductor substrate 1 that there is no hole region 4 and emitter electrode 48 utilize dielectric film 2,20,17 and the silicon layer 21 of floating be formed with electric field relief areas ER.Thus, with identical in situation illustrated in fig. 3, be applied in high-tension emitter electrode 48 and the voltage that is fixed between the Semiconductor substrate 1 of earthing potential is split into the voltage drop that is caused by capacitor C1V and the voltage drop that is caused by capacitor C2V with respect to collector electrode 49, electric field is relaxed longitudinally.
(second case)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 4, this electric field relief areas ER is spaced from each other the compartment of terrain and is formed with from N as shown in figure 18
-The surface of semiconductor layer 3 arrives dielectric film 20a, 20b, the 20c of dielectric film 2.
In this case, identical with the situation that Fig. 5 is described, be applied in high-tension emitter electrode 48(N
-Semiconductor layer 3a) and the voltage of the silicon layer 21 of floating is split into the voltage drop that caused by capacitor C1H, the voltage drop that is caused by capacitor C2H and the voltage drop that is caused by capacitor C3H, horizontal electric field is relaxed.
(the 3rd example)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 6, this electric field relief areas ER as shown in figure 19, to cover from N
-The mode of the sidewall of the groove of the surface arrival dielectric film 2 of semiconductor layer 3 is formed with dielectric film 20a, 20b, and then is formed with in the mode of filling this groove polysilicon film 22a, the 22b that is isolated by electricity respectively.
In this case, identical with the situation that Fig. 7 is described, be applied in high-tension emitter electrode 48(N
-Semiconductor layer 3a) and the voltage of the silicon layer 21 of floating is split into the voltage drop that caused by capacitor C1H, the voltage drop that caused by capacitor C2H, the voltage drop that is caused by capacitor C3H and the voltage drop that is caused by capacitor C4H.Consequently, in semiconductor device SD, particularly horizontal electric field is relaxed.And, by forming simultaneously when the groove isolation construction that is formed for semiconductor element electricity isolation, thereby can form electric field relief areas ER in the situation that can not increase process number.
(the 4th example)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 8, this electric field relief areas ER is formed with the polysilicon film 22c that is isolated by electricity as shown in figure 20 in dielectric film 17.
In this case, identical with the situation that Fig. 9 is described, be applied in high-tension emitter electrode 48 and be fixed in that voltage between the Semiconductor substrate 1 of earthing potential is split into the voltage drop that caused by capacitor C1V, the voltage drop that is caused by capacitor C2V and the voltage drop that is caused by capacitor C3V.Consequently, in semiconductor device SD, particularly electric field is relaxed longitudinally.And, by forming simultaneously polysilicon film 22c when forming the gate electrode 47 of LDMOS, thereby can form electric field relief areas ER in the situation that can not increase process number.
(the 5th example)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 10, this electric field relief areas ER as shown in figure 21, except be formed with polysilicon film 22c in dielectric film 17, also at dielectric film 17 and float and be formed with dielectric film 23 between silicon layer 21, and be formed with the polysilicon film 22d that is isolated by electricity in this dielectric film 23.
In this case, identical with the situation that Figure 11 is described, be applied in high-tension emitter electrode 48(N
-Semiconductor layer 3a) and be fixed in voltage drop that voltage between the Semiconductor substrate 1 of earthing potential is split into the voltage drop that caused by capacitor C1V, caused by capacitor C2V, the voltage drop that is caused by capacitor C3V and the voltage drop that is caused by capacitor C4V.Consequently, in semiconductor device SD, particularly electric field is relaxed longitudinally.
Like this, in this semiconductor device (first case～the 5th example), the zone that is being launched utmost point electrode 48 and Semiconductor substrate 1 and clips, with with emitter electrode 48 partly in opposite directions mode form hole region 4, the zone that does not form hole region is set on the other hand, thus, and comparing with the semiconductor device that the integral body mode in opposite directions of emitter electrode is formed with hole region, can suppress the reduction of the mechanical strength of semiconductor device SD when guaranteeing vertical and horizontal withstand voltage.
Execution mode 8
At this, as the semiconductor element SE4(that forms at the SOI substrate with reference to Figure 22～Figure 26), enumerate the DMOS(LDMOS of the horizontal type of p channel-type) describe for example.
(first case)
As shown in figure 22, be positioned at N
-Part (the N in the regulation zone of semiconductor layer 3
- Semiconductor layer 3a) in, from N
-The surface of semiconductor layer 3a is formed with p type impurity zone 51 as source electrode to the degree of depth of regulation.To surround from the side the mode in this p type impurity zone 51 with the below, from N
-The surface of semiconductor layer 3a is to the N-type extrinsic region 52 that is formed with than 51 dark zones, p type impurity zone as main body (base stage).
At the N from N-type extrinsic region 52 partition distance
-The part of semiconductor layer 3a is from N
-The surface of semiconductor layer 3a is formed with p type impurity zone 53 as drain electrode to the degree of depth of regulation.At the N that is clipped by N-type extrinsic region 52 and p type impurity zone 53
-The part of semiconductor layer 3a is from N
-The surface of semiconductor layer 3a is formed with P as drift region to the degree of depth of regulation
-Extrinsic region 54.By p type impurity zone 51 and P
-On the surface of the part of the N-type extrinsic region 52 that extrinsic region 54 clips, be formed with gate electrode 56 across gate insulating film 55.
Be formed with dielectric film 17 in the mode that covers this gate electrode 56.Be formed with on the surface of dielectric film 17 via regional 51 source electrodes 57 that contact with N-type extrinsic region 52 of the peristome that is formed at dielectric film 17 and p type impurity.In addition, the regulation zone on the surface of dielectric film 17 is formed with via regional 53 drain electrodes that contact 58 of other peristome that is formed at dielectric film 17 and p type impurity.
In addition, about the structure of in addition hole region 4 and electric field relief areas ER etc., since identical with semiconductor device SD shown in Figure 1, so to the same Reference numeral of same member mark, no longer repeat its explanation.
Then, to the LDMOS of the semiconductor element SE4(p channel-type in above-mentioned semiconductor device SD) work describe.At first, to gate electrode 56 apply threshold voltage than regulation (＜0V) low voltage, thus, be positioned at gate electrode 56 under the part of N-type extrinsic region 52 form the raceway groove of p-type.When raceway groove is formed, from source electrode 57 through raceway groove and P
-Extrinsic region 54 is to regional 53 injected holes of p type impurity.Thus, become from the state (conducting state) of source side towards the drain side current flowing.
On the other hand, when gate electrode 56 being applied than the high voltage of threshold voltage, the raceway groove that is formed at N-type extrinsic region 52 disappears.When raceway groove disappeared, the hole was towards P
-The mobile of extrinsic region 54 stops, and becomes the cut state of electric current (cut-off state).
In above-mentioned semiconductor device SD, at the LDMOS of semiconductor element SE4(p channel-type) under state for cut-off, become and apply the state of the voltage of high pressure to source electrode 57 with respect to drain electrode 58, N
-The roughly whole zone of semiconductor layer 3a is depleted.At this moment, as illustrated in execution mode 1, at roughly depleted N
-The electric field of the generation of interfaces of semiconductor layer 3a and dielectric film 2 is relaxed by hole region 4.
On the other hand, the zone between the Semiconductor substrate 1 that there is no hole region 4 and source electrode 57 utilize dielectric film 2,20,17 and the silicon layer 21 of floating be formed with electric field relief areas ER.Thus, with identical in situation illustrated in fig. 3, be applied in high-tension source electrode 57 and the voltage that is fixed between the Semiconductor substrate 1 of earthing potential is split into the voltage drop that is caused by capacitor C1V and the voltage drop that is caused by capacitor C2V with respect to drain electrode 58, electric field is relaxed longitudinally.
(second case)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 4, this electric field relief areas ER is spaced from each other the compartment of terrain and is formed with from N as shown in figure 23
-The surface of semiconductor layer 3 arrives dielectric film 20a, 20b, the 20c of dielectric film 2.
In this case, identical with the situation that Fig. 5 is described, be applied in high-tension source electrode 57(N
-Semiconductor layer 3a) and the voltage of the silicon layer 21 of floating is split into the voltage drop that caused by capacitor C1H, the voltage drop that is caused by capacitor C2H and the voltage drop that is caused by capacitor C3H, horizontal electric field is relaxed.
(the 3rd example)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 6, this electric field relief areas ER as shown in figure 24, to cover from N
-The mode of the sidewall of the groove of the surface arrival dielectric film 2 of semiconductor layer 3 is formed with dielectric film 20a, 20b, and then is formed with in the mode of filling this groove polysilicon film 22a, the 22b that is isolated by electricity respectively.
In this case, identical with the situation that Fig. 7 is described, be applied in high-tension source electrode 57(N
-Semiconductor layer 3a) and the voltage of the silicon layer 21 of floating is split into the voltage drop that caused by capacitor C1H, the voltage drop that caused by capacitor C2H, the voltage drop that is caused by capacitor C3H and the voltage drop that is caused by capacitor C4H.Consequently, in semiconductor device SD, particularly horizontal electric field is relaxed.And, by forming simultaneously when the groove isolation construction that is formed for semiconductor element electricity isolation, thereby can form electric field relief areas ER in the situation that can not increase process number.
(the 4th example)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 8, this electric field relief areas ER is formed with the polysilicon film 22c that is isolated by electricity as shown in figure 25 in dielectric film 17.
In this case, identical with the situation that Fig. 9 is described, be applied in high-tension source electrode 57 and be fixed in that voltage between the Semiconductor substrate 1 of earthing potential is split into the voltage drop that caused by capacitor C1V, the voltage drop that is caused by capacitor C2V and the voltage drop that is caused by capacitor C3V.Consequently, in semiconductor device SD, particularly electric field is relaxed longitudinally.And, by forming simultaneously polysilicon film 22c when forming the gate electrode 56 of LDMOS, thereby can form electric field relief areas ER in the situation that can not increase process number.
(the 5th example)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 10, this electric field relief areas ER as shown in figure 26, except be formed with polysilicon film 22c in dielectric film 17, also at dielectric film 17 and float and be formed with dielectric film 23 between silicon layer 21, and be formed with the polysilicon film 22d that is isolated by electricity in this dielectric film 23.
In this case, identical with the situation that Figure 11 is described, be applied in high-tension source electrode 57(N
-Semiconductor layer 3a) and be fixed in voltage drop that voltage between the Semiconductor substrate 1 of earthing potential is split into the voltage drop that caused by capacitor C1V, caused by capacitor C2V, the voltage drop that is caused by capacitor C3V and the voltage drop that is caused by capacitor C4V.Consequently, in semiconductor device SD, particularly electric field is relaxed longitudinally.
Like this, in this semiconductor device (first case～the 5th example), in the zone that is clipped by source electrode 57 and Semiconductor substrate 1, with with source electrode 57 partly in opposite directions mode form hole region 4, the zone that does not form hole region is set on the other hand, thus, and comparing with the semiconductor device that the integral body mode in opposite directions of source electrode is formed with hole region, can suppress the reduction of the mechanical strength of semiconductor device SD when guaranteeing vertical and horizontal withstand voltage.
Execution mode 9
At this, as the semiconductor element SE5(that forms at the SOI substrate with reference to Figure 27～Figure 31), enumerate the PIN(P Intrinsic N of horizontal type) diode is that example describes.
(first case)
As shown in figure 27, be positioned at N
-Part (the N in the regulation zone of semiconductor layer 3
- Semiconductor layer 3a) in, from N
-The surface of semiconductor layer 3a is formed with N-type extrinsic region 61 as negative electrode to the degree of depth of regulation.At the N from N-type extrinsic region 61 partition distance
-The part of semiconductor layer 3a is from N
-The surface of semiconductor layer 3a is formed with p type impurity zone 62 as anode to the degree of depth of regulation.
Be formed with dielectric film 17 in the mode that covers this N-type extrinsic region 61 and p type impurity zone 62.Regulation zone on the surface of dielectric film 17 is formed with the cathode electrode 63 that contacts with N-type extrinsic region 61 via the peristome that is formed at dielectric film 17.In addition, be formed with on the surface of dielectric film 17 via regional 62 anode electrodes that contact 64 of other peristome that is formed at dielectric film 17 and p type impurity.
In addition, about the structure of in addition hole region 4 and electric field relief areas ER etc., since identical with semiconductor device SD shown in Figure 1, so to the same Reference numeral of same member mark, no longer repeat its explanation.
Then, to the semiconductor element SE5(PIN diode in above-mentioned semiconductor device SD) work describe.Apply positive voltage and target electrode 63 applies negative voltage (forward) by antianode electrode 64, thereby to N
-Semiconductor layer 3a is from N-type extrinsic region 61 injection electronics and from regional 62 injected holes of p type impurity, N
-The conductance of semiconductor layer 3a improves, and becomes the state (forward bias state) from anode side cathode side current flowing.
On the other hand, apply negative voltage and target electrode 63 applies positive voltage (oppositely) by antianode electrode 64, thereby be injected into N
-Electronics and the hole of semiconductor layer 3a finally disappear, and become the cut state of electric current (reverse-bias state).
In above-mentioned semiconductor device SD, at semiconductor element SE5(PIN diode) be under back-biased state, target electrode 63 applies positive voltage, and antianode electrode 64 applies negative voltage, thus, N
-The roughly whole zone of semiconductor layer 3a is depleted.At this moment, as what illustrated, at roughly depleted N
-The electric field of the generation of interfaces of semiconductor layer 3a and dielectric film 2 is relaxed by hole region 4.
On the other hand, the zone between the Semiconductor substrate 1 that there is no hole region 4 and cathode electrode 63 utilize dielectric film 2,20,17 and the silicon layer 21 of floating be formed with electric field relief areas ER.Thus, with identical in situation illustrated in fig. 3, the voltage that is applied in the cathode electrode 63 of positive voltage and is fixed between the Semiconductor substrate 1 of earthing potential is split into the voltage drop that is caused by capacitor C1V and the voltage drop that is caused by capacitor C2V, and electric field is relaxed longitudinally.
(second case)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 4, this electric field relief areas ER is spaced from each other the compartment of terrain and is formed with from N as shown in figure 28
-The surface of semiconductor layer 3 arrives dielectric film 20a, 20b, the 20c of dielectric film 2.
In this case, identical with the situation that Fig. 5 is described, be applied in the cathode electrode 63(N of positive voltage
-Semiconductor layer 3a) and the voltage of the silicon layer 21 of floating is split into the voltage drop that caused by capacitor C1H, the voltage drop that is caused by capacitor C2H and the voltage drop that is caused by capacitor C3H, horizontal electric field is relaxed.
(the 3rd example)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 6, this electric field relief areas ER as shown in figure 29, to cover from N
-The mode of the sidewall of the groove of the surface arrival dielectric film 2 of semiconductor layer 3 is formed with dielectric film 20a, 20b, and then is formed with in the mode of filling this groove polysilicon film 22a, the 22b that is isolated by electricity respectively.
In this case, identical with the situation that Fig. 7 is described, be applied in the cathode electrode 63(N of positive voltage
-Semiconductor layer 3a) and the voltage of the silicon layer 21 of floating is split into the voltage drop that caused by capacitor C1H, the voltage drop that caused by capacitor C2H, the voltage drop that is caused by capacitor C3H and the voltage drop that is caused by capacitor C4H.Consequently, in semiconductor device SD, particularly horizontal electric field is relaxed.And, by forming simultaneously when the groove isolation construction that is formed for semiconductor element electricity isolation, thereby can form electric field relief areas ER in the situation that can not increase process number.
(the 4th example)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 8, this electric field relief areas ER is formed with the polysilicon film 22c that is isolated by electricity as shown in figure 30 in dielectric film 17.
In this case, identical with the situation that Fig. 9 is described, be applied in the cathode electrode 63 of positive voltage and be fixed in that voltage between the Semiconductor substrate 1 of earthing potential is split into the voltage drop that caused by capacitor C1V, the voltage drop that is caused by capacitor C2V and the voltage drop that is caused by capacitor C3V.Consequently, in semiconductor device SD, particularly electric field is relaxed longitudinally.
(the 5th example)
In this semiconductor device SD, as the electric field relief areas, also can use the electric field relief areas ER same with electric field relief areas ER shown in Figure 10, this electric field relief areas ER as shown in figure 31, except be formed with polysilicon film 22c in dielectric film 17, also at dielectric film 17 and float and be formed with dielectric film 23 between silicon layer 21, and be formed with the polysilicon film 22d that is isolated by electricity in this dielectric film 23.
In this case, identical with the situation that Figure 11 is described, be applied in the cathode electrode 63(N of positive voltage
-Semiconductor layer 3a) and be fixed in voltage drop that voltage between the Semiconductor substrate 1 of earthing potential is split into the voltage drop that caused by capacitor C1V, caused by capacitor C2V, the voltage drop that is caused by capacitor C3V and the voltage drop that is caused by capacitor C4V.Consequently, in semiconductor device SD, particularly electric field is relaxed longitudinally.
Like this, in this semiconductor device (first case～the 5th example), in the zone that is clipped by cathode electrode 63 and Semiconductor substrate 1, with with cathode electrode 63 partly in opposite directions mode form hole region 4, the zone that does not form hole region is set on the other hand, thus, and comparing with the semiconductor device that the integral body mode in opposite directions of cathode electrode is formed with hole region, can suppress the reduction of the mechanical strength of semiconductor device SD when guaranteeing vertical and horizontal withstand voltage.
In addition, in the semiconductor device of each above-mentioned execution mode, the configuration structure that shows as hole region 4 is to N
-Semiconductor layer 3a and all situations of identical configuration structure of silicon layer 21 of floating.As the distortion of the configuration structure of hole region 4, can consider following such configuration structure.That is, as the zone (regional A) and the N that are conceived to be affected the Semiconductor substrate 1 that withstand voltage hole region 4 surrounds
-During the relative position relationship of semiconductor layer 3a, regional A and N with Semiconductor substrate 1 are arranged
- Semiconductor layer 3a clips dielectric film 2(BOX layer) do not have mutually the mode of part in opposite directions dispose the configuration structure (configuration structure A) of hole region 4 and with regional A and the N of Semiconductor substrate 1
- Semiconductor layer 3a clips dielectric film 2(BOX layer) mode that has mutually a part in opposite directions disposes the configuration structure (configuration structure B) of hole region 4.
As configuration structure A, the configuration structure of the hole region 4 in the semiconductor device of each above-mentioned execution mode, for example also has shown in figure 32 like that hole region 4 from N
-The configuration structure (configuration structure A1) in the zone of the region extension under semiconductor layer 3a to the silicon layer 21 of floating.In addition, also has as shown in figure 33 like that the configuration structure (configuration structure A2) that disposes hole region 4 directly over the dielectric film 2 of the side that is positioned at hole region 4 in the mode that dielectric film 20 grades are arranged.
In configuration structure A1, guaranteed to be applied in earthing potential Semiconductor substrate 1 regional A be applied in high-tension N
-Semiconductor layer 3a apart from S1, be favourable aspect withstand voltage (electric field).Yet, in this configuration structure A1, because at N
-When semiconductor layer 3 forms the groove that is filled dielectric film 20 hole region 4 be positioned at the zone that forms groove under, so be required higher precision on manufacturing process.In addition, in configuration structure A2, although regional A and the N of Semiconductor substrate 1
- Semiconductor layer 3a compares apart from S1(with reference to Figure 32 apart from S2) short, but guarantee that as being used for withstand voltage distance is sufficient distance.
On the other hand, as configuration structure B, extend to N just like the regional A with Semiconductor substrate 1 as shown in Figure 34
-The mode in the zone under semiconductor layer 3a disposes the configuration structure of hole region 4.In this configuration structure B, because at N
-When semiconductor layer 3 forms the groove that is filled dielectric film 20 the regional A of Semiconductor substrate 1 be positioned at the zone that forms groove under, so be favourable on manufacturing process.
Yet, in this configuration structure B, because have the regional A of the Semiconductor substrate 1 that is applied in earthing potential and be applied in high-tension N
-Semiconductor layer 3a is the mutual part in opposite directions of dielectric film 2 of t across thickness, so normally strict aspect withstand voltage (electric field).Thereby according to inventors' evaluation, clear and definite is, as regional A and the N of Semiconductor substrate 1
- Semiconductor layer 3a mutually in opposite directions apart from S3, need to be suppressed at N-type extrinsic region 12(with reference to Fig. 1 etc.), N-type extrinsic region 31(is with reference to Figure 12 etc.), N-type extrinsic region 42(is with reference to Figure 17 etc.), N-type extrinsic region 52(is with reference to Figure 22 etc.) or N-type extrinsic region 61(with reference to Figure 27 etc.) horizontal length left and right.
In addition, in the semiconductor device of each above-mentioned execution mode, as being formed at N
-The semiconductor element of semiconductor layer 3a is enumerated IGBT, DMOS, PIN diode is that example is illustrated.As semiconductor element, except these semiconductor elements, also can form semiconductor elements such as MOS transistor, bipolar transistor, diode, diffusion resistance and electric capacity.
Although explain and show the present invention, can be interpreted as obviously that this only is used for illustration, do not become restriction, scope of invention is made an explanation by appending claims.
Claims (12)
1. semiconductor device wherein, possesses:
Semiconductor substrate has first type surface and is applied in earthed voltage;
The first dielectric film forms in the mode of the described first type surface that covers described Semiconductor substrate;
The semiconductor layer of the conductivity type of regulation forms in the mode that covers described the first dielectric film;
The second dielectric film forms in the mode that covers described semiconductor layer;
The first electrode forms in the mode in the regulation zone that covers described the second dielectric film, and is applied in the voltage of the regulation higher than described earthed voltage,
In the zone that is clipped by described the first electrode and described Semiconductor substrate, exist:
Be formed with the zone in cavity between described Semiconductor substrate and described the first dielectric film; And
Be not formed with the zone in cavity between described Semiconductor substrate and described the first dielectric film,
Be positioned at the zone that is formed with described cavity directly over the part of described semiconductor layer be formed with the element-forming region that is electrically connected to and is formed with the semiconductor element of regulation with described the first electrode,
Be formed with the electric field relief areas between the part of the described Semiconductor substrate in the zone that be not formed with described cavity and described the first electrode,
In described electric field relief areas, be formed with at the voltage of the described regulation that is applied to described the first electrode and be applied to a plurality of capacitors that are connected in series between the described earthed voltage of described Semiconductor substrate.
2. semiconductor device according to claim 1, wherein,
In described electric field relief areas, be formed with the section of floating that is isolated by electricity between described the first dielectric film and described the second dielectric film,
Described capacitor comprises:
The first capacitor is connected to described Semiconductor substrate and described floating between section; And
The second capacitor is connected to described the first electrode and described floating between section.
3. semiconductor device according to claim 1, wherein, described capacitor comprises the 3rd capacitor, described the 3rd capacitor's series is connected to described floating between section and described element-forming region.
4. semiconductor device according to claim 3, wherein, described the 3rd capacitor comprises a plurality of the 3rd dielectric films, and described a plurality of the 3rd dielectric films consist of the dielectric of described the 3rd capacitor in the described devices spaced apart ground formation respectively between section and described element-forming region of floating.
5. semiconductor device according to claim 4, wherein, described the 3rd capacitor comprises the first conduction body of being isolated by electricity, described the first conduction body is formed at each in a plurality of described the 3rd dielectric films, consists of the electrode of described the 3rd capacitor.
6. semiconductor device according to claim 2, wherein, described the second capacitor comprises the second conduction body of being isolated by electricity, described the second conduction body is formed in described the second dielectric film, consists of the electrode of described the second capacitor.
7. semiconductor device according to claim 6, wherein,
Described the second capacitor comprises:
The 4th dielectric film is formed on described the second dielectric film and described floating between section, consists of the dielectric of described the second capacitor; And
The 3rd conduction body by the electricity isolation is formed in described the 4th dielectric film, consists of the electrode of described the second capacitor.
8. semiconductor device according to claim 1, wherein,
In described element-forming region, as described semiconductor element, be formed with the horizontal type insulated gate bipolar transistor of the n channel-type that comprises collector and emitter,
Described the first electrode is electrically connected to described collector electrode as collector electrode.
9. semiconductor device according to claim 1, wherein,
In described element-forming region, as described semiconductor element, be formed with the DMOS transistor of the horizontal type of the n channel-type that comprises drain electrode and source electrode,
Described the first electrode is electrically connected to described drain electrode as drain electrode.
10. semiconductor device according to claim 1, wherein,
In described element-forming region, as described semiconductor element, be formed with the horizontal type insulated gate bipolar transistor of the p channel-type that comprises collector and emitter,
Described the first electrode is electrically connected to described emitter as emitter electrode.
11. semiconductor device according to claim 1, wherein,
In described element-forming region, as described semiconductor element, be formed with the DMOS transistor of the horizontal type of the p channel-type that comprises drain electrode and source electrode,
Described the first electrode is electrically connected to described source electrode as source electrode.
12. semiconductor device according to claim 1, wherein,
In described element-forming region, as described semiconductor element, be formed with the horizontal type diode that comprises negative electrode and anode,
Described the first electrode is connected with described cathodic electricity as cathode electrode.
Applications Claiming Priority (2)
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| JP2012104502A JP5762353B2 (en) | 2012-05-01 | 2012-05-01 | Semiconductor device |
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| US (1) | US8710617B2 (en) |
| JP (1) | JP5762353B2 (en) |
| KR (1) | KR101459396B1 (en) |
| CN (1) | CN103383944B (en) |
| DE (1) | DE102013207698B4 (en) |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104966712A (en) * | 2015-06-05 | 2015-10-07 | 上海交通大学 | Solid-state insulating dielectric pulse power switch and preparation method thereof |
| CN106206291A (en) * | 2016-07-26 | 2016-12-07 | 电子科技大学 | A kind of RC LIGBT device and preparation method thereof |
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|---|---|---|---|---|
| JP6155911B2 (en) | 2013-07-04 | 2017-07-05 | 三菱電機株式会社 | Semiconductor device |
| US9093567B2 (en) * | 2013-11-05 | 2015-07-28 | Freescale Semiconductor, Inc. | Diodes with multiple junctions and fabrication methods therefor |
| DE102015121100B4 (en) * | 2015-12-03 | 2022-01-20 | Infineon Technologies Ag | SEMICONDUCTOR DEVICE WITH TRENCH EDGE TERMINATION |
| US10050139B2 (en) | 2016-06-24 | 2018-08-14 | Infineon Technologies Ag | Semiconductor device including a LDMOS transistor and method |
| JP7160167B2 (en) * | 2018-12-28 | 2022-10-25 | 三菱電機株式会社 | semiconductor equipment |
| JP7001050B2 (en) * | 2018-12-28 | 2022-01-19 | 三菱電機株式会社 | Semiconductor device |
| US10971632B2 (en) * | 2019-06-24 | 2021-04-06 | Semiconductor Components Industries, Llc | High voltage diode on SOI substrate with trench-modified current path |
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- 2013-04-16 KR KR1020130041467A patent/KR101459396B1/en not_active IP Right Cessation
- 2013-04-26 DE DE102013207698.3A patent/DE102013207698B4/en active Active
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| JPH0653310A (en) * | 1991-03-18 | 1994-02-25 | Toshiba Corp | Semiconductor device and its manufacture method |
| CN1518095A (en) * | 2003-01-27 | 2004-08-04 | ��ʽ���������Ƽ� | Integrated semiconductor device and its manufacturing method |
| US20050056906A1 (en) * | 2003-07-25 | 2005-03-17 | Shinichi Jimbo | Semiconductor device |
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| CN104966712A (en) * | 2015-06-05 | 2015-10-07 | 上海交通大学 | Solid-state insulating dielectric pulse power switch and preparation method thereof |
| CN104966712B (en) * | 2015-06-05 | 2017-12-15 | 上海交通大学 | A kind of solid isolation medium pulse power switch and preparation method thereof |
| CN106206291A (en) * | 2016-07-26 | 2016-12-07 | 电子科技大学 | A kind of RC LIGBT device and preparation method thereof |
| CN106206291B (en) * | 2016-07-26 | 2019-05-10 | 电子科技大学 | A kind of RC-LIGBT device and preparation method thereof |
Also Published As
| Publication number | Publication date |
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| JP5762353B2 (en) | 2015-08-12 |
| US20130292740A1 (en) | 2013-11-07 |
| JP2013232577A (en) | 2013-11-14 |
| CN103383944B (en) | 2016-03-09 |
| DE102013207698B4 (en) | 2016-09-22 |
| TWI485855B (en) | 2015-05-21 |
| TW201403820A (en) | 2014-01-16 |
| DE102013207698A1 (en) | 2013-11-07 |
| KR20130122912A (en) | 2013-11-11 |
| KR101459396B1 (en) | 2014-11-07 |
| US8710617B2 (en) | 2014-04-29 |
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