JP4624084B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device using a stacked structure in which a substrate, a dielectric layer, and an upper semiconductor layer are stacked, and a method for manufacturing the same. In particular, the present invention relates to a semiconductor device in which a dielectric layer is filled with air or a space maintained in a vacuum is formed, and a manufacturing method thereof.

A semiconductor device is known in which a semiconductor switching element is formed in an upper semiconductor layer stacked on a dielectric layer. A lateral MOSFET is known as an example of a semiconductor switching element. The npn lateral MOSFET includes an n ⁺ type drain region, an n ⁻ type drift region, a p ⁻ type body region, and an n ⁺ type source region on the surface of the upper semiconductor layer. n ⁺ -type source region p ^- which is formed in the mold body region, p ^- -type body region n ⁺ -type source region and the n ^- separating type drift region. A MOS gate is opposed to a p ⁻ type body region that separates the n ⁺ type source region and the n ⁻ type drift region. The on / off of the MOSFET is controlled by the gate voltage applied to the MOS gate. While the npn-type MOSFET is in the OFF state, a high potential is applied to the n ⁺ -type drain region, and the n ⁺ -type source region is grounded (a low potential is applied). When the lateral MOSFET is turned on, a current flows between the n ⁺ type drain region and the n ⁺ type source region, and the voltage applied to the n ⁺ type drain region decreases. In this specification, a region to which a high potential is applied when the semiconductor switching element is off is generically referred to as a high potential semiconductor region, and a semiconductor region maintained at a low potential is generically referred to as a low potential semiconductor region. In the case of the npn type MOSFET, the n ⁺ type drain region and the n ⁻ type drift region are high potential semiconductor regions, and the p ⁻ type body region and the n ⁺ type source region are low potential semiconductor regions.
When the npn-type lateral MOSFET is off, an electric field exceeding the critical electric field is concentrated on the interface between the n ⁻ -type drift region and the dielectric layer located below the n ⁺ -type drain region, so that avalanche breakdown is likely to occur. It is known. Therefore, by taking measures to increase the amount of electric field that can be held in the dielectric layer located below the n ⁺ -type drain region, the semiconductor device can have a high breakdown voltage. Patent Document 1 discloses a technique for forming a space in a dielectric layer. By forming a space in the dielectric layer and filling the space with air or maintaining a vacuum, a high electric field can be maintained by the space. That is, by forming a space in the dielectric layer, electric field concentration at the interface between the drift region and the dielectric layer can be suppressed, the amount of electric field held in the space can be increased, and thus a high breakdown voltage semiconductor device You will be able to get Patent Documents 2 to 8 also disclose reference techniques.
JP-A-6-188438 JP 2004-146461 A JP-A-11-274500 JP 2000-58649 A JP 2001-274398 A JP 2003-188250 A JP2003-188281 JP 2004-115592 A

In Patent Document 1, in order to form a space in a dielectric layer, a substrate whose surface is covered with an oxide film, a back surface is covered with an oxide film, and a recess is formed in a part of the oxide film. It proposes a method of forming a space defined by the recess by laminating semiconductor layers.
However, according to the technique of forming a space by bonding a substrate and a semiconductor layer, it is difficult to specify the position of the formed space from the outside due to the presence of the semiconductor layer. For this reason, it is difficult to match the position of the space formed inside with the position of the high potential semiconductor region. If the positional relationship between the high-potential semiconductor region and the space does not match, it is difficult to increase the breakdown voltage of the semiconductor device.
In the present invention, a semiconductor device is formed using a stacked structure in which a substrate, a dielectric layer, and an upper semiconductor layer are stacked. The present invention provides a method of manufacturing a semiconductor device in which a space formed in a dielectric layer and a high potential semiconductor region are stably adjusted to a predetermined positional relationship. In addition, the present invention provides a semiconductor device in which a space formed in a dielectric layer and a high potential semiconductor region are stably adjusted to a predetermined positional relationship.

In one manufacturing method of a semiconductor device disclosed in this specification, a high-potential semiconductor region and a low-potential semiconductor region are formed in the upper semiconductor layer of a stacked structure in which a substrate, a dielectric layer, and an upper semiconductor layer are stacked. And manufacturing a semiconductor device by forming a space between the high potential semiconductor region and the substrate, the step of forming the high potential semiconductor region in the upper semiconductor layer, and the high potential semiconductor region And forming a trench that penetrates the high potential semiconductor region and reaches the dielectric layer from the surface of the upper semiconductor layer, and selects the dielectric layer by an etching fluid supplied to the trench. And etching to form the space over a predetermined distance from the trench.
Another method for manufacturing a semiconductor device disclosed in the present specification is to form a high potential semiconductor region in the upper semiconductor layer of a stacked structure in which a substrate, a dielectric layer, and an upper semiconductor layer are stacked. A method of manufacturing a semiconductor device by forming a space between the high-potential semiconductor region and the substrate, forming a mask layer with an opening on the surface of the stacked structure, and exposing at an opening of the mask layer A trench forming step of forming a trench reaching the dielectric layer from the surface of the upper semiconductor layer, and selectively etching the dielectric layer with an etching fluid supplied to the trench, and the etching is performed over a predetermined distance from the trench. An etching step for forming a space, an enlargement step for enlarging a cross section of the trench rather than an opening of the mask layer, and after the etching step and the enlargement step And a step of closing the trench while leaving the space between the upper semiconductor layer and the substrate, and in the closing step, the trench is closed by a CVD method over the mask layer. It is characterized by.
The technology disclosed in this specification forms a high-potential semiconductor region in an upper semiconductor layer of a stacked structure in which a substrate, a dielectric layer, and an upper semiconductor layer are stacked. The present invention relates to a method for manufacturing a semiconductor device by forming a space therebetween.
Another manufacturing method disclosed in this specification includes a step of forming a trench reaching the dielectric layer from the surface of the upper semiconductor layer in the vicinity of the high potential semiconductor region, and a dielectric by an etching fluid supplied to the trench. And a step of selectively etching the body layer to form a space over a predetermined distance from the trench.
The high potential semiconductor region means a semiconductor region to which a high potential is applied when the semiconductor switching element is off, and includes, for example, a drain region, a collector region, or a cathode region. The etching fluid is a material whose etching rate of the dielectric layer is larger than that of the substrate and the upper semiconductor layer, and can mainly etch the dielectric layer. The etching fluid is often a liquid, but may be a gas.
According to the above manufacturing method, the etching fluid can be supplied to the dielectric layer using the trench, the dielectric layer extending from the trench toward the side can be etched, and the trench from the trench to the side. A space extending over a predetermined distance can be formed. Since the trench is formed in the vicinity of the high potential semiconductor region, a space is formed between the high potential semiconductor region and the substrate. A space is formed between the high potential semiconductor region and the substrate as long as the positional relationship between the trench exposed on the surface of the multilayer structure and the high potential semiconductor region formed on the surface side of the multilayer structure is taken into consideration. The positional relationship between the high potential semiconductor region and the space is stably adjusted to a predetermined positional relationship.
Since a space can be formed under the high potential semiconductor region and a high electric field can be maintained in the space, a high breakdown voltage semiconductor device can be obtained.

A high potential semiconductor region forming step may be performed after the trench forming step.
According to the above manufacturing method, since the high potential semiconductor region can be formed in the vicinity of the trench, the positional relationship between the high potential semiconductor region and the space can be matched.

Prior to the trench formation step, a high potential semiconductor region formation step may be performed.
According to the above manufacturing method, since the trench can be formed in the vicinity of the high potential semiconductor region, the positional relationship between the high potential semiconductor region and the space can be matched.

In the trench formation step, it is preferable to form a plurality of trench groups in the vicinity of the high potential semiconductor region.
According to the above manufacturing method, it is possible to form a space that spreads in a plane in a range where the trench group is dispersed. Since a space extending not only directly under the high potential semiconductor region but also laterally can be formed, a semiconductor device capable of maintaining a high electric field in a wide range can be obtained. In addition, a semiconductor device with a high breakdown voltage can be obtained.

After the etching step, it is preferable to perform a step of closing the trench while leaving a space between the upper semiconductor layer and the substrate.
There is no particular limitation on the method for closing the trench and the material used for closing. As a material used for closing, for example, a material mainly composed of silicon nitride, a material mainly composed of silicon oxide, polysilicon, aluminum, tungsten, or the like can be suitably used.
A space formed between the upper semiconductor layer and the substrate, that is, a space extending in the dielectric layer can be sealed from the outside, and the environment of the space can be maintained.

In the closing step, it is preferable to close the trench by a CVD method.
By appropriately selecting the type of reaction gas, the trench can be closed with a desired material.

Prior to the trench formation step, it is preferable to perform a step of forming a mask layer with an opening on the surface of the laminated structure. Prior to the closing step, it is preferable to perform a step of enlarging the cross section of the trench rather than the opening of the mask layer. In the closing step, it is preferable to perform the CVD method over the mask layer.
According to the above manufacturing method, it is possible to create a gas flow that blows into a wide trench after passing through a narrow opening. When the gas is blown into the wide trench after passing through the narrow opening, the gas swirls and the gas flow toward the trench side wall is activated. Crystals can be grown from the side wall of the trench, and the trench can be closed while leaving a space below.

In one semiconductor device disclosed in this specification, a high potential semiconductor region and a low potential semiconductor region are formed in the upper semiconductor layer of an SOI substrate in which a substrate, a dielectric layer, and an upper semiconductor layer are stacked. In the semiconductor device, a space is formed between the high-potential semiconductor region and the substrate, and a blocking member that blocks the trench that penetrates the high-potential semiconductor region and reaches the space from the surface of the upper semiconductor layer. The space extends in the same plane as the dielectric layer, is formed below the high-potential semiconductor region, and is not formed below the low-potential semiconductor region. Features.
In another semiconductor device disclosed in this specification , a high potential semiconductor region is formed in an upper semiconductor layer of a stacked structure in which a substrate, a dielectric layer, and an upper semiconductor layer are stacked. A space is formed between the semiconductor region and the substrate. Another semiconductor device disclosed in this specification is characterized in that a closing member that closes a trench reaching the dielectric layer from the surface of the upper semiconductor layer exists in the vicinity of the high-potential semiconductor region. .
This semiconductor device represents a semiconductor device embodied by the manufacturing method disclosed in this specification . In this semiconductor device, a space is formed between the high-potential semiconductor region and the substrate. Since a high electric field can be maintained in this space, the breakdown voltage is increased.

It is preferable that a plurality of blocking members are arranged in the vicinity of the high potential semiconductor region.
A wide space is formed corresponding to the area where the trench counties are dispersed. Therefore, a semiconductor device with a higher breakdown voltage is obtained.

  According to the present invention, the positional relationship between the space formed in the dielectric layer and the high potential semiconductor region can be stably adjusted to a predetermined positional relationship, and a high breakdown voltage semiconductor device can be stably manufactured. .

The main features of the examples are listed.
(First Embodiment) The semiconductor switching element has a concentric structure.
(Second Embodiment) The thickness and impurity concentration of the drift region are adjusted so that the RESURF effect is obtained.
(Third embodiment) The trenches and the blocking members are distributed at substantially equal intervals.
(Fourth Mode) The space is substantially from the high potential semiconductor region toward the low potential semiconductor region in a plane parallel to the direction connecting the high potential semiconductor region (eg, drain region) and the low potential semiconductor region (eg, source region). It is formed in a flat shape.

1 and 2 are longitudinal sectional views of the semiconductor device 10. FIG. 3 shows a cross-sectional view corresponding to line III-III in FIGS. FIG. 1 is a longitudinal sectional view corresponding to the line II in FIG. 3, and FIG. 2 is a longitudinal section corresponding to the line II-II. Although the semiconductor device 10 is formed using a semiconductor material containing silicon as a main component, the same effects as described below can be obtained even when other semiconductor materials are used.
The semiconductor device 10 includes a semiconductor substrate 22. A dielectric layer 24 is stacked on the upper surface of the semiconductor substrate 22. An upper semiconductor layer 26 is stacked on the upper surface of the dielectric layer 24. The dielectric layer 24 is buried between the semiconductor substrate 22 and the upper semiconductor layer 26.
The semiconductor substrate 22 is formed of silicon single crystal and is grounded via a back electrode or the like (not shown). The buried dielectric layer 24 is made of silicon oxide and is locally removed to form a space 62. The space 62 is in a substantially vacuum state. When the space 62 is viewed in plan, it spreads in a substantially circular shape, and has a substantially cylindrical shape with a low height. As will be described later, the space 62 extends laterally with the lower position of the drain region 48 as the center.

The n ⁻ type upper semiconductor layer 26 is formed of silicon single crystal and covers the space 62. The upper semiconductor layer 26 is widened laterally from the range shown in FIGS. 1 to 3, and a plurality of semiconductor devices (not shown) of a type different from the semiconductor device 10 are incorporated in the widened range. It is generally called a composite element or a composite device.
In the upper semiconductor layer 26, an insulating isolation trench 32 is formed that makes a circular ring around the area where the space 62 is formed. The insulating isolation trench 32 is made of silicon oxide and extends from the surface of the upper semiconductor layer 26 to the buried dielectric layer 24. The insulating isolation trench 32 insulates and isolates the inner island region from the remaining upper semiconductor layer 26. In this embodiment, a lateral MOSFET is formed in this island region. Note that the upper semiconductor layer 26 in the island region can be referred to as a drift region 47 when evaluated from the functional aspect of the MOSFET. The thickness of the drift region 47 (the thickness of the upper semiconductor layer 26 and the thickness in the vertical direction of the paper) and the impurity concentration are adjusted so that the RESURF effect is obtained.

A p ⁻ -type body region 42 that makes a circuit along the insulating isolation trench 32 is formed on the surface of the island-shaped region. An n ⁺ -type source region 46 and a p ⁺ -type body contact region 44 are formed on the surface portion in the body region 42. The n ⁺ type source region 46 and the p ⁺ type body contact region 44 make a round along the body region 42. Source region 46 is separated from drift region 47 by body region 42. The source region 42 and the body contact region 44 are in contact with the source electrode S. A gate electrode G made of polysilicon is opposed to the surface of the body region 42 that separates the source region 46 and the drift region 47 through a gate insulating film 52 made of silicon oxide.

As shown in FIGS. 1 and 3, a drain region 48 (an example of a high-potential semiconductor region) is formed at a substantially central portion of the island-shaped region. A trench that penetrates the drain region 48 and reaches the space 62 from the surface of the upper semiconductor layer 26 is formed, and the closing member 34 closes the trench. The closing member 34 closes the trench from the vicinity of the bottom of the trench to the surface, and is in direct contact with the drain region 48. The closing member 34 is made of silicon nitride and has a circular cross section as shown in FIG. The drain region 48 is formed on the surface of the upper semiconductor layer 26 at a position surrounding the periphery of the closing member 34. The drain region 48 is in contact with the drain electrode D.
As shown in FIGS. 2 and 3, a plurality of trenches are formed in the vicinity of the drain region 48, and each is closed with a closing member 36 made of silicon nitride. The blocking member 36 group reaches a space 62 that spreads in a plane from the surface of the drift region 47. The blocking member 36 group is distributed at substantially equal intervals around the drain region 48. The cross section of the blocking member 36 group is circular as shown in FIG.
A field oxide film 54 extends from the vicinity of the drain region 34 to the gate electrode G on the surface of the drift region 47. The field oxide film 54 can alleviate the electric field at the surface portion of the drift region 47.

Next, the operation when the semiconductor device 10 is turned on will be described.
When a voltage higher than the threshold voltage is applied to the gate electrode G in a state where the source electrode S is grounded and a positive voltage is applied to the drain electrode D, an inversion layer is formed in the body region 42 facing the gate electrode G. As a result, the semiconductor device 10 is turned on. The current flows from the drain region 48 to the source region 46 via the drift region 47 and the inversion layer.
Although the blocking members 36 are made of insulating silicon nitride, the blocking members 36 are arranged in a distributed manner, so that the current flow is not hindered. Current can flow from the drain region 48 to the source region 46.

Next, the operation when the semiconductor device 10 is off will be described.
When a voltage lower than the threshold voltage is applied to the gate electrode G while the source electrode S is grounded and a positive voltage is applied to the drain electrode D, the inversion layer in the body region 42 facing the gate electrode G is It disappears and the semiconductor device 10 is turned off. At this time, the drift region 47 is depleted in a wide range by a depletion layer extending from the pn junction interface with the body region 42 and a depletion layer extending from the interface with the buried dielectric layer 24 or the space 62 on the back surface. Since the semiconductor device of this embodiment has a concentric structure, a region where the depletion layer extends can be formed in a well-balanced manner. Thereby, the electric field of the surface part of the drift region 47 is relaxed, and a RESURF effect can be obtained.
Since the semiconductor substrate 22 is grounded when the semiconductor device 10 is off, it is necessary to maintain a potential difference corresponding to the voltage applied to the drain region 48 in the vertical direction of the semiconductor device 10. The semiconductor device 10 has a space 62 below the drain region 48. The space 62 can hold a high electric field as compared with the case of the embedded dielectric layer 24 alone. Therefore, the potential difference shared by the space 62 is large, and as a result, the electric field value in the drift region 47 can be reduced. This phenomenon will be described with reference to FIG. FIG. 12 shows the electric field distribution in the semiconductor device 10.
The horizontal axis of FIG. 12 indicates the electric field strength, and the vertical axis indicates the depth of the semiconductor device 10. Each symbol on the vertical axis corresponds to each region of the semiconductor device 10. 10 in the figure indicated by the solid line is the electric field intensity distribution of the semiconductor device 10, and 12 in the figure indicated by the broken line is the electric field intensity distribution in the comparative example that does not have the space 62. As shown in FIG. 12, by forming the space 62, a high electric field can be maintained in that region. Therefore, the amount of electric field that can be held in the vertical direction can be increased without increasing the electric field strength at the interface between the drift region 47 and the space 62. An electric field exceeding the critical electric field is concentrated at the interface between the drift region 47 and the space 62 below the drain region 48, and avalanche breakdown is likely to occur. However, as described above, by increasing the electric field held in the space 62, the drift region The electric field concentration at the interface between the space 47 and the space 62 can be kept low. Therefore, avalanche breakdown at this interface is suppressed, and as a result, a semiconductor device with a high breakdown voltage is obtained.
Furthermore, in the present embodiment, since the space 62 is spread out in a plane, a high electric field can be maintained not only in the space 62 positioned below the drain region 48 but also in the range where the space 62 extends sideways. Therefore, the semiconductor device has a higher breakdown voltage.
Further, in comparison with the conventional structure, the semiconductor device can be made thinner while obtaining the same breakdown voltage.

Next, a method for manufacturing the semiconductor device 10 will be described with reference to FIGS.
First, an SOI substrate is prepared in which a semiconductor substrate 22 made of silicon single crystal, a buried dielectric layer 24 made of silicon oxide, and an upper semiconductor layer 26 made of n ⁻ -type silicon single crystal are stacked.
Next, a trench reaching the buried dielectric layer 24 from the surface of the upper semiconductor layer 26 is formed by, for example, the RIE (Reactive Ion Etching) method. Next, a thermal oxidation method, a CVD (Chemical Vapor Deposition) method, or the like is performed to fill the trench with silicon oxide, thereby forming the insulating isolation trench 32. As shown in FIG. 3, the insulating isolation trench 32 is formed in a circle. The island-shaped region surrounded by the insulating isolation trench 32 is isolated from the remaining upper semiconductor layer 26. The upper semiconductor layer 26 in the island region is used as a drift region 47 of the MOSFET.

Next, as shown in FIG. 5, a mask layer 72 made of silicon nitride (Si ₃ N ₄ ) is formed on the surface of the upper semiconductor layer 26 by, eg, CVD. On the mask layer 72, a resist film 74 in which circular openings 74a and 74b are dispersedly arranged is formed by using a photolithography technique. The opening 74 a corresponds to the central closing member 34 shown in FIGS. 1 to 3, and the opening width is slightly narrower than the width of the central closing member 34. The opening 74b corresponds to the group of closing members 36 shown in FIGS. 1 to 3, and the opening width is formed to be slightly narrower than the width of the closing member 36 group. The reason why the opening width is narrow is made clear by a later process.

Next, as shown in FIG. 6, a buried dielectric is formed by a dry etching method using a gas such as sulfur hexafluoride (SF ₆ ), nitrogen trifluoride (NF ₃ ), or silicon tetrafluoride (SiF ₄ ). Trenches 76a and 76b reaching the body layer 24 are formed.
Next, as shown in FIG. 7, after removing the resist film 74, trenches 76a and 76b are defined by a CDE (Chemical Dry Etching) method using, for example, a mixed gas of tetrafluoromethane (CF ₄ ) and oxygen. The side wall (formed on the upper semiconductor layer 26) to be selectively etched is slightly etched. Thereby, the widths of the trenches 76a and 76b are increased from L1 to L2, and the cross section is enlarged. Since the mask layer 72 is not etched, a step is formed between the mask layer 72 and the side walls that define the trenches 76a and 76b in the direction in which the trenches 76a and 76b extend (the vertical direction in the drawing).
Next, as shown in FIG. 8, for example, an etchant such as hydrofluoric acid (HF), dilute hydrogen fluoride water (DHF), or buffered hydrofluoric acid (BHF) is supplied to the trenches 76a and 76b to embed the dielectric. Layer 24 is wet etched. Instead of wet etching, gas etching using a mixed gas of hydrofluoric acid and methanol may be used. Thereby, the buried dielectric layer 24 is isotropically etched. Accordingly, the space 62 extending from the adjacent trenches 76a and 76b is connected to obtain a space 62 that is spread in a plane. Here, let us consider a case where, in the wet etching process, only the trench 76a is formed and the trench 76b group is not formed. In this case, when the etching solution is supplied through the trench 76a to form the space 62 that is spread over the surface, the time required for the wet etching process becomes long, and the side wall that defines the trench 76a is deteriorated by the etching solution. May occur. For this reason, the problem that the characteristic of a semiconductor device deteriorates may generate | occur | produce. On the other hand, by forming a plurality of trenches 76b as in the present embodiment, a space that spreads in a plane can be formed in a short time, and the side walls that define the trenches 76a and 76b are deteriorated. The situation can be avoided. Even when only the trench 76 a is formed, a space can be formed below the drain region 48. Therefore, a high breakdown voltage semiconductor device can be obtained.

Next, as shown in FIG. 9, the trenches 76 a and 76 b are closed with silicon nitride by plasma CVD using a plasma gas such as a mixed gas of monosilane (SiH ₄ ) and ammonia (NH ₃ ). At this time, the gas that has entered the trenches 76a and 76b is swirled by a step between the silicon nitride film 72 and the side walls that define the trenches 76a and 76b, and an air flow toward the side walls that define the trenches 76a and 76b is formed. Therefore, crystals grow preferentially on the surface of the side wall that defines the trenches 76a and 76b. Therefore, it is possible to selectively close only the trenches 76a and 76b without closing the space 62. Thereby, the central closing member 34 and the closing member 36 group are formed. By forming the central blocking member 34 and the blocking member 36 group, the heat dissipation of the semiconductor device 10 is improved. Further, there is a case where a resist film or the like is applied to the surface of the upper semiconductor layer 26 in a later process. In such a process, a situation in which a resist film or the like enters the trenches 76a and 76b can be avoided. Since the plasma CVD method is performed under reduced pressure, the formed space 62 is in a substantially vacuum state. Generation | occurrence | production of dew condensation etc. can be suppressed because the space 62 is a substantially vacuum state.

Next, after planarizing the surface of the upper semiconductor layer 26 using, for example, a CMP (Chemical Mechanical Polishing) technique, ion implantation is performed in a region surrounding the central blocking member 34 as shown in FIG. Thus, the drain region 48 is formed. Thereby, a state in which the space 62 exists below the drain region 48 can be obtained with certainty.
Thereafter, by using a conventionally known technique or a technique that can be easily conceived by those skilled in the art, another structure of the MOSFET shown in FIGS. 1 to 3 can be formed, and the semiconductor device 10 can be obtained.

The above manufacturing method may be the following modification.
In the state shown in FIG. 4, the drain region 48 may be formed first on the surface portion of the drift region 47. In this case, a trench is formed from the vicinity of the drain region 48, and the space 62 is formed using the trench. As a result, the positional relationship between the drain region 48 and the space 62 is always stable, and the positional relationship in which the drain region 48 exists almost at the center position in the space 62 when viewed in plan can be reliably obtained.
The blocking member 36 group may use a conductive material, for example, silicon, polysilicon, aluminum, tungsten, or the like containing impurities instead of silicon nitride. In this case, the on-resistance of the semiconductor device can be reduced.
Further, in order to close the trench, it is possible to use a highly viscous coating film instead of the CVD method.
Further, the semiconductor device 100 shown in the cross-sectional view of the main part in FIG. This modification is an example in which arc-shaped blocking members 136 are distributed around the drain region 148. In this case, a current can flow through between the adjacent blocking members 136 (182 in the figure). By adjusting the width between the blocking members 136, the number of divisions of the arc-shaped blocking member 136, or the like, a desired amount of current can be realized in the semiconductor device. Also in this case, the space can be reliably formed below the drain region 148 by forming the space using the trench corresponding to the arc-shaped closing member 136.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In the above embodiment, an example in which a MOSFET is formed as a semiconductor switching element has been described. However, for example, a semiconductor switching element such as a diode, IGBT, or thyristor may be formed.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

The principal part sectional view corresponding to the II line of Drawing 3 is shown. The principal part sectional view corresponding to the II-II line of Drawing 3 is shown. The principal part sectional drawing corresponding to the III-III line of Drawing 1 and Drawing 2 is shown. Sectional drawing of the principal part of the semiconductor device in the middle of a manufacturing process is shown (1). Sectional drawing of the principal part of the semiconductor device in the middle of a manufacturing process is shown (2). Sectional drawing of the principal part of the semiconductor device in the middle of a manufacturing process is shown (3). Sectional drawing of the principal part of the semiconductor device in process of a manufacturing process is shown (4). Sectional drawing of the principal part of the semiconductor device in the middle of a manufacturing process is shown (5). Sectional drawing of the principal part of the semiconductor device in the middle of a manufacturing process is shown (6). Sectional drawing of the principal part of the semiconductor device in the middle of a manufacturing process is shown (7). The principal part sectional drawing of the semiconductor device of a modification is shown. The electric field strength distribution of the semiconductor device of an Example is shown.

Explanation of symbols

22: semiconductor substrate 24: buried dielectric layer 26: upper semiconductor layer 32: insulation isolation trench 34: central blocking member 36: blocking member 42: body region 44: body contact region 46: source region 47: drift region 48: drain region 52: Gate insulating film 54: Field oxide film 62: Space 72: Mask layer

Claims (8)

Together with the substrate and the dielectric layer and the upper semiconductor layer to form a high potential semiconductor region and a low-potential semiconductor region in the upper semiconductor layer of the laminated structure are stacked, the space between the substrate and the high-potential semiconductor region Is a method for manufacturing a semiconductor device,
Forming the high potential semiconductor region in the upper semiconductor layer;
After forming the high-potential semiconductor region, a trench forming step of forming a trench through the high-potential semiconductor region reaches the dielectric layer from the surface of the upper semiconductor layer,
And an etching step of selectively etching the dielectric layer by etching fluid supplied to the trench, to form the space ranging from the trench to a predetermined distance,
A method for manufacturing a semiconductor device, comprising: Wherein the trench forming step, between the high-potential semiconductor region and the low potential semiconductor region, a manufacturing method of claim 1, wherein the forming a plurality of trenches groups. Wherein after the etching process, the leaving a space between the upper semiconductor layer and the substrate, the manufacturing method according to claim 1 or 2 which comprises carrying out the occlusion process for closing the trench. 4. The manufacturing method according to claim 3 , wherein in the closing step, the trench is closed by a CVD method. And the step of forming the apertured mask layer on the surface of the laminated structure before the trench formation step,
Prior to the closing step, than the opening of the mask layer and performing step to expand the cross-section of the trench,
5. The manufacturing method according to claim 4 , wherein, in the closing step, a CVD method is performed over the mask layer. A high potential semiconductor region is formed in the upper semiconductor layer of the stacked structure in which a substrate, a dielectric layer, and an upper semiconductor layer are stacked, and a space is formed between the high potential semiconductor region and the substrate to form a semiconductor A method of manufacturing a device,
Forming a mask layer with an opening on the surface of the laminated structure;
Forming a trench reaching the dielectric layer from the surface of the upper semiconductor layer exposed in the opening of the mask layer;
An etching step of selectively etching the dielectric layer with an etching fluid supplied to the trench to form the space over a predetermined distance from the trench;
An enlarging step of enlarging the cross section of the trench rather than the opening of the mask layer;
After the etching step and the expansion step, the step of closing the trench while leaving the space between the upper semiconductor layer and the substrate,
In the closing step, the trench is closed by a CVD method over the mask layer. High potential semiconductor region and a low-potential semiconductor region in the upper semiconductor layer of the SOI substrate in which the substrate and the dielectric layer and the upper semiconductor layer is laminated and is formed, the space between the substrate and the high-potential semiconductor region Is a semiconductor device formed,
There is a blocking member that blocks the trench that penetrates the high potential semiconductor region and reaches the space from the surface of the upper semiconductor layer,
The space extends in the same plane as the dielectric layer, is formed below the high-potential semiconductor region, and is not formed below the low-potential semiconductor region. . 8. The semiconductor device according to claim 7 , wherein a plurality of blocking members are distributed between the high potential semiconductor region and the low potential semiconductor region .

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