JP5124999B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP5124999B2
JP5124999B2 JP2006166177A JP2006166177A JP5124999B2 JP 5124999 B2 JP5124999 B2 JP 5124999B2 JP 2006166177 A JP2006166177 A JP 2006166177A JP 2006166177 A JP2006166177 A JP 2006166177A JP 5124999 B2 JP5124999 B2 JP 5124999B2
Authority
JP
Japan
Prior art keywords
region
semiconductor device
conductivity type
type
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006166177A
Other languages
Japanese (ja)
Other versions
JP2007335658A (en
Inventor
功 吉川
節子 脇本
均 栗林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2006166177A priority Critical patent/JP5124999B2/en
Priority to US11/763,625 priority patent/US8080846B2/en
Priority to DE102007027519.8A priority patent/DE102007027519B4/en
Publication of JP2007335658A publication Critical patent/JP2007335658A/en
Application granted granted Critical
Publication of JP5124999B2 publication Critical patent/JP5124999B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

この発明は、主として電力変換装置等に使用される半導体装置およびその製造方法に関し、特にダイオード、ＭＩＳＦＥＴまたはＩＧＢＴ等のパワー半導体装置に設けられた終端構造に特徴を有する半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device mainly used for a power converter and the like and a manufacturing method thereof, and more particularly to a semiconductor device characterized by a termination structure provided in a power semiconductor device such as a diode, MISFET or IGBT, and a manufacturing method thereof.

一般に、ダイオードやＭＩＳＦＥＴ（金属−絶縁膜−半導体構造を有する絶縁ゲート型電界効果トランジスタ）やＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）等のデバイスは、一枚の半導体ウェハ内に多数、形成される。そのようなデバイスでは、終端構造として、プレーナ型の接合終端構造が採用されることが多い。プレーナ型の接合終端構造は、その構造部内に電界の曲率部分を有するため、活性部内の平面状の接合に比べて電界集中による高電界部分ができやすい。   In general, a large number of devices such as diodes, MISFETs (insulated gate field effect transistors having a metal-insulating film-semiconductor structure), and IGBTs (insulated gate bipolar transistors) are formed in one semiconductor wafer. Such a device often employs a planar junction termination structure as the termination structure. Since the planar junction termination structure has a curvature portion of the electric field in the structure portion, a high electric field portion due to electric field concentration is easily formed as compared with the planar junction in the active portion.

終端構造部内に高電界部分ができると、活性部よりも先に終端構造部がブレークダウンの臨界電界に到達するため、低い耐圧となってしまう。そこで、従来より、プレーナ型の接合終端構造として、フローティングガードリング構造、フィールドプレート構造またはリサーフ構造等や、それらを適宜組み合わせた構造を採用することによって、耐圧を確保している（例えば、特許文献１、特許文献２参照。）。   If a high electric field portion is formed in the termination structure portion, the termination structure portion reaches a breakdown critical electric field before the active portion, resulting in a low breakdown voltage. Therefore, conventionally, as a planar type junction termination structure, a floating guard ring structure, a field plate structure, a RESURF structure, or the like, or a structure in which they are appropriately combined, is secured (for example, Patent Documents). 1, see Patent Document 2.).

また、ｐ型仕切り領域とｎ型ドリフト領域を交互に複数並置した超接合型半導体装置に関して、終端構造領域の下にまでｐ型仕切り領域とｎ型ドリフト領域の超接合層を形成した装置が公知である（例えば、特許文献３、特許文献４参照。）。このような装置では、終端構造領域の下の超接合層は、ｐ型仕切り領域とｎ型ドリフト領域のチャージバランスを保つものか、またはドリフト層と同一導電型の層を付け加えフローティングガードリング構造、フィールドプレート構造またはリサーフ構造を形成した構造となっている。また、超接合層を有する活性部の外側に絶縁領域を設け、この絶縁領域で耐圧を保持するようにした超接合型半導体装置が公知である（例えば、特許文献５参照。）。   Also, with respect to a superjunction semiconductor device in which a plurality of p-type partition regions and n-type drift regions are juxtaposed alternately, a device in which a super-junction layer of a p-type partition region and an n-type drift region is formed under the termination structure region is known. (For example, see Patent Document 3 and Patent Document 4). In such a device, the superjunction layer under the termination structure region maintains the charge balance between the p-type partition region and the n-type drift region, or adds a layer having the same conductivity type as the drift layer, and a floating guard ring structure, A field plate structure or a RESURF structure is formed. Also, a superjunction semiconductor device is known in which an insulating region is provided outside an active portion having a superjunction layer, and the withstand voltage is maintained in the insulating region (see, for example, Patent Document 5).

ここで、超接合型半導体装置とは、ドリフト層が、一様、かつ単一の導電型層ではなく、第１導電型の半導体領域（例えば、ｎ型のドリフト領域）と第２導電型の半導体領域（例えば、ｐ型の仕切り領域）が交互に繰り返し接合された層になっている半導体装置のことである。   Here, in the super junction type semiconductor device, the drift layer is not a uniform and single conductivity type layer, but a first conductivity type semiconductor region (for example, an n-type drift region) and a second conductivity type. It is a semiconductor device in which semiconductor regions (for example, p-type partition regions) are layers that are alternately and repeatedly joined.

特開平２−２２８６９号公報JP-A-2-22869 特開２００１−１８５７２７号公報JP 2001-185727 A 特開２００４−３１９７３２号公報JP 2004-319732 A 特開２００３−１１５５８９号公報JP 2003-115589 A 特開２００１−２４４４６１号公報JP 2001-244461 A

しかしながら、従来のプレーナ型の接合終端構造は、活性部の周囲に形成され、かつその表面が、耐圧を支える主接合のある活性部の表面と同一の表面に形成されることが多い。その場合、平面状のｐｎ接合により生じる電界上昇と、終端構造部内の接合面に曲率部分があることによって電界集中が起こり、高電界部分が生じることとの相乗効果によって、活性部よりも先に終端構造部がブレークダウンの臨界電界に到達してしまい、耐圧が低くなってしまうという問題点がある。ここで、耐圧を支える主接合とは、逆方向に電圧が印加されるｐｎ接合のことである。   However, the conventional planar junction termination structure is often formed around the active portion, and its surface is often formed on the same surface as the surface of the active portion having the main junction that supports the breakdown voltage. In that case, the electric field concentration caused by the planar pn junction and the electric field concentration occurs due to the presence of the curvature portion on the junction surface in the termination structure portion, and the synergistic effect that the high electric field portion occurs, before the active portion. There is a problem in that the termination structure part reaches a critical electric field for breakdown and the breakdown voltage is lowered. Here, the main junction that supports the breakdown voltage is a pn junction to which a voltage is applied in the reverse direction.

この発明は、上述した従来技術による問題点を解消するため、接合終端構造の耐圧を向上させた半導体装置およびその製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a manufacturing method thereof in which the breakdown voltage of a junction termination structure is improved in order to eliminate the above-described problems caused by the prior art.

上述した課題を解決し、目的を達成するため、請求項１の発明にかかる半導体装置は、半導体基板の厚さ方向に電流を流す縦型の半導体装置であって、前記半導体基板の表面側に選択的に形成された第２導電型ベース領域と、該半導体基板の裏面側の第１導電型半導体基板層と、該第１導電型半導体基板層と該第２導電型ベース領域の間であって該第１導電型半導体基板層よりも低不純物濃度の第１導電型ドリフト層とからなる活性部領域と、前記第２導電型ベース領域に電気的に接続された第１主電極と、前記半導体基板の切断面に沿った外周四面に形成される第１導電型ピラー領域と、前記活性部領域を囲み、かつ該活性部領域から第１導電型ピラー領域までの間すべてと該半導体基板の表面から前記第１導電型半導体基板層までの間すべてとにかけて形成される第２導電型半導体領域を有する終端構造部と、前記半導体基板の裏面側に電気的に接続された第２主電極と、を備えることを特徴とする。 In order to solve the above-described problems and achieve the object, the semiconductor device according to the invention of claim 1 is a vertical semiconductor device that allows current to flow in the thickness direction of the semiconductor substrate, and is provided on the surface side of the semiconductor substrate. a second conductivity type base region selectively formed between the semiconductor substrate and the back surface-side first conductivity type semiconductor substrate layer of, the first conductivity type semiconductor substrate layer and said second conductivity type base region met An active region composed of a first conductivity type drift layer having a lower impurity concentration than the first conductivity type semiconductor substrate layer, a first main electrode electrically connected to the second conductivity type base region, A first conductivity type pillar region formed on four outer peripheral surfaces along a cut surface of the semiconductor substrate; and all of the region between the active part region and the first conductivity type pillar region surrounding the active part region and the semiconductor substrate; A space from the surface to the first conductive type semiconductor substrate layer A terminal structure having a second conductivity type semiconductor region formed over the Tet, characterized in that it comprises a second main electrode electrically connected to the back surface side of the semiconductor substrate.

また、請求項２の発明にかかる半導体装置は、請求項１に記載の発明において、前記第２導電型半導体領域に更に第１導電型半導体領域を付加し、該第２導電型半導体領域の平均不純物濃度から第１導電型半導体領域の平均不純物濃度を差し引いた平均不純物濃度が２．５×１０14ｃｍ-3以下の第２導電型であることを特徴とする。 A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein a first conductive type semiconductor region is further added to the second conductive type semiconductor region, and an average of the second conductive type semiconductor region is provided. An average impurity concentration obtained by subtracting the average impurity concentration of the first conductivity type semiconductor region from the impurity concentration is a second conductivity type of 2.5 × 10 14 cm −3 or less.

また、請求項３の発明にかかる半導体装置は、請求項１又は請求項２に記載の発明において、前記第１導電型ドリフト層が、第１導電型のドリフト領域、又は交互に複数配置した第１導電型のドリフト領域と第２導電型の仕切り領域であることを特徴とする。 A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein the first conductivity type drift layer is a first conductivity type drift region or a plurality of alternately arranged drift regions. It is a drift region of one conductivity type and a partition region of a second conductivity type.

また、請求項４の発明にかかる半導体装置は、請求項１〜３のいずれか一つに記載の発明において、前記第２導電型半導体領域と前記第１導電型ドリフト層の接合界面が傾斜していることを特徴とする。 According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the junction interface between the second conductive type semiconductor region and the first conductive type drift layer is inclined. It is characterized by.

また、請求項５の発明にかかる半導体装置は、請求項１〜４のいずれか一つに記載の発明において、前記第２導電型半導体領域と、前記第１導電型半導体基板層との間に、絶縁層が付加されていることを特徴とする。 A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein the second conductive type semiconductor region and the first conductive type semiconductor substrate layer are interposed between the second conductive type semiconductor region and the first conductive type semiconductor substrate layer. In addition , an insulating layer is added .

また、請求項６の発明にかかる半導体装置は、請求項１〜５のいずれか一つに記載の発明において、前記第２導電型半導体領域が、前記第２導電型ベース領域に接していることを特徴とする。   A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to any one of the first to fifth aspects, wherein the second conductive type semiconductor region is in contact with the second conductive type base region. It is characterized by.

また、請求項７の発明にかかる半導体装置は、請求項１〜６のいずれか一つに記載の発明において、前記第２導電型半導体領域の表面の前記半導体基板の切断側に、第１導電型チャネルストッパ領域が設けられていることを特徴とする。   A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to any one of the first to sixth aspects, wherein the first conductive material is disposed on the cut side of the semiconductor substrate on the surface of the second conductive type semiconductor region. A mold channel stopper region is provided.

また、請求項８の発明にかかる半導体装置は、請求項７に記載の発明において、前記第１導電型ピラー領域と前記第１導電型チャネルストッパ領域が接することを特徴とする。   According to an eighth aspect of the present invention, in the semiconductor device according to the seventh aspect, the first conductivity type pillar region and the first conductivity type channel stopper region are in contact with each other.

また、請求項９の発明にかかる半導体装置は、請求項１〜８のいずれか一つに記載の発明において、前記第２導電型ベース領域に接し、かつ前記第２導電型半導体領域の少なくとも一部の表面を被う絶縁膜の上に伸びるフィールドプレート構造が設けられていることを特徴とする。   A semiconductor device according to a ninth aspect of the invention is the semiconductor device according to any one of the first to eighth aspects, wherein the semiconductor device is in contact with the second conductive type base region and at least one of the second conductive type semiconductor regions. A field plate structure extending on an insulating film covering the surface of the portion is provided.

また、請求項１０の発明にかかる半導体装置は、請求項１に記載の発明において、素電荷をｑとし、シリコンの誘電率をεSiとし、半導体の臨界電界強度をＥcriticalとし、前記第２導電型半導体領域の厚さおよび濃度をそれぞれｔおよびＮ2とすると、
［Ｎ2＜εSi×Ｅcritical／（ｑ×ｔ）］
であることを特徴とする。 A semiconductor device according to a tenth aspect of the present invention is the semiconductor device according to the first aspect, wherein the elementary charge is q, the dielectric constant of silicon is ε Si , the critical electric field strength of the semiconductor is E critical, and the second If the thickness and concentration of the conductive semiconductor region are t and N 2 , respectively,
[N 2 <ε Si × E critical / (q × t)]
It is characterized by being.

また、請求項１１の発明にかかる半導体装置は、請求項１０に記載の発明において、［Ｎ2＜０．８×εSi×Ｅcritical／（ｑ×ｔ）］
であることを特徴とする。 The semiconductor device according to claim 11 is the semiconductor device according to claim 10, wherein [N 2 <0.8 × ε Si × E critical / (q × t)].
It is characterized by being.

また、請求項１２の発明にかかる半導体装置は、請求項６に記載の発明において、前記第２導電型ベース領域の、前記第２導電型半導体領域への突出量をＷprojectionとし、前記第２導電型半導体領域の厚さをｔとすると、
Ｗprojection＞０．２×ｔ
であることを特徴とする。 A semiconductor device according to a twelfth aspect of the present invention is the semiconductor device according to the sixth aspect of the present invention, wherein a projection amount of the second conductivity type base region to the second conductivity type semiconductor region is W projection , If the thickness of the conductive semiconductor region is t,
W projection > 0.2 × t
It is characterized by being.

また、請求項１３の発明にかかる半導体装置は、請求項１２に記載の発明において、Ｗprojection＞０．４×ｔ
であることを特徴とする。 A semiconductor device according to a thirteenth aspect of the present invention is the semiconductor device according to the twelfth aspect of the present invention, wherein W projection > 0.4 × t
It is characterized by being.

また、請求項１４の発明にかかる半導体装置は、請求項１〜１３のいずれか一つに記載の発明において、前記縦型の半導体装置が、ダイオード、ＭＯＳＦＥＴ及びＩＧＢＴのいずれかであることを特徴とする。   A semiconductor device according to a fourteenth aspect of the present invention is the semiconductor device according to any one of the first to thirteenth aspects, wherein the vertical semiconductor device is any one of a diode, a MOSFET, and an IGBT. And

また、請求項１５の発明にかかる半導体装置の製造方法は、請求項１に記載の半導体装置の製造方法であって、前記半導体基板に複数のトレンチをエッチングで形成した後、前記トレンチ間に残った半導体基板領域を熱酸化し、前記熱酸化により生じた酸化膜を除去し、この酸化膜を除去した部分を少なくとも第２導電型のエピタキシャル層で満たし前記第２導電型半導体領域を形成することを特徴とする。 A semiconductor device manufacturing method according to a fifteenth aspect of the present invention is the semiconductor device manufacturing method according to the first aspect, wherein a plurality of trenches are formed in the semiconductor substrate by etching, and then remain between the trenches. The semiconductor substrate region is thermally oxidized, the oxide film generated by the thermal oxidation is removed, and the portion where the oxide film is removed is filled with at least a second conductivity type epitaxial layer to form the second conductivity type semiconductor region. It is characterized by.

また、請求項１６の発明にかかる半導体装置の製造方法は、請求項１に記載の半導体装置の製造方法であって、前記半導体基板に複数のトレンチをエッチングで形成した後、前記トレンチを第２導電型のエピタキシャル層で満たし、更にトレンチ間に第２導電型の不純物拡散を行い前記第２導電型半導体領域を形成することを特徴とする。 According to a sixteenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the first aspect, wherein a plurality of trenches are formed in the semiconductor substrate by etching, and then the second trenches are formed. The second conductive type semiconductor region is formed by filling with a conductive type epitaxial layer and further diffusing a second conductive type impurity between the trenches.

また、請求項１７の発明にかかる半導体装置の製造方法は、請求項１に記載の半導体装置の製造方法であって、前記半導体基板に湿式異方性エッチングでトレンチを形成し、前記トレンチを第２導電型のエピタキシャル層で満たし、前記第２導電型半導体領域を形成することを特徴とする。 A semiconductor device manufacturing method according to claim 17 is the semiconductor device manufacturing method according to claim 1, wherein a trench is formed in the semiconductor substrate by wet anisotropic etching, and the trench is The second conductive type semiconductor region is formed by filling with a two conductive type epitaxial layer.

また、請求項１８の発明にかかる半導体装置の製造方法は、請求項１５〜１７のいずれか一つに記載の発明において、前記エピタキシャル層で満たした後、熱酸化と熱酸化後の前記半導体基板表面の研磨を行うことを特徴とする。 A method of manufacturing a semiconductor device according to an invention of claim 18 is the invention according to any one of claims 15 to 17, wherein the semiconductor substrate is filled with the epitaxial layer, and then subjected to thermal oxidation and thermal oxidation. It is characterized by polishing the surface.

請求項１の発明によれば、終端構造部における第２導電型半導体領域が活性部におけるドリフト層の導電型（第１導電型）と逆になり、ベース領域の導電型（第２導電型）と同じになる。また、請求項２の発明によれば、終端構造部における第２導電型半導体領域の実効的な導電型がベース領域の導電型（第２導電型）と同じになる。従って、いずれの場合も、終端構造部の耐圧を支える主接合が第１主電極側でなくなり、終端構造部の耐圧を支える主接合と活性部の耐圧を支える主接合が同一面でなくなるので、平面接合の電界上昇が第１導電型の半導体基板層と第２導電型半導体領域で起こるようになる。   According to the first aspect of the present invention, the second conductivity type semiconductor region in the termination structure portion is opposite to the conductivity type of the drift layer in the active portion (first conductivity type), and the conductivity type of the base region (second conductivity type). Will be the same. According to the invention of claim 2, the effective conductivity type of the second conductivity type semiconductor region in the termination structure portion is the same as the conductivity type of the base region (second conductivity type). Therefore, in either case, the main junction supporting the breakdown voltage of the termination structure portion is not on the first main electrode side, and the main junction supporting the breakdown voltage of the termination structure portion and the main junction supporting the breakdown voltage of the active portion are not on the same plane. An electric field rise at the planar junction occurs in the first conductive type semiconductor substrate layer and the second conductive type semiconductor region.

また、請求項１０、１１の発明によれば、終端構造部の下の半導体基板層から第１主面に空乏層が届く。特に、請求項１１の発明によれば、空乏層が確実に第１主面に届く。   According to the tenth and eleventh aspects of the present invention, the depletion layer reaches the first main surface from the semiconductor substrate layer under the termination structure portion. In particular, according to the invention of claim 11, the depletion layer reliably reaches the first main surface.

また、請求項１５又は１６の発明にかかる半導体装置の製造方法は、厚い第２導電型半導体領域を容易に形成することができる。   In the semiconductor device manufacturing method according to the fifteenth or sixteenth aspect of the invention, the thick second conductivity type semiconductor region can be easily formed.

本発明にかかる半導体装置によれば、プレーナ型の接合終端構造を有する半導体装置において、平面接合の電界上昇と、電界集中による高電界部分ができることの相乗効果が現れるのを防ぐことができる。それによって、プレーナ型の接合終端構造内の電界がブレークダウンを起こす電界に到達しにくくなるので、接合終端構造の耐圧を向上させるという効果を奏する。また、本発明にかかる半導体装置の製造方法によれば、プレーナ型の接合終端構造を有し、かつ接合終端構造の耐圧を向上させた半導体装置が得られるという効果を奏する。   According to the semiconductor device of the present invention, in a semiconductor device having a planar type junction termination structure, it is possible to prevent a synergistic effect between an electric field rise of a planar junction and a high electric field portion due to electric field concentration from appearing. This makes it difficult for the electric field in the planar junction termination structure to reach an electric field that causes breakdown, thereby improving the breakdown voltage of the junction termination structure. In addition, according to the method for manufacturing a semiconductor device according to the present invention, it is possible to obtain a semiconductor device having a planar junction termination structure and having an improved breakdown voltage of the junction termination structure.

以下に添付図面を参照して、この発明にかかる半導体装置およびその製造方法の好適な実施の形態を詳細に説明する。本明細書および添付図面においては、ｎまたはｐを冠記した層や領域では、それぞれ電子または正孔が多数キャリアであることを意味する。また、ｎやｐに付す＋および−は、それぞれ相対的に不純物濃度が高いおよび低いことを意味する。また、各実施の形態では第１導電型をｎ型とし、第２導電型をｐ型として説明する。なお、以下の実施の形態の説明および添付図面において、同様の構成には同一の符号を付し、重複する説明を省略する。   Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is relatively high and low, respectively. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

実施の形態１．
（半導体装置の構成）
図１−１および図１−２は、本発明の実施の形態１にかかる半導体装置の要部の構成を示す図であり、図１−１は終端構造部３００を示すための断面図であり、図１−２は活性部２００を示すための斜視図である。図１−１および図１−２に示すように、半導体装置１００は、ＭＯＳＦＥＴ（金属−酸化膜−半導体構造を有するＦＥＴ）やＩＧＢＴやダイオードなどの素子が形成される活性部２００と、この活性部２００を囲む終端構造部３００を備えている。終端構造部３００は、半導体装置１００の第１主面側に配置されている。 Embodiment 1 FIG.
(Configuration of semiconductor device)
FIGS. 1-1 and 1-2 are diagrams showing the configuration of the main part of the semiconductor device according to the first embodiment of the present invention, and FIG. 1-1 is a sectional view for showing the termination structure unit 300. FIGS. FIGS. 1-2 is a perspective view for showing the active part 200. FIG. As shown in FIGS. 1-1 and 1-2, the semiconductor device 100 includes an active part 200 in which elements such as MOSFETs (FETs having a metal-oxide film-semiconductor structure), IGBTs, and diodes are formed. The terminal structure part 300 surrounding the part 200 is provided. Termination structure 300 is disposed on the first main surface side of semiconductor device 100.

十分に不純物濃度の高いｎ型半導体基板層１が、活性部２００の領域と終端構造部３００の領域にわたって設けられている。活性部２００の領域では、複数のｐ型仕切り領域２と複数のｎ型ドリフト領域３が交互に並置されてなる超接合層４が、ｎ型半導体基板層１に接してその上に設けられている。   An n-type semiconductor substrate layer 1 having a sufficiently high impurity concentration is provided over the region of the active part 200 and the region of the termination structure part 300. In the region of the active part 200, a superjunction layer 4 in which a plurality of p-type partition regions 2 and a plurality of n-type drift regions 3 are alternately arranged is provided on and in contact with the n-type semiconductor substrate layer 1. Yes.

例えば半導体装置１００が縦型のトレンチＭＯＳＦＥＴである場合には、選択的に形成されたｐベース領域またはｐボディ領域（以下、ｐベース／ボディ領域とする）５と、該ｐベース／ボディ領域５内に選択的に形成されたソース領域６３と、ｐベース／ボディ領域５よりも深く形成されたトレンチ６４と、トレンチ６４内に酸化膜１２よりも薄いゲート絶縁膜６５を介して形成されるゲート電極６６と、ゲート電極６６上を覆う層間絶縁膜１５と、ｐベース／ボディ領域５とソース領域６３に電気的に接続するソース電極６が、半導体装置１００の第１主面側に設けられている。図１−２の斜視図では理解を容易にするためにソース電極６を省略している。この実施の形態では、トレンチのゲート電極６６の伸びる方向と、複数のｐ型仕切り領域２と複数のｎ型ドリフト領域３が交互に並置されてなる超接合層４が伸びる方向とが直交するようになっている。このように直交させるとｐベース／ボディ領域５と超接合層４が確実に接するようになるので、前記第１主面側の各領域と超接合層４の合わせこみが容易となり、位置合わせが容易である。ｎ型半導体基板層１は、ＭＯＳＦＥＴのドレイン領域となる。ドレイン電極７は、半導体装置１００の第２主面側に設けられており、ｎ型半導体基板層１に電気的に接続する。   For example, when the semiconductor device 100 is a vertical trench MOSFET, a selectively formed p base region or p body region (hereinafter referred to as p base / body region) 5, and the p base / body region 5. A source region 63 selectively formed therein, a trench 64 formed deeper than the p base / body region 5, and a gate formed in the trench 64 via a gate insulating film 65 thinner than the oxide film 12. Electrode 66, interlayer insulating film 15 covering gate electrode 66, and source electrode 6 electrically connected to p base / body region 5 and source region 63 are provided on the first main surface side of semiconductor device 100. Yes. In the perspective view of FIG. 1-2, the source electrode 6 is omitted for easy understanding. In this embodiment, the direction in which the gate electrode 66 of the trench extends is orthogonal to the direction in which the superjunction layer 4 in which the plurality of p-type partition regions 2 and the plurality of n-type drift regions 3 are alternately juxtaposed is orthogonal. It has become. Since the p base / body region 5 and the superjunction layer 4 are surely in contact with each other in this way, it is easy to align each region on the first main surface side with the superjunction layer 4, and alignment is possible. Easy. The n-type semiconductor substrate layer 1 becomes a drain region of the MOSFET. The drain electrode 7 is provided on the second main surface side of the semiconductor device 100 and is electrically connected to the n-type semiconductor substrate layer 1.

一方、終端構造部３００の領域では、ｐ型仕切り領域８が、ｎ型半導体基板層１に接してその上に設けられている。このｐ型仕切り領域８は、ｐベース／ボディ領域５に接している。ｐ型仕切り領域８と半導体装置１００の切断面９との間には、ｎ型チャネルストッパ領域１０とこれに接するｎ型ピラー領域１１が設けられている。ｎ型チャネルストッパ領域１０は、半導体装置１００の第１主面側に設けられている。ｎ型ピラー領域１１は、半導体装置１００の切断面９に沿って、ｎ型チャネルストッパ領域１０とｎ型半導体基板層１の間に設けられている。   On the other hand, in the region of the termination structure portion 300, the p-type partition region 8 is provided on and in contact with the n-type semiconductor substrate layer 1. The p-type partition region 8 is in contact with the p base / body region 5. Between the p-type partition region 8 and the cut surface 9 of the semiconductor device 100, an n-type channel stopper region 10 and an n-type pillar region 11 in contact therewith are provided. The n-type channel stopper region 10 is provided on the first main surface side of the semiconductor device 100. The n-type pillar region 11 is provided between the n-type channel stopper region 10 and the n-type semiconductor substrate layer 1 along the cut surface 9 of the semiconductor device 100.

活性部２００に設けられたｐベース／ボディ領域５の終端構造部３００との境界部分と、ｎ型チャネルストッパ領域１０の間の、ｐ型仕切り領域８の第１主面側は、酸化シリコンなどの酸化膜１２により被われている。この酸化膜１２の上に選択的にフィールドプレート１３，１４が設けられている。   The first main surface side of the p-type partition region 8 between the boundary portion between the termination structure 300 of the p base / body region 5 provided in the active portion 200 and the n-type channel stopper region 10 is silicon oxide or the like. The oxide film 12 is covered. Field plates 13 and 14 are selectively provided on the oxide film 12.

ソース電極６は、活性部２００から終端構造部３００側へ伸び、活性部２００寄りに配置されたフィールドプレート１３に、層間絶縁膜１５に開口するコンタクトホールを介して接触している。終端構造部３００におけるフィールドプレート構造は、これらｐ型仕切り領域８を被う酸化膜１２、活性部２００寄りに配置されたフィールドプレート１３およびこれに接するソース電極６の終端部により構成されている。   The source electrode 6 extends from the active portion 200 toward the termination structure portion 300 and contacts the field plate 13 disposed near the active portion 200 through a contact hole opened in the interlayer insulating film 15. The field plate structure in the termination structure portion 300 is composed of the oxide film 12 covering the p-type partition region 8, the field plate 13 disposed near the active portion 200, and the termination portion of the source electrode 6 in contact with the field plate.

また、ｎ型チャネルストッパ領域１０寄りに配置されたフィールドプレート１４には、ｎ型チャネルストッパ領域１０に接するチャネルストッパ電極１６が、層間絶縁膜１５に開口するコンタクトホールを介して接触している。終端構造部３００は、パッシベーション膜１７により被われている。なお、図１−１には、半導体装置１００の断面構成とともに、ｐ型仕切り領域８に、終端構造部３００における等電位線（７本の折れ線）が示されている。   In addition, a channel stopper electrode 16 in contact with the n-type channel stopper region 10 is in contact with the field plate 14 disposed near the n-type channel stopper region 10 through a contact hole opened in the interlayer insulating film 15. The termination structure 300 is covered with the passivation film 17. In FIG. 1A, equipotential lines (seven broken lines) in the termination structure 300 are shown in the p-type partition region 8 along with the cross-sectional configuration of the semiconductor device 100.

（終端構造部下のｐ型仕切り領域に対するｐベース／ボディ領域の突出量）
本発明者らは、終端構造部３００の下のｐ型仕切り領域８とｐベース／ボディ領域５が電気的に接続されており、さらにｐベース／ボディ領域５が終端構造部３００の下のｐ型仕切り領域８に対して突出するように設計されていると、安定的に高い耐圧が得られることを見出した。図２は、ｐ型仕切り領域８の厚さ（基板横方向）を５０μｍとしたときの終端構造部３００の下のｐ型仕切り領域８に対するｐベース／ボディ領域５の突出量と耐圧の関係を示す特性図である。 (Projection amount of p base / body region relative to p-type partition region under terminal structure)
The inventors of the present invention electrically connect the p-type partition region 8 below the termination structure 300 and the p base / body region 5, and the p base / body region 5 is p below the termination structure 300. It has been found that when it is designed to protrude with respect to the mold partition region 8, a high withstand voltage can be stably obtained. FIG. 2 shows the relationship between the protrusion amount of the p base / body region 5 and the withstand voltage with respect to the p type partition region 8 below the termination structure 300 when the thickness of the p type partition region 8 (substrate lateral direction) is 50 μm. FIG.

図２より、ｐベース／ボディ領域５の突出量が１０μｍ（ｐ型仕切り領域８の厚さの１/５）以上、好ましくは２０μｍ（ｐ型仕切り領域８の厚さの２/５）以上であれば、安定的に高い耐圧が得られることがわかる。これを、ｐベース／ボディ領域５の突出量およびｐ型仕切り領域８の厚さをそれぞれＷprojectionおよびｔとして一般化すると、次の（１）式を満たすと安定的に高い耐圧が得られ、（２）式を満たすとより安定して高い耐圧が得られる。
Ｗprojection＞０．２×ｔ ・・・（１）
Ｗprojection＞０．４×ｔ ・・・（２） From FIG. 2, the protrusion amount of the p base / body region 5 is 10 μm (1/5 of the thickness of the p-type partition region 8) or more, preferably 20 μm (2/5 of the thickness of the p-type partition region 8) or more. If it exists, it turns out that a high withstand voltage is stably obtained. When this is generalized as the projection amount of the p base / body region 5 and the thickness of the p-type partition region 8 respectively as W projection and t, a high breakdown voltage can be stably obtained when the following equation (1) is satisfied. When the expression (2) is satisfied, a high breakdown voltage can be obtained more stably.
W projection > 0.2 × t (1)
W projection > 0.4 × t (2)

（終端構造部下のｐ型仕切り領域の不純物濃度範囲）
また、本発明者らは、終端構造部３００の下のｐ型仕切り領域８の不純物濃度に好適な濃度範囲が存在することを見出した。図３は、ｐ型仕切り領域８の厚さを５０μｍとしたときのｐ型仕切り領域８の不純物濃度と耐圧の関係を示す特性図である。図３より、終端構造部３００の下のｐ型仕切り領域８の不純物濃度は、２．５×１０14ｃｍ-3以下、好ましくは２．０×１０14ｃｍ-3以下であれば、高い耐圧が得られることがわかる。 (Impurity concentration range of the p-type partition region under the termination structure)
Further, the present inventors have found that there is a concentration range suitable for the impurity concentration of the p-type partition region 8 under the termination structure portion 300. FIG. 3 is a characteristic diagram showing the relationship between the impurity concentration of the p-type partition region 8 and the breakdown voltage when the thickness of the p-type partition region 8 is 50 μm. As shown in FIG. 3, when the impurity concentration of the p-type partition region 8 under the termination structure 300 is 2.5 × 10 14 cm −3 or less, preferably 2.0 × 10 14 cm −3 or less, a high breakdown voltage is obtained. It can be seen that

ここで、終端構造部３００の下のｐ型仕切り領域８の不純物濃度が２．５×１０14ｃｍ-3であるということは、おおよそ、終端構造部３００の下のｐ型仕切り領域８とｎ型半導体基板層１からなるｐｎ接合から広がる空間電荷領域がｐ型仕切り領域８の表面層に到達し得る程度の不純物濃度であるということである。終端構造部３００の下のｐ型仕切り領域８の不純物濃度が２．５×１０14ｃｍ-3よりも高い場合には、空間電荷領域がｐ型仕切り領域８の表面層に到達できないため、終端構造部３００の下のｐ型仕切り領域８とｎ型半導体基板層１からなるｐｎ接合によって耐圧が決定されることになり、耐圧が低くなってしまう。 Here, the impurity concentration of the p-type partition region 8 below the termination structure 300 is 2.5 × 10 14 cm −3 , which is roughly the same as that of the p-type partition region 8 and n under the termination structure 300. This means that the space charge region extending from the pn junction made of the type semiconductor substrate layer 1 has an impurity concentration that can reach the surface layer of the p-type partition region 8. When the impurity concentration of the p-type partition region 8 under the termination structure 300 is higher than 2.5 × 10 14 cm −3 , the space charge region cannot reach the surface layer of the p-type partition region 8, The breakdown voltage is determined by the pn junction composed of the p-type partition region 8 and the n-type semiconductor substrate layer 1 under the structure 300, and the breakdown voltage is lowered.

図４は、終端構造部３００の下のｐ型仕切り領域８の不純物濃度を５．０×１０14ｃｍ-3としたときのアバランシェ降伏時のキャリア発生状況をシミュレートした結果を示す図である。図４において上段および下段は、それぞれ半導体装置１００の要部断面構成およびキャリア発生状況を示しており、同図に点線および一点鎖線で示すように、活性部２００および終端構造部３００の各領域の位置は一致させている。図４より、終端構造部３００の下のｐ型仕切り領域８とｎ型半導体基板層１からなるｐｎ接合でキャリアが発生しており、この部分でアバランシェ降伏して耐圧が決定されていることがわかる。 FIG. 4 is a diagram showing a result of simulating the carrier generation state at the time of avalanche breakdown when the impurity concentration of the p-type partition region 8 under the termination structure 300 is 5.0 × 10 14 cm −3 . . In FIG. 4, the upper stage and the lower stage respectively show the cross-sectional configuration of the principal part of the semiconductor device 100 and the carrier generation state. As shown by the dotted line and the alternate long and short dash line in FIG. The positions are matched. As shown in FIG. 4, carriers are generated in a pn junction composed of the p-type partition region 8 and the n-type semiconductor substrate layer 1 below the termination structure 300, and the breakdown voltage is determined by avalanche breakdown at this portion. Recognize.

従って、終端構造部３００の下のｐ型仕切り領域８の好適な不純物濃度を、ｎ型半導体基板層１と終端構造部３００の下のｐ型仕切り領域８からなるｐｎ接合から広がる空間電荷領域が半導体表面層に到達するように決定するとよい。一般に、不純物濃度がＮである半導体層中に広がる空間電荷領域の厚さをｔDepとすると、半導体層の濃度Ｎは、ポアソン方程式により次の（３）式で表される。ただし、素電荷をｑとし、シリコンの誘電率をεSiとし、シリコンの臨界電界強度をＥcriticalとする。
Ｎ＝εSi×Ｅcritical／（ｑ×ｔDep） ・・・（３） Accordingly, a suitable impurity concentration in the p-type partition region 8 under the termination structure 300 is set to a space charge region extending from the pn junction composed of the n-type semiconductor substrate layer 1 and the p-type partition region 8 under the termination structure 300. It may be determined to reach the semiconductor surface layer. In general, when the thickness of a space charge region extending in a semiconductor layer having an impurity concentration of N is t Dep , the concentration N of the semiconductor layer is expressed by the following equation (3) according to the Poisson equation. Here, the elementary charge is q, the dielectric constant of silicon is ε Si, and the critical electric field strength of silicon is E critical .
N = ε Si × E critical / (q × t Dep ) (3)

従って、終端構造部３００の下のｐ型仕切り領域８の不純物濃度および厚さをそれぞれＮ2およびｔとすると、次の（４）式を満たすとよい。（４）式を満たすことにより、空乏層が終端構造部３００の下のｎ型半導体基板層１から半導体装置１００の第１主面に届く。また、好ましくは、次の（５）式を満たすと、空乏層が半導体装置１００の第１主面に確実に届くのでよい。
Ｎ2＜εSi×Ｅcritical／（ｑ×ｔ） ・・・（４）
Ｎ2＜０．８×εSi×Ｅcritical／（ｑ×ｔ） ・・・（５） Therefore, if the impurity concentration and thickness of the p-type partition region 8 under the termination structure 300 are N 2 and t, respectively, the following equation (4) is preferably satisfied. By satisfying the expression (4), the depletion layer reaches the first main surface of the semiconductor device 100 from the n-type semiconductor substrate layer 1 under the termination structure unit 300. Further, preferably, when the following expression (5) is satisfied, the depletion layer can surely reach the first main surface of the semiconductor device 100.
N 2 <ε Si × E critical / (q × t) (4)
N 2 <0.8 × ε Si × E critical / (q × t) (5)

（ｎ型ピラー領域の不純物濃度）
ｎ型ピラー領域１１の不純物濃度がｎ型ドリフト領域３の不純物濃度と同じかまたはほぼ同じであるとよい。そうすれば、半導体装置１００を製造する際に、ｎ型ピラー領域１１とｎ型ドリフト領域３を同時に作製することができる。それによって、それらを別々に作製するよりも工程数が少なくて済むので、製造コストが低減され、安価な半導体装置が得られる。 (Impurity concentration of n-type pillar region)
The impurity concentration of the n-type pillar region 11 may be the same as or substantially the same as the impurity concentration of the n-type drift region 3. Then, when manufacturing the semiconductor device 100, the n-type pillar region 11 and the n-type drift region 3 can be simultaneously manufactured. As a result, the number of steps can be reduced as compared with manufacturing them separately, so that the manufacturing cost is reduced and an inexpensive semiconductor device can be obtained.

（半導体装置の製造方法）
次に、半導体装置１００の製造方法について説明する。ここでは、一例として、耐圧６００Ｖの超接合型ＭＯＳＦＥＴの製造方法について、その終端構造部３００を中心に説明する。図５〜図１２は、製造段階の半導体装置１００の要部断面図である。 (Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 100 will be described. Here, as an example, a method for manufacturing a super-junction MOSFET having a withstand voltage of 600 V will be described focusing on the termination structure 300. 5 to 12 are cross-sectional views of main parts of the semiconductor device 100 at the manufacturing stage.

ｎ型半導体基板層１の上に、活性部２００となる領域ではｐ型仕切り領域２とｎ型ドリフト領域３の超接合層４、終端構造部３００の形成領域ではｐ型仕切り領域８、および半導体装置１００の切断面９となる領域ではｎ型ピラー領域１１が、それぞれ例えば５０μｍの厚さに形成された半導体基板を形成する。超接合層４のｐ型仕切り領域２とｎ型ドリフト領域３は、それぞれ例えば６μｍピッチで交互に配置されている。   On the n-type semiconductor substrate layer 1, the super junction layer 4 between the p-type partition region 2 and the n-type drift region 3 in the region to be the active portion 200, the p-type partition region 8 in the formation region of the termination structure portion 300, and the semiconductor In the region to be the cut surface 9 of the device 100, a semiconductor substrate in which the n-type pillar region 11 is formed to a thickness of, for example, 50 μm is formed. The p-type partition regions 2 and the n-type drift regions 3 of the superjunction layer 4 are alternately arranged with a pitch of 6 μm, for example.

超接合層４のｐ型仕切り領域２およびｎ型ドリフト領域３は、それぞれボロン等のｐ型不純物およびリン等のｎ型不純物を含む。超接合層４では、ｐ型仕切り領域２およびｎ型ドリフト領域３の各不純物濃度の平均濃度は、例えば約３×１０15ｃｍ-3程度である。終端構造部３００の形成領域のｐ型仕切り領域８は、例えば１．０×１０14ｃｍ-3程度のボロン等のｐ型不純物を含む。ｎ型ピラー領域１１は、超接合層４のｎ型ドリフト領域３と同程度のリン等のｎ型不純物を含む。 The p-type partition region 2 and the n-type drift region 3 of the superjunction layer 4 contain a p-type impurity such as boron and an n-type impurity such as phosphorus, respectively. In the superjunction layer 4, the average impurity concentration of the p-type partition region 2 and the n-type drift region 3 is, for example, about 3 × 10 15 cm −3 . The p-type partition region 8 in the formation region of the termination structure 300 includes a p-type impurity such as boron of about 1.0 × 10 14 cm −3 , for example. The n-type pillar region 11 contains n-type impurities such as phosphorus, which are about the same as the n-type drift region 3 of the superjunction layer 4.

このような半導体基板を簡便に形成する方法の一つとして、図５〜図９に示す方法がある。まず、高不純物濃度のｎ型Ｓｉ半導体基板１８の上に、不純物として例えば１．０×１０14ｃｍ-3程度のボロンを含むｐ型半導体層１９を例えば６〜１０μｍ程度の厚さに成長させる（図５）。次いで、フォトレジストをマスク２０にして超接合層４のｐ型仕切り領域２となる箇所に所定濃度の例えばボロン（Ｂ）をイオン注入する（図６）。図６において、符号２１で示す領域は、ボロン等のｐ型不純物の注入領域である。 One method for easily forming such a semiconductor substrate is shown in FIGS. First, a p-type semiconductor layer 19 containing, for example, about 1.0 × 10 14 cm −3 of boron as an impurity is grown on the high impurity concentration n-type Si semiconductor substrate 18 to a thickness of, for example, about 6 to 10 μm. (FIG. 5). Next, for example, boron (B) having a predetermined concentration is ion-implanted into a portion that becomes the p-type partition region 2 of the super-junction layer 4 using the photoresist 20 as a mask (FIG. 6). In FIG. 6, a region denoted by reference numeral 21 is an implanted region of p-type impurities such as boron.

また、別のフォトレジストをマスク２２にして超接合層４のｎ型ドリフト領域３とｎ型ピラー領域１１となる箇所に所定濃度の例えばリン（Ｐ）をイオン注入する（図７）。図７において、符号２３で示す領域は、リン等のｎ型不純物の注入領域である。なお、図７の工程を先に行ってから図６の工程を行ってもよい。この図６の工程と図７の工程を交互にそれぞれ５〜８回程度繰り返す（図８）。   Further, for example, phosphorus (P) having a predetermined concentration is ion-implanted into the n-type drift region 3 and the n-type pillar region 11 of the super junction layer 4 using another photoresist as a mask 22 (FIG. 7). In FIG. 7, a region denoted by reference numeral 23 is an implanted region of n-type impurities such as phosphorus. Note that the step of FIG. 6 may be performed after the step of FIG. 7 is performed first. The process of FIG. 6 and the process of FIG. 7 are alternately repeated about 5 to 8 times (FIG. 8).

その後、例えば１１５０℃で１０時間程度の熱処理を行うことによって、上述したようなｎ型半導体基板層１上に、超接合層４のｐ型仕切り領域２およびｎ型ドリフト領域３と、ｐ型仕切り領域８と、ｎ型ピラー領域１１を有する超接合基板２４ができあがる（図９）。この超接合基板２４では、図６および図７の工程において不純物が注入されなかった領域が、終端構造部３００の下のｐ型仕切り領域８となる。このようにしてできた超接合基板２４を用いる。   Thereafter, for example, by performing heat treatment at 1150 ° C. for about 10 hours, the p-type partition region 2 and the n-type drift region 3 of the superjunction layer 4 and the p-type partition are formed on the n-type semiconductor substrate layer 1 as described above. A superjunction substrate 24 having the region 8 and the n-type pillar region 11 is completed (FIG. 9). In this superjunction substrate 24, the region where impurities are not implanted in the steps of FIGS. 6 and 7 becomes the p-type partition region 8 below the termination structure portion 300. The super-bonded substrate 24 thus formed is used.

図１０に示すように、超接合基板２４の超接合層４の側の主面（第１主面）に例えば厚さ０．８μｍ程度の酸化膜１２を形成する。そして、フォトリソグラフィおよびエッチング工程によって、その酸化膜１２の、終端構造部３００以外の部分を取り除く。次いで、図には現れていないが、ゲート酸化膜を例えば１００ｎｍ程度の厚さに形成し、その上にポリシリコンを成長させる。そして、気相拡散法またはイオン注入法により、そのポリシリコン中に十分な濃度の不純物を導入し、フォトリソグラフィおよびエッチング工程によって所定の形状のゲート電極を形成する。このとき、終端構造部３００では、１段目のフィールドプレート１３，１４が形成される。   As shown in FIG. 10, an oxide film 12 having a thickness of, for example, about 0.8 μm is formed on the main surface (first main surface) of the super bonding substrate 24 on the super bonding layer 4 side. Then, portions other than the termination structure portion 300 of the oxide film 12 are removed by photolithography and etching processes. Next, although not shown in the figure, a gate oxide film is formed to a thickness of about 100 nm, for example, and polysilicon is grown thereon. Then, a sufficient concentration of impurities is introduced into the polysilicon by a vapor phase diffusion method or an ion implantation method, and a gate electrode having a predetermined shape is formed by a photolithography and etching process. At this time, in the termination structure 300, the first-stage field plates 13 and 14 are formed.

次いで、超接合基板２４の第１主面側から、例えば１×１０14ｃｍ-2程度のドーズ量でボロンのイオン注入を行い、熱処理を行う。また、超接合基板２４の第１主面側から、フォトレジストをマスクとして例えば１×１０15ｃｍ-2程度のドーズ量でボロンのイオン注入を行う。さらに、超接合基板２４の第１主面側から、フォトレジストをマスクとして例えば５×１０15ｃｍ-2程度のドーズ量で砒素のイオン注入を行い、熱処理を行う。 Next, boron is ion-implanted from the first main surface side of the superjunction substrate 24 at a dose of, for example, about 1 × 10 14 cm −2 to perform heat treatment. Further, boron ions are implanted from the first main surface side of the superjunction substrate 24 with a dose of about 1 × 10 15 cm −2 using a photoresist as a mask. Further, arsenic ions are implanted from the first main surface side of the superjunction substrate 24 at a dose of, for example, about 5 × 10 15 cm −2 using a photoresist as a mask, and heat treatment is performed.

これらのイオン注入工程と熱処理工程によって、図１０には現れていないが、活性部２００にｐベース領域、ｐボディ領域およびソース領域が形成される。このとき、終端構造部３００では、ｐベース／ボディ領域５とｎ型チャネルストッパ領域１０が形成される（図１０）。次いで、超接合基板２４の第１主面側に、例えばリンやボロン等を含む酸化シリコンの膜を約１．１μｍの厚さに生成し、所定のフォトリソグラフィおよびエッチング工程によって、その酸化シリコンの膜にコンタクトホールを形成する。そして、例えば９００℃程度でリフローを行い、層間絶縁膜１５を形成する（図１１）。   Although not shown in FIG. 10, the p base region, the p body region, and the source region are formed in the active portion 200 by these ion implantation process and heat treatment process. At this time, in the termination structure 300, the p base / body region 5 and the n-type channel stopper region 10 are formed (FIG. 10). Next, a silicon oxide film containing, for example, phosphorus or boron is formed on the first main surface side of the superjunction substrate 24 to a thickness of about 1.1 μm, and the silicon oxide film is formed by a predetermined photolithography and etching process. Contact holes are formed in the film. Then, for example, reflow is performed at about 900 ° C. to form an interlayer insulating film 15 (FIG. 11).

次いで、超接合基板２４の第１主面側に、例えばシリコンを１％含有するアルミニウム膜を約３μｍの厚さに成膜し、フォトリソグラフィおよびエッチング工程によって、そのアルミニウム膜からソース電極６とチャネルストッパ電極１６を形成する（図１２）。次いで、超接合基板２４の第１主面側に、例えばポリイミド膜を１０μｍ程度の厚さに成膜し、フォトリソグラフィおよびエッチング工程によって、そのポリイミド膜からパッシベーション膜１７を形成する。   Next, an aluminum film containing, for example, 1% silicon is formed to a thickness of about 3 μm on the first main surface side of the superjunction substrate 24, and the source electrode 6 and the channel are formed from the aluminum film by photolithography and etching processes. A stopper electrode 16 is formed (FIG. 12). Next, a polyimide film, for example, is formed to a thickness of about 10 μm on the first main surface side of the super junction substrate 24, and a passivation film 17 is formed from the polyimide film by photolithography and etching processes.

次いで、超接合基板２４の第２主面側、すなわちｎ型半導体基板層１の側にチタン、ニッケルおよび金を順次成膜し、ドレイン電極７を形成する。このようにして、図１−１および図１−２に示すような超接合型ＭＯＳＦＥＴの活性部２００と、多段フィールドプレート構造およびチャネルストッパ構造を有する終端構造部３００が完成する。最後に、ダイサーによって、同一ウェハ内で隣り合うチャネルストッパ電極１６の間の、半導体装置１００が形成されていない領域で個々のチップに切り分けることによって、個々の超接合型ＭＯＳＦＥＴが完成する。なお、この製造方法で形成されたＭＯＳＦＥＴは、縦型のプレーナＭＯＳＦＥＴである。   Next, titanium, nickel, and gold are sequentially formed on the second main surface side of the superjunction substrate 24, that is, the n-type semiconductor substrate layer 1 side, and the drain electrode 7 is formed. In this manner, the active portion 200 of the superjunction MOSFET as shown in FIGS. 1-1 and 1-2, and the termination structure portion 300 having the multistage field plate structure and the channel stopper structure are completed. Finally, each superjunction MOSFET is completed by cutting into individual chips in a region where the semiconductor device 100 is not formed between adjacent channel stopper electrodes 16 in the same wafer by a dicer. The MOSFET formed by this manufacturing method is a vertical planar MOSFET.

（従来例との比較）
実施の形態１の半導体装置と従来構成の超接合型半導体装置（従来例Ａとする）について、耐圧を調べた結果を図１３に示す。また、アバランシェ降伏時の電位分布、電界分布およびインパクトイオン化率をシミュレーションによって比較した結果をそれぞれ図１４、図１５および図１６に示す。さらに、図１７に、実施の形態１の半導体装置と従来例Ａについて、アバランシェ降伏時の活性部寄りのフィールドプレート端および酸化膜段差部における電界強度の深さ方向の分布を示す。 (Comparison with conventional example)
FIG. 13 shows the result of examining the breakdown voltage of the semiconductor device of the first embodiment and the superjunction semiconductor device having the conventional configuration (conventional example A). In addition, the results of comparing the potential distribution, electric field distribution, and impact ionization rate during avalanche breakdown by simulation are shown in FIGS. 14, 15, and 16, respectively. Further, FIG. 17 shows the distribution in the depth direction of the electric field strength at the field plate edge and the oxide film step portion near the active portion at the time of avalanche breakdown for the semiconductor device of the first embodiment and Conventional Example A.

なお、図１８に示すように、従来例Ａの半導体装置１０００は、終端構造部３００とその下のｎ型半導体基板層１の間の半導体領域１００８の導電型をｎ型にした以外は、実施の形態１の半導体装置１００と同じ構造のものである。図１３より、実施の形態１の半導体装置１００の耐圧は、従来例Ａよりも高いアバランシェ降伏電圧を示すことがわかる。また、図１４より、実施の形態１の半導体装置１００および従来例Ａのいずれでも、電位面がフィールドプレート端で曲率を有しており、それら曲率の部分の電界が高くなっていることが予想される。   As shown in FIG. 18, the semiconductor device 1000 of the conventional example A is implemented except that the conductivity type of the semiconductor region 1008 between the termination structure 300 and the n-type semiconductor substrate layer 1 thereunder is n-type. The semiconductor device 100 has the same structure as that of the first embodiment. FIG. 13 shows that the breakdown voltage of the semiconductor device 100 of the first embodiment shows a higher avalanche breakdown voltage than the conventional example A. Further, from FIG. 14, it is expected that in both the semiconductor device 100 of the first embodiment and the conventional example A, the potential surface has a curvature at the end of the field plate, and the electric field in the portion of the curvature is high. Is done.

図１５より、実施の形態１の半導体装置１００のフィールドプレート端の電界強度は、従来例Ａのフィールドプレート端の電界強度と同様に高くなっていることがわかる。しかしながら、図１７より、実施の形態１の半導体装置１００の方が従来例Ａよりも、フィールドプレート端の電界強度が低いことがわかる。   From FIG. 15, it can be seen that the electric field strength at the field plate end of the semiconductor device 100 of the first embodiment is as high as the electric field strength at the field plate end of the conventional example A. However, it can be seen from FIG. 17 that the electric field strength at the field plate edge is lower in the semiconductor device 100 of the first embodiment than in the conventional example A.

これは、実施の形態１の半導体装置１００では、電圧を支える主接合面がｎ型半導体基板層１と終端構造部３００の下のｐ型仕切り領域８の界面にあり、ｐベース／ボディ領域５が形成されている第１主面に向かって電界強度が低下している。それに対して、従来例Ａでは、終端構造部３００の下の半導体領域１００８がｎ型であるため、電圧を支える主接合面がｎ型半導体領域１００８の表面層、すなわちｐベース／ボディ領域５の形成面にある。従って、従来例Ａでは、平面接合の電界上昇と、電界集中による高電界部分ができることの相乗効果が現れてしまう。   This is because, in the semiconductor device 100 of the first embodiment, the main junction surface supporting the voltage is at the interface between the n-type semiconductor substrate layer 1 and the p-type partition region 8 under the termination structure 300, and the p base / body region 5 The electric field strength decreases toward the first main surface on which is formed. On the other hand, in the conventional example A, since the semiconductor region 1008 under the termination structure 300 is n-type, the main junction surface supporting the voltage is the surface layer of the n-type semiconductor region 1008, that is, the p base / body region 5. On the forming surface. Therefore, in the conventional example A, there is a synergistic effect that the electric field rise of the planar junction and a high electric field portion due to electric field concentration are formed.

図１６より、従来例Ａでは、２段目フィールドプレート端でのインパクトイオン化率が高くなっており、この部分で耐圧が決定されていることがわかる。それに対して、実施の形態１の半導体装置１００では、活性部２００においてインパクトイオン化率が高くなっており、活性部２００のｐｎ主接合の設計耐圧を確保できることがわかる。   From FIG. 16, it can be seen that, in Conventional Example A, the impact ionization rate at the end of the second stage field plate is high, and the breakdown voltage is determined at this portion. In contrast, in the semiconductor device 100 of the first embodiment, the impact ionization rate is high in the active part 200, and it can be seen that the design breakdown voltage of the pn main junction of the active part 200 can be ensured.

実施の形態１によれば、終端構造部３００の主接合（逆バイアスされるｐｎ接合）は、超接合基板２４のｐベース領域側ではなく、ｎ型半導体基板層１と終端構造部３００の下のｐ型仕切り領域８からなるｐｎ接合になる。つまり、平面状の接合の電界上昇が現れる部位が、ｎ型半導体基板層１と終端構造部３００の下のｐ型仕切り領域８の界面となる。従って、超接合基板２４のｐベース領域側に電界集中による高電界部分が生じても、従来のような相乗効果が現れないので、活性部２００のｐｎ主接合の設計耐圧を確保することができる。   According to the first embodiment, the main junction (reversely biased pn junction) of the termination structure 300 is not on the p base region side of the superjunction substrate 24, but under the n-type semiconductor substrate layer 1 and the termination structure 300. This is a pn junction consisting of the p-type partition region 8. That is, the portion where the electric field rise of the planar junction appears is the interface between the n-type semiconductor substrate layer 1 and the p-type partition region 8 under the termination structure portion 300. Therefore, even if a high electric field portion due to electric field concentration is generated on the p base region side of the superjunction substrate 24, the synergistic effect as in the conventional case does not appear, so that the design breakdown voltage of the pn main junction of the active portion 200 can be ensured. .

実施の形態２．
（半導体装置の断面構成）
図１９は、本発明の実施の形態２にかかる半導体装置の要部の構成を示す断面図である。図１９に示すように、実施の形態２の半導体装置１１０が実施の形態１と異なるのは、終端構造部３００とｎ型半導体基板層１の間の半導体領域がｐ型仕切り領域２５とｎ型ドリフト領域２６からなる超接合層２７になっていることである。そして、この終端構造部３００の下の超接合層２７は、平均濃度ＮAveが例えば１．０×１０14ｃｍ-3程度のｐ型になっている。その他の構成は、実施の形態１と同じであるので、重複する説明を省略する。この場合も、平均濃度ＮAveが２．５×１０14ｃｍ-3以下、好ましくは２．０×１０14ｃｍ-3以下のｐ型になっていれば、高い耐圧が得られる。 Embodiment 2. FIG.
(Cross-sectional configuration of semiconductor device)
FIG. 19 is a cross-sectional view showing a configuration of a main part of the semiconductor device according to the second embodiment of the present invention. As shown in FIG. 19, the semiconductor device 110 of the second embodiment is different from the first embodiment in that the semiconductor region between the termination structure 300 and the n-type semiconductor substrate layer 1 is the p-type partition region 25 and the n-type. That is, the super junction layer 27 is formed of the drift region 26. The superjunction layer 27 below the termination structure 300 is p-type having an average concentration N Ave of, for example, about 1.0 × 10 14 cm −3 . The other configuration is the same as that of the first embodiment, and thus a duplicate description is omitted. Also in this case, a high breakdown voltage can be obtained if the p-type has an average concentration N Ave of 2.5 × 10 14 cm −3 or less, preferably 2.0 × 10 14 cm −3 or less.

（終端構造部下の超接合層の平均不純物濃度範囲）
平均濃度ＮAveは、終端構造部３００とその下のｎ型半導体基板層１とに挟まれる超接合層２７の体積をＶEdgeとし、この超接合層２７中のｎ型不純物およびｐ型不純物の総量をそれぞれＮ1およびＮ2（ただし、｜Ｎ2｜≧｜Ｎ1｜）とすると、次の（６）式で表される。
ＮAve＝（｜Ｎ2｜−｜Ｎ1｜）／ＶEdge ・・・（６） (Average impurity concentration range of super-junction layer under termination structure)
The average concentration N Ave is defined as the volume of the superjunction layer 27 sandwiched between the termination structure 300 and the n-type semiconductor substrate layer 1 underneath is V Edge, and the n-type impurities and p-type impurities in the superjunction layer 27 When the total amount is N 1 and N 2 (where | N 2 | ≧ | N 1 |), it is expressed by the following equation (6).
N Ave = (| N 2 | − | N 1 |) / V Edge (6)

従って、実施の形態２では、終端構造部３００とその下のｎ型半導体基板層１とに挟まれる超接合層２７におけるｐ型仕切り領域２５の厚さをｔとすると、（４）式および（５）式は、それぞれ次の（７）式および（８）式のように書き換えられる。
ＮAve＜εSi×Ｅcritical／（ｑ×ｔ） ・・・（７）
ＮAve＜０．８×εSi×Ｅcritical／（ｑ×ｔ） ・・・（８） Therefore, in the second embodiment, assuming that the thickness of the p-type partition region 25 in the superjunction layer 27 sandwiched between the termination structure 300 and the n-type semiconductor substrate layer 1 therebelow is t (4) and ( Equation (5) can be rewritten as the following equations (7) and (8).
N Ave <ε Si × E critical / (q × t) (7)
N Ave <0.8 × ε Si × E critical / (q × t) (8)

上記（７）式を満たすことにより、空乏層が終端構造部３００の下のｎ型半導体基板層１から半導体装置１１０の第１主面に届く。また、上記（８）式を満たすと、空乏層が半導体装置１１０の第１主面に確実に届く。   By satisfying the above expression (7), the depletion layer reaches the first main surface of the semiconductor device 110 from the n-type semiconductor substrate layer 1 under the termination structure portion 300. Further, when the above formula (8) is satisfied, the depletion layer reliably reaches the first main surface of the semiconductor device 110.

（半導体装置の平面構成）
図２０〜図２２は、本発明の実施の形態２にかかる半導体装置の要部の構成を示す平面図である。これらの図は、ｐベース／ボディ領域５、ｎ型チャネルストッパ領域１０、および超接合層２７のｐ型仕切り領域２５とｎ型ドリフト領域２６の各表面よりも上の構成を省略し、これらの領域の表面を示している。 (Planar configuration of semiconductor device)
20 to 22 are plan views showing the configuration of the main part of the semiconductor device according to the second embodiment of the present invention. These figures omit the structures above the surfaces of the p base / body region 5, the n-type channel stopper region 10, and the p-type partition region 25 and the n-type drift region 26 of the superjunction layer 27. The surface of the region is shown.

実施の形態２の半導体装置１１０では、図２０に示すように、終端構造部３００において、すべてのｐ型仕切り領域２５またはｎ型ドリフト領域２６が一方向にのみ伸びるストライプ状に形成されていてもよい。また、図２１に示すように、終端構造部３００において、ｐ型仕切り領域２５またはｎ型ドリフト領域２６の伸びる方向が矩形状のチップの隣り合う辺で９０°異なっていてもよい。さらに、図２２に示すように、終端構造部３００において、ｐ型仕切り領域２５またはｎ型ドリフト領域２６の表面形状が円形状、すなわちｐ型仕切り領域２５またはｎ型ドリフト領域２６が円柱状に形成されていてもよい。   In the semiconductor device 110 according to the second embodiment, as shown in FIG. 20, in the termination structure 300, all the p-type partition regions 25 or the n-type drift regions 26 may be formed in a stripe shape extending only in one direction. Good. Further, as shown in FIG. 21, in the termination structure 300, the extending direction of the p-type partition region 25 or the n-type drift region 26 may be different by 90 ° between adjacent sides of the rectangular chip. Further, as shown in FIG. 22, in the termination structure 300, the surface shape of the p-type partition region 25 or the n-type drift region 26 is circular, that is, the p-type partition region 25 or the n-type drift region 26 is formed in a cylindrical shape. May be.

（半導体装置の製造方法）
次に、半導体装置１１０の製造方法について説明する。ここでは、一例として、耐圧６００Ｖの超接合型ＭＯＳＦＥＴの製造方法について、その終端構造部３００を中心に説明する。図２３〜図２７は、製造段階の半導体装置１１０の要部断面図である。 (Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 110 will be described. Here, as an example, a method for manufacturing a super-junction MOSFET having a withstand voltage of 600 V will be described focusing on the termination structure 300. 23 to 27 are main-portion cross-sectional views of the semiconductor device 110 at the manufacturing stage.

ｎ型半導体基板層１の上に、活性部２００となる領域ではｐ型仕切り領域２とｎ型ドリフト領域３の超接合層４、終端構造部３００の形成領域ではｐ型仕切り領域２５とｎ型ドリフト領域２６の超接合層２７、および半導体装置１１０の切断面９となる領域ではｎ型ピラー領域１１がそれぞれ形成された半導体基板を形成する。   On the n-type semiconductor substrate layer 1, the super junction layer 4 of the p-type partition region 2 and the n-type drift region 3 is formed in the region to be the active portion 200, and the p-type partition region 25 and the n-type are formed in the region where the termination structure portion 300 is formed. A semiconductor substrate in which the n-type pillar region 11 is formed in each of the super junction layer 27 in the drift region 26 and the region to be the cut surface 9 of the semiconductor device 110 is formed.

このような半導体基板を簡便に形成する方法の一つとして、図２３〜図２７に示す方法がある。まず、不純物として例えば２．０×１０18ｃｍ-3程度のアンチモンを含むｎ型Ｓｉ半導体基板２８の上に、例えば１５Ωｃｍ程度のｎ型半導体層２９を例えば６〜１０μｍ程度の厚さに成長させる（図２３）。次いで、ｎ型半導体層２９の全面に例えばリンを１０13ｃｍ-2オーダーのドーズ量でイオン注入する（図２４）。図２４において、符号３０で示す領域は、リン等のｎ型不純物の注入領域である。 As one method for forming such a semiconductor substrate simply, there is a method shown in FIGS. First, on the n-type Si semiconductor substrate 28 containing, for example, about 2.0 × 10 18 cm −3 of antimony as an impurity, an n-type semiconductor layer 29 of about 15 Ωcm is grown to a thickness of, for example, about 6 to 10 μm. (FIG. 23). Next, for example, phosphorus is ion-implanted into the entire surface of the n-type semiconductor layer 29 at a dose of the order of 10 13 cm −2 (FIG. 24). In FIG. 24, a region indicated by reference numeral 30 is an implanted region of n-type impurities such as phosphorus.

次いで、リン等の注入面にフォトレジストを塗布し、そのフォトレジストの所定の箇所を開口させてマスク３１とする。その際、終端構造部３００の形成領域では、ｐベース／ボディ領域５が形成される箇所よりもマスク３１の開口幅が広くなるように加工しておく。活性部２００となる領域では、このマスク３１の開口幅に対応してチャージバランスが取れるように所定濃度のボロン等のｐ型不純物をイオン注入する。   Next, a photoresist is applied to the implantation surface of phosphorus or the like, and a predetermined portion of the photoresist is opened to form a mask 31. At that time, in the region where the termination structure 300 is formed, the mask 31 is processed so that the opening width of the mask 31 is wider than the portion where the p base / body region 5 is formed. In a region to be the active portion 200, a p-type impurity such as boron having a predetermined concentration is ion-implanted so as to achieve charge balance corresponding to the opening width of the mask 31.

上述したように、終端構造部３００の形成領域では、マスク３１の開口幅が広いので、終端構造部３００の形成領域に注入されるボロン等の量がリン等の量よりも多くなる（図２５）。図２５において、符号３２で示す領域は、ボロン等のｐ型不純物の注入領域である。この図２４の工程と図２５の工程を交互にそれぞれ５〜８回程度繰り返す（図２６）。   As described above, since the opening width of the mask 31 is wide in the formation region of the termination structure 300, the amount of boron or the like implanted into the formation region of the termination structure 300 is larger than the amount of phosphorus or the like (FIG. 25). ). In FIG. 25, a region indicated by reference numeral 32 is an implanted region of p-type impurities such as boron. The process of FIG. 24 and the process of FIG. 25 are alternately repeated about 5 to 8 times (FIG. 26).

その後、例えば１１５０℃で１０時間程度の熱処理を行うことによって、上述したようなｎ型半導体基板層１上に、超接合層４，２７のｐ型仕切り領域２，２５およびｎ型ドリフト領域３，２６と、ｎ型ピラー領域１１を有する超接合基板３３ができあがる（図２７）。この超接合基板３３を用い、実施の形態１と同様にして、ゲート酸化膜、ゲート電極、フィールドプレート１３，１４、ｐベース／ボディ領域５、ソース領域、ｎ型チャネルストッパ領域１０、層間絶縁膜１５、ソース電極６およびチャネルストッパ電極１６を形成し（図１０〜図１２参照）、さらにパッシベーション膜１７およびドレイン電極７を形成する。   Thereafter, for example, by performing a heat treatment at 1150 ° C. for about 10 hours, the p-type partition regions 2 and 25 of the superjunction layers 4 and 27 and the n-type drift region 3 are formed on the n-type semiconductor substrate layer 1 as described above. 26 and the super-junction substrate 33 having the n-type pillar region 11 is completed (FIG. 27). Using this super junction substrate 33, the gate oxide film, the gate electrode, the field plates 13, 14, the p base / body region 5, the source region, the n-type channel stopper region 10, the interlayer insulating film in the same manner as in the first embodiment. 15. A source electrode 6 and a channel stopper electrode 16 are formed (see FIGS. 10 to 12), and a passivation film 17 and a drain electrode 7 are formed.

このようにして、図１９に示すような超接合型ＭＯＳＦＥＴの活性部２００と、多段フィールドプレート構造およびチャネルストッパ構造を有する終端構造部３００が完成する。最後に、ダイサーによって、同一ウェハ内で隣り合うチャネルストッパ電極１６の間の、半導体装置１１０が形成されていない領域で個々のチップに切り分けることによって、個々の超接合型ＭＯＳＦＥＴが完成する。   In this way, the superjunction MOSFET active part 200 as shown in FIG. 19 and the termination structure part 300 having a multi-stage field plate structure and a channel stopper structure are completed. Finally, each superjunction MOSFET is completed by cutting into individual chips in a region where the semiconductor device 110 is not formed between adjacent channel stopper electrodes 16 in the same wafer by a dicer.

実施の形態２によれば、終端構造部３００における電界分布が実施の形態１とほぼ同様になる。従って、超接合基板３３のｐベース領域側に電界集中による高電界部分が生じても、従来のような相乗効果が現れないので、活性部２００のｐｎ主接合の設計耐圧を確保することができる。   According to the second embodiment, the electric field distribution in termination structure unit 300 is substantially the same as in the first embodiment. Therefore, even if a high electric field portion due to electric field concentration occurs on the p base region side of the superjunction substrate 33, the synergistic effect as in the conventional case does not appear, so that the design breakdown voltage of the pn main junction of the active portion 200 can be ensured. .

実施の形態３．
（半導体装置の構成）
図２８は、本発明の実施の形態３にかかる半導体装置の要部の構成を示す断面図である。図２８に示すように、実施の形態３の半導体装置１２０が実施の形態１と異なるのは、活性部２００においてｐベース／ボディ領域５に接するｎ型ドリフト領域３がｐ型仕切り領域によって複数に分割されていないことである。活性部２００のｎ型ドリフト領域３の濃度は、例えば２．５×１０14ｃｍ-3程度である。終端構造部３００の下のｐ型仕切り領域８の濃度は、例えば１．０×１０14ｃｍ-3程度である。その他の構成は、実施の形態１と同じであるので、重複する説明を省略する。 Embodiment 3 FIG.
(Configuration of semiconductor device)
FIG. 28 is a cross-sectional view showing the configuration of the main part of the semiconductor device according to the third embodiment of the present invention. As shown in FIG. 28, the semiconductor device 120 of the third embodiment is different from that of the first embodiment in that there are a plurality of n-type drift regions 3 in contact with the p base / body region 5 in the active portion 200 by p-type partition regions. It is not divided. The concentration of the n-type drift region 3 in the active part 200 is, for example, about 2.5 × 10 14 cm −3 . The concentration of the p-type partition region 8 under the termination structure 300 is, for example, about 1.0 × 10 14 cm −3 . The other configuration is the same as that of the first embodiment, and thus a duplicate description is omitted.

（半導体装置の製造方法）
次に、半導体装置１２０の製造方法について説明する。ここでは、一例として、耐圧６００ＶのＭＯＳＦＥＴの製造方法について、その終端構造部３００を中心に説明する。図２９〜図３４は、製造段階の半導体装置１２０の要部断面図である。 (Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 120 will be described. Here, as an example, a method for manufacturing a MOSFET having a withstand voltage of 600 V will be described focusing on the termination structure 300. FIGS. 29 to 34 are cross-sectional views of main parts of the semiconductor device 120 at the manufacturing stage.

ｎ型半導体基板層１の上に、活性部２００となる領域ではｎ型ドリフト領域３、終端構造部３００の形成領域ではｐ型仕切り領域８、および半導体装置１２０の切断面９となる領域ではｎ型ピラー領域１１がそれぞれ形成された半導体基板を形成する。このような半導体基板を簡便に形成する方法の一つとして、図２９〜図３４に示す方法がある。   On the n-type semiconductor substrate layer 1, the n-type drift region 3 is formed in the region to be the active portion 200, the p-type partition region 8 is formed in the formation region of the termination structure 300, and the n is formed in the region to be the cut surface 9 of the semiconductor device 120. A semiconductor substrate on which the mold pillar regions 11 are respectively formed is formed. As one method for forming such a semiconductor substrate simply, there is a method shown in FIGS.

まず、不純物として例えば２．０×１０18ｃｍ-3程度のアンチモンを含むｎ型Ｓｉ半導体基板２８の上に、不純物として例えば２．５×１０14ｃｍ-3程度のリンを含むｎ型半導体層３４を例えば５０μｍ程度の厚さにエピタキシャル成長させる（図２９）。次いで、そのｎ型半導体層３４の、終端構造部３００の形成領域に該当する部分に、幅が例えば１５０μｍで、深さが５０μｍ程度のトレンチ３５を形成する（図３０）。 First, on an n-type Si semiconductor substrate 28 containing, for example, about 2.0 × 10 18 cm −3 of antimony as an impurity, an n-type semiconductor layer containing, for example, about 2.5 × 10 14 cm −3 of phosphorus. 34 is epitaxially grown to a thickness of about 50 μm, for example (FIG. 29). Next, a trench 35 having a width of, for example, 150 μm and a depth of about 50 μm is formed in a portion corresponding to the formation region of the termination structure portion 300 of the n-type semiconductor layer 34 (FIG. 30).

トレンチ３５を形成するにあたっては、熱酸化を行ってｎ型半導体層３４の表面に酸化膜を成長させ、この酸化膜の、終端構造部３００の形成領域を開口させたマスク３６を用い、ＲＩＥ（反応性イオンエッチング）によりドライエッチングを行う。その際、トレンチエッチング前のマスク３６の厚さを例えば約２．４μｍにしておけば、マスク３６は、トレンチエッチングによってエッチングされ、トレンチエッチング終了時に例えば約０．４μｍの厚さで残る。   In forming the trench 35, thermal oxidation is performed to grow an oxide film on the surface of the n-type semiconductor layer 34, and a mask 36 in which the formation region of the termination structure portion 300 of the oxide film is opened is used. Dry etching is performed by reactive ion etching. At this time, if the thickness of the mask 36 before the trench etching is set to about 2.4 μm, for example, the mask 36 is etched by the trench etching and remains at a thickness of about 0.4 μm at the end of the trench etching.

トレンチエッチングには、例えばＩＣＰ（誘導結合プラズマ）方式のプラズマエッチャーを用いる。エッチング条件は、例えば、ＨＢｒガス、ＳＦ6ガスおよびＯ2ガスの流量をそれぞれ４０ｓｃｃｍ、１２０ｓｃｃｍおよび１２０ｓｃｃｍとし、プラズマソースパワーを１２００Ｗとし、バイアスパワーを１４０Ｗとし、圧力を３．３Ｐａとし、エッチング時間を１５分とする。 For trench etching, for example, an ICP (inductively coupled plasma) plasma etcher is used. Etching conditions are, for example, that the flow rates of HBr gas, SF 6 gas, and O 2 gas are 40 sccm, 120 sccm, and 120 sccm, the plasma source power is 1200 W, the bias power is 140 W, the pressure is 3.3 Pa, and the etching time is 15 minutes.

ここでは、ＩＣＰ方式のＲＩＥエッチングを例にしたが、これに限らず、所望の幅および深さのトレンチ３５を形成することができれば、例えばＥＣＲ（電子サイクロトロン共鳴）方式のプラズマエッチャーや、ボッシュ式トレンチエッチャーなどを用いてもよい。また、トレンチ３５がｎ型Ｓｉ半導体基板２８とｎ型半導体層３４の界面よりも例えば１０μｍ程度まで浅くてもよいし、あるいは深くてもよい。   Here, the ICP type RIE etching is taken as an example. However, the present invention is not limited to this, and if a trench 35 having a desired width and depth can be formed, for example, an ECR (electron cyclotron resonance) type plasma etcher, a Bosch type, etc. A trench etcher or the like may be used. Further, the trench 35 may be shallower, for example, to about 10 μm or deeper than the interface between the n-type Si semiconductor substrate 28 and the n-type semiconductor layer 34.

次いで、トレンチ３５内にｐ型不純物として例えば１．０×１０14ｃｍ-3程度のボロンを含むｐ型半導体層３７をエピタキシャル成長させる（図３１）。その際、例えば約１０００℃の常圧雰囲気中でＴＣＳ（トリクロロシラン）を原料に用いてｐ型半導体層３７を成長させてもよいし、減圧雰囲気中でＤＣＳ（ジクロロシラン）を原料に用いてｐ型半導体層３７を成長させてもよい。その場合のエピタキシャル成長レートは、例えば０．３〜３μｍ／ｍｉｎである。 Next, a p-type semiconductor layer 37 containing, for example, about 1.0 × 10 14 cm −3 of boron as a p-type impurity is epitaxially grown in the trench 35 (FIG. 31). At this time, for example, the p-type semiconductor layer 37 may be grown using TCS (trichlorosilane) as a raw material in a normal pressure atmosphere of about 1000 ° C., or using DCS (dichlorosilane) as a raw material in a reduced pressure atmosphere. The p-type semiconductor layer 37 may be grown. In this case, the epitaxial growth rate is, for example, 0.3 to 3 μm / min.

次いで、ｐ型半導体層３７の、マスク３６の表面よりも盛り上がった部分を、例えばＣＭＰ（化学的機械研磨）により削り取る（図３２）。その際、マスク３６とした酸化膜がストッパとなるように、シリコン／酸化シリコンの選択比が十分に大きいスラリーを用いる。例えば、（株）フジミインコーポレーテッド製の高純度コロイダルシリカスラリーｐｌａｎｅｒｌｉｔｅ−６１０３を用いる。そして、代表的な研磨条件として、トップリング圧力を３００〜６００ｈＰａとし、テーブル回転数を５０〜１００ｒｐｍとする。この条件でのシリコン／酸化シリコンの選択比は約１００倍である。なお、ＣＭＰ等を行う前に熱酸化を行ってもよい。   Next, a portion of the p-type semiconductor layer 37 that is raised above the surface of the mask 36 is scraped off by, for example, CMP (Chemical Mechanical Polishing) (FIG. 32). At this time, a slurry having a sufficiently large silicon / silicon oxide selection ratio is used so that the oxide film used as the mask 36 serves as a stopper. For example, a high-purity colloidal silica slurry planarlite-6103 manufactured by Fujimi Incorporated is used. As typical polishing conditions, the top ring pressure is set to 300 to 600 hPa, and the table rotation speed is set to 50 to 100 rpm. Under this condition, the silicon / silicon oxide selection ratio is about 100 times. Note that thermal oxidation may be performed before performing CMP or the like.

次いで、熱酸化を行う。この熱酸化では、ｐ型半導体層３７の酸化レートがマスク３６とした酸化膜の酸化レートよりも速いので、ｐ型半導体層３７およびマスク３６とした酸化膜の全面にわたって均一な酸化膜３８が形成される（図３３）。この酸化膜３８の厚さは、例えば８００ｎｍ程度でよい。   Next, thermal oxidation is performed. In this thermal oxidation, since the oxidation rate of the p-type semiconductor layer 37 is faster than the oxidation rate of the oxide film used as the mask 36, a uniform oxide film 38 is formed over the entire surface of the oxide film used as the p-type semiconductor layer 37 and the mask 36. (FIG. 33). The thickness of the oxide film 38 may be about 800 nm, for example.

次いで、ＨＦウェット洗浄によるエッチングによって酸化膜３８を除去する。図３３の熱酸化工程を行わずにＨＦエッチングを行って、トレンチエッチングの際にマスク３６とした酸化膜を除去してもよいが、その場合には、ｎ型半導体層３４の表面とｐ型半導体層３７の表面の間に、マスク３６の厚さ（例えば、０．４μｍ）に相当する段差が生じる。図３３の熱酸化工程を行うことによって、酸化膜３８を除去した後に段差のない平坦な表面が得られる。   Next, the oxide film 38 is removed by etching by HF wet cleaning. The HF etching may be performed without performing the thermal oxidation step of FIG. 33 to remove the oxide film used as the mask 36 during the trench etching. In this case, the surface of the n-type semiconductor layer 34 and the p-type are removed. A step corresponding to the thickness of the mask 36 (for example, 0.4 μm) occurs between the surfaces of the semiconductor layer 37. By performing the thermal oxidation process of FIG. 33, a flat surface without a step is obtained after the oxide film 38 is removed.

このようにして、ｎ型半導体基板層１上にｎ型ドリフト領域３、ｎ型ピラー領域１１およびｐ型仕切り領域８を有するエピタキシャル基板３９ができあがる（図３４）。このエピタキシャル基板３９を用い、実施の形態１と同様にして、ゲート酸化膜、ゲート電極、フィールドプレート１３，１４、ｐベース／ボディ領域５、ソース領域、ｎ型チャネルストッパ領域１０、層間絶縁膜１５、ソース電極６およびチャネルストッパ電極１６を形成し（図１０〜図１２参照）、さらにパッシベーション膜１７およびドレイン電極７を形成する。   In this way, an epitaxial substrate 39 having the n-type drift region 3, the n-type pillar region 11, and the p-type partition region 8 is formed on the n-type semiconductor substrate layer 1 (FIG. 34). Using this epitaxial substrate 39, the gate oxide film, the gate electrode, the field plates 13, 14, the p base / body region 5, the source region, the n-type channel stopper region 10, and the interlayer insulating film 15 in the same manner as in the first embodiment. The source electrode 6 and the channel stopper electrode 16 are formed (see FIGS. 10 to 12), and the passivation film 17 and the drain electrode 7 are further formed.

このようにして、図２８に示すようなＭＯＳＦＥＴの活性部２００と、多段フィールドプレート構造およびチャネルストッパ構造を有する終端構造部３００が完成する。最後に、ダイサーによって、同一ウェハ内で隣り合うチャネルストッパ電極１６の間の、半導体装置１２０が形成されていない領域で個々のチップに切り分けることによって、個々のＭＯＳＦＥＴが完成する。   In this way, the MOSFET active portion 200 as shown in FIG. 28 and the termination structure portion 300 having a multi-stage field plate structure and a channel stopper structure are completed. Finally, individual MOSFETs are completed by dicing into individual chips in a region where the semiconductor device 120 is not formed between adjacent channel stopper electrodes 16 in the same wafer.

（終端構造部下のｐ型仕切り領域の平面形状）
図３５は、終端構造部下のｐ型仕切り領域の平面形状を示す平面図であり、図３６は、そのｐ型仕切り領域の角になる部分を拡大した図である。図３５に示すように、終端構造部３００の下のｐ型仕切り領域８は、活性部２００の周囲を囲むように配置される。このｐ型仕切り領域８の角になる部分の幅が直線部分の幅と同じであると、終端構造部３００での電界集中が起こりにくくなり、理想的である。従って、終端構造部３００の下のｐ型仕切り領域８の幅は、角の部分も直線部分も同じであるとよい。 (Planar shape of the p-type partition region under the termination structure)
FIG. 35 is a plan view showing a planar shape of the p-type partition region under the termination structure portion, and FIG. 36 is an enlarged view of a corner portion of the p-type partition region. As shown in FIG. 35, the p-type partition region 8 below the termination structure unit 300 is arranged so as to surround the periphery of the active unit 200. When the width of the portion that becomes the corner of the p-type partition region 8 is the same as the width of the straight line portion, the electric field concentration in the termination structure portion 300 hardly occurs, which is ideal. Therefore, the width of the p-type partition region 8 under the termination structure 300 is preferably the same for both the corner portion and the straight portion.

しかし、上述した製造プロセスのように、トレンチ３５内にｐ型仕切り領域８となるｐ型半導体層３７をエピタキシャル成長させる場合、トレンチ側壁の面方位が（１００）であるときに最も成長レートが高くなり、それ以外の面方位では成長レートが低くなる。従って、図３５に示すｐ型仕切り領域８の直線部分のトレンチ側壁の面方位を（１００）に設定してエピタキシャル成長を行うと、ｐ型仕切り領域８の角になる部分のトレンチ側壁の面方位は（１００）ではないので、その角になる部分でのエピタキシャル成長レートが低くなってしまう。   However, when the p-type semiconductor layer 37 to be the p-type partition region 8 is epitaxially grown in the trench 35 as in the manufacturing process described above, the growth rate is highest when the surface orientation of the trench sidewall is (100). In other plane orientations, the growth rate is low. Therefore, when epitaxial growth is performed with the surface orientation of the trench sidewall of the straight portion of the p-type partition region 8 shown in FIG. 35 set to (100), the surface orientation of the trench sidewall at the corner of the p-type partition region 8 is Since it is not (100), the epitaxial growth rate at the corner becomes low.

そのため、トレンチ３５内をｐ型半導体層３７で完全に埋めるまでに時間がかかってしまうことがある。そこで、図３６に示すように、ｐ型仕切り領域８の角になる部分のトレンチ形状を、円弧状ではなく、階段状とする。ｐ型仕切り領域８の角になる部分のトレンチ形状を階段状にすると、円弧状である場合に比べて、ｐ型半導体層３７のエピタキシャル成長レートが高くなる。つまり、短時間でトレンチ３５をｐ型半導体層３７で埋めることができるので、スループットが向上し、生産性がよくなる。   Therefore, it may take time until the trench 35 is completely filled with the p-type semiconductor layer 37. Therefore, as shown in FIG. 36, the trench shape at the corner of the p-type partition region 8 is not a circular arc but a step shape. When the trench shape at the corner of the p-type partition region 8 is stepped, the epitaxial growth rate of the p-type semiconductor layer 37 is higher than that in the case of an arc shape. That is, since the trench 35 can be filled with the p-type semiconductor layer 37 in a short time, the throughput is improved and the productivity is improved.

（従来例との比較）
実施の形態３の半導体装置と従来構成の半導体装置（従来例Ｂとする）について、耐圧を調べた結果を図３７に示す。また、アバランシェ降伏時の電位分布、電界分布およびインパクトイオン化率をシミュレーションによって比較した結果をそれぞれ図３８、図３９および図４０に示す。なお、図４１に示すように、従来例Ｂの半導体装置２０００は、終端構造部３００とその下のｎ型半導体基板層１の間の半導体領域２００８の導電型をｎ型にした以外は、実施の形態３の半導体装置１２０と同じ構造のものである。 (Comparison with conventional example)
FIG. 37 shows the results of examining the breakdown voltage of the semiconductor device of the third embodiment and the semiconductor device having the conventional configuration (conventional example B). In addition, the results of comparing the potential distribution, electric field distribution, and impact ionization rate during avalanche breakdown by simulation are shown in FIGS. 38, 39, and 40, respectively. As shown in FIG. 41, the semiconductor device 2000 of the conventional example B is implemented except that the conductivity type of the semiconductor region 2008 between the termination structure 300 and the n-type semiconductor substrate layer 1 thereunder is n-type. The semiconductor device 120 has the same structure as that of the third embodiment.

図３７より、実施の形態３の半導体装置１２０の耐圧は、従来例Ｂよりも高いアバランシェ降伏電圧を示すことがわかる。また、図３８より、実施の形態３の半導体装置１２０および従来例Ｂのいずれでも、電位面がフィールドプレート端で曲率を有しており、それら曲率の部分の電界が高くなっていることが予想される。しかし、図３９より、実施の形態３の半導体装置１２０のフィールドプレート端の電界強度は、従来例Ｂのフィールドプレート端の電界強度よりも低いことがわかる。   From FIG. 37, it can be seen that the breakdown voltage of the semiconductor device 120 of the third embodiment shows a higher avalanche breakdown voltage than that of the conventional example B. 38, it is expected that in both the semiconductor device 120 of the third embodiment and the conventional example B, the potential surface has a curvature at the end of the field plate, and the electric field at those curvature portions is high. Is done. However, FIG. 39 shows that the electric field strength at the field plate end of the semiconductor device 120 of the third embodiment is lower than the electric field strength at the field plate end of the conventional example B.

これは、実施の形態３の半導体装置１２０では、電圧を支える主接合面がｎ型半導体基板層１と終端構造部３００の下のｐ型仕切り領域８の界面にあり、ｐベース／ボディ領域５が形成されている第１主面に向かって電界強度が低下している。それに対して、従来例Ｂでは、終端構造部３００の下の半導体領域２００８がｎ型であるため、電圧を支える主接合面がｎ型半導体領域２００８の表面層、すなわちｐベース／ボディ領域５の形成面にある。従って、従来例Ｂでは、平面接合の電界上昇と、電界集中による高電界部分ができることの相乗効果が現れてしまう。   This is because, in the semiconductor device 120 of the third embodiment, the main junction surface supporting the voltage is at the interface between the n-type semiconductor substrate layer 1 and the p-type partition region 8 under the termination structure 300, and the p base / body region 5 The electric field strength decreases toward the first main surface on which is formed. On the other hand, in the conventional example B, since the semiconductor region 2008 under the termination structure 300 is n-type, the main junction surface that supports the voltage is the surface layer of the n-type semiconductor region 2008, that is, the p base / body region 5. On the forming surface. Therefore, in the conventional example B, there is a synergistic effect that the electric field rise of the planar junction and a high electric field portion due to electric field concentration are formed.

図４０より、従来例Ｂでは、２段目フィールドプレート端でのインパクトイオン化率が高くなっており、この部分で耐圧が決定されていることがわかる。それに対して、実施の形態３の半導体装置１２０では、活性部２００においてインパクトイオン化率が高くなっており、活性部２００のｐｎ主接合の設計耐圧を確保できることがわかる。   From FIG. 40, it can be seen that in Conventional Example B, the impact ionization rate at the end of the second stage field plate is high, and the breakdown voltage is determined at this portion. On the other hand, in the semiconductor device 120 of the third embodiment, the impact ionization rate is high in the active part 200, and it can be seen that the design breakdown voltage of the pn main junction of the active part 200 can be ensured.

実施の形態３によれば、終端構造部３００における電界分布が実施の形態１とほぼ同様になる。従って、エピタキシャル基板３９のｐベース領域側に電界集中による高電界部分が生じても、従来のような相乗効果が現れないので、活性部２００のｐｎ主接合の設計耐圧を確保することができる。   According to the third embodiment, the electric field distribution in termination structure unit 300 is substantially the same as in the first embodiment. Therefore, even if a high electric field portion due to electric field concentration is generated on the p base region side of the epitaxial substrate 39, the synergistic effect as in the conventional case does not appear, so that the design breakdown voltage of the pn main junction of the active portion 200 can be ensured.

実施の形態４．
（半導体装置の構成）
図４２は、本発明の実施の形態４にかかる半導体装置の要部の構成を示す断面図である。図４２に示すように、実施の形態４は実施の形態３の変形例である。実施の形態４の半導体装置１３０が実施の形態３と異なるのは、ｎ型半導体基板層１と終端構造部３００の下のｐ型仕切り領域８との間に数百〜千数百ｎｍ程度の厚さの絶縁層である酸化シリコンよりなる酸化膜層４０が設けられていることである。その他の構成は、実施の形態３と同じであるので、重複する説明を省略する。 Embodiment 4 FIG.
(Configuration of semiconductor device)
FIG. 42 is a cross-sectional view showing the configuration of the main part of the semiconductor device according to the fourth embodiment of the present invention. As shown in FIG. 42, the fourth embodiment is a modification of the third embodiment. The semiconductor device 130 of the fourth embodiment is different from that of the third embodiment in that it is several hundred to several hundreds of nanometers between the n-type semiconductor substrate layer 1 and the p-type partition region 8 under the termination structure 300. That is, an oxide film layer 40 made of silicon oxide which is an insulating layer having a thickness is provided. Other configurations are the same as those in the third embodiment, and thus redundant description is omitted.

（半導体装置の製造方法）
次に、半導体装置１３０の製造方法について説明する。ここでは、一例として、耐圧６００ＶのＭＯＳＦＥＴの製造方法について、その終端構造部３００を中心に説明する。図４３〜図４８は、製造段階の半導体装置１３０の要部断面図である。 (Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 130 will be described. Here, as an example, a method for manufacturing a MOSFET having a withstand voltage of 600 V will be described focusing on the termination structure 300. 43 to 48 are main-portion cross-sectional views of the semiconductor device 130 at the manufacturing stage.

ｎ型半導体基板層１の上に、活性部２００となる領域ではｎ型ドリフト領域３、終端構造部３００の形成領域ではｐ型仕切り領域８、および半導体装置１３０の切断面９となる領域ではｎ型ピラー領域１１がそれぞれ形成された半導体基板を形成する。このような半導体基板を簡便に形成する方法の一つとして、図４３〜図４８に示す方法がある。   On the n-type semiconductor substrate layer 1, the n-type drift region 3 is formed in the region to be the active part 200, the p-type partition region 8 is formed in the formation region of the termination structure 300, and the n is formed in the region to be the cut surface 9 of the semiconductor device 130. A semiconductor substrate on which the mold pillar regions 11 are respectively formed is formed. One method for easily forming such a semiconductor substrate is shown in FIGS.

まず、不純物として例えば２．０×１０18ｃｍ-3程度のアンチモンを含むｎ型Ｓｉ半導体基板２８と、不純物として例えば１．０×１０14ｃｍ-3程度のボロンを含むｐ型半導体層４１の間に、数百ｎｍ程度の厚さの酸化膜層４０が挟まれたＳＯＩ基板４２を用意する（図４３）。その際、ｐ型半導体層４１の厚さを所望のｎ型ドリフト領域３の厚さにすることが望ましい。 First, an n-type Si semiconductor substrate 28 containing, for example, about 2.0 × 10 18 cm −3 of antimony as an impurity, and a p-type semiconductor layer 41 containing, for example, about 1.0 × 10 14 cm −3 of boron as an impurity. An SOI substrate 42 in which an oxide film layer 40 having a thickness of about several hundred nm is sandwiched therebetween is prepared (FIG. 43). At this time, it is desirable to set the thickness of the p-type semiconductor layer 41 to the desired thickness of the n-type drift region 3.

次いで、熱酸化を行って、ｐ型半導体層４１の表面に所定の厚さの酸化膜を成長させる。そして、その酸化膜の、活性部２００およびｎ型ピラー領域１１に該当する部分を開口してマスク４３とし、周知のトレンチエッチング技術によりｐ型半導体層４１にトレンチ４４を形成する（図４４）。その際、トレンチエッチング技術として、異方性ドライエッチングや、｛１１１｝面ＳＯＩ基板４２の異方性湿式エッチングを行うことによって、トレンチ４４の側壁の角度は、ｎ型Ｓｉ半導体基板２８の主面に対して９０°またはほぼ９０°になる。   Next, thermal oxidation is performed to grow an oxide film having a predetermined thickness on the surface of the p-type semiconductor layer 41. Then, a portion corresponding to the active portion 200 and the n-type pillar region 11 of the oxide film is opened as a mask 43, and a trench 44 is formed in the p-type semiconductor layer 41 by a well-known trench etching technique (FIG. 44). At that time, by performing anisotropic dry etching or anisotropic wet etching of the {111} plane SOI substrate 42 as a trench etching technique, the angle of the sidewall of the trench 44 is changed to the main surface of the n-type Si semiconductor substrate 28. Is 90 ° or almost 90 °.

次いで、トレンチ４４の底に残る酸化膜層４０を除去する（図４５）。ｐ型半導体層４１の、トレンチエッチング後に残った部分と、ｎ型Ｓｉ半導体基板２８の間には、酸化膜層４０が残る。次いで、トレンチ４４内に不純物として例えば２．５×１０14ｃｍ-3程度のリンを含むｎ型半導体層４５をエピタキシャル成長させる（図４６）。 Next, the oxide film layer 40 remaining at the bottom of the trench 44 is removed (FIG. 45). The oxide film layer 40 remains between the portion of the p-type semiconductor layer 41 remaining after the trench etching and the n-type Si semiconductor substrate 28. Next, an n-type semiconductor layer 45 containing, for example, about 2.5 × 10 14 cm −3 of phosphorus as an impurity is epitaxially grown in the trench 44 (FIG. 46).

次いで、マスク４３とした酸化膜をストッパとして、ｎ型半導体層４５の、マスク４３の表面よりも盛り上がった部分を、例えばＣＭＰにより削り取る（図４７）。なお、ＣＭＰ等を行う前に熱酸化を行ってもよい。次いで、熱酸化を行い、ｎ型半導体層４５およびマスク４３とした酸化膜の全面にわたって例えば８００ｎｍ程度の均一な厚さの酸化膜を形成する。この酸化膜を除去することによって、段差のない平坦な表面が得られる。   Next, using the oxide film as the mask 43 as a stopper, the portion of the n-type semiconductor layer 45 that is raised from the surface of the mask 43 is scraped off by, for example, CMP (FIG. 47). Note that thermal oxidation may be performed before performing CMP or the like. Next, thermal oxidation is performed to form an oxide film having a uniform thickness of, for example, about 800 nm over the entire surface of the oxide film used as the n-type semiconductor layer 45 and the mask 43. By removing this oxide film, a flat surface without a step is obtained.

このようにして、ｎ型半導体基板層１上にｎ型ドリフト領域３、ｎ型ピラー領域１１、酸化膜層４０およびｐ型仕切り領域８を有する部分ＳＯＩ基板４６ができあがる（図４８）。この部分ＳＯＩ基板４６を用い、実施の形態１と同様にして、ゲート酸化膜、ゲート電極、フィールドプレート１３，１４、ｐベース／ボディ領域５、ソース領域、ｎ型チャネルストッパ領域１０、層間絶縁膜１５、ソース電極６およびチャネルストッパ電極１６を形成し（図１０〜図１２参照）、さらにパッシベーション膜１７およびドレイン電極７を形成する。   In this way, a partial SOI substrate 46 having the n-type drift region 3, the n-type pillar region 11, the oxide film layer 40, and the p-type partition region 8 is formed on the n-type semiconductor substrate layer 1 (FIG. 48). Using this partial SOI substrate 46, in the same manner as in the first embodiment, the gate oxide film, the gate electrode, the field plates 13, 14, the p base / body region 5, the source region, the n-type channel stopper region 10, and the interlayer insulating film 15. A source electrode 6 and a channel stopper electrode 16 are formed (see FIGS. 10 to 12), and a passivation film 17 and a drain electrode 7 are formed.

このようにして、図４２に示すようなＭＯＳＦＥＴの活性部２００と、多段フィールドプレート構造およびチャネルストッパ構造を有する終端構造部３００が完成する。最後に、ダイサーによって、同一ウェハ内で隣り合うチャネルストッパ電極１６の間の、半導体装置１３０が形成されていない領域で個々のチップに切り分けることによって、個々のＭＯＳＦＥＴが完成する。   In this way, the MOSFET active portion 200 as shown in FIG. 42 and the termination structure portion 300 having a multi-stage field plate structure and a channel stopper structure are completed. Finally, individual MOSFETs are completed by dicing into individual chips in a region where the semiconductor device 130 is not formed between adjacent channel stopper electrodes 16 in the same wafer.

実施の形態４によれば、終端構造部３００における電界分布が実施の形態１とほぼ同様になる。従って、部分ＳＯＩ基板４６のｐベース領域側に電界集中による高電界部分が生じても、従来のような相乗効果が現れないので、活性部２００のｐｎ主接合の設計耐圧を確保することができる。また、ｎ型ドリフト領域３の厚さの精度が実施の形態３よりも高い。なお、酸化膜層４０に代えて、ｎ型半導体基板層１と終端構造部３００の下のｐ型仕切り領域８との間に、ｎ型半導体基板層１よりも濃度の低いｎ型低濃度層を設けてもよい。   According to the fourth embodiment, the electric field distribution in termination structure unit 300 is substantially the same as in the first embodiment. Therefore, even if a high electric field portion due to electric field concentration occurs on the p base region side of the partial SOI substrate 46, a synergistic effect as in the conventional case does not appear, and therefore the design breakdown voltage of the pn main junction of the active portion 200 can be ensured. . Further, the accuracy of the thickness of the n-type drift region 3 is higher than that of the third embodiment. Instead of the oxide film layer 40, an n-type low concentration layer having a lower concentration than the n-type semiconductor substrate layer 1 is provided between the n-type semiconductor substrate layer 1 and the p-type partition region 8 below the termination structure 300. May be provided.

実施の形態５．
（半導体装置の構成）
図４９は、本発明の実施の形態５にかかる半導体装置の要部の構成を示す断面図である。図４９に示すように、実施の形態５は実施の形態４の変形例である。実施の形態５の半導体装置１４０が実施の形態４と異なるのは、終端構造部３００の下のｐ型仕切り領域８がフィールドプレート構造が設けられた側からｎ型半導体基板層１の側へ向かって広がっていることである。 Embodiment 5 FIG.
(Configuration of semiconductor device)
FIG. 49 is a cross-sectional view showing the configuration of the main part of the semiconductor device according to the fifth embodiment of the present invention. As shown in FIG. 49, the fifth embodiment is a modification of the fourth embodiment. The semiconductor device 140 of the fifth embodiment is different from that of the fourth embodiment in that the p-type partition region 8 under the termination structure 300 is directed from the side where the field plate structure is provided to the n-type semiconductor substrate layer 1 side. Is spreading.

活性部２００のｎ型ドリフト領域３およびｎ型ピラー領域１１と、終端構造部３００の下のｐ型仕切り領域８との境界面は、ｎ型半導体基板層１の主面に対して５５°またはほぼ５５°の角度をなして傾いている。この境界部分では、ｎ型ドリフト領域３およびｎ型ピラー領域１１がｐ型仕切り領域８の上になっている。その他の構成は、実施の形態４と同じであるので、重複する説明を省略する。   The boundary surface between the n-type drift region 3 and the n-type pillar region 11 of the active part 200 and the p-type partition region 8 under the termination structure 300 is 55 ° with respect to the main surface of the n-type semiconductor substrate layer 1 or It is inclined at an angle of approximately 55 °. At this boundary portion, the n-type drift region 3 and the n-type pillar region 11 are on the p-type partition region 8. The other configuration is the same as that of the fourth embodiment, and a duplicate description is omitted.

（半導体装置の製造方法）
半導体装置１４０の製造方法は、実施の形態４と同じである。ただし、実施の形態４の図４４に示すトレンチ形成工程において、トレンチ４４を、その側壁がｎ型Ｓｉ半導体基板２８の主面に対して５５°またはほぼ５５°の角度で傾くように形成する。そのためには、｛１１１｝面ＳＯＩ基板４２の異方性湿式エッチングを行うようにすればよく、異方性湿式エッチングを行った場合、５４．７°の角度となる。実施の形態５によれば、実施の形態４と同様の効果が得られる。 (Method for manufacturing semiconductor device)
The manufacturing method of the semiconductor device 140 is the same as that of the fourth embodiment. However, in the trench formation step shown in FIG. 44 of the fourth embodiment, the trench 44 is formed so that the side wall thereof is inclined at an angle of 55 ° or approximately 55 ° with respect to the main surface of the n-type Si semiconductor substrate 28. For that purpose, the anisotropic wet etching of the {111} plane SOI substrate 42 may be performed, and when the anisotropic wet etching is performed, the angle becomes 54.7 °. According to the fifth embodiment, the same effect as in the fourth embodiment can be obtained.

実施の形態６．
（半導体装置の構成）
図５０は、本発明の実施の形態６にかかる半導体装置の要部の構成を示す断面図である。図５０に示すように、実施の形態６は実施の形態３の変形例である。実施の形態６の半導体装置１５０が実施の形態３と異なるのは、終端構造部３００の下の半導体層が、ｐ型仕切り領域８と、活性部２００から伸びるｎ型ドリフト領域３およびｎ型ピラー領域１１とで形成されていることである。 Embodiment 6 FIG.
(Configuration of semiconductor device)
FIG. 50 is a cross-sectional view showing the configuration of the main part of the semiconductor device according to the sixth embodiment of the present invention. As shown in FIG. 50, the sixth embodiment is a modification of the third embodiment. The semiconductor device 150 of the sixth embodiment is different from that of the third embodiment in that the semiconductor layer under the termination structure portion 300 includes the p-type partition region 8, the n-type drift region 3 and the n-type pillar extending from the active portion 200. That is, the region 11 is formed.

ｎ型ドリフト領域３およびｎ型ピラー領域１１とｐ型仕切り領域８との境界面は、終端構造部３００の下に位置し、ｐ型仕切り領域８、ｎ型ドリフト領域３およびｐベース／ボディ領域５などの半導体層の主面に対して５５°またはほぼ５５°の角度をなして傾いている。この境界部分では、ｐ型仕切り領域８がｎ型ドリフト領域３およびｎ型ピラー領域１１の上になっている。また、ｐ型仕切り領域８は、ｎ型半導体基板層１に達している。その他の構成は、実施の形態３と同じであるので、重複する説明を省略する。   The boundary surface between n-type drift region 3 and n-type pillar region 11 and p-type partition region 8 is located below termination structure 300, and includes p-type partition region 8, n-type drift region 3, and p base / body region. It is inclined at an angle of 55 ° or almost 55 ° with respect to the main surface of the semiconductor layer such as 5. At this boundary portion, the p-type partition region 8 is above the n-type drift region 3 and the n-type pillar region 11. The p-type partition region 8 reaches the n-type semiconductor substrate layer 1. Other configurations are the same as those in the third embodiment, and thus redundant description is omitted.

（半導体装置の製造方法）
次に、半導体装置１５０の製造方法について説明する。ここでは、一例として、耐圧６００ＶのＭＯＳＦＥＴの製造方法について、その終端構造部３００を中心に説明する。図５１〜図５５は、製造段階の半導体装置１５０の要部断面図である。 (Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 150 will be described. Here, as an example, a method for manufacturing a MOSFET having a withstand voltage of 600 V will be described focusing on the termination structure 300. 51 to 55 are cross-sectional views of main parts of the semiconductor device 150 at the manufacturing stage.

ｎ型半導体基板層１の上に、ｎ型ドリフト領域３、ｐ型仕切り領域８およびｎ型ピラー領域１１が上述した断面形状をなすように形成された半導体基板を形成する。このような半導体基板を簡便に形成する方法の一つとして、図５１〜図５５に示す方法がある。   On the n-type semiconductor substrate layer 1, a semiconductor substrate is formed in which the n-type drift region 3, the p-type partition region 8, and the n-type pillar region 11 are formed to have the above-described cross-sectional shape. One method for easily forming such a semiconductor substrate is shown in FIGS.

まず、不純物として例えば２．０×１０18ｃｍ-3程度のアンチモンを含むｎ型Ｓｉ半導体基板２８の上に、不純物として例えば２．５×１０14ｃｍ-3程度のリンを含むｎ型半導体層３４を成長させる（図２９参照）。実施の形態６では、ｎ型Ｓｉ半導体基板２８として、面方位が｛１００｝である基板を用いる。 First, on an n-type Si semiconductor substrate 28 containing, for example, about 2.0 × 10 18 cm −3 of antimony as an impurity, an n-type semiconductor layer containing, for example, about 2.5 × 10 14 cm −3 of phosphorus. 34 is grown (see FIG. 29). In the sixth embodiment, a substrate having a {100} plane orientation is used as the n-type Si semiconductor substrate 28.

次いで、熱酸化を行って、ｎ型半導体層３４の表面に所定の厚さの酸化膜を成長させ、その酸化膜の、終端構造部３００に該当する部分を開口してマスク４７とする。そして、ＴＭＡＨ（水酸化テトラメチルアンモニウム）等を用いて、｛１１１｝面が露出するように湿式異方性エッチングを行い、ｎ型半導体層３４に断面形状がＶ字状の溝（以下、Ｖ溝とする）４８を形成する（図５１）。Ｖ溝４８は基板面に対して５４．７°（約５５°）である。Ｖ溝４８の底はｎ型Ｓｉ半導体基板２８に達していてもよいし、達していなくてもよい。ここで、ＴＭＡＨ水溶液はマイクロピラミットの形成を避けつつ、エッチングレートを確保するために、濃度１０ｗｔ％の液を用い、エッチングは８０℃で行った。この時のエッチングレートは０．５μｍ／ｍｉｎであった。ＴＭＡＨ水溶液によるエッチングでは（１００）、（１１０）面に比べて（１１１）面のエッチングレートが１／１００程度であり、自然に（１１１）面が形成され、（１１１）面が形成された時点でエッチングがほとんど進まなくなる。そのため、再現性のよいＶ溝の形成が可能となった。酸化膜の開口幅を１００μｍとするとＶ溝の深さは約７０μｍとなった。また、シリコン半導体基板と熱酸化による酸化膜とのエッチングレートの比が１００００であり、Ｖ溝形成時においては、数ｎｍ程度しかエッチングされない。よって、酸化膜厚としては、ＲＩＥでの異方性エッチングによって溝を形成する場合に比べ薄くすることができ、１００ｎｍの厚さでよい。   Next, thermal oxidation is performed to grow an oxide film having a predetermined thickness on the surface of the n-type semiconductor layer 34, and a portion corresponding to the termination structure portion 300 is opened to form a mask 47. Then, wet anisotropic etching is performed using TMAH (tetramethylammonium hydroxide) or the like so that the {111} plane is exposed, and the n-type semiconductor layer 34 has a V-shaped groove (hereinafter referred to as V-shaped groove). 48) (FIG. 51). The V-groove 48 is 54.7 ° (about 55 °) with respect to the substrate surface. The bottom of the V groove 48 may or may not reach the n-type Si semiconductor substrate 28. Here, as the TMAH aqueous solution, a liquid having a concentration of 10 wt% was used in order to ensure the etching rate while avoiding the formation of micropyramit, and the etching was performed at 80 ° C. The etching rate at this time was 0.5 μm / min. In the etching with the TMAH aqueous solution, the etching rate of the (111) plane is about 1/100 compared to the (100) and (110) planes, and the (111) plane is naturally formed and the (111) plane is formed. Etching hardly progresses. Therefore, it becomes possible to form a V-groove with good reproducibility. When the opening width of the oxide film was 100 μm, the depth of the V groove was about 70 μm. Further, the etching rate ratio between the silicon semiconductor substrate and the oxide film formed by thermal oxidation is 10000, and only about several nm is etched when the V-groove is formed. Therefore, the oxide film thickness can be reduced as compared with the case where the groove is formed by anisotropic etching by RIE, and may be 100 nm.

次いで、Ｖ溝４８内にｐ型不純物として例えば１．０×１０14ｃｍ-3程度のボロンを含むｐ型半導体層４９をエピタキシャル成長させる（図５２）。エピタキシャル成長はトリクロロシラン又はジクロロシランをシリコン原料とし、ドーパントガスとしてジボラン（Ｂ2Ｈ6）を用い、更に同時に塩化水素（ＨＣｌ）を供給することで酸化膜上へのポリシリコンの成長を抑制しＶ溝部のみにエピタキシャル成長させた。このことにより、良質なＶ溝の埋め込みが可能になると共に、後のＣＭＰによる半導体基板表面の平坦化が容易になった。成長温度は９５０℃〜１１００℃がエピタキシャル成長レート０．３〜３μｍ／ｍｉｎを確保でき望ましい。Ｖ溝への埋め込みのため、埋め込みの際にボイドの形成が起こらないことも利点である。垂直な溝であると、トレンチ開口部分が埋め込みの途中で閉じてしまってボイドの発生が起こり特性・プロセス上好ましくないことがある。次いで、マスク４７とした酸化膜をストッパとして、ｐ型半導体層４９の、マスク４７の表面よりも盛り上がった部分を、例えばＣＭＰにより削り取る（図５３）。研磨の方法は、ＣＭＰを用い、酸化膜がストッパとなるようシリコンと酸化膜のエッチング選択比が十分大きいスラリを用いるのが有効であった。例えば、（株）フジミインコーポレーテッド製の高純度コロイダルシリカスラリPlanerlite-6103を用い、研磨条件トップリング圧力＝３００〜６００ｈPa、テーブル回転数５０〜１００ｒ／ｍｉｎとした。この条件でのシリコン／酸化膜の選択比は約１００倍であった。なお、ＣＭＰ等を行う前に熱酸化を行ってもよい。次いで、熱酸化を行い、ｐ型半導体層４９およびマスク４７とした酸化膜の全面にわたって例えば８００ｎｍ程度の均一な厚さの酸化膜を形成する。この酸化膜を除去することによって、段差のない平坦な表面が得られる。 Next, a p-type semiconductor layer 49 containing, for example, about 1.0 × 10 14 cm −3 of boron as a p-type impurity is epitaxially grown in the V groove 48 (FIG. 52). In the epitaxial growth, trichlorosilane or dichlorosilane is used as a silicon raw material, diborane (B 2 H 6 ) is used as a dopant gas, and hydrogen chloride (HCl) is simultaneously supplied to suppress growth of polysilicon on the oxide film. Epitaxial growth was performed only in the groove. This makes it possible to bury a good V-groove and facilitate the flattening of the semiconductor substrate surface by subsequent CMP. The growth temperature is preferably from 950 ° C. to 1100 ° C. because an epitaxial growth rate of 0.3 to 3 μm / min can be secured. Another advantage is that void formation does not occur during the embedding because of the embedding in the V-groove. If it is a vertical groove, the trench opening may be closed in the middle of filling and voids may occur, which may be undesirable in terms of characteristics and processes. Next, using the oxide film used as the mask 47 as a stopper, the portion of the p-type semiconductor layer 49 that is raised from the surface of the mask 47 is scraped off by, for example, CMP (FIG. 53). As a polishing method, it was effective to use CMP and use a slurry having a sufficiently large etching selection ratio between silicon and the oxide film so that the oxide film serves as a stopper. For example, a high-purity colloidal silica slurry Planerlite-6103 manufactured by Fujimi Incorporated was used, and the polishing conditions were the top ring pressure = 300 to 600 hPa and the table rotation speed 50 to 100 r / min. Under this condition, the silicon / oxide selective ratio was about 100 times. Note that thermal oxidation may be performed before performing CMP or the like. Next, thermal oxidation is performed to form an oxide film having a uniform thickness of, for example, about 800 nm over the entire surface of the oxide film used as the p-type semiconductor layer 49 and the mask 47. By removing this oxide film, a flat surface without a step is obtained.

このようにして、ｎ型半導体基板層１上にｎ型ドリフト領域３、ｎ型ピラー領域１１およびｐ型仕切り領域８を有するエピタキシャル基板５０ができあがる（図５５）。このエピタキシャル基板５０を用い、実施の形態１と同様にして、ゲート酸化膜、ゲート電極、フィールドプレート１３，１４、ｐベース／ボディ領域５、ソース領域、ｎ型チャネルストッパ領域１０、層間絶縁膜１５、ソース電極６およびチャネルストッパ電極１６を形成し（図１０〜図１２参照）、さらにパッシベーション膜１７およびドレイン電極７を形成する。   Thus, the epitaxial substrate 50 having the n-type drift region 3, the n-type pillar region 11, and the p-type partition region 8 on the n-type semiconductor substrate layer 1 is completed (FIG. 55). Using this epitaxial substrate 50, the gate oxide film, the gate electrode, the field plates 13, 14, the p base / body region 5, the source region, the n-type channel stopper region 10, and the interlayer insulating film 15 in the same manner as in the first embodiment. The source electrode 6 and the channel stopper electrode 16 are formed (see FIGS. 10 to 12), and the passivation film 17 and the drain electrode 7 are further formed.

このようにして、図５０に示すようなＭＯＳＦＥＴの活性部２００と、多段フィールドプレート構造およびチャネルストッパ構造を有する終端構造部３００が完成する。最後に、ダイサーによって、同一ウェハ内で隣り合うチャネルストッパ電極１６の間の、半導体装置１５０が形成されていない領域で個々のチップに切り分けることによって、個々のＭＯＳＦＥＴが完成する。   In this manner, the MOSFET active portion 200 as shown in FIG. 50 and the termination structure portion 300 having a multi-stage field plate structure and a channel stopper structure are completed. Finally, individual MOSFETs are completed by dicing into individual chips in a region where the semiconductor device 150 is not formed between adjacent channel stopper electrodes 16 in the same wafer.

実施の形態６によれば、実施の形態３と同様の効果が得られる。なお、ｐ型仕切り領域８は、ｎ型半導体基板層１に達していてもよいし、達していなくてもよい。さらには、ｐ型仕切り領域８とｎ型ドリフト領域３との境界面が、ｐ型仕切り領域８、ｎ型ドリフト領域３およびｐベース／ボディ領域５などの半導体層の主面に対して９０°またはほぼ９０°の角度をなしていてもよい。   According to the sixth embodiment, the same effect as in the third embodiment can be obtained. Note that the p-type partition region 8 may or may not reach the n-type semiconductor substrate layer 1. Furthermore, the boundary surface between p-type partition region 8 and n-type drift region 3 is 90 ° with respect to the main surface of the semiconductor layer such as p-type partition region 8, n-type drift region 3 and p base / body region 5. Alternatively, the angle may be approximately 90 °.

（実施の形態３〜６を適用したダイオードと従来例との比較）
実施の形態３〜６において活性部２００にＭＯＳＦＥＴの代わりにダイオードを形成したものと、図４１に示す従来例Ｂを適用したダイオードとを比較した結果について説明する。耐圧を調べた結果を図５６に示す。図５６より、実施の形態３〜６を適用したダイオードの耐圧は、いずれも従来例Ｂを適用したダイオードよりも高い耐圧を示すことがわかる。 (Comparison between the diode to which the third to sixth embodiments are applied and the conventional example)
A description will be given of a result of comparison between the third to sixth embodiments in which a diode is formed in the active portion 200 instead of the MOSFET and a diode to which the conventional example B shown in FIG. 41 is applied. The results of examining the breakdown voltage are shown in FIG. FIG. 56 shows that the breakdown voltage of the diode to which the third to sixth embodiments are applied is higher than that of the diode to which the conventional example B is applied.

また、アバランシェ降伏時のキャリア発生状況をシミュレートした結果を図５７に示す。図５７においては、上から順に従来例Ｂ、実施の形態３、実施の形態４、実施の形態５および実施の形態６をそれぞれ適用したダイオードの結果である。図５７より、従来例Ｂを適用したダイオードでは、終端構造部３００の下の半導体領域２００８（フィールドプレート端部）において多くのキャリアが発生していることがわかる。このことから、終端構造部３００でアバランシェ降伏しているといえる。   FIG. 57 shows the result of simulating the carrier generation state at the time of avalanche breakdown. FIG. 57 shows the results of the diodes to which Conventional Example B, Embodiment 3, Embodiment 4, Embodiment 5, and Embodiment 6 are applied in order from the top. From FIG. 57, it can be seen that in the diode to which the conventional example B is applied, many carriers are generated in the semiconductor region 2008 (end of the field plate) under the termination structure 300. From this, it can be said that the avalanche breakdown occurs in the termination structure 300.

それに対して、実施の形態３〜６を適用したダイオードでは、いずれもｐベース／ボディ領域５の下の活性部２００において多くのキャリアが発生していることがわかる。このことから、活性部２００でアバランシェ降伏しているといえる。従って、実施の形態３〜６によれば、活性部２００のｐｎ主接合の設計耐圧を確保した半導体装置が得られることがわかる。   On the other hand, in the diodes to which the third to sixth embodiments are applied, it can be seen that many carriers are generated in the active part 200 under the p base / body region 5. From this, it can be said that the avalanche yields in the active part 200. Therefore, according to the third to sixth embodiments, it is understood that a semiconductor device in which the design breakdown voltage of the pn main junction of the active part 200 is ensured can be obtained.

実施の形態７．
実施の形態７は、実施の形態３のエピタキシャル基板３９を別の方法で製造するものである。図５８〜図６０は、実施の形態７による製造段階のエピタキシャル基板３９の要部断面図である。まず、実施の形態３と同様にして、ｎ型Ｓｉ半導体基板２８の上に例えば５０μｍの厚さのｎ型半導体層３４をエピタキシャル成長させる（図２９参照）。 Embodiment 7 FIG.
In the seventh embodiment, the epitaxial substrate 39 of the third embodiment is manufactured by another method. 58 to 60 are cross-sectional views of main parts of epitaxial substrate 39 in the manufacturing stage according to the seventh embodiment. First, in the same manner as in the third embodiment, an n-type semiconductor layer 34 having a thickness of, for example, 50 μm is epitaxially grown on the n-type Si semiconductor substrate 28 (see FIG. 29).

次いで、実施の形態３と同様にして、終端構造部３００の形成領域において、幅が例えば１５０μｍとなる領域に、例えば２μｍの幅のトレンチ５１を例えば１μｍのトレンチ間距離で５０本形成する。この場合、トレンチのピッチは３μｍとなる。トレンチ５１の深さは、例えば５０μｍである（図５８）。このように幅の狭いトレンチ５１を複数形成することによって、幅の広いトレンチを形成する場合に生じやすいトレンチエッチング時の反応生成物の発生量を抑えることができる。   Next, in the same manner as in the third embodiment, 50 trenches 51 having a width of 2 μm, for example, are formed in a region having a width of 150 μm, for example, at a distance of 1 μm between the trenches. In this case, the pitch of the trench is 3 μm. The depth of the trench 51 is, for example, 50 μm (FIG. 58). By forming a plurality of narrow trenches 51 in this way, it is possible to suppress the amount of reaction products generated during trench etching that is likely to occur when a wide trench is formed.

従って、ブラックシリコンと呼ばれる柱状の突起物の生成を抑えることができるので、コストが安く、かつエッチング欠陥が生じないトレンチエッチングプロセスを実現できる。一般に、ブラックシリコンが発生すると、デバイスの特性が劣化する。ブラックシリコンの発生を防ぐためには、トレンチエッチング装置のチャンバー内を頻繁にクリーニングする必要があり、コストの増大を招く。   Therefore, since the generation of columnar protrusions called black silicon can be suppressed, it is possible to realize a trench etching process that is low in cost and free from etching defects. In general, when black silicon is generated, device characteristics deteriorate. In order to prevent the generation of black silicon, it is necessary to frequently clean the inside of the chamber of the trench etching apparatus, resulting in an increase in cost.

トレンチ５１の形成後、熱酸化を行う。上述したように、トレンチ間に残るｎ型半導体層３４よりなるシリコン柱の幅が１μｍであるので、厚さ１μｍの熱酸化を行うことによって、シリコン柱は完全に酸化シリコンとなる。それによって、トレンチ５１が酸化シリコンで埋まり、終端構造部３００の形成領域に例えば幅が１５０μｍで、深さが５０μｍの酸化物領域５２ができる（図５９）。   After the trench 51 is formed, thermal oxidation is performed. As described above, since the width of the silicon pillar made of the n-type semiconductor layer 34 remaining between the trenches is 1 μm, the silicon pillar becomes completely silicon oxide by performing thermal oxidation with a thickness of 1 μm. Thereby, the trench 51 is filled with silicon oxide, and an oxide region 52 having a width of, for example, 150 μm and a depth of 50 μm is formed in the formation region of the termination structure 300 (FIG. 59).

次いで、酸化物領域５２を除く領域の上にレジスト膜などを被せてその下の酸化膜を保護し、その状態でＨＦによるウェットエッチングを行い、酸化物領域５２を除去する。このようにして、終端構造部３００の形成領域に、図３０のトレンチ３５と同様の凹部５３ができる（図６０）。これ以降は、図３１〜図３４のプロセスに従うことによって、図３４に示すエピタキシャル基板３９が得られる。   Next, a region other than the oxide region 52 is covered with a resist film or the like to protect the underlying oxide film, and in this state, wet etching with HF is performed to remove the oxide region 52. In this manner, a recess 53 similar to the trench 35 in FIG. 30 is formed in the formation region of the termination structure 300 (FIG. 60). Thereafter, the epitaxial substrate 39 shown in FIG. 34 is obtained by following the processes of FIGS.

実施の形態８．
実施の形態８は、実施の形態３のエピタキシャル基板３９を別の方法で製造するものである。図６１〜図６４は、実施の形態８による製造段階のエピタキシャル基板３９の要部断面図である。まず、実施の形態３と同様にして、ｎ型Ｓｉ半導体基板２８の上に例えば５０μｍの厚さのｎ型半導体層３４をエピタキシャル成長させる（図２９参照）。ｎ型半導体層３４の平均不純物濃度は、例えば２．５×１０14ｃｍ-3程度である。 Embodiment 8 FIG.
In the eighth embodiment, the epitaxial substrate 39 of the third embodiment is manufactured by another method. 61 to 64 are cross-sectional views of main parts of epitaxial substrate 39 in the manufacturing stage according to the eighth embodiment. First, in the same manner as in the third embodiment, an n-type semiconductor layer 34 having a thickness of, for example, 50 μm is epitaxially grown on the n-type Si semiconductor substrate 28 (see FIG. 29). The average impurity concentration of the n-type semiconductor layer 34 is, for example, about 2.5 × 10 14 cm −3 .

次いで、実施の形態３と同様にして、終端構造部３００の形成領域において、幅が例えば１５０μｍとなる領域に、例えば５μｍの幅のトレンチ５４を例えば５μｍのトレンチ間距離で１５本形成する。この場合、トレンチ５４のピッチは１０μｍとなる。トレンチ５４の深さは、例えば５０μｍである（図６１）。次いで、実施の形態３と同様にして、トレンチ５４内にｐ型不純物として例えば３．５×１０14ｃｍ-3程度のボロンを含むｐ型半導体層５５をエピタキシャル成長させる（図６２）。 Next, in the same manner as in the third embodiment, 15 trenches 54 having a width of, for example, 5 μm are formed in a region having a width of, for example, 150 μm in the formation region of the termination structure portion 300 with a distance between trenches of, for example, 5 μm. In this case, the pitch of the trenches 54 is 10 μm. The depth of the trench 54 is, for example, 50 μm (FIG. 61). Next, in the same manner as in the third embodiment, a p-type semiconductor layer 55 containing, for example, about 3.5 × 10 14 cm −3 of boron as a p-type impurity is epitaxially grown in the trench 54 (FIG. 62).

次いで、実施の形態３と同様にして、トレンチエッチングの際にマスク３６とした酸化膜をストッパとして、ｐ型半導体層５５の、マスク３６の表面よりも盛り上がった部分を、例えばＣＭＰにより削り取る（図６３）。なお、ＣＭＰ等を行う前に熱酸化を行ってもよい。次いで、例えば１１５０°で３時間の熱処理を行って、ｐ型半導体層５５に含まれるｐ型不純物（ここでは、ボロン）を拡散させる。   Next, in the same manner as in the third embodiment, the portion of the p-type semiconductor layer 55 that is raised from the surface of the mask 36 is scraped off by CMP, for example, using the oxide film used as the mask 36 at the time of trench etching as a stopper (FIG. 63). Note that thermal oxidation may be performed before performing CMP or the like. Next, for example, heat treatment is performed at 1150 ° C. for 3 hours to diffuse p-type impurities (here, boron) contained in the p-type semiconductor layer 55.

この拡散条件で熱処理を行うことにより、ｐ型不純物の拡散距離が約３μｍになり、ｐ型半導体層５５に含まれていたｐ型不純物が、トレンチ間に残っていたｎ型半導体層３４よりなるシリコン柱の中に拡散する。そして、終端構造部３００の形成領域に例えば幅が１５０μｍで、深さが５０μｍのｐ型仕切り領域８が形成される。ｐ型仕切り領域８の平均不純物濃度は、例えば１．０×１０14ｃｍ-3程度になる。 By performing the heat treatment under this diffusion condition, the diffusion distance of the p-type impurity becomes about 3 μm, and the p-type impurity contained in the p-type semiconductor layer 55 is made of the n-type semiconductor layer 34 remaining between the trenches. It diffuses into the silicon pillar. Then, a p-type partition region 8 having a width of, for example, 150 μm and a depth of 50 μm is formed in the region where the termination structure portion 300 is formed. The average impurity concentration of the p-type partition region 8 is, for example, about 1.0 × 10 14 cm −3 .

この熱処理によって、トレンチ５４内に埋め込まれたｐ型半導体層５５の表面に例えば約０．４μｍの厚さの酸化膜５６が成長する（図６４）。次いで、ＨＦによるウェットエッチングを行い、トレンチエッチングの際にマスク３６とした酸化膜と拡散熱処理によって生じた酸化膜５６を除去する。このようにして、図３４に示すエピタキシャル基板３９が得られる。   By this heat treatment, an oxide film 56 having a thickness of, for example, about 0.4 μm is grown on the surface of the p-type semiconductor layer 55 buried in the trench 54 (FIG. 64). Next, wet etching with HF is performed to remove the oxide film used as the mask 36 during the trench etching and the oxide film 56 generated by the diffusion heat treatment. In this way, an epitaxial substrate 39 shown in FIG. 34 is obtained.

なお、ｎ型半導体層３４とｐ型半導体層５５の不純物濃度は、上記値に限らない。上述した製造プロセスによって作製されたエピタキシャル基板３９を用いてＭＯＳＦＥＴデバイスを作製したときに、その最終段階において、終端構造部３００の下のｐ型仕切り領域８の不純物濃度が１．０×１０14ｃｍ-3程度になればよい。 Note that the impurity concentrations of the n-type semiconductor layer 34 and the p-type semiconductor layer 55 are not limited to the above values. When a MOSFET device is manufactured using the epitaxial substrate 39 manufactured by the manufacturing process described above, the impurity concentration of the p-type partition region 8 under the termination structure 300 is 1.0 × 10 14 cm at the final stage. It should be about -3 .

また、上述した製造プロセスでは、図６４の工程でｐ型不純物の拡散を行うとしたが、この工程を省略し、上述した製造プロセスによって作製されたエピタキシャル基板３９を用いてＭＯＳＦＥＴデバイスを作製する際の熱処理工程でｐ型半導体層５５中のｐ型不純物の拡散を行うようにしてもよい。つまり、エピタキシャル基板３９を作製する段階からＭＯＳＦＥＴデバイスが完成する段階までの全過程を通したサーマルバジェットを合わせて、最終的に所望のｐ型仕切り領域８が形成されていればよい。   In the manufacturing process described above, the p-type impurity is diffused in the step of FIG. 64. However, when this step is omitted and a MOSFET device is manufactured using the epitaxial substrate 39 manufactured by the manufacturing process described above. The p-type impurity in the p-type semiconductor layer 55 may be diffused in the heat treatment step. That is, the desired p-type partition region 8 may be finally formed by combining the thermal budget through the entire process from the stage of manufacturing the epitaxial substrate 39 to the stage of completing the MOSFET device.

図６１の工程で形成されるトレンチ５４の平面形状について説明する。図６５に示すパターンは、終端構造部３００の角部において、隣り合うトレンチ５４を平行なまま円弧状に９０°湾曲させたものである。ただし、このパターンでは、実施の形態３において説明したように、トレンチ側面の面方位が、エピタキシャル成長レートの低い面方位になり、トレンチ５４内をｐ型半導体層５５で完全に埋めるまでに時間がかかってしまうことがある。これを回避するには、図６６または図６７に示すパターンにするのがよい。なお、上述した製造プロセスの説明においてトレンチ５４を例えば１５本形成するとしたが、図６５〜図６７では、図が繁雑になるのを避けるため、１５本全部を示さずに、一部を省略している。   The planar shape of the trench 54 formed in the step of FIG. 61 will be described. In the pattern shown in FIG. 65, the adjacent trenches 54 are curved in a circular arc shape by 90 ° at the corners of the termination structure 300. However, in this pattern, as described in the third embodiment, the plane orientation of the trench side face becomes a plane orientation with a low epitaxial growth rate, and it takes time until the trench 54 is completely filled with the p-type semiconductor layer 55. May end up. In order to avoid this, the pattern shown in FIG. 66 or 67 is preferable. In the above description of the manufacturing process, for example, 15 trenches 54 are formed. However, in FIG. 65 to FIG. 67, some of the 15 trenches 54 are not shown in order to avoid complicated illustrations. ing.

図６６に示すパターンは、すべてのトレンチ５４の長手方向を同一の方向とし、終端構造部３００の角部において、隣り合うトレンチ５４の終端の位置を少しずつずらすことによって、複数のトレンチ５４を束ねたトレンチ全体の形成領域を円弧状に９０°湾曲させたものである。図６７に示すパターンは、すべてのトレンチ５４の長手方向を、半導体装置の切断面９（同図に一点鎖線で示す）に対して９０°の角度をなす方向とし、終端構造部３００の角部のトレンチ５４については、その長手方向を隣り合う切断面９のいずれか一方の切断面９に対して９０°の角度をなす方向としたものである。   In the pattern shown in FIG. 66, the longitudinal directions of all the trenches 54 are made the same direction, and the end positions of the adjacent trenches 54 are slightly shifted at the corners of the termination structure portion 300 to bundle a plurality of trenches 54. A region where the entire trench is formed is curved in an arc shape by 90 °. In the pattern shown in FIG. 67, the longitudinal direction of all the trenches 54 is a direction that forms an angle of 90 ° with respect to the cut surface 9 of the semiconductor device (indicated by the alternate long and short dash line in FIG. 67). For the trench 54, the longitudinal direction is set to a direction that forms an angle of 90 ° with respect to any one of the adjacent cut surfaces 9.

図６６または図６７に示すパターンであれば、すべてのトレンチ側壁がエピタキシャル成長レートの高い面方位になるので、短時間ですべてのトレンチ５４をｐ型半導体層５５で埋めることができる。また、図６７に示すパターンでは、高温熱処理を行うことが困難である場合に、終端構造部３００の下にｎ型ドリフト領域となるｎ型半導体層３４が残ってしまっても、電界集中が起こり難い理想的な終端構造が得られる。   With the pattern shown in FIG. 66 or 67, all trench sidewalls have a plane orientation with a high epitaxial growth rate, so that all trenches 54 can be filled with the p-type semiconductor layer 55 in a short time. In the pattern shown in FIG. 67, when it is difficult to perform high-temperature heat treatment, electric field concentration occurs even if the n-type semiconductor layer 34 serving as the n-type drift region remains under the termination structure 300. Difficult ideal termination structure is obtained.

なお、図６１の工程で、例えば７μｍの幅のトレンチ５４を例えば５μｍのトレンチ間距離で形成し、トレンチ間に残るｎ型半導体層３４の平均不純物濃度と、図６２の工程でトレンチ５４を埋めるｐ型半導体層５５の平均不純物濃度を同じになるようにしてもよい。このようにしても、上述した製造プロセスの場合と同様に、電界集中が起こり難い理想的な終端構造を作製することができる。   61, for example, a trench 54 having a width of 7 μm is formed with a distance between trenches of 5 μm, for example, and the average impurity concentration of the n-type semiconductor layer 34 remaining between the trenches and the trench 54 are filled in the step of FIG. The average impurity concentration of the p-type semiconductor layer 55 may be the same. Even in this case, as in the case of the manufacturing process described above, an ideal termination structure in which electric field concentration hardly occurs can be manufactured.

実施の形態９．
実施の形態９は、実施の形態３のエピタキシャル基板３９を別の方法で製造するものである。図６８〜図７３は、実施の形態９による製造段階のエピタキシャル基板３９の要部断面図である。まず、不純物として例えば２．０×１０18ｃｍ-3程度のアンチモンを含むｎ型Ｓｉ半導体基板２８の上に、不純物として例えば１．０×１０14ｃｍ-3程度のボロンを含むｐ型半導体層５７を例えば５０μｍ程度の厚さにエピタキシャル成長させる（図６８）。 Embodiment 9 FIG.
In the ninth embodiment, the epitaxial substrate 39 of the third embodiment is manufactured by another method. 68 to 73 are cross-sectional views of main parts of epitaxial substrate 39 in the manufacturing stage according to the ninth embodiment. First, on an n-type Si semiconductor substrate 28 containing, for example, about 2.0 × 10 18 cm −3 of antimony as an impurity, a p-type semiconductor layer containing, for example, about 1.0 × 10 14 cm −3 of boron as an impurity. 57 is epitaxially grown to a thickness of about 50 μm, for example (FIG. 68).

次いで、実施の形態３と同様にして、ｐ型半導体層５７の、活性部２００となる領域と、チップの切断面９となる箇所に接する部分にトレンチ５８，５９を形成する（図６９）。活性部２００となる領域のトレンチ５８については、その幅および奥行きが例えば３ｍｍであり、深さが例えば５０μｍ程度である。チップの切断面９となる箇所に接する部分のトレンチ５９については、その幅が例えば２０μｍ以上であり、深さは例えば５０μｍ程度である。   Next, in the same manner as in the third embodiment, trenches 58 and 59 are formed in a portion of the p-type semiconductor layer 57 that is in contact with the region that becomes the active portion 200 and the portion that becomes the cut surface 9 of the chip (FIG. 69). About the trench 58 of the area | region used as the active part 200, the width and depth are 3 mm, for example, and the depth is about 50 micrometers, for example. The width of the trench 59 that is in contact with the portion that becomes the cut surface 9 of the chip is, for example, 20 μm or more and the depth is, for example, about 50 μm.

トレンチエッチングを行う際には、例えば酸化膜をマスク６０として用いる。なお、トレンチ５８，５９がｎ型Ｓｉ半導体基板２８とｐ型半導体層５７の界面よりも例えば１０μｍ程度まで浅くてもよいし、あるいは深くてもよい。   When performing trench etching, for example, an oxide film is used as the mask 60. The trenches 58 and 59 may be shallower or deeper than the interface between the n-type Si semiconductor substrate 28 and the p-type semiconductor layer 57, for example, by about 10 μm.

次いで、実施の形態３と同様にして、トレンチ５８，５９内にｎ型不純物として例えば２．５×１０14ｃｍ-3程度のリンまたは砒素を含むｎ型半導体層６１をエピタキシャル成長させる（図７０）。次いで、実施の形態３と同様にして、トレンチエッチングの際にマスク６０とした酸化膜をストッパとして、ｎ型半導体層６１の、マスク６０の表面よりも盛り上がった部分を、例えばＣＭＰにより削り取る（図７１）。なお、ＣＭＰ等を行う前に熱酸化を行ってもよい。 Next, in the same manner as in the third embodiment, an n-type semiconductor layer 61 containing, for example, about 2.5 × 10 14 cm −3 of phosphorus or arsenic as an n-type impurity is epitaxially grown in the trenches 58 and 59 (FIG. 70). . Next, in the same manner as in the third embodiment, the portion of the n-type semiconductor layer 61 that is raised from the surface of the mask 60 is scraped off by CMP, for example, using the oxide film that has been used as the mask 60 at the time of trench etching as a stopper (FIG. 71). Note that thermal oxidation may be performed before performing CMP or the like.

次いで、実施の形態３と同様にして、熱酸化を行い、ｎ型半導体層６１およびマスク６０とした酸化膜の全面にわたって均一な厚さの酸化膜６２を形成する（図７２）。そして、実施の形態３と同様にして、この酸化膜６２を除去することによって、段差のない平坦な表面が得られる。このようにして、ｎ型半導体基板層１上にｎ型ドリフト領域３、ｎ型ピラー領域１１およびｐ型仕切り領域８を有するエピタキシャル基板３９ができあがる（図７３、図３４）。   Next, in the same manner as in the third embodiment, thermal oxidation is performed to form an oxide film 62 having a uniform thickness over the entire surface of the oxide film used as the n-type semiconductor layer 61 and the mask 60 (FIG. 72). Then, in the same manner as in the third embodiment, by removing the oxide film 62, a flat surface without a step can be obtained. Thus, the epitaxial substrate 39 having the n-type drift region 3, the n-type pillar region 11, and the p-type partition region 8 is formed on the n-type semiconductor substrate layer 1 (FIGS. 73 and 34).

図７４は、終端構造部下の半導体（ｐ型仕切り領域およびｎ型ピラー領域）の平面形状を示す平面図である。図７４に示すように、終端構造部３００の下のｐ型仕切り領域８は、活性部２００の回りを囲むように配置される。このｐ型仕切り領域８の角になる部分が直線部分と同じ例えば１５０μｍの幅であると、電界集中が起こりにくい理想的な終端構造が得られる。なお、ｎ型ピラー領域１１の幅が２０μｍ以上であれば、空乏層を止めるストッパとして有効であるが、ｎ型ピラー領域１１の幅をさらに広くしてチップの切断面９、すなわちスクライブラインまで達するようにしてもよい。   FIG. 74 is a plan view showing a planar shape of the semiconductor (p-type partition region and n-type pillar region) under the termination structure portion. As shown in FIG. 74, the p-type partition region 8 under the termination structure portion 300 is arranged so as to surround the active portion 200. When the corner portion of the p-type partition region 8 has the same width as that of the straight line portion, for example, 150 μm, an ideal termination structure in which electric field concentration hardly occurs can be obtained. If the width of the n-type pillar region 11 is 20 μm or more, it is effective as a stopper for stopping the depletion layer, but the width of the n-type pillar region 11 is further increased to reach the cut surface 9 of the chip, that is, the scribe line. You may do it.

また、実施の形態７において、実施の形態９と同様に、ｎ型Ｓｉ半導体基板上にｐ型半導体層をエピタキシャル成長させ、そのｐ型のエピタキシャル成長層に幅の狭いトレンチを複数形成し、熱酸化によって酸化物領域を形成し、その酸化物領域を除去してできた凹部にｎ型半導体をエピタキシャル成長させることによって、ｎ型ドリフト領域とｎ型ピラー領域を形成するようにしてもよい。さらに、実施の形態８において、実施の形態９と同様に、ｎ型Ｓｉ半導体基板上にｐ型半導体層をエピタキシャル成長させ、そのｐ型のエピタキシャル成長層に幅の狭いトレンチを複数形成し、エピタキシャル成長を行ってトレンチをｎ型半導体で埋め、ｎ型不純物を熱拡散させることによって、ｎ型ドリフト領域とｎ型ピラー領域を形成するようにしてもよい。   In the seventh embodiment, similarly to the ninth embodiment, a p-type semiconductor layer is epitaxially grown on an n-type Si semiconductor substrate, a plurality of narrow trenches are formed in the p-type epitaxial growth layer, and thermal oxidation is performed. An n-type drift region and an n-type pillar region may be formed by forming an oxide region and epitaxially growing an n-type semiconductor in a recess formed by removing the oxide region. Further, in the eighth embodiment, similarly to the ninth embodiment, a p-type semiconductor layer is epitaxially grown on an n-type Si semiconductor substrate, a plurality of narrow trenches are formed in the p-type epitaxial growth layer, and epitaxial growth is performed. Alternatively, the n-type drift region and the n-type pillar region may be formed by filling the trench with an n-type semiconductor and thermally diffusing the n-type impurity.

以上において本発明は、上述した各実施の形態１〜９に限らず、種々変更可能である。例えば、上述した実施の形態１〜９では、活性部２００をｎ型半導体層で構成したものと、複数のｎ型ドリフト領域とｐ型仕切り領域とからなる超接合層で構成したものについて説明したが、これらに限らず、終端構造部３００の下の仕切り領域の導電型が活性部２００のドリフト領域の導電型と異なっていれば、いかなる組み合わせにおいても同様の効果が得られる。また、終端構造を、多段フィールドプレート構造に代えて、従来からあるフィールドリミッティングリング構造や、フィールドリミッティングリング構造とフィールドプレート構造を併用したものや、リサーフ構造としても、同様の効果が得られる。   In the above, this invention is not restricted to each Embodiment 1-9 mentioned above, A various change is possible. For example, in the above-described first to ninth embodiments, the active part 200 is configured with an n-type semiconductor layer and the active part 200 is configured with a super junction layer including a plurality of n-type drift regions and p-type partition regions. However, the present invention is not limited thereto, and the same effect can be obtained in any combination as long as the conductivity type of the partition region under the termination structure 300 is different from the conductivity type of the drift region of the active part 200. In addition, the same effect can be obtained by using a conventional field limiting ring structure, a combination of a field limiting ring structure and a field plate structure, or a resurf structure instead of the multistage field plate structure. .

さらに、ＭＯＳＦＥＴに限らず、ＩＧＢＴやダイオードが形成されていてもよい。また、各実施の形態１〜９中に記載した寸法、濃度、温度、圧力、時間、回転数などは一例であり、本発明はそれらの値に限定されるものではない。また、本発明は、第１導電型をｐ型とし、第２導電型をｎ型としても同様に成り立つ。   Furthermore, not only MOSFET but IGBT and diode may be formed. Moreover, the dimension, density | concentration, temperature, pressure, time, rotation speed etc. which were described in each Embodiment 1-9 are examples, and this invention is not limited to those values. Further, the present invention is similarly established when the first conductivity type is p-type and the second conductivity type is n-type.

以上のように、本発明にかかる半導体装置およびその製造方法は、電力変換装置用の半導体装置に有用である。   As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for a semiconductor device for a power conversion device.

本発明の実施の形態１にかかる半導体装置の構成を示す要部構成図である。1 is a main part configuration diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention; 本発明の実施の形態１にかかる半導体装置の構成を示す要部構成図である。1 is a main part configuration diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention; 終端構造部下のｐ型仕切り領域へのｐベース／ボディ領域の突出量と耐圧の関係を示す特性図である。It is a characteristic view showing the relationship between the protrusion amount of the p base / body region to the p-type partition region under the termination structure and the breakdown voltage. 終端構造部下のｐ型仕切り領域の不純物濃度と耐圧の関係を示す特性図である。It is a characteristic view which shows the relationship between the impurity concentration of the p-type partition area | region under a termination | terminus structure part, and a proof pressure. アバランシェ降伏時のキャリア発生状況のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the carrier generation condition at the time of avalanche breakdown. 図１の半導体装置の製造段階における要部断面図である。FIG. 2 is a fragmentary cross-sectional view of the semiconductor device of FIG. 1 at the manufacturing stage. 図１の半導体装置の製造段階における要部断面図である。FIG. 2 is a fragmentary cross-sectional view of the semiconductor device of FIG. 1 at the manufacturing stage. 図１の半導体装置の製造段階における要部断面図である。FIG. 2 is a fragmentary cross-sectional view of the semiconductor device of FIG. 1 at the manufacturing stage. 図１の半導体装置の製造段階における要部断面図である。FIG. 2 is a fragmentary cross-sectional view of the semiconductor device of FIG. 1 at the manufacturing stage. 図１の半導体装置の製造段階における要部断面図である。FIG. 2 is a fragmentary cross-sectional view of the semiconductor device of FIG. 1 at the manufacturing stage. 図１の半導体装置の製造段階における要部断面図である。FIG. 2 is a fragmentary cross-sectional view of the semiconductor device of FIG. 1 at the manufacturing stage. 図１の半導体装置の製造段階における要部断面図である。FIG. 2 is a fragmentary cross-sectional view of the semiconductor device of FIG. 1 at the manufacturing stage. 図１の半導体装置の製造段階における要部断面図である。FIG. 2 is a fragmentary cross-sectional view of the semiconductor device of FIG. 1 at the manufacturing stage. 耐圧のシミュレーション結果を示す図である。It is a figure which shows the simulation result of a proof pressure. アバランシェ降伏時の電位分布のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the electric potential distribution at the time of avalanche breakdown. アバランシェ降伏時の電界分布のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the electric field distribution at the time of avalanche breakdown. アバランシェ降伏時のインパクトイオン化率のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the impact ionization rate at the time of avalanche breakdown. アバランシェ降伏時のフィールドプレート構造における電界強度の深さ方向の分布を示す特性図である。It is a characteristic view which shows the distribution of the depth direction of the electric field strength in the field plate structure at the time of avalanche breakdown. 図１３〜図１７において比較に用いた従来例の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the prior art example used for the comparison in FIGS. 13-17. 本発明の実施の形態２にかかる半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device concerning Embodiment 2 of this invention. 本発明の実施の形態２にかかる半導体装置の構成を示す要部平面図である。It is a principal part top view which shows the structure of the semiconductor device concerning Embodiment 2 of this invention. 本発明の実施の形態２にかかる半導体装置の構成を示す要部平面図である。It is a principal part top view which shows the structure of the semiconductor device concerning Embodiment 2 of this invention. 本発明の実施の形態２にかかる半導体装置の構成を示す要部平面図である。It is a principal part top view which shows the structure of the semiconductor device concerning Embodiment 2 of this invention. 図１９の半導体装置の製造段階における要部断面図である。FIG. 20 is a fragmentary cross-sectional view of the semiconductor device of FIG. 19 at the manufacturing stage; 図１９の半導体装置の製造段階における要部断面図である。FIG. 20 is a fragmentary cross-sectional view of the semiconductor device of FIG. 19 at the manufacturing stage; 図１９の半導体装置の製造段階における要部断面図である。FIG. 20 is a fragmentary cross-sectional view of the semiconductor device of FIG. 19 at the manufacturing stage; 図１９の半導体装置の製造段階における要部断面図である。FIG. 20 is a fragmentary cross-sectional view of the semiconductor device of FIG. 19 at the manufacturing stage; 図１９の半導体装置の製造段階における要部断面図である。FIG. 20 is a fragmentary cross-sectional view of the semiconductor device of FIG. 19 at the manufacturing stage; 本発明の実施の形態３にかかる半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device concerning Embodiment 3 of this invention. 図２８の半導体装置の製造段階における要部断面図である。FIG. 29 is an essential part cross-sectional view of the semiconductor device of FIG. 28 at the manufacturing stage. 図２８の半導体装置の製造段階における要部断面図である。FIG. 29 is an essential part cross-sectional view of the semiconductor device of FIG. 28 at the manufacturing stage. 図２８の半導体装置の製造段階における要部断面図である。FIG. 29 is an essential part cross-sectional view of the semiconductor device of FIG. 28 at the manufacturing stage. 図２８の半導体装置の製造段階における要部断面図である。FIG. 29 is an essential part cross-sectional view of the semiconductor device of FIG. 28 at the manufacturing stage. 図２８の半導体装置の製造段階における要部断面図である。FIG. 29 is an essential part cross-sectional view of the semiconductor device of FIG. 28 at the manufacturing stage. 図２８の半導体装置の製造段階における要部断面図である。FIG. 29 is an essential part cross-sectional view of the semiconductor device of FIG. 28 at the manufacturing stage. 終端構造部下のｐ型仕切り領域の平面形状を示す平面図である。It is a top view which shows the planar shape of the p-type partition area | region under a termination | terminus structure part. 終端構造部の角部におけるｐ型仕切り領域の平面形状を拡大して示す平面図である。It is a top view which expands and shows the planar shape of the p-type partition area | region in the corner | angular part of a termination | terminus structure part. 耐圧のシミュレーション結果を示す図である。It is a figure which shows the simulation result of a proof pressure. アバランシェ降伏時の電位分布のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the electric potential distribution at the time of avalanche breakdown. アバランシェ降伏時の電界分布のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the electric field distribution at the time of avalanche breakdown. アバランシェ降伏時のインパクトイオン化率のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the impact ionization rate at the time of avalanche breakdown. 図３７〜図４０において比較に用いた従来例の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the prior art example used for the comparison in FIGS. 37-40. 本発明の実施の形態４にかかる半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device concerning Embodiment 4 of this invention. 図４２の半導体装置の製造段階における要部断面図である。43 is a fragmentary cross-sectional view of the semiconductor device of FIG. 42 at the manufacturing stage. FIG. 図４２の半導体装置の製造段階における要部断面図である。43 is a fragmentary cross-sectional view of the semiconductor device of FIG. 42 at the manufacturing stage. FIG. 図４２の半導体装置の製造段階における要部断面図である。43 is a fragmentary cross-sectional view of the semiconductor device of FIG. 42 at the manufacturing stage. FIG. 図４２の半導体装置の製造段階における要部断面図である。43 is a fragmentary cross-sectional view of the semiconductor device of FIG. 42 at the manufacturing stage. FIG. 図４２の半導体装置の製造段階における要部断面図である。43 is a fragmentary cross-sectional view of the semiconductor device of FIG. 42 at the manufacturing stage. FIG. 図４２の半導体装置の製造段階における要部断面図である。43 is a fragmentary cross-sectional view of the semiconductor device of FIG. 42 at the manufacturing stage. FIG. 本発明の実施の形態５にかかる半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device concerning Embodiment 5 of this invention. 本発明の実施の形態６にかかる半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device concerning Embodiment 6 of this invention. 図５０の半導体装置の製造段階における要部断面図である。FIG. 51 is a main-portion cross-sectional view of the semiconductor device of FIG. 50 in a manufacturing stage; 図５０の半導体装置の製造段階における要部断面図である。FIG. 51 is a main-portion cross-sectional view of the semiconductor device of FIG. 50 in a manufacturing stage; 図５０の半導体装置の製造段階における要部断面図である。FIG. 51 is a main-portion cross-sectional view of the semiconductor device of FIG. 50 in a manufacturing stage; 図５０の半導体装置の製造段階における要部断面図である。FIG. 51 is a main-portion cross-sectional view of the semiconductor device of FIG. 50 in a manufacturing stage; 図５０の半導体装置の製造段階における要部断面図である。FIG. 51 is a main-portion cross-sectional view of the semiconductor device of FIG. 50 in a manufacturing stage; 耐圧のシミュレーション結果を示す図である。It is a figure which shows the simulation result of a proof pressure. アバランシェ降伏時のキャリア発生状況のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the carrier generation condition at the time of avalanche breakdown. 本発明の実施の形態７にかかる半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning Embodiment 7 of this invention. 本発明の実施の形態７にかかる半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning Embodiment 7 of this invention. 本発明の実施の形態７にかかる半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning Embodiment 7 of this invention. 本発明の実施の形態８にかかる半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning Embodiment 8 of this invention. 本発明の実施の形態８にかかる半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning Embodiment 8 of this invention. 本発明の実施の形態８にかかる半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning Embodiment 8 of this invention. 本発明の実施の形態８にかかる半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning Embodiment 8 of this invention. 終端構造部の角部におけるトレンチの平面形状を拡大して示す平面図である。It is a top view which expands and shows the planar shape of the trench in the corner | angular part of a termination | terminus structure part. 終端構造部の角部におけるトレンチの平面形状を拡大して示す平面図である。It is a top view which expands and shows the planar shape of the trench in the corner | angular part of a termination | terminus structure part. 終端構造部の角部におけるトレンチの平面形状を拡大して示す平面図である。It is a top view which expands and shows the planar shape of the trench in the corner | angular part of a termination | terminus structure part. 本発明の実施の形態９にかかる半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning Embodiment 9 of this invention. 本発明の実施の形態９にかかる半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning Embodiment 9 of this invention. 本発明の実施の形態９にかかる半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning Embodiment 9 of this invention. 本発明の実施の形態９にかかる半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning Embodiment 9 of this invention. 本発明の実施の形態９にかかる半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning Embodiment 9 of this invention. 本発明の実施の形態９にかかる半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning Embodiment 9 of this invention. 終端構造部下の半導体の平面形状を示す平面図である。It is a top view which shows the planar shape of the semiconductor under a termination | terminus structure part.

符号の説明Explanation of symbols

１ 半導体基板層
２，８，２５ 第２導電型半導体領域
３，２６ 第１導電型半導体領域
５ 第２導電型ベース領域
６ 第１主電極
７ 第２主電極
９ チップの切断面
１０ 第１導電型チャネルストッパ領域
１１ 第１導電型ピラー領域
１２ 絶縁膜
１３，１４ フィールドプレート構造
１６ チャネルストッパ電極
２８ 第１導電型半導体基板
３４，６１ 第１導電型半導体
３５，５１，５４，５８，５９ トレンチ
３７，５５，５７ 第２導電型半導体
４０ 絶縁層
５２ 酸化物
５３ 凹部
１００，１１０，１２０，１３０，１４０，１５０ 半導体装置
２００ 活性部領域
３００ 終端構造部領域 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate layer 2,8,25 2nd conductivity type semiconductor region 3,26 1st conductivity type semiconductor region 5 2nd conductivity type base region 6 1st main electrode 7 2nd main electrode 9 Cutting surface of chip 10 1st conductivity Type channel stopper region 11 first conductive type pillar region 12 insulating film 13, 14 field plate structure 16 channel stopper electrode 28 first conductive type semiconductor substrate 34, 61 first conductive type semiconductor 35, 51, 54, 58, 59 trench 37 , 55, 57 Second conductivity type semiconductor 40 Insulating layer 52 Oxide 53 Recess 100, 110, 120, 130, 140, 150 Semiconductor device 200 Active region 300 Termination structure region

Claims (18)

半導体基板の厚さ方向に電流を流す縦型の半導体装置であって、
前記半導体基板の表面側に選択的に形成された第２導電型ベース領域と、該半導体基板の裏面側の第１導電型半導体基板層と、該第１導電型半導体基板層と該第２導電型ベース領域の間であって該第１導電型半導体基板層よりも低不純物濃度の第１導電型ドリフト層とからなる活性部領域と、
前記第２導電型ベース領域に電気的に接続された第１主電極と、
前記半導体基板の切断面に沿った外周四面に形成される第１導電型ピラー領域と、
前記活性部領域を囲み、かつ該活性部領域から第１導電型ピラー領域までの間すべてと該半導体基板の表面から前記第１導電型半導体基板層までの間すべてとにかけて形成される第２導電型半導体領域を有する終端構造部と、
前記半導体基板の裏面側に電気的に接続された第２主電極と、
を備えることを特徴とする半導体装置。 A vertical semiconductor device that allows current to flow in the thickness direction of a semiconductor substrate,
Wherein the second conductive type base region selectively formed on the surface side of the semiconductor substrate, the and the back side first conductivity type semiconductor substrate layer of a semiconductor substrate, said first conductivity type semiconductor substrate layer and said second conductive An active region composed of a first conductivity type drift layer having a lower impurity concentration than the first conductivity type semiconductor substrate layer between the type base regions;
A first main electrode electrically connected to the second conductivity type base region;
A first conductivity type pillar region formed on four outer peripheral surfaces along the cut surface of the semiconductor substrate;
Second conductivity formed surrounding the active portion region and extending from the active portion region to the first conductivity type pillar region and all from the surface of the semiconductor substrate to the first conductivity type semiconductor substrate layer. A termination structure having a type semiconductor region;
A second main electrode electrically connected to the back side of the semiconductor substrate;
A semiconductor device comprising: 前記第２導電型半導体領域に更に第１導電型半導体領域を付加し、該第２導電型半導体領域の平均不純物濃度から第１導電型半導体領域の平均不純物濃度を差し引いた平均不純物濃度が２．５×１０14ｃｍ-3以下の第２導電型であることを特徴とする請求項１に記載の半導体装置。 A first conductivity type semiconductor region is further added to the second conductivity type semiconductor region, and an average impurity concentration obtained by subtracting the average impurity concentration of the first conductivity type semiconductor region from the average impurity concentration of the second conductivity type semiconductor region is 2. The semiconductor device according to claim 1, wherein the semiconductor device is of a second conductivity type of 5 × 10 14 cm −3 or less. 前記第１導電型ドリフト層が、第１導電型のドリフト領域、又は交互に複数配置した第１導電型のドリフト領域と第２導電型の仕切り領域であることを特徴とする請求項１又は請求項２に記載の半導体装置。 The first conductivity type drift layer is a first conductivity type drift region, or a plurality of alternately arranged first conductivity type drift regions and second conductivity type partition regions. Item 3. The semiconductor device according to Item 2. 前記第２導電型半導体領域と前記第１導電型ドリフト層の接合界面が傾斜していることを特徴とする請求項１〜３のいずれか一つに記載の半導体装置。 The semiconductor device according to claim 1 , wherein a junction interface between the second conductivity type semiconductor region and the first conductivity type drift layer is inclined. 前記第２導電型半導体領域と、前記第１導電型半導体基板層との間に、絶縁層が付加されていることを特徴とする請求項１〜４のいずれか一つに記載の半導体装置。 5. The semiconductor device according to claim 1 , wherein an insulating layer is added between the second conductive type semiconductor region and the first conductive type semiconductor substrate layer. 6. . 前記第２導電型半導体領域が、前記第２導電型ベース領域に接していることを特徴とする請求項１〜５のいずれか一つに記載の半導体装置。   6. The semiconductor device according to claim 1, wherein the second conductivity type semiconductor region is in contact with the second conductivity type base region. 前記第２導電型半導体領域の表面の前記半導体基板の切断側に、第１導電型チャネルストッパ領域が設けられていることを特徴とする請求項１〜６のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein a first conductivity type channel stopper region is provided on a cut side of the semiconductor substrate on a surface of the second conductivity type semiconductor region. . 前記第１導電型ピラー領域と前記第１導電型チャネルストッパ領域が接することを特徴とする請求項７に記載の半導体装置。   8. The semiconductor device according to claim 7, wherein the first conductivity type pillar region and the first conductivity type channel stopper region are in contact with each other. 前記第２導電型ベース領域に接し、かつ前記第２導電型半導体領域の少なくとも一部の表面を被う絶縁膜の上に伸びるフィールドプレート構造が設けられていることを特徴とする請求項１〜８のいずれか一つに記載の半導体装置。   2. A field plate structure extending on an insulating film that is in contact with the second conductivity type base region and covers at least a part of the surface of the second conductivity type semiconductor region is provided. 9. The semiconductor device according to any one of 8. 素電荷をｑとし、シリコンの誘電率をεSiとし、半導体の臨界電界強度をＥcriticalとし、前記第２導電型半導体領域の厚さおよび濃度をそれぞれｔおよびＮ2とすると、
［Ｎ2＜εSi×Ｅcritical／（ｑ×ｔ）］
であることを特徴とする請求項１に記載の半導体装置。 If the elementary charge is q, the dielectric constant of silicon is ε Si , the critical electric field strength of the semiconductor is E critical, and the thickness and concentration of the second conductivity type semiconductor region are t and N 2 , respectively,
[N 2 <ε Si × E critical / (q × t)]
The semiconductor device according to claim 1, wherein: ［Ｎ2＜０．８×εSi×Ｅcritical／（ｑ×ｔ）］
であることを特徴とする請求項１０に記載の半導体装置。 [N 2 <0.8 × ε Si × E critical / (q × t)]
The semiconductor device according to claim 10, wherein: 前記第２導電型ベース領域の、前記第２導電型半導体領域への突出量をＷprojectionとし、前記第２導電型半導体領域の厚さをｔとすると、
Ｗprojection＞０．２×ｔ
であることを特徴とする請求項６に記載の半導体装置。 When the projection amount of the second conductivity type base region to the second conductivity type semiconductor region is W projection and the thickness of the second conductivity type semiconductor region is t,
W projection > 0.2 × t
The semiconductor device according to claim 6, wherein: Ｗprojection＞０．４×ｔ
であることを特徴とする請求項１２に記載の半導体装置。 W projection > 0.4 × t
The semiconductor device according to claim 12, wherein: 前記縦型の半導体装置が、ダイオード、ＭＯＳＦＥＴ及びＩＧＢＴのいずれかであることを特徴とする請求項１〜１３のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein the vertical semiconductor device is any one of a diode, a MOSFET, and an IGBT. 請求項１に記載の半導体装置の製造方法であって、前記半導体基板に複数のトレンチをエッチングで形成した後、前記トレンチ間に残った半導体基板領域を熱酸化し、前記熱酸化により生じた酸化膜を除去し、この酸化膜を除去した部分を少なくとも第２導電型のエピタキシャル層で満たし前記第２導電型半導体領域を形成することを特徴とする半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein a plurality of trenches are formed in the semiconductor substrate by etching, a semiconductor substrate region remaining between the trenches is thermally oxidized, and the oxidation generated by the thermal oxidation A method of manufacturing a semiconductor device, comprising: removing a film, filling a portion where the oxide film is removed with at least a second conductivity type epitaxial layer, and forming the second conductivity type semiconductor region. 請求項１に記載の半導体装置の製造方法であって、前記半導体基板に複数のトレンチをエッチングで形成した後、前記トレンチを第２導電型のエピタキシャル層で満たし、更にトレンチ間に第２導電型の不純物拡散を行い前記第２導電型半導体領域を形成することを特徴とする半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1 , wherein after forming a plurality of trenches in the semiconductor substrate by etching, the trenches are filled with an epitaxial layer of a second conductivity type, and the second conductivity type is further formed between the trenches. A method of manufacturing a semiconductor device, wherein the second conductivity type semiconductor region is formed by performing impurity diffusion. 請求項１に記載の半導体装置の製造方法であって、前記半導体基板に湿式異方性エッチングでトレンチを形成し、前記トレンチを第２導電型のエピタキシャル層で満たし、前記第２導電型半導体領域を形成することを特徴とする半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein a trench is formed in the semiconductor substrate by wet anisotropic etching, the trench is filled with a second conductivity type epitaxial layer, and the second conductivity type semiconductor region is formed. Forming a semiconductor device. 前記エピタキシャル層で満たした後、熱酸化と熱酸化後の前記半導体基板表面の研磨を行うことを特徴とする請求項１５〜１７のいずれか一つに記載の半導体装置の製造方法。 The semiconductor device manufacturing method according to claim 15, wherein after the filling with the epitaxial layer, thermal oxidation and polishing of the semiconductor substrate surface after thermal oxidation are performed.
JP2006166177A 2006-06-15 2006-06-15 Semiconductor device and manufacturing method thereof Expired - Fee Related JP5124999B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2006166177A JP5124999B2 (en) 2006-06-15 2006-06-15 Semiconductor device and manufacturing method thereof
US11/763,625 US8080846B2 (en) 2006-06-15 2007-06-15 Semiconductor device having improved breakdown voltage and method of manufacturing the same
DE102007027519.8A DE102007027519B4 (en) 2006-06-15 2007-06-15 Semiconductor device and method of making the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006166177A JP5124999B2 (en) 2006-06-15 2006-06-15 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2007335658A JP2007335658A (en) 2007-12-27
JP5124999B2 true JP5124999B2 (en) 2013-01-23

Family

ID=38690468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006166177A Expired - Fee Related JP5124999B2 (en) 2006-06-15 2006-06-15 Semiconductor device and manufacturing method thereof

Country Status (3)

Country Link
US (1) US8080846B2 (en)
JP (1) JP5124999B2 (en)
DE (1) DE102007027519B4 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5298488B2 (en) 2007-09-28 2013-09-25 富士電機株式会社 Semiconductor device
US8239176B2 (en) * 2008-02-13 2012-08-07 Feng Ma Simulation methods and systems for carriers having multiplications
JP5455461B2 (en) * 2009-06-17 2014-03-26 キヤノン株式会社 Silicon substrate processing method and liquid discharge head substrate manufacturing method
CN102473721B (en) 2009-07-31 2015-05-06 富士电机株式会社 Semiconductor apparatus
US9230810B2 (en) 2009-09-03 2016-01-05 Vishay-Siliconix System and method for substrate wafer back side and edge cross section seals
JP5543758B2 (en) 2009-11-19 2014-07-09 ルネサスエレクトロニクス株式会社 Semiconductor device
TWI407568B (en) 2010-11-22 2013-09-01 Sinopower Semiconductor Inc Semiconductor device
JP5719167B2 (en) 2010-12-28 2015-05-13 ルネサスエレクトロニクス株式会社 Semiconductor device
US8829640B2 (en) * 2011-03-29 2014-09-09 Alpha And Omega Semiconductor Incorporated Configuration and method to generate saddle junction electric field in edge termination
US9882044B2 (en) * 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs
JP2016162861A (en) * 2015-02-27 2016-09-05 株式会社東芝 Semiconductor device
JP7017035B2 (en) * 2017-07-27 2022-02-08 株式会社デンソー Manufacturing method of semiconductor device
DE102018115637A1 (en) * 2018-06-28 2020-01-02 Infineon Technologies Ag Power semiconductor component
US10957759B2 (en) * 2018-12-21 2021-03-23 General Electric Company Systems and methods for termination in silicon carbide charge balance power devices
CN112117330B (en) * 2020-09-21 2024-05-07 南京华瑞微集成电路有限公司 Device structure for improving withstand voltage of deep-groove super-junction MOSFET and process method thereof

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4999684A (en) 1988-05-06 1991-03-12 General Electric Company Symmetrical blocking high voltage breakdown semiconducotr device
US4904609A (en) 1988-05-06 1990-02-27 General Electric Company Method of making symmetrical blocking high voltage breakdown semiconductor device
JPH10270686A (en) 1997-03-27 1998-10-09 Matsushita Electron Corp Insulated gate bipolar transistor
JP3951522B2 (en) 1998-11-11 2007-08-01 富士電機デバイステクノロジー株式会社 Super junction semiconductor device
JP3940518B2 (en) 1999-03-10 2007-07-04 株式会社東芝 High voltage semiconductor element
JP4696337B2 (en) 1999-10-15 2011-06-08 富士電機システムズ株式会社 Semiconductor device
JP2001244461A (en) 2000-02-28 2001-09-07 Toyota Central Res & Dev Lab Inc Vertical semiconductor device
JP4764987B2 (en) 2000-09-05 2011-09-07 富士電機株式会社 Super junction semiconductor device
JP3899231B2 (en) 2000-12-18 2007-03-28 株式会社豊田中央研究所 Semiconductor device
JP3731520B2 (en) * 2001-10-03 2006-01-05 富士電機デバイステクノロジー株式会社 Semiconductor device and manufacturing method thereof
JP3973395B2 (en) 2001-10-16 2007-09-12 株式会社豊田中央研究所 Semiconductor device and manufacturing method thereof
JP4126915B2 (en) * 2002-01-30 2008-07-30 富士電機デバイステクノロジー株式会社 Semiconductor device
JP3908572B2 (en) * 2002-03-18 2007-04-25 株式会社東芝 Semiconductor element
JP2004200441A (en) 2002-12-19 2004-07-15 Toyota Central Res & Dev Lab Inc Semiconductor device and its manufacturing method
JP3721172B2 (en) 2003-04-16 2005-11-30 株式会社東芝 Semiconductor device
JP4631268B2 (en) * 2003-10-29 2011-02-16 富士電機システムズ株式会社 Semiconductor device
JP4289123B2 (en) * 2003-10-29 2009-07-01 富士電機デバイステクノロジー株式会社 Semiconductor device
JP4904673B2 (en) * 2004-02-09 2012-03-28 富士電機株式会社 Semiconductor device and manufacturing method of semiconductor device
JP4967236B2 (en) * 2004-08-04 2012-07-04 富士電機株式会社 Semiconductor element

Also Published As

Publication number Publication date
US20070290267A1 (en) 2007-12-20
US8080846B2 (en) 2011-12-20
DE102007027519B4 (en) 2016-11-24
JP2007335658A (en) 2007-12-27
DE102007027519A1 (en) 2007-12-20

Similar Documents

Publication Publication Date Title
JP5124999B2 (en) Semiconductor device and manufacturing method thereof
US9818860B2 (en) Silicon carbide semiconductor device and method for producing the same
US10263082B2 (en) Semiconductor device having a gate electrode formed inside a trench
US7714383B2 (en) Semiconductor device
JP5196980B2 (en) Semiconductor device
US8598657B2 (en) Semiconductor device
US7595241B2 (en) Method for fabricating silicon carbide vertical MOSFET devices
JP3506676B2 (en) Semiconductor device
JP5476689B2 (en) Manufacturing method of semiconductor device
JP2008182054A (en) Semiconductor device
US7989884B2 (en) Structure for making a top-side contact to a substrate
US20080261358A1 (en) Manufacture of Lateral Semiconductor Devices
JP2004047967A (en) Semiconductor device and method for manufacturing same
JP2004064063A (en) High voltage vertical type dmos transistor, and method for producing the same
CN103765594B (en) Sic semiconductor device
CN108962993B (en) Semiconductor device and method for manufacturing the same
TWI539577B (en) Integrated gate runner and field implant termination for trench devices
US8017494B2 (en) Termination trench structure for mosgated device and process for its manufacture
JP2009200300A (en) Semiconductor device, and method of manufacturing the same
JP5509543B2 (en) Manufacturing method of semiconductor device
JP2007173319A (en) Insulated-gate semiconductor device and manufacturing method thereof
JP2009141307A (en) Method of manufacturing semiconductor device
JP2018041853A (en) Semiconductor device and semiconductor device manufacturing method
JP4929594B2 (en) Semiconductor device and manufacturing method of semiconductor device
US11705506B2 (en) Lateral trench transistor device

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20080204

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20080204

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20080205

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090323

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20091112

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20091112

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20091112

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20110422

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120517

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120522

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120723

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20121002

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20121015

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5124999

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20151109

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees