JP3731520B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP3731520B2
JP3731520B2 JP2001307314A JP2001307314A JP3731520B2 JP 3731520 B2 JP3731520 B2 JP 3731520B2 JP 2001307314 A JP2001307314 A JP 2001307314A JP 2001307314 A JP2001307314 A JP 2001307314A JP 3731520 B2 JP3731520 B2 JP 3731520B2
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JP2003115589A (en
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高広 佐藤
勝典 上野
進 岩本
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

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  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、ＭＯＳＦＥＴ（絶縁ゲート型電界効果トランジスタ）、ＩＧＢＴ（伝導度変調型ＭＯＳＦＥＴ）、バイポーラトンラジスタ等の能動素子やダイオード等の受動素子に適用可能で高耐圧化と大電流容量化が両立する縦形パワー半導体装置及びその製造方法に関する。
【０００２】
基板の両面に電極部を備えてその基板の厚さ方向に電流を流す縦形ドリフト部を持つ縦形半導体装置においては、オン抵抗（電流容量）と耐圧との間にはトレードオフ関係が存在することから、縦形ドリフト部として、不純物濃度を高めたｎ型の縦形領域とｐ型の縦形領域とを基板の横方向へ交互に繰り返した並列ｐｎ構造を採用することが知られている。しかし、この並列ｐｎ構造の縦形ドリフト部では速く空乏化するものの、ドリフト部の周りの耐圧構造部では空乏層が外方向や基板深部へは拡がり難く、電界強度がシリコンの臨界電界強度に速く達し、耐圧構造部で耐圧が低下してしまうので、耐圧構造部にも並列ｐｎ構造を採用することが知られている。
【０００３】
図９は縦形ＭＯＳＦＥＴにおけるドリフト部及び素子外周部（耐圧構造部）を示す平面図、図１０は図９中のＡ−Ａ′線に沿って切断した状態を示す縦断面図、図１１は図９中のＢ−Ｂ′線に沿って切断した状態を示す縦断面図である。なお、図９ではドリフト部の１／４を斜線部分で示してある。
【０００４】
このｎチャネル縦形ＭＯＳＦＥＴは、裏側のドレイン電極１８が導電接触した低抵抗のｎ＋ ドレイン層（コンタクト層）１１の上に形成された第１の並列ｐｎ構造のドレイン・ドリフト部２２と、このドリフト部２２の表面層に選択的に形成された素子活性領域たる高不純物濃度のｐベース領域（ｐウェル，チャネル領域）１３ａと、そのｐベース領域１３ａ内の表面側に選択的に形成された高不純物濃度のｎ＋ ソース領域１４と、基板表面上にゲート絶縁膜１５を介して設けられたポリシリコン等のゲート電極層１６と、層間絶縁膜１９ａに開けたコンタクト孔を介してｐベース領域１３ａ及びｎ＋ ソース領域１４に跨って導電接触するソース電極１７とを有している。ウェル状のｐベース領域１３ａの中にｎ＋ ソース領域１４が浅く形成されており、２重拡散型ＭＯＳ部を構成している。なお、２６はｐ＋ コンタクト領域で、また、図示しない部分でゲート電極層１６の上に金属膜のゲート配線が導電接触している。
【０００５】
第１の並列ｐｎ構造のドレイン・ドリフト部２２は、基板の厚み方向に層状縦形のｎ型ドリフト電路領域２２ａと基板の厚み方向に層状縦形のｐ型仕切領域２２ｂとを交互に繰り返して接合した構造である。ｎ型のドリフト電路領域２２ａは、その上端がｐベース領域１３ａの挾間領域１２ｅに達し、その下端がｎ＋ ドレイン層１１に接している。また、ｐ型の仕切領域２２ｂは、その上端がｐベース領域１３ａのウェル底面に接し、その下端がｎ＋ ドレイン層１１に接している。
【０００６】
基板表面とｎ＋ ドレイン層１１との間で縦形ドリフト部２２の周りの耐圧構造部２０には、基板の厚さ方向に配向する層状縦形のｎ型領域２０ａと、基板の厚さ方向に配向する層状縦形のｐ型領域２０ｂとを交互に繰り返して接合して成る第２の並列ｐｎ構造が形成されている。耐圧構造部２０の第２の並列ｐｎ構造の表面上には、表面保護及び安定化のために、熱酸化膜又は燐シリカガラス（ＰＳＧ）から成る酸化膜（絶縁膜）２３が成膜されている。
【０００７】
耐圧構造部２０の表面側にはｐベース領域を取り囲むように多重のｐ型リング２０ｃが巡らされている。このｐ型リング２０ｃは第２の並列ｐｎ構造の多数のｐ型領域２０ｂと電気的に接続するものである。
【０００８】
ゲートをソースにショートし、ドレイン電位を正に高めていくと、ドリフト部２２の第１の並列ｐｎ構造は、ｎ型ドリフト電路領域２２ａがｎ＋ ドレイン層（コンタクト層）１１に導電接続していると共にｐ型の仕切領域２２ｂがｐベース領域１３ａに導電接続しているため、早期に空乏化し、ドリフト部２２から耐圧構造部２０へと空乏層が拡張する。ここで、ｐ型リング２０ｃがない場合、耐圧構造部２０の第２の並列ｐｎ構造のうち、一端がｐベース領域１３ａ又はドリフト部２２の仕切領域２２ｂに直接接続しているｐ型領域２０ｂｂ（図９のドリフト部２２からＹ方向の領域）ではＹ方向に空乏層が拡張するものの、一端がｐベース領域１３ａ又はドリフト部２２の仕切領域２２ｂに直接接続していないｐ型領域２０ｂａは電位浮遊状態でガードリングとしてのみ機能するために、ドリフト部２２から空乏層のＸ方向への拡張が弱く、臨界電界に達し易い。ところが、ｐ型リング２０ｃが存在すると、一端がｐベース領域１３ａ又はドリフト部２２の仕切領域２２ｂに直接接続していないｐ型領域２０ｂａはｐ型リング２０ｃを介して一端がｐベース領域１３ａ又はドリフト部２２の仕切領域２２ｂに直接接続しているｐ型領域２０ｂｂに電気的に接続されているため、ｐ型領域２０ｂａの電位浮遊状態が解消し、ｐ型領域２０ｂａはソース電位側に固定されるので、ｐ型領域２０ｂａでのｐｎ接合も確実に逆バイアスになり、空乏層がドリフト部２２からＸ方向へ拡張する。従って、高耐圧化を図ることができる。
【０００９】
【発明が解決しようとする課題】
しかしながら、図９乃至図１１に示す縦形ＭＯＳＦＥＴにあっては、次のような問題点があった。
【００１０】
即ち、並列ｐｎ構造はエピタキシャル層の成長と選択的イオン打ち込みとを繰り返した後熱拡散で形成するものであるから、耐圧構造部２０の並列ｐｎ構造はドリフト部２２の並列ｐｎ構造と同時に形成される。耐圧構造部２０の並列ｐｎ構造はドリフト部２２のオン抵抗の低減のために不純物濃度が高くなっているため、ｐ型領域２０ｂｂのｐ型リング２０ｃまでの距離に応じた電圧降下が少ないので、複数のｐ型リング２０ｃ間に相互電位差が現れ難く、耐圧構造部２０の表面電界が緩和され難くなる。耐圧構造部２０のｐ型領域２０ｂの幅がドレイン部２２の仕切領域２２ｂの幅よりも狭いと、抵抗断面の縮小によりｐ型領域２０ｂの距離に応じた電圧降下が現れるため、ｐ型領域２０ｂとｐ型リング２０ｃとの交差点の電位はある程度ドレイン部２２からの距離に応じた電位となるものの、ｐ型リング２０ｃの本数が増える。これでは、リング間隔を拡げざるを得ないため、耐圧構造部２０の占有面積の拡大を招き、集積化の障害になる。
【００１１】
そこで、上記問題点に鑑み、本発明の課題は、ドリフト部の周りの耐圧構造部が並列ｐｎ構造を有する半導体装置において、その耐圧構造部の占有面積の拡大を招かずに、耐圧構造部の表面電界を緩和でき、高耐圧化を図ることができる半導体装置及びその製造方法を提供することにある。
【００１２】
【課題を解決するための手段】
上記課題を解決するために、本発明に係る半導体装置の基本構造は、基板の第１主面側に形成された素子活性部に導電接続する第１の電極層と、基板の第２主面側に形成された第１導電型の低抵抗層に導電接続する第２の電極層と、素子活性部と低抵抗層との間に介在し、オン状態ではドリフト電流を縦方向に流すと共にオフ状態では空乏化する縦形ドリフト部と、縦形ドリフト部の周りで第１主面と低抵抗層との間に介在し、オフ状態では空乏化する耐圧構造部とを有し、縦形ドリフト部及び耐圧構造部が基板の厚み方向に配向する縦形第１導電型領域と基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る並列ｐｎ構造を有する。ここで、基板の第１主面側に形成された素子活性部とは、例えば縦型ＭＯＳＦＥＴの場合は第１主面側で反転層を形成するチャネル拡散層とソース領域を含むスイッチング部、バイポーラトランジスタの場合はエミッタ又はコレクタ領域を含むスイッチング部であり、ドリフト部の第１主面側の能動又は受動部分を指す。
【００１３】
そして、本発明においては、耐圧構造部が、並列ｐｎ構造の第１主面側に接続する第１導電型の高抵抗層を有し、耐圧構造部の並列ｐｎ構造の長さがドリフト部の並列ｐｎ構造の長さよりも短いことを特徴する。第１導電型の高抵抗層がない並列ｐｎ構造の場合に比して、表面電界を緩和できる。この高抵抗層は第１導電型と第２導電型の不純物の双方をドープして形成することができる。
【００１４】
また、本発明は、素子活性部の周りで縦形第２導電型領域に非接続で高抵抗層の主面側に形成された第２導電型のリングとを有することを特徴する。第２導電型のリングが耐圧構造部の縦形第２導電型領域に接続していないため、オフ状態の場合、耐圧構造部における縦形第２導電型領域の幅の広狭に拘わらず、第２導電型のリングには素子活性部又はドリフト部からの距離に応じた電圧降下が現れるので、耐圧構造部の表面電界が緩和される。
【００１５】
第２導電型のリングが間隔をおいて複数形成されている構造では、リング間隔を拡げずとも、耐圧構造部の表面電界を緩和できるので、耐圧構造部の占有面積を縮小でき、高集積化を図ることができる。
【００１６】
ここで、耐圧構造部の並列ｐｎ構造の長さはドリフト部の並列ｐｎ構造の長さよりも第１主面側において短いことが望ましい。
【００１７】
更に、耐圧構造部の並列ｐｎ構造のｐｎ繰り返しピッチを縦形ドリフト部の並列ｐｎ構造のｐｎ繰り返しピッチよりも狭くすることが望ましい。遮断瞬時では構造耐圧部での空乏層の拡張がドリフト部よりも早まり、ダイナミック・アバランシェ・ブレイクダウンが構造耐圧部では発生し難くなり、安定した耐圧の確保が可能である。
【００１８】
耐圧構造部の周囲には第１導電型のチャネルストッパー領域が形成されていることが望ましい。漏れ電流を低減できる。このチャネルストッパー領域は側縁領域を介して低抵抗層に接続していても良い。耐圧構造部の周囲が第２電極層の電位となるため、耐圧構造部の占有面積を縮小化でき、また素子耐圧の安定化を図ることができる。
【００１９】
次に、本発明は、基板の第１主面側に形成された素子活性部に導電接続する第１の電極層と、基板の第２主面側に形成された第１導電型の低抵抗層に導電接続する第２の電極層と、素子活性部と前記低抵抗層との間に介在し、オン状態ではドリフト電流を縦方向に流すと共にオフ状態では空乏化する縦形ドリフト部と、前記縦形ドリフト部の周りで第１主面と低抵抗層との間に介在し、オフ状態では空乏化する耐圧構造部とを有し、縦形ドリフト部及び耐圧構造部が基板の厚み方向に配向する縦形第１導電型領域と前記基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る並列ｐｎ構造を有し、耐圧構造部は並列ｐｎ構造の主面側に接続する第１導電型の高抵抗層と素子活性部の周りで縦形第２導電型領域に非接続で前記高抵抗層の主面側に形成された第２導電型のリングとを有する半導体装置の製造方法に関する。
【００２０】
この製造方法は、第１導電型の低抵抗基体上の縦形ドリフト部及び耐圧構造部を形成すべき領域において、第１導電型高抵抗のエピタキシャル層を成長させた後、そのエピタキシャル層に離散的に配置した不純物導入窓を介して第２の導電型の不純物イオンを選択的に導入する工程を繰り返す第１の段階と、次いで、新たに第１導電型高抵抗のエピタキシャル層を成長させた後、耐圧構造部を形成すべき領域をマスクした状態で、縦形ドリフト部を形成すべき領域において第２の導電型の不純物イオンを離散的に配置した不純物導入窓を介して選択的に導入する工程を少なくとも１回行う第２の段階と、しかる後、熱処理を施して各エピタキシャル層に選択的に導入した不純物を熱拡散させて層違いの熱拡散領域同士を上下相互に接続し、並列ｐｎ構造を形成する第３の段階と、を有することを特徴とする。なお、各エピタキシャル層毎の全面にイオン注入により第１導電型の不純物を導入し、形成される縦形のｎ型領域の不純物濃度を高め、縦形ドリフト部のオン抵抗の低減を図っても構わない。
【００２１】
このように、各エピタキシャル層に仕込んだ不純物を最後に熱拡散させて会合させ、縦形第１導電型領域と縦形第２導電型領域とを一気に形成するものであるから、並列ｐｎ構造の形成が容易であるが、第２の段階では耐圧構造部のエピタキシャル層がマスクで覆われているため、不純物イオンの導入が阻止されているので、耐圧構造部の並列ｐｎ構造の長さはドリフト部のそれに比して短くすることができ、耐圧構造部の並列ｐｎ構造の上に形成される第１導電型高抵抗のエピタキシャル層に第２導電型のリングを形成できる。ドリフト部及び耐圧構造部の並列ｐｎ構造が同じ長さの場合に比し、特段のプロセス追加を招かずに済む。
【００２２】
この製造方法においては、各エピタキシャル層毎の全面にイオン注入により第１導電型の不純物を導入する場合、上層側のエピタキシャル層での耐圧構造部では第１導電型の不純物導入を阻止するための専用のマスクの成膜及びその除去工程を必要とし、工程数の増加を招く。そこで、第２の段階としては、新たに第１導電型高抵抗のエピタキシャル層を成長させた後、全面に第１の導電型の不純物イオンを導入してから、耐圧構造部を形成すべき領域での不純物導入窓のピッチと窓幅が前記縦形ドリフト部を形成すべき領域でのピッチと窓幅よりも狭いマスクを形成して第２の導電型の不純物イオンを選択的に導入する工程を少なくとも１回行う方法を採用する。上層側のエピタキシャル層の耐圧構造部となるべき領域には、ドリフト部となるべき範囲での不純物導入窓のピッチ及び窓幅よりも狭いピッチ及び窓幅のマスクが覆われているので、熱拡散工程では、導入された分散的な狭限定領域の第２の不純物はその拡散により第１の不純物の拡散と混ざり合うことから、上層側のエピタキシャル層の耐圧構造部に当たる部分には第２導電型の領域が形成されず、略一様な第１導電型の高抵抗層が形成される。従って、第１導電型の不純物導入を阻止するための専用のマスクの成膜及びその除去工程を必要とせず、製造プロセスの簡略化と半導体装置の低コスト化を図ることができる。
【００２３】
【発明の実施の形態】
［実施例１］
図１は本発明の実施例１に係る縦形ＭＯＳＦＥＴ素子のチップを示す概略平面図、図２は図１中のＡ−Ａ′線に沿って切断した状態を示す縦断面図、図３は図１中のＢ−Ｂ′線に沿って切断した状態を示す縦断面図である。なお、図１ではドリフト部の１／４を斜線部分で示してある。
【００２４】
本例の縦形ＭＯＳＦＥＴは、裏側のドレイン電極１８が導電接触した低抵抗のｎ＋ ドレイン層（コンタクト層）１１の上に形成された第１の並列ｐｎ構造のドレイン・ドリフト部２２と、このドリフト部２２の表面層に選択的に形成された素子活性領域たる高不純物濃度のｐベース領域（ｐウェル）１３ａと、そのｐベース領域１３ａ内の表面側に選択的に形成された高不純物濃度のｎ＋ ソース領域１４と、基板表面上にゲート絶縁膜１５を介して設けられたポリシリコン等のゲート電極層１６と、層間絶縁膜１９ａに開けたコンタクト孔を介してｐベース領域１３ａ及びｎ＋ ソース領域１４に跨って導電接触するソース電極１７とを有している。ウェル状のｐベース領域１３ａの中にｎ＋ ソース領域１４が浅く形成されており、２重拡散型ＭＯＳ部を構成している。なお、２６はｐ＋ コンタクト領域で、また、図示しない部分でゲート電極層１６の上に金属膜のゲート配線が導電接触している。
【００２５】
第１の並列ｐｎ構造のドレイン・ドリフト部２２は、基板の厚み方向に層状縦形のｎ型ドリフト電路領域２２ａと基板の厚み方向に層状縦形のｐ型仕切領域２２ｂとを交互に繰り返して接合した構造である。ｎ型のドリフト電路領域２２ａは、その上端がｐベース領域１３の挾間領域１２ｅに達し、その下端がｎ＋ ドレイン層１１に接している。また、ｐ型の仕切領域２２ｂは、その上端がｐベース領域１３ａのウェル底面に接し、その下端がｎ＋ ドレイン層１１に接している。
【００２６】
縦形ドリフト部２２の周りの耐圧構造部１２０は、基板の厚さ方向に配向する層状縦形のｎ型領域１２０ａと、基板の厚さ方向に配向する層状縦形のｐ型領域１２０ｂとを交互に繰り返して接合して成る第２の並列ｐｎ構造を有している。この耐圧構造部１２０の第２の並列ｐｎ構造の長さ（基板厚方向の長さ）は縦形ドリフト部２２の第１の並列ｐｎ構造のそれよりも短くなっている。また本例の場合、耐圧構造部１２０の第２の並列ｐｎ構造の繰り返しピッチは縦形ドリフト部２２の第１の並列ｐｎ構造の繰り返しピッチと同じである。耐圧構造部１２０のうち、第２の並列ｐｎ構造の主面側にはｎ型の高抵抗層１２２が形成されている。そして、ｐベース領域１３ａの周りには複数のｐ型リング１２４ａ〜１２４ｅが形成されている。各ｐ型リング１２４ａ〜１２４ｅは第２の並列ｐｎ構造のｐ型領域１２０ｂに非接続で高抵抗層１２２の主面側に形成されており、図１に示すように、平面ｙ方向ではｐ型領域１２０ｂに直交し、平面ｘ方向ではｐ型領域１２０ｂに平行している。
【００２７】
耐圧構造部１２０の周りにはｎ型側縁領域１２６が形成されており、ｎ型側縁領域１２６の主面側にはｎ＋ のチャネルストッパー領域１２８が形成されている。なお、耐圧構造部１２０の主面上には、表面保護及び安定化のために、熱酸化膜又は燐シリカガラス（ＰＳＧ）から成る酸化膜（絶縁膜）２３が成膜されている。
【００２８】
このように、複数のｐ型リング１２４ａ〜１２４ｅが耐圧構造部１２０の第２の並列ｐｎ構造のｐ型領域１２０ｂに直接接続していないため、オフ状態では、ｐ型リング１２４ａ〜１２４ｅにはｐベース領域１３ａ又はドリフト部２２からの距離に応じた電圧降下が現れるので、耐圧構造部１２０の表面電界が緩和される。また、耐圧構造部１２０の占有面積を縮小でき、高集積化を図ることができる。
【００２９】
また、チャネルストッパー領域１２０が形成されているため、漏れ電流を低減できる。このチャネルストッパー領域１２０は側縁領域１２６を介してｎ＋ ドレイン層１１に接続されているため、耐圧構造部１２０の周囲がドレイン電圧となるため、耐圧構造部１２０の占有面積を縮小化でき、また素子耐圧の安定化を図ることができる。また、遮断瞬時では構造耐圧部１２０での空乏層の拡張がドリフト部２２よりも早まり、ダイナミック・アバランシェ・ブレイクダウンが耐圧構造部１２０では発生し難くなり、安定した耐圧の確保が可能である。
【００３０】
なお、本例ではｐ型リング１２４ａ〜１２４ｅの表面が酸化膜２３で覆われているが、ｐ型リング１２４ａ〜１２４ｅに接続してフィールドプレートが形成されていても耐圧を保持することができる。
【００３１】
［実施例２］
図４は本発明の実施例２に係る縦形ＭＯＳＦＥＴを示す部分縦断面図である。本例の実施例１と異なる点は、耐圧構造部２２０の第２の並列ｐｎ構造の繰り返しピッチが縦形ドリフト部２２の第１の並列ｐｎ構造の繰り返しピッチよりも狭いところにある。第２の並列ｐｎ構造のｐ型領域２２０ｂが幅狭になっても、ｐ型リング１２４ａ〜１２４ｅを幅狭に合わせる必要がなく、それらの間隔を自由に設計できる。また、遮断瞬時では構造耐圧部２２０での空乏層の拡張がドリフト部２２よりも早まり、ダイナミック・アバランシェ・ブレイクダウンが耐圧構造部２２０では発生し難くなり、安定した耐圧の確保が可能である。
【００３２】
［実施例３］
図５は本発明の実施例３に係る縦形ＭＯＳＦＥＴを示す部分縦断面図である。
【００３３】
本例と実施例１との違いは、ドリフト部２２２の第１の並列ｐｎ構造の上端側にも高抵抗層１２２が形成されており、ｐベース領域１３ａにはｐ型仕切領域２２ｂが接続していないと共に、ｎ型ドリフト電路領域２２ａもｐベース領域１３の挾間領域１２ｅに接続していないところにある。従って、ドリフト部２２２の第１の並列ｐｎ構造の上端と耐圧構造部１２０の第２の並列ｐｎ構造の上端とが斉一している。
【００３４】
本例の場合、実施例１及び２の場合に比し、並列ｐｎ構造を形成する際のエピタキシャル層の成長回数とイオン注入回数を減らすことができ、低コスト化を図ることができる。勿論、従来のＭＯＳＦＥＴに比べ、同じ耐圧クラスで十分に低いオン抵抗を得ることができる。なお、本例においても、実施例２と同様に、耐圧構造部１２０の第２の並列ｐｎ構造の繰り返しピッチをドリフト部２２の第１の並列ｐｎ構造の繰り返しピッチよりも狭くしても、同様の効果を得ることができる。
【００３５】
［実施例４］
図６（ａ）〜（ｇ）は本発明の実施例１の製造方法を示す工程断面図である。
【００３６】
まず、図６（ａ）に示す如く、ｎ＋ ドレイン層１１となるべきｎ型の低抵抗半導体基体の上に第１層目のｎ型高抵抗のエピタキシャル層３０ａを成長させる。
【００３７】
次いで、図６（ｂ）に示す如く、イオン注入法によりｎ型の不純物となる燐イオン３１を注入し、エピタキシャル層３０ａの表面下に燐原子３２を導入する。
【００３８】
次いで、図６（ｃ）に示す如く、エピタキシャル層３０ａの表面に、フォトリソグラフィーによりドリフト部２２及びその耐圧構造部１２０となるべき範囲で同一ピッチの不純物導入窓３３ａが開けられたレジストマスク３３を形成した後、イオン注入法によりｐ型の不純物となるホウ素イオン３４を注入し、エピタキシャル層３０ａの表面下にホウ素原子３５を選択的に導入する。なお、燐イオン３１の注入工程とホウ素イオン３４の注入工程はどちらを先にしても構わない。また、エピタキシャル層３０ａが高不純物濃度である場合は、その逆導電型のホウ素イオン３４の選択的導入だけで良い。
【００３９】
次いで、レジストマスク３３を除去した後、図６（ｄ）に示す如く、第１層目のエピタキシャル層３０ａの上に第２層目のｎ型高抵抗のエピタキシャル層３０ｂを成長させて、上記と同様な不純物導入工程を施し、更に、第３層目のｎ型高抵抗のエピタキシャル層３０ｃを成長させる。なお、要求される耐圧クラスに応じて、エピタキシャル層の成長工程と不純物導入工程とを交互に繰り返す。この後、ドリフト部２２となるべき範囲を窓開けしたレジストマスク３６で覆い、イオン注入法によりｎ型の不純物となる燐イオン３１を注入し、エピタキシャル層３０ｃのドリフト部２２となるべき表面下に燐原子３２を導入する。
【００４０】
次いで、図６（ｅ）に示す如く、レジストマスク３６の外、フォトリソグラフィーによりドリフト部２２となるべき範囲で同一ピッチの不純物導入窓３３ａが開けられたレジストマスク３３を形成した後、イオン注入法によりｐ型の不純物となるホウ素イオン３４を注入し、エピタキシャル層３０ｃの表面下にホウ素原子３５を選択的に導入する。
【００４１】
次いで、レジストマスク３６及びレジストマスク３３を除去した後、図６（ｆ）に示す如く、第４層目のｎ型高抵抗のエピタキシャル層３０ｄを成長させる。
【００４２】
しかる後、図６（ｇ）に示す如く、熱処理によってエピタキシャル層３０ａ〜３０ｄに導入されて仕込まれた燐元素３２とホウ素元素３５を同時に一斉熱拡散させて、各拡散中心から拡散する拡散単位領域を上下相互に接続させ、ドリフト部２２におけるｎ型のドリフト電路領域２２ａとｐ型の仕切領域２２ｂ並びに耐圧構造部１２０のｎ型領域１２０ａとｐ型領域１２０ｂとを同時に形成する。これらの縦形領域は拡散単位領域の相互連結で形成されたものであるから、熱拡散が十分であればｐｎ接合は略平坦面として観察できるが、拡散中心を最大濃度部として濃度分布を呈している。なお、並列ｐｎ構造のｐｎ接合は平坦面である必要もないことから、凹であっても構わない。
【００４３】
第３層目のエピタキシャル層３０ｃの耐圧構造部１２０となるべき領域にはレジストマスク３６が覆われていたので、不純物導入がなく、第４層目のエピタキシャル層３０ｄの耐圧構造部１２０に当たる部分がｎ型の高抵抗層１２２として残る。この後、第４層目のエピタキシャル層３０ｃ又はその上層の成長させたエピタキシャル層に通常のプロセスによりｐベース領域１３ａ及びｐ型リング１２４ａ〜１２４ｅを同時に形成し、２重拡散型ＭＯＳＦＥＴを完成する。
【００４４】
このように、各エピタキシャル層３０ａ〜３０ｄに仕込んだ不純物を最後に熱拡散させて会合させて並列ｐｎ構造を形成することができるが、耐圧構造部１２０のエピタキシャル層３０ｃがレジストマスク３６で覆われていたため、不純物イオンの導入が阻止されているので、耐圧構造部１２０の並列ｐｎ構造の長さはドリフト部２２のそれに比して短くすることができ、エピタキシャル層３０ｃにｐ型リング１２４ａ〜１２４ｅをｐベース領域１３ａと同時に形成できる。ドリフト部２２及び耐圧構造部１２０の並列ｐｎ構造が同じ長さの場合に比し、特段のプロセス追加を招かずに済み、低コスト化を図ることができる。
【００４５】
なお、実施例２のように、耐圧構造部２２０の第２の並列ｐｎ構造の繰り返しピッチが縦形ドリフト部２２の第１の並列ｐｎ構造の繰り返しピッチよりも狭い構造を得るためには、図６（ｃ）に示すレジストマスク３３を、ドリフト部２２となるべき範囲での不純物導入窓のピッチ及び窓幅よりも耐圧構造部２２０となるべき範囲での不純物導入窓３３ｃのピッチ及び窓幅を狭くする。
【００４６】
［実施例５］
図７（ａ）〜（ｇ）は本発明の実施例１に係る別の製造方法を示す工程断面図である。
【００４７】
本例においては、（ａ）〜（ｃ）の工程を繰り返すところまでは実施例４と同じである。次いで、レジストマスク３３を除去した後、図７（ｄ）に示す如く、第１層目のエピタキシャル層３０ａの上に第２層目のｎ型高抵抗のエピタキシャル層３０ｂを成長させて、上記と同様な不純物導入工程を施し、更に、第３層目のｎ型高抵抗のエピタキシャル層３０ｃを成長させる。なお、要求される耐圧クラスに応じて、エピタキシャル層の成長工程と不純物導入工程とを交互に繰り返す。この後、イオン注入法によりｎ型の不純物となる燐イオン３１を全面注入し、エピタキシャル層３０ｃの表面下に燐原子３２を導入する。
【００４８】
次いで、図７（ｅ）に示す如く、ドリフト部２２となるべき範囲での不純物導入窓３３ｂのピッチ及び窓幅よりも耐圧構造部１２０となるべき範囲での不純物導入窓３３ｃのピッチ及び窓幅が狭いレジストマスク３３′をフォトリソグラフィーにより形成した後、イオン注入法によりｐ型の不純物となるホウ素イオン３４を注入し、エピタキシャル層３０ｃの表面下にホウ素原子３５を選択的に導入する。
【００４９】
次いで、レジストマスク３３′を除去した後、図７（ｆ）に示す如く、第４層目のｎ型高抵抗のエピタキシャル層３０ｄを成長させる。
【００５０】
しかる後、図７（ｇ）に示す如く、熱処理によってエピタキシャル層３０ａ〜３０ｄに導入されて仕込まれた燐元素３２とホウ素元素３５を同時に一斉熱拡散させて、各拡散中心から拡散する拡散単位領域を上下相互に接続させ、ドリフト部２２におけるｎ型のドリフト電路領域２２ａとｐ型の仕切領域２２ｂ並びに耐圧構造部１２０のｎ型領域１２０ａとｐ型領域１２０ｂとを同時に形成する。これらの縦形領域は拡散単位領域の相互連結で形成されたものであるから、熱拡散が十分であればｐｎ接合は略平坦面として観察できるが、拡散中心を最大濃度部として濃度分布を呈している。なお、並列ｐｎ構造のｐｎ接合は平坦面である必要もないことから、凹であっても構わない。
【００５１】
第３層目のエピタキシャル層３０ｃの耐圧構造部１２０となるべき領域には、ドリフト部２２となるべき範囲での不純物導入窓３３ｂのピッチ及び窓幅よりも狭いピッチ及び窓幅のレジストマスク３６が覆われていたので、熱拡散工程では、導入された分散的な狭限定領域のホウ素原子３５はその拡散により燐元素３２の拡散と混ざり合うことから、第４層目のエピタキシャル層３０ｄの耐圧構造部１２０に当たる部分にはｐ型領域が形成されず、略一様なｎ型の高抵抗層１２２が形成される。従って、実施例５における図６（ｄ）のような、燐イオン３１の導入を阻止するための専用のレジストマスク３６の成膜及びその除去工程を間挿する必要がなく、製造プロセスの簡略化と半導体装置の低コスト化を図ることができる。
【００５２】
なお、この後、第４層目のエピタキシャル層３０ｃ又はその上層の成長させたエピタキシャル層に通常のプロセスによりｐベース領域１３ａ及びｐ型リング１２４ａ〜１２４ｅを同時に形成し、２重拡散型ＭＯＳＦＥＴを完成する。
【００５３】
［実施例６］
図８（ａ）〜（ｅ）は本発明の実施例３の製造方法を示す工程断面図である。
【００５４】
本例においては、（ａ）〜（ｃ）の工程を繰り返すところまでは実施例４と同じである。なお、要求される耐圧クラスに応じて、エピタキシャル層の成長工程と不純物導入工程とを交互に繰り返す。次いで、レジストマスク３３を除去した後、図７（ｄ）に示す如く、第１層目のエピタキシャル層３０ａの上に第２層目のｎ型高抵抗のエピタキシャル層３０ｂを成長させる。
【００５５】
しかる後、図８（ｅ）に示す如く、熱処理によってエピタキシャル層３０ａ〜３０ｄに導入されて仕込まれた燐元素３２とホウ素元素３５を同時に一斉熱拡散させて、各拡散中心から拡散する拡散単位領域を上下相互に接続させ、ドリフト部２２２におけるｎ型のドリフト電路領域２２ａとｐ型の仕切領域２２ｂ並びに耐圧構造部１２０のｎ型領域１２０ａとｐ型領域１２０ｂとを同時に形成する。これらの縦形領域は拡散単位領域の相互連結で形成されたものであるから、熱拡散が十分であればｐｎ接合は略平坦面として観察できるが、拡散中心を最大濃度部として濃度分布を呈している。なお、並列ｐｎ構造のｐｎ接合は平坦面である必要もないことから、凹であっても構わない。この後、通常のプロセスによりｐベース領域１３ａ及びｐ型リング１２４ａ〜１２４ｅを同時に形成し、２重拡散型ＭＯＳＦＥＴを完成する。本例の場合、並列ｐｎ構造を形成する際のエピタキシャル層の成長回数とイオン注入回数を減らすことができ、低コスト化を図ることができる。
【００５６】
以上説明したように、本発明においては、耐圧構造部が、並列ｐｎ構造の第１主面側に接続する第１導電型の高抵抗層を有し、耐圧構造部の並列ｐｎ構造の長さがドリフト部の並列ｐｎ構造の長さよりも短いことを特徴する。第１導電型の高抵抗層がない並列ｐｎ構造の場合に比して、表面電界を緩和できる。また、素子活性部の周りで縦形第２導電型領域に非接続で高抵抗層の主面側に形成された第２導電型のリングとを有することを特徴する。第２導電型のリングが耐圧構造部の縦形第２導電型領域に接続していないため、オフ状態の場合、耐圧構造部における縦形第２導電型領域の幅の広狭に拘わらず、第２導電型のリングには素子活性部又はドリフト部からの距離に応じた電圧降下が現れるので、耐圧構造部の表面電界が緩和される。
【００５７】
第２導電型のリングが間隔をおいて複数形成されている構造では、リング間隔を拡げずとも、耐圧構造部の表面電界を緩和できるので、耐圧構造部の占有面積を縮小でき、高集積化を図ることができる。
【００５８】
また、本発明の製造方法において、第２の段階では耐圧構造部のエピタキシャル層がマスクで覆われているため、不純物イオンの導入が阻止されているので、耐圧構造部の並列ｐｎ構造の長さはドリフト部のそれに比して短くすることができ、耐圧構造部の並列ｐｎ構造の上に形成される第１導電型高抵抗のエピタキシャル層に第２導電型のリングを形成できる。ドリフト部及び耐圧構造部の並列ｐｎ構造が同じ長さの場合に比し、特段のプロセス追加を招かずに済む。
【図面の簡単な説明】
【図１】本発明の実施例１に係る縦形ＭＯＳＦＥＴ素子のチップを示す概略平面図である。
【図２】図１中のＡ−Ａ′線に沿って切断した状態を示す縦断面図である。
【図３】図１中のＢ−Ｂ′線に沿って切断した状態を示す縦断面図である。
【図４】本発明の実施例２に係る縦形ＭＯＳＦＥＴを示す部分縦断面図である。
【図５】本発明の実施例３に係る縦形ＭＯＳＦＥＴを示す部分縦断面図である。
【図６】（ａ）〜（ｇ）は本発明の実施例１の製造方法を示す工程断面図である。
【図７】（ａ）〜（ｇ）は本発明の実施例１の別の製造方法を示す工程断面図である。
【図８】（ａ）〜（ｅ）は本発明の実施例３の製造方法を示す工程断面図である。
【図９】縦形ＭＯＳＦＥＴにおけるドリフト部及び素子外周部（耐圧構造部）を示す平面図である。
【図１０】図９中のＡ−Ａ′線に沿って切断した状態を示す縦断面図である。
【図１１】図９中のＢ−Ｂ′線に沿って切断した状態を示す縦断面図である。
【符号の説明】
１１…ｎ＋ ドレイン層（コンタクト層）
１２ｅ…ｐベース領域の挾間領域
１３ａ…ｐベース領域（ｐウェル）
１４…ｎ＋ ソース領域
１５…ゲート絶縁膜
１６…ゲート電極層
１７…ソース電極
１８…ドレイン電極
１９ａ…層間絶縁膜
２２，２２２…ドレイン・ドリフト部
２２ａ…層状縦形のｎ型ドリフト電路領域
２２ｂ…層状縦形のｐ型仕切領域
２３…酸化膜（絶縁膜）
２６…ｐ＋ コンタクト領域
３０ａ〜３０ｅ…ｎ型高抵抗のエピタキシャル層
３１…燐イオン
３２…燐原子
３３ａ〜３３ｃ…不純物導入窓
３３，３３′，３６…レジストマスク
３４…ホウ素イオン
３５…ホウ素原子
１２０，２２０…耐圧構造部
１２０ａ，２２０ａ…層状縦形のｎ型領域
１２０ｂ，２２０ｂ…層状縦形のｐ型領域
１２２…ｎ型の高抵抗層
１２４ａ〜１２４ｅ…ｐ型リング
１２６…ｎ型側縁領域
１２８…ｎ＋ のチャネルストッパー領域[0001]
BACKGROUND OF THE INVENTION
The present invention can be applied to active elements such as MOSFETs (insulated gate field effect transistors), IGBTs (conductivity modulation MOSFETs) and bipolar transistors, and passive elements such as diodes. The present invention relates to a compatible vertical power semiconductor device and a method for manufacturing the same.
[0002]
In a vertical semiconductor device that has electrode portions on both sides of a substrate and has a vertical drift portion that allows current to flow in the thickness direction of the substrate, there must be a trade-off relationship between on-resistance (current capacity) and breakdown voltage. Therefore, it is known to adopt a parallel pn structure in which an n-type vertical region and a p-type vertical region with an increased impurity concentration are alternately repeated in the horizontal direction of the substrate as the vertical drift portion. However, although the vertical drift portion of this parallel pn structure quickly depletes, the depletion layer does not easily extend outward or deep in the substrate in the breakdown voltage structure around the drift portion, and the electric field strength quickly reaches the critical electric field strength of silicon. Since the breakdown voltage is lowered in the breakdown voltage structure, it is known to adopt a parallel pn structure in the breakdown voltage structure.
[0003]
9 is a plan view showing a drift portion and an element outer peripheral portion (withstand voltage structure portion) in the vertical MOSFET, FIG. 10 is a longitudinal sectional view showing a state cut along the line AA ′ in FIG. 9, and FIG. 9 is a longitudinal sectional view showing a state cut along a line BB ′ in FIG. In FIG. 9, ¼ of the drift portion is indicated by a hatched portion.
[0004]
This n-channel vertical MOSFET has a low resistance n-type in which the drain electrode 18 on the back side is in conductive contact.+A drain / drift portion 22 having a first parallel pn structure formed on the drain layer (contact layer) 11, and a high impurity concentration p which is an element active region selectively formed on the surface layer of the drift portion 22 Base region (p well, channel region) 13a and n of high impurity concentration selectively formed on the surface side in the p base region 13a+The source region 14, the gate electrode layer 16 such as polysilicon provided on the substrate surface via the gate insulating film 15, and the p base regions 13a and n through the contact holes opened in the interlayer insulating film 19a+A source electrode 17 in conductive contact with the source region 14; N in the well-shaped p base region 13a+The source region 14 is formed shallow and constitutes a double diffusion type MOS portion. 26 is p+The gate wiring of the metal film is in conductive contact on the gate electrode layer 16 in the contact region and in a portion (not shown).
[0005]
The drain / drift portion 22 of the first parallel pn structure has a layered vertical n-type drift circuit region 22a and a layered vertical p-type partition region 22b alternately and repeatedly joined in the thickness direction of the substrate. It is a structure. The n-type drift circuit region 22a has an upper end that reaches the intercostal region 12e of the p base region 13a, and a lower end that is n+It is in contact with the drain layer 11. The upper end of the p-type partition region 22b is in contact with the well bottom surface of the p base region 13a, and the lower end is n.+It is in contact with the drain layer 11.
[0006]
Substrate surface and n+In the breakdown voltage structure 20 around the vertical drift portion 22 between the drain layer 11 and the drain layer 11, a layered vertical n-type region 20a oriented in the thickness direction of the substrate and a layered vertical p oriented in the thickness direction of the substrate. A second parallel pn structure is formed by alternately joining the mold regions 20b. An oxide film (insulating film) 23 made of a thermal oxide film or phosphor silica glass (PSG) is formed on the surface of the second parallel pn structure of the breakdown voltage structure 20 for surface protection and stabilization. Yes.
[0007]
Multiple p-type rings 20c are wound around the surface side of the breakdown voltage structure 20 so as to surround the p base region. The p-type ring 20c is electrically connected to a large number of p-type regions 20b having a second parallel pn structure.
[0008]
When the gate is shorted to the source and the drain potential is increased positively, the first parallel pn structure of the drift portion 22 has an n-type drift current path region 22a of n+Since it is conductively connected to the drain layer (contact layer) 11 and the p-type partition region 22b is conductively connected to the p base region 13a, it is depleted early and the depletion layer from the drift portion 22 to the breakdown voltage structure portion 20 Expands. Here, in the case where there is no p-type ring 20c, the p-type region 20bb (one end of the second parallel pn structure of the breakdown voltage structure 20 is directly connected to the p base region 13a or the partition region 22b of the drift portion 22). Although the depletion layer extends in the Y direction in the Y direction region from the drift portion 22 in FIG. 9, the p-type region 20ba whose one end is not directly connected to the p base region 13a or the partition region 22b of the drift portion 22 has a potential floating. Since it functions only as a guard ring in a state, the expansion of the depletion layer from the drift portion 22 in the X direction is weak, and a critical electric field is easily reached. However, when the p-type ring 20c is present, the p-type region 20ba whose one end is not directly connected to the partition region 22b of the p-base region 13a or the drift portion 22 has one end connected to the p-base region 13a or the drift via the p-type ring 20c. Since it is electrically connected to the p-type region 20bb directly connected to the partition region 22b of the portion 22, the potential floating state of the p-type region 20ba is eliminated, and the p-type region 20ba is fixed to the source potential side. Therefore, the pn junction in the p-type region 20ba is also reliably reverse-biased, and the depletion layer extends from the drift portion 22 in the X direction. Therefore, a high breakdown voltage can be achieved.
[0009]
[Problems to be solved by the invention]
However, the vertical MOSFETs shown in FIGS. 9 to 11 have the following problems.
[0010]
That is, since the parallel pn structure is formed by thermal diffusion after repeating the growth of the epitaxial layer and selective ion implantation, the parallel pn structure of the withstand voltage structure 20 is formed simultaneously with the parallel pn structure of the drift part 22. The Since the parallel pn structure of the breakdown voltage structure portion 20 has a high impurity concentration to reduce the on-resistance of the drift portion 22, the voltage drop corresponding to the distance from the p-type region 20bb to the p-type ring 20c is small. A mutual potential difference is unlikely to appear between the plurality of p-type rings 20c, and the surface electric field of the breakdown voltage structure 20 is difficult to be relaxed. If the width of the p-type region 20b of the breakdown voltage structure 20 is narrower than the width of the partition region 22b of the drain portion 22, a voltage drop corresponding to the distance of the p-type region 20b appears due to the reduction of the resistance cross section. Although the potential at the intersection between the p-type ring 20c and the p-type ring 20c becomes a potential corresponding to the distance from the drain part 22 to some extent, the number of p-type rings 20c increases. In this case, since the ring interval must be increased, the occupation area of the pressure-resistant structure 20 is increased, which is an obstacle to integration.
[0011]
Accordingly, in view of the above problems, an object of the present invention is to provide a semiconductor device having a parallel pn structure in the breakdown voltage structure around the drift portion without increasing the occupation area of the breakdown voltage structure. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can alleviate a surface electric field and achieve a high breakdown voltage.
[0012]
[Means for Solving the Problems]
  In order to solve the above problems, a basic structure of a semiconductor device according to the present invention includes a first electrode layer that is conductively connected to an element active portion formed on the first main surface side of a substrate, and a second main surface of the substrate. Is interposed between the second electrode layer conductively connected to the first resistance type low resistance layer formed on the side, the element active portion and the low resistance layer, and in the ON state, a drift current flows in the vertical direction and is turned off. In the state, the vertical drift portion is depleted, and is interposed between the first main surface and the low resistance layer around the vertical drift portion.TheA vertical first conductivity type region in which the vertical drift portion and the breakdown voltage structure portion are oriented in the thickness direction of the substrate, and a vertical second conductivity type region in which the vertical drift portion and the withstand voltage structure portion are oriented in the thickness direction of the substrate; Have a parallel pn structure in which these are joined alternately. Here, the element active portion formed on the first main surface side of the substrate is, for example, a switching portion including a channel diffusion layer and a source region forming an inversion layer on the first main surface side in the case of a vertical MOSFET, bipolar In the case of a transistor, it is a switching part including an emitter or collector region, and indicates an active or passive part on the first main surface side of the drift part.
[0013]
  In the present invention, the breakdown voltage structure portion has a parallel pn structure.FirstHigh resistance layer of the first conductivity type connected to the main surface sideThe length of the parallel pn structure of the breakdown voltage structure portion is shorter than the length of the parallel pn structure of the drift portion.It is characterized by that. The surface electric field can be relaxed as compared with the parallel pn structure without the first conductive type high resistance layer. This high resistance layer can be formed by doping both the first conductivity type and the second conductivity type impurities.
[0014]
In addition, the present invention is characterized in that it has a second conductivity type ring formed on the main surface side of the high resistance layer without being connected to the vertical second conductivity type region around the element active portion. Since the second conductivity type ring is not connected to the vertical second conductivity type region of the breakdown voltage structure portion, in the off state, the second conductivity type regardless of the width of the vertical second conductivity type region in the breakdown voltage structure portion. Since a voltage drop corresponding to the distance from the element active portion or the drift portion appears in the ring of the mold, the surface electric field of the breakdown voltage structure portion is relaxed.
[0015]
In a structure in which a plurality of rings of the second conductivity type are formed at intervals, the surface electric field of the breakdown voltage structure portion can be relaxed without increasing the ring interval, so the area occupied by the breakdown voltage structure portion can be reduced and high integration can be achieved. Can be achieved.
[0016]
  Here, the length of the parallel pn structure of the breakdown voltage structure portion is longer than the length of the parallel pn structure of the drift portion.Desirably short on the first main surface side.
[0017]
Furthermore, it is desirable to make the pn repetition pitch of the parallel pn structure of the breakdown voltage structure portion narrower than the pn repetition pitch of the parallel pn structure of the vertical drift portion. At the moment of interruption, the expansion of the depletion layer in the structural withstand voltage part is earlier than in the drift part, and dynamic avalanche breakdown is less likely to occur in the structural withstand voltage part, and a stable withstand voltage can be secured.
[0018]
It is desirable that a channel stopper region of the first conductivity type is formed around the breakdown voltage structure portion. Leakage current can be reduced. The channel stopper region may be connected to the low resistance layer through the side edge region. Since the periphery of the breakdown voltage structure portion becomes the potential of the second electrode layer, the area occupied by the breakdown voltage structure portion can be reduced, and the breakdown voltage of the element can be stabilized.
[0019]
  Next, the present invention provides a first electrode layer that is conductively connected to the element active portion formed on the first main surface side of the substrate, and a first conductivity type low resistance formed on the second main surface side of the substrate. A second electrode layer conductively connected to the layer, a vertical drift portion interposed between the element active portion and the low-resistance layer, wherein a drift current flows in a vertical direction in an on state and is depleted in an off state; It is interposed between the first main surface and the low resistance layer around the vertical drift portion.TheA vertical first conductivity type region in which the vertical drift portion and the breakdown voltage structure portion are oriented in the thickness direction of the substrate, and a vertical second conductivity type region in which the vertical drift portion and the withstand voltage structure portion are oriented in the thickness direction of the substrate. Are connected in parallel, and the breakdown voltage structure portion has a first conductive type high-resistance layer connected to the main surface side of the parallel pn structure and a vertical second conductivity around the element active portion. The present invention relates to a method of manufacturing a semiconductor device having a second conductivity type ring formed on a main surface side of the high resistance layer without being connected to a mold region.
[0020]
In this manufacturing method, after growing a first conductivity type high resistance epitaxial layer in a region where a vertical drift portion and a breakdown voltage structure portion on a first conductivity type low resistance substrate are to be formed, the epitaxial layer is discretely formed on the epitaxial layer. A first step of repeating the step of selectively introducing impurity ions of the second conductivity type through the impurity introduction window disposed in the step, and then after newly growing a first conductivity type high resistance epitaxial layer The step of selectively introducing impurity ions of the second conductivity type through the impurity introduction windows discretely arranged in the region where the vertical drift portion is to be formed in a state where the region where the breakdown voltage structure portion is to be formed is masked A second step of performing at least once, and then heat-diffusing the impurities selectively introduced into the respective epitaxial layers by heat treatment to connect the heat diffusion regions of different layers to each other vertically. And having a third step of forming a pn structure. The first conductivity type impurity may be introduced into the entire surface of each epitaxial layer by ion implantation to increase the impurity concentration of the formed vertical n-type region and reduce the on-resistance of the vertical drift portion. .
[0021]
As described above, since the impurities charged in each epitaxial layer are finally thermally diffused and associated to form the vertical first conductive type region and the vertical second conductive type region at a stretch, the formation of the parallel pn structure can be achieved. Although it is easy, since the epitaxial layer of the breakdown voltage structure portion is covered with a mask in the second stage and the introduction of impurity ions is blocked, the length of the parallel pn structure of the breakdown voltage structure portion is equal to that of the drift portion. Compared to this, the second conductive type ring can be formed in the first conductive type high resistance epitaxial layer formed on the parallel pn structure of the breakdown voltage structure portion. Compared to the case where the parallel pn structure of the drift portion and the breakdown voltage structure portion have the same length, it is not necessary to add a special process.
[0022]
  In this manufacturing method, when the first conductivity type impurity is introduced into the entire surface of each epitaxial layer by ion implantation, the breakdown voltage structure portion in the upper epitaxial layer is used to prevent the introduction of the first conductivity type impurity. Dedicated mask deposition and removal processes are required, which increases the number of processes. Therefore, as a second stage, after a new first conductivity type high resistance epitaxial layer is grown,After introducing impurity ions of the first conductivity type over the entire surface,Impurity ions of the second conductivity type are formed by forming a mask in which the pitch and window width of the impurity introduction window in the region where the breakdown voltage structure portion is to be formed are narrower than the pitch and window width in the region where the vertical drift portion is to be formed. A method of performing the step of selectively introducing at least once is adopted. The region to be the breakdown voltage structure portion of the epitaxial layer on the upper layer side is covered with a mask having a pitch and window width narrower than the pitch and window width of the impurity introduction window in the range to be the drift portion. In the process, since the introduced second impurity in the narrow and narrow region is mixed with the diffusion of the first impurity due to the diffusion, the second conductivity type is present in the portion corresponding to the breakdown voltage structure portion of the upper epitaxial layer. This region is not formed, and a substantially uniform high resistance layer of the first conductivity type is formed. Therefore, it is not necessary to form and remove a dedicated mask for preventing the introduction of the first conductivity type impurity, and the manufacturing process can be simplified and the cost of the semiconductor device can be reduced.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
[Example 1]
1 is a schematic plan view showing a chip of a vertical MOSFET element according to Embodiment 1 of the present invention, FIG. 2 is a longitudinal sectional view showing a state cut along the line AA 'in FIG. 1, and FIG. 1 is a longitudinal sectional view showing a state cut along a line BB ′ in FIG. In FIG. 1, ¼ of the drift portion is indicated by a hatched portion.
[0024]
The vertical MOSFET of this example has a low resistance n-type in which the drain electrode 18 on the back side is in conductive contact.+A drain / drift portion 22 having a first parallel pn structure formed on the drain layer (contact layer) 11, and a high impurity concentration p which is an element active region selectively formed on the surface layer of the drift portion 22 Base region (p well) 13a and n of high impurity concentration selectively formed on the surface side in p base region 13a+The source region 14, the gate electrode layer 16 such as polysilicon provided on the substrate surface via the gate insulating film 15, and the p base regions 13a and n through the contact holes opened in the interlayer insulating film 19a+A source electrode 17 in conductive contact with the source region 14; N in the well-shaped p base region 13a+The source region 14 is formed shallow and constitutes a double diffusion type MOS portion. 26 is p+The gate wiring of the metal film is in conductive contact on the gate electrode layer 16 in the contact region and in a portion (not shown).
[0025]
The drain / drift portion 22 of the first parallel pn structure has a layered vertical n-type drift circuit region 22a and a layered vertical p-type partition region 22b alternately and repeatedly joined in the thickness direction of the substrate. It is a structure. The upper end of the n-type drift electric circuit region 22a reaches the interspace region 12e of the p base region 13, and the lower end thereof is n+It is in contact with the drain layer 11. The upper end of the p-type partition region 22b is in contact with the well bottom surface of the p base region 13a, and the lower end is n.+It is in contact with the drain layer 11.
[0026]
The breakdown voltage structure 120 around the vertical drift portion 22 alternately repeats a layered vertical n-type region 120a oriented in the thickness direction of the substrate and a layered vertical p-type region 120b oriented in the thickness direction of the substrate. And having a second parallel pn structure formed by bonding. The length (length in the substrate thickness direction) of the second parallel pn structure of the breakdown voltage structure portion 120 is shorter than that of the first parallel pn structure of the vertical drift portion 22. In the case of this example, the repetition pitch of the second parallel pn structure of the breakdown voltage structure portion 120 is the same as the repetition pitch of the first parallel pn structure of the vertical drift portion 22. An n-type high resistance layer 122 is formed on the main surface side of the second parallel pn structure in the breakdown voltage structure 120. A plurality of p-type rings 124a to 124e are formed around the p base region 13a. Each of the p-type rings 124a to 124e is not connected to the p-type region 120b of the second parallel pn structure and is formed on the main surface side of the high resistance layer 122. As shown in FIG. It is orthogonal to the region 120b and is parallel to the p-type region 120b in the plane x direction.
[0027]
An n-type side edge region 126 is formed around the breakdown voltage structure 120, and n-type side edge region 126 has n on the main surface side.+The channel stopper region 128 is formed. An oxide film (insulating film) 23 made of a thermal oxide film or phosphor silica glass (PSG) is formed on the main surface of the pressure-resistant structure portion 120 for surface protection and stabilization.
[0028]
As described above, since the plurality of p-type rings 124a to 124e are not directly connected to the p-type region 120b of the second parallel pn structure of the breakdown voltage structure 120, the p-type rings 124a to 124e have p in the off state. Since a voltage drop corresponding to the distance from the base region 13a or the drift portion 22 appears, the surface electric field of the breakdown voltage structure portion 120 is relaxed. In addition, the area occupied by the pressure-resistant structure 120 can be reduced, and high integration can be achieved.
[0029]
Further, since the channel stopper region 120 is formed, the leakage current can be reduced. The channel stopper region 120 is n through the side edge region 126.+Since the drain voltage is connected to the drain layer 11, the area around the breakdown voltage structure 120 becomes a drain voltage, so that the area occupied by the breakdown voltage structure 120 can be reduced and the breakdown voltage of the element can be stabilized. In addition, at the instant of interruption, the expansion of the depletion layer in the structural withstand voltage portion 120 is earlier than in the drift portion 22, and dynamic avalanche breakdown is less likely to occur in the withstand voltage structure portion 120, so that a stable withstand voltage can be secured.
[0030]
In this example, the surfaces of the p-type rings 124a to 124e are covered with the oxide film 23. However, the breakdown voltage can be maintained even if a field plate is formed connected to the p-type rings 124a to 124e.
[0031]
[Example 2]
FIG. 4 is a partial longitudinal sectional view showing a vertical MOSFET according to Embodiment 2 of the present invention. The difference of this example from Example 1 is that the repetition pitch of the second parallel pn structure of the breakdown voltage structure 220 is narrower than the repetition pitch of the first parallel pn structure of the vertical drift portion 22. Even if the p-type region 220b of the second parallel pn structure becomes narrow, it is not necessary to adjust the p-type rings 124a to 124e narrowly, and the interval between them can be designed freely. In addition, the depletion layer expands at the structural withstand voltage unit 220 earlier than the drift unit 22 at the instant of interruption, so that a dynamic avalanche breakdown is less likely to occur at the withstand voltage structure unit 220 and a stable withstand voltage can be secured.
[0032]
[Example 3]
FIG. 5 is a partial longitudinal sectional view showing a vertical MOSFET according to Embodiment 3 of the present invention.
[0033]
The difference between this example and Example 1 is that the high resistance layer 122 is also formed on the upper end side of the first parallel pn structure of the drift portion 222, and the p-type partition region 22b is connected to the p base region 13a. In addition, the n-type drift electric circuit region 22 a is not connected to the interspace region 12 e of the p base region 13. Therefore, the upper end of the first parallel pn structure of the drift portion 222 and the upper end of the second parallel pn structure of the breakdown voltage structure portion 120 are uniform.
[0034]
In the case of this example, the number of times of epitaxial layer growth and the number of ion implantations when forming the parallel pn structure can be reduced as compared with the case of Examples 1 and 2, and the cost can be reduced. Of course, a sufficiently low on-resistance can be obtained with the same breakdown voltage class as compared with the conventional MOSFET. Even in this example, similarly to the second embodiment, even if the repetition pitch of the second parallel pn structure of the breakdown voltage structure portion 120 is made smaller than the repetition pitch of the first parallel pn structure of the drift portion 22, the same applies. The effect of can be obtained.
[0035]
[Example 4]
6A to 6G are process cross-sectional views illustrating the manufacturing method according to the first embodiment of the present invention.
[0036]
First, as shown in FIG.+A first n-type high-resistance epitaxial layer 30a is grown on an n-type low-resistance semiconductor substrate to be the drain layer 11.
[0037]
Next, as shown in FIG. 6B, phosphorus ions 31 that become n-type impurities are implanted by ion implantation, and phosphorus atoms 32 are introduced below the surface of the epitaxial layer 30a.
[0038]
Next, as shown in FIG. 6C, a resist mask 33 is formed on the surface of the epitaxial layer 30a, in which impurity introduction windows 33a having the same pitch are opened in a range to be the drift portion 22 and the breakdown voltage structure portion 120 by photolithography. After the formation, boron ions 34 that become p-type impurities are implanted by an ion implantation method, and boron atoms 35 are selectively introduced below the surface of the epitaxial layer 30a. Note that either the phosphorus ion 31 implantation step or the boron ion 34 implantation step may be performed first. Further, when the epitaxial layer 30a has a high impurity concentration, it is only necessary to selectively introduce boron ions 34 of the reverse conductivity type.
[0039]
Next, after removing the resist mask 33, as shown in FIG. 6D, a second n-type high-resistance epitaxial layer 30b is grown on the first epitaxial layer 30a. A similar impurity introduction step is performed, and a third n-type high resistance epitaxial layer 30c is further grown. Note that the epitaxial layer growth step and the impurity introduction step are alternately repeated according to the required breakdown voltage class. Thereafter, the region to be the drift portion 22 is covered with a resist mask 36 having a window opened, and phosphorus ions 31 to be n-type impurities are implanted by an ion implantation method, and below the surface to be the drift portion 22 of the epitaxial layer 30c. A phosphorus atom 32 is introduced.
[0040]
Next, as shown in FIG. 6E, after forming the resist mask 33 in which the impurity introduction windows 33a having the same pitch are opened in the range to be the drift portion 22 by photolithography, after the resist mask 36, ion implantation is performed. Then, boron ions 34 that become p-type impurities are implanted, and boron atoms 35 are selectively introduced below the surface of the epitaxial layer 30c.
[0041]
Next, after removing the resist mask 36 and the resist mask 33, as shown in FIG. 6F, a fourth n-type high resistance epitaxial layer 30d is grown.
[0042]
Thereafter, as shown in FIG. 6G, the diffusion unit region diffused from each diffusion center by simultaneously thermally diffusing the phosphorus element 32 and the boron element 35 introduced into the epitaxial layers 30a to 30d by heat treatment. Are connected to each other so that the n-type drift circuit region 22a and the p-type partition region 22b in the drift portion 22 and the n-type region 120a and the p-type region 120b of the breakdown voltage structure portion 120 are formed simultaneously. Since these vertical regions are formed by interconnecting diffusion unit regions, if thermal diffusion is sufficient, the pn junction can be observed as a substantially flat surface, but exhibits a concentration distribution with the diffusion center as the maximum concentration portion. Yes. Note that the pn junction of the parallel pn structure does not need to be a flat surface, and may be concave.
[0043]
Since the resist mask 36 is covered in the region to be the breakdown voltage structure portion 120 of the third epitaxial layer 30c, no impurity is introduced, and the portion corresponding to the breakdown voltage structure portion 120 of the fourth epitaxial layer 30d is formed. The n-type high resistance layer 122 remains. Thereafter, the p base region 13a and the p-type rings 124a to 124e are simultaneously formed in the fourth epitaxial layer 30c or the epitaxial layer grown thereon by a normal process to complete a double diffusion MOSFET.
[0044]
As described above, the impurities prepared in the epitaxial layers 30 a to 30 d can be finally thermally diffused and associated to form a parallel pn structure. However, the epitaxial layer 30 c of the breakdown voltage structure 120 is covered with the resist mask 36. Therefore, since the introduction of impurity ions is blocked, the length of the parallel pn structure of the breakdown voltage structure 120 can be made shorter than that of the drift portion 22, and the p-type rings 124a to 124e are formed in the epitaxial layer 30c. Can be formed simultaneously with the p base region 13a. Compared with the case where the parallel pn structure of the drift part 22 and the pressure | voltage resistant structure part 120 is the same length, it does not invite a special process addition and can achieve cost reduction.
[0045]
In order to obtain a structure in which the repetition pitch of the second parallel pn structure of the breakdown voltage structure 220 is narrower than the repetition pitch of the first parallel pn structure of the vertical drift section 22 as in the second embodiment, FIG. In the resist mask 33 shown in (c), the pitch and window width of the impurity introduction window 33c in the range to be the breakdown voltage structure portion 220 are narrower than the pitch and window width of the impurity introduction window in the range to be the drift portion 22. To do.
[0046]
[Example 5]
7A to 7G are process cross-sectional views illustrating another manufacturing method according to the first embodiment of the present invention.
[0047]
This example is the same as Example 4 until the steps (a) to (c) are repeated. Next, after removing the resist mask 33, as shown in FIG. 7D, a second n-type high-resistance epitaxial layer 30b is grown on the first epitaxial layer 30a. A similar impurity introduction step is performed, and a third n-type high resistance epitaxial layer 30c is further grown. Note that the epitaxial layer growth step and the impurity introduction step are alternately repeated according to the required breakdown voltage class. Thereafter, phosphorus ions 31 that are n-type impurities are implanted entirely by ion implantation to introduce phosphorus atoms 32 under the surface of the epitaxial layer 30c.
[0048]
Next, as shown in FIG. 7 (e), the pitch and window width of the impurity introduction windows 33 c in the range to be the breakdown voltage structure portion 120 than the pitch and window width of the impurity introduction windows 33 b in the range to be the drift portion 22. After forming a resist mask 33 'having a narrow width by photolithography, boron ions 34 as p-type impurities are implanted by ion implantation, and boron atoms 35 are selectively introduced below the surface of the epitaxial layer 30c.
[0049]
Next, after removing the resist mask 33 ', a fourth n-type high resistance epitaxial layer 30d is grown as shown in FIG.
[0050]
Thereafter, as shown in FIG. 7G, the diffusion unit region diffused from each diffusion center by simultaneously thermally diffusing the phosphorus element 32 and the boron element 35 introduced into the epitaxial layers 30a to 30d by heat treatment. Are connected to each other so that the n-type drift electric circuit region 22a and the p-type partition region 22b in the drift portion 22 and the n-type region 120a and the p-type region 120b of the breakdown voltage structure portion 120 are formed simultaneously. Since these vertical regions are formed by interconnecting diffusion unit regions, if thermal diffusion is sufficient, the pn junction can be observed as a substantially flat surface, but exhibits a concentration distribution with the diffusion center as the maximum concentration portion. Yes. Note that the pn junction of the parallel pn structure does not need to be a flat surface, and may be concave.
[0051]
A resist mask 36 having a pitch and window width narrower than the pitch and window width of the impurity introduction windows 33b in the range to be the drift portion 22 is formed in the region to be the breakdown voltage structure portion 120 of the third epitaxial layer 30c. In the thermal diffusion process, since the introduced boron atoms 35 in the narrow and limited region are mixed with the diffusion of the phosphorus element 32 by the diffusion, the breakdown voltage structure of the fourth epitaxial layer 30d is covered. A p-type region is not formed in a portion corresponding to the portion 120, and a substantially uniform n-type high resistance layer 122 is formed. Therefore, it is not necessary to interpose the film formation and removal process of the dedicated resist mask 36 for preventing the introduction of phosphorus ions 31 as shown in FIG. Thus, the cost of the semiconductor device can be reduced.
[0052]
Thereafter, the p base region 13a and the p-type rings 124a to 124e are simultaneously formed in the fourth epitaxial layer 30c or the epitaxial layer grown thereon by a normal process to complete a double diffusion type MOSFET. To do.
[0053]
[Example 6]
8A to 8E are process cross-sectional views illustrating the manufacturing method of Example 3 of the present invention.
[0054]
This example is the same as Example 4 until the steps (a) to (c) are repeated. Note that the epitaxial layer growth step and the impurity introduction step are alternately repeated according to the required breakdown voltage class. Next, after removing the resist mask 33, as shown in FIG. 7D, a second n-type high resistance epitaxial layer 30b is grown on the first epitaxial layer 30a.
[0055]
  After that, FIG.(E)As shown in FIG. 4, the phosphorus element 32 and the boron element 35 introduced and introduced into the epitaxial layers 30a to 30d by heat treatment are simultaneously thermally diffused so that the diffusion unit regions diffusing from the respective diffusion centers are connected to each other vertically and drift The n-type drift electric circuit region 22a and the p-type partition region 22b in the portion 222 and the n-type region 120a and the p-type region 120b of the breakdown voltage structure 120 are formed simultaneously. Since these vertical regions are formed by interconnecting diffusion unit regions, if thermal diffusion is sufficient, the pn junction can be observed as a substantially flat surface, but exhibits a concentration distribution with the diffusion center as the maximum concentration portion. Yes. Note that the pn junction of the parallel pn structure does not need to be a flat surface, and may be concave. Thereafter, the p base region 13a and the p-type rings 124a to 124e are simultaneously formed by a normal process to complete a double diffusion MOSFET.In the case of this example, the number of epitaxial layer growths and the number of ion implantations when forming the parallel pn structure can be reduced, and the cost can be reduced.
[0056]
  As described above, in the present invention, the breakdown voltage structure portion has a parallel pn structure.FirstHigh resistance layer of the first conductivity type connected to the main surface sideThe length of the parallel pn structure of the breakdown voltage structure portion is shorter than the length of the parallel pn structure of the drift portion.It is characterized by that. The surface electric field can be relaxed as compared with the parallel pn structure without the first conductive type high resistance layer. Further, it is characterized in that it has a second conductivity type ring formed on the main surface side of the high resistance layer without being connected to the vertical second conductivity type region around the element active portion. Since the second conductivity type ring is not connected to the vertical second conductivity type region of the breakdown voltage structure portion, in the off state, the second conductivity type regardless of the width of the vertical second conductivity type region in the breakdown voltage structure portion. Since a voltage drop corresponding to the distance from the element active portion or the drift portion appears in the ring of the mold, the surface electric field of the breakdown voltage structure portion is relaxed.
[0057]
In a structure in which a plurality of rings of the second conductivity type are formed at intervals, the surface electric field of the breakdown voltage structure portion can be relaxed without increasing the ring interval, so the area occupied by the breakdown voltage structure portion can be reduced and high integration can be achieved. Can be achieved.
[0058]
Further, in the manufacturing method of the present invention, since the epitaxial layer of the breakdown voltage structure portion is covered with the mask in the second stage, the introduction of impurity ions is prevented, so the length of the parallel pn structure of the breakdown voltage structure portion Can be made shorter than that of the drift portion, and a second conductivity type ring can be formed in the first conductivity type high resistance epitaxial layer formed on the parallel pn structure of the breakdown voltage structure portion. Compared to the case where the parallel pn structure of the drift portion and the breakdown voltage structure portion have the same length, it is not necessary to add a special process.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing a chip of a vertical MOSFET element according to Embodiment 1 of the present invention.
FIG. 2 is a longitudinal sectional view showing a state cut along line AA ′ in FIG. 1;
FIG. 3 is a longitudinal sectional view showing a state cut along line BB ′ in FIG. 1;
FIG. 4 is a partial longitudinal sectional view showing a vertical MOSFET according to a second embodiment of the invention.
FIG. 5 is a partial longitudinal sectional view showing a vertical MOSFET according to a third embodiment of the invention.
6A to 6G are process cross-sectional views illustrating the manufacturing method of Example 1 of the present invention.
FIGS. 7A to 7G are process cross-sectional views illustrating another manufacturing method according to the first embodiment of the present invention. FIGS.
FIGS. 8A to 8E are process cross-sectional views illustrating a manufacturing method according to Example 3 of the present invention. FIGS.
FIG. 9 is a plan view showing a drift portion and an element outer peripheral portion (withstand voltage structure portion) in a vertical MOSFET.
10 is a longitudinal sectional view showing a state cut along the line AA ′ in FIG. 9;
11 is a longitudinal sectional view showing a state cut along the line BB ′ in FIG. 9;
[Explanation of symbols]
11 ... n+Drain layer (contact layer)
12e ... p-base region
13a ... p base region (p well)
14 ... n+Source area
15 ... Gate insulating film
16 ... Gate electrode layer
17 ... Source electrode
18 ... Drain electrode
19a ... Interlayer insulating film
22, 222 ... Drain / drift section
22a ... Layered vertical n-type drift circuit region
22b ... Layered vertical p-type partition region
23 ... Oxide film (insulating film)
26 ... p+Contact area
30a-30e ... n-type high resistance epitaxial layer
31 ... Phosphorus ion
32 ... Phosphorus atom
33a-33c ... Impurity introduction window
33, 33 ′, 36... Resist mask
34 ... Boron ion
35 ... Boron atom
120, 220 ... withstand pressure structure
120a, 220a ... Layered vertical n-type region
120b, 220b ... Layered vertical p-type region
122... N-type high resistance layer
124a-124e ... p-type ring
126 ... n-type side edge region
128 ... n+Channel stopper area

Claims (10)

基板の第１主面側に形成された素子活性部に導電接続する第１の電極層と、前記基板の第２主面側に形成された第１導電型の低抵抗層に導電接続する第２の電極層と、前記素子活性部と前記低抵抗層との間に介在し、オン状態ではドリフト電流を縦方向に流すと共にオフ状態では空乏化する縦形ドリフト部と、前記縦形ドリフト部の周りで前記第１主面と前記低抵抗層との間に介在し、オフ状態では空乏化する耐圧構造部とを有し、前記縦形ドリフト部及び前記耐圧構造部が前記基板の厚み方向に配向する縦形第１導電型領域と前記基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る並列ｐｎ構造を有する半導体装置において、
前記耐圧構造部は、前記並列ｐｎ構造の前記第１主面側に接続する第１導電型の高抵抗層を有し、前記耐圧構造部の並列ｐｎ構造の長さが前記ドリフト部の並列ｐｎ構造の長さよりも短いことを特徴する半導体装置。A first electrode layer that is conductively connected to the element active portion formed on the first main surface side of the substrate, and a first conductive layer that is conductively connected to the low resistance layer of the first conductivity type formed on the second main surface side of the substrate. and second electrode layers, wherein said element active portion interposed between the low-resistance layer, and the vertical drift region deplete in the off state with flow drift current in the vertical direction in the on state, around the vertical drift region in interposed between the low-resistance layer and the first major surface, and a pressure-resistant structure portion for depletion in the off state, the orientation wherein the vertical drift region and the breakdown withstanding section in the thickness direction of the substrate In a semiconductor device having a parallel pn structure in which vertical first conductive type regions and vertical second conductive type regions oriented in the thickness direction of the substrate are alternately and repeatedly joined,
The pressure-resistant structure can have a high resistance layer of a first conductivity type connected to said first main surface side of the parallel pn structure, parallel pn length of the parallel pn structure of the withstand voltage structure is the drift region A semiconductor device characterized by being shorter than the length of the structure . 請求項１において、前記高抵抗層が第１導電型と第２導電型の不純物の双方をドープして形成されていることを特徴する半導体装置。  2. The semiconductor device according to claim 1, wherein the high resistance layer is formed by doping both impurities of a first conductivity type and a second conductivity type. 請求項１において、前記素子活性部の周りで前記縦形第２導電型領域に非接続で前記高抵抗層の主面側に形成された第２導電型のリングとを有することを特徴する半導体装置。  2. The semiconductor device according to claim 1, further comprising a second conductivity type ring formed on the main surface side of the high resistance layer so as not to be connected to the vertical second conductivity type region around the element active portion. . 請求項３において、前記第２導電型のリングが間隔をおいて複数形成されていることを特徴とする半導体装置。  4. The semiconductor device according to claim 3, wherein a plurality of the second conductivity type rings are formed at intervals. 請求項１乃至請求項４のいずれか一項において、前記耐圧構造部の並列ｐｎ構造の長さは前記ドリフト部の並列ｐｎ構造の長さよりも前記第１主面側において短いことを特徴とする半導体装置。In any one of claims 1 to 4, the length of the parallel pn structure of the pressure-resistant structure is characterized by a short in the first main surface side than the length of the parallel pn structure of the drift region Semiconductor device. 請求項１乃至請求項５のいずれか一項において、前記耐圧構造部の並列ｐｎ構造のｐｎ繰り返しピッチは前記縦形ドリフト部の並列ｐｎ構造のｐｎ繰り返しピッチよりも狭いことを特徴とする半導体装置。  6. The semiconductor device according to claim 1, wherein a pn repetition pitch of the parallel pn structure of the breakdown voltage structure portion is narrower than a pn repetition pitch of the parallel pn structure of the vertical drift portion. 請求項１乃至請求項６のいずれか一項において、前記耐圧構造部の周囲に形成された第１導電型のチャネルストッパー領域を有することを特徴とする半導体装置。  7. The semiconductor device according to claim 1, further comprising a first conductivity type channel stopper region formed around the breakdown voltage structure portion. 請求項７において、前記チャネルストッパー領域は第１導電型の側縁領域を介して前記低抵抗層に接続していることを特徴とする半導体装置。  8. The semiconductor device according to claim 7, wherein the channel stopper region is connected to the low resistance layer through a side edge region of a first conductivity type. 基板の第１主面側に形成された素子活性部に導電接続する第１の電極層と、前記基板の第２主面側に形成された第１導電型の低抵抗層に導電接続する第２の電極層と、前記素子活性部と前記低抵抗層との間に介在し、オン状態ではドリフト電流を縦方向に流すと共にオフ状態では空乏化する縦形ドリフト部と、前記縦形ドリフト部の周りで前記第１主面と前記低抵抗層との間に介在し、オフ状態では空乏化する耐圧構造部とを有し、前記縦形ドリフト部及び前記耐圧構造部が前記基板の厚み方向に配向する縦形第１導電型領域と前記基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る並列ｐｎ構造を有し、前記耐圧構造部は前記並列ｐｎ構造の主面側に接続する第１導電型の高抵抗層と前記素子活性部の周りで前記縦形第２導電型領域に非接続で前記高抵抗層の主面側に形成された第２導電型のリングとを有する半導体装置の製造方法であって、
第１導電型の低抵抗基体上の前記縦形ドリフト部及び前記耐圧構造部を形成すべき領域において、第１導電型高抵抗のエピタキシャル層を成長させた後、そのエピタキシャル層に離散的に配置した不純物導入窓を介して第２の導電型の不純物イオンを選択的に導入する工程を繰り返す第１の段階と、次いで、新たに第１導電型高抵抗のエピタキシャル層を成長させた後、前記耐圧構造部を形成すべき領域をマスクした状態で、前記縦形ドリフト部を形成すべき領域において第２の導電型の不純物イオンを離散的に配置した不純物導入窓を介して選択的に導入する工程を少なくとも１回行う第２の段階と、しかる後、熱処理を施して前記各エピタキシャル層に選択的に導入した前記不純物を熱拡散させて層違いの熱拡散領域同士を上下相互に接続し、前記並列ｐｎ構造を形成する第３の段階と、を有することを特徴とする半導体装置の製造方法。A first electrode layer that is conductively connected to the element active portion formed on the first main surface side of the substrate, and a first conductive layer that is conductively connected to the low resistance layer of the first conductivity type formed on the second main surface side of the substrate. A vertical drift portion interposed between the electrode active layer 2, the element active portion and the low resistance layer, which flows a drift current in the vertical direction in the on state and is depleted in the off state, and around the vertical drift portion in interposed between the low-resistance layer and the first major surface, and a pressure-resistant structure portion for depletion in the off state, the orientation wherein the vertical drift region and the breakdown withstanding section in the thickness direction of the substrate A vertical pn structure in which vertical first conductivity type regions and vertical second conductivity type regions oriented in the thickness direction of the substrate are alternately and repeatedly joined, and the breakdown voltage structure portion is a main part of the parallel pn structure. Around the first active type high resistance layer connected to the surface side and the element active portion Serial A method of manufacturing a semiconductor device having a second conductivity type of the ring formed on a main surface of the high resistance layer in a non-connected to the vertical second conductivity type region,
In the region where the vertical drift portion and the breakdown voltage structure portion on the first conductivity type low resistance substrate are to be formed, the first conductivity type high resistance epitaxial layer is grown and then discretely disposed on the epitaxial layer. First step of repeating the step of selectively introducing impurity ions of the second conductivity type through the impurity introduction window, and then newly growing a first conductivity type high resistance epitaxial layer, A step of selectively introducing impurity ions of the second conductivity type through impurity introduction windows discretely arranged in the region where the vertical drift portion is to be formed in a state where the region where the structure portion is to be formed is masked; The second stage performed at least once, and then thermally treated to diffuse the impurities selectively introduced into the respective epitaxial layers by heat treatment, so that the heat diffusion regions of different layers are in contact with each other vertically. And, a method of manufacturing a semiconductor device characterized by having a third step of forming the parallel pn structure. 基板の第１主面側に形成された素子活性部に導電接続する第１の電極層と、前記基板の第２主面側に形成された第１導電型の低抵抗層に導電接続する第２の電極層と、前記素子活性部と前記低抵抗層との間に介在し、オン状態ではドリフト電流を縦方向に流すと共にオフ状態では空乏化する縦形ドリフト部と、前記縦形ドリフト部の周りで前記第１主面と前記低抵抗層との間に介在し、オフ状態では空乏化する耐圧構造部とを有し、前記縦形ドリフト部及び前記耐圧構造部が前記基板の厚み方向に配向する縦形第１導電型領域と前記基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る並列ｐｎ構造を有し、前記耐圧構造部は前記並列ｐｎ構造の主面側に接続する第１導電型の高抵抗層と前記素子活性部の周りで前記縦形第２導電型領域に非接続で前記高抵抗層の主面側に形成された第２導電型のリングとを有する半導体装置の製造方法であって、
第１導電型の低抵抗基体上の前記縦形ドリフト部及び前記耐圧構造部を形成すべき領域において、第１導電型高抵抗のエピタキシャル層を成長させた後、そのエピタキシャル層に離散的に配置した不純物導入窓を介して第２の導電型の不純物イオンを選択的に導入する工程を繰り返す第１の段階と、次いで、新たに第１導電型高抵抗のエピタキシャル層を成長させた後、全面に第１の導電型の不純物イオンを導入してから、前記耐圧構造部を形成すべき領域での不純物導入窓のピッチと窓幅が前記縦形ドリフト部を形成すべき領域でのピッチと窓幅よりも狭いマスクを形成して第２の導電型の不純物イオンを選択的に導入する工程を少なくとも１回行う第２の段階と、しかる後、熱処理を施して前記各エピタキシャル層に選択的に導入した前記不純物を熱拡散させて層違いの熱拡散領域同士を上下相互に接続し、前記並列ｐｎ構造を形成する第３の段階と、を有することを特徴とする半導体装置の製造方法。A first electrode layer that is conductively connected to the element active portion formed on the first main surface side of the substrate, and a first conductive layer that is conductively connected to the low resistance layer of the first conductivity type formed on the second main surface side of the substrate. A vertical drift portion interposed between the electrode active layer 2, the element active portion and the low resistance layer, which flows a drift current in the vertical direction in the on state and is depleted in the off state, and around the vertical drift portion in interposed between the low-resistance layer and the first major surface, and a pressure-resistant structure portion for depletion in the off state, the orientation wherein the vertical drift region and the breakdown withstanding section in the thickness direction of the substrate A vertical pn structure in which vertical first conductivity type regions and vertical second conductivity type regions oriented in the thickness direction of the substrate are alternately and repeatedly joined, and the breakdown voltage structure portion is a main part of the parallel pn structure. Around the first active type high resistance layer connected to the surface side and the element active portion Serial A method of manufacturing a semiconductor device having a second conductivity type of the ring formed on a main surface of the high resistance layer in a non-connected to the vertical second conductivity type region,
In the region where the vertical drift portion and the breakdown voltage structure portion on the first conductivity type low resistance substrate are to be formed, the first conductivity type high resistance epitaxial layer is grown and then discretely disposed on the epitaxial layer. A first step of repeating the step of selectively introducing impurity ions of the second conductivity type through the impurity introduction window, and then a new first conductivity type high resistance epitaxial layer is grown and then applied to the entire surface. After introducing the impurity ions of the first conductivity type, the pitch and window width of the impurity introduction window in the region where the breakdown voltage structure portion is to be formed are larger than the pitch and window width in the region where the vertical drift portion is to be formed. A second step of forming a narrow mask and selectively introducing impurity ions of the second conductivity type at least once, and then performing heat treatment to selectively introduce each of the epitaxial layers. in front The method of manufacturing a semiconductor device which impurities are thermally diffused to connect the heat diffusion region between layers difference vertically mutually and having a third step of forming the parallel pn structure.
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