JP4882212B2

JP4882212B2 - Vertical semiconductor device

Info

Publication number: JP4882212B2
Application number: JP2004238080A
Authority: JP
Inventors: 庄一山内; 仁山口; 隆司鈴木; 京子中島
Original assignee: Denso Corp; Toyota Central R&D Labs Inc
Current assignee: Denso Corp; Toyota Central R&D Labs Inc
Priority date: 2003-08-20
Filing date: 2004-08-18
Publication date: 2012-02-22
Anticipated expiration: 2024-08-18
Also published as: JP2005101560A

Description

本発明は、高耐圧な縦型半導体装置に関するものであり、例えばＭＯＳに好適である。 The present invention relates to a vertical semiconductor device having a high withstand voltage, and is suitable for a MOS, for example.

従来の縦型ＭＯＳ電界効果トランジスタ等（以下、縦型ＭＯＳＦＥＴという）の構造を図１１に示す（特許文献１参照）。この構造においては、Ｎ型半導体領域２とＰ型半導体領域３とが、基板深さ方向に対して一定の深さを有するトレンチ状に存在し、これらが半導体基板１上に交互に並んで配置されている。これは「スーパージャンクション構造」として知られるコラム構造であり、半導体基板１上にこのコラム構造を有するコラム領域４を形成し、このコラム領域４上に、ソース領域７とゲート領域１１とボディ領域６からなるアクティブ領域１３を形成することによって、高耐圧かつ低オン抵抗を実現する素子構造とされている。 The structure of a conventional vertical MOS field effect transistor or the like (hereinafter referred to as a vertical MOSFET) is shown in FIG. 11 (see Patent Document 1). In this structure, the N-type semiconductor region 2 and the P-type semiconductor region 3 exist in a trench shape having a constant depth in the substrate depth direction, and these are arranged alternately on the semiconductor substrate 1. Has been. This is a column structure known as a “super junction structure”. A column region 4 having this column structure is formed on a semiconductor substrate 1, and a source region 7, a gate region 11, and a body region 6 are formed on the column region 4. By forming the active region 13 made of the above, an element structure that achieves a high breakdown voltage and a low on-resistance is obtained.

このコラム領域の外周部分１４１においては、Ｎ型半導体領域（以下、Ｎ型コラム領域２とする）とＰ型半導体領域（以下、Ｐ型コラム領域３とする）との接合耐圧を高めることが重要である。従って、特許文献１においては、Ｎ型コラム領域２とＰ型コラム領域３とが半導体基板１上に交互に並ぶ断面構造において、アクティブ領域１３の最外周部分からコラム領域４の終端１６までの距離が、コラム構造４の深さと同等以上に設定されている。
特開２００２−１８４９８５号公報 In the outer peripheral portion 141 of this column region, it is important to increase the junction breakdown voltage between the N-type semiconductor region (hereinafter referred to as N-type column region 2) and the P-type semiconductor region (hereinafter referred to as P-type column region 3). It is. Therefore, in Patent Document 1, in the cross-sectional structure in which the N-type column region 2 and the P-type column region 3 are alternately arranged on the semiconductor substrate 1, the distance from the outermost peripheral portion of the active region 13 to the end 16 of the column region 4 However, it is set to be equal to or greater than the depth of the column structure 4.
JP 2002-184985 A

図２は、Ｎ型コラム領域２とＰ型コラム領域３とが半導体基板上に交互に並んで構成されたコラム領域４のレイアウト図である。 FIG. 2 is a layout diagram of a column region 4 in which N-type column regions 2 and P-type column regions 3 are alternately arranged on a semiconductor substrate.

この図に示したように、Ｐ型コラム領域３は複数本が短冊状に並べられて構成され、それぞれが多角形とされている。ここでいう短冊状の多角形は対向する一組の長辺を有すると共に、その長辺の両端に位置する短辺を有して構成された形状のものをいう。従って例えば四角形の場合、２組の向かい合う辺のうち一組を引き延ばした形状となり、引き延ばした辺が長辺、他の辺が短辺となる。多角形が六角形の場合は一組の向かい合う辺を引き延ばした形状となり、引き延ばした一組の辺が長辺、他の対向する２組の辺が短辺となる。なお、アクティブ領域１３の位置関係を明確にするために、本図中に一点鎖線にしてアクティブ領域１３を示してある。 As shown in this figure, the P-type column region 3 is formed by arranging a plurality of strips in a strip shape, each of which is a polygon. Here, the strip-shaped polygon has a pair of long sides opposed to each other and has a short side located at both ends of the long side. Therefore, for example, in the case of a quadrangle, one of the two pairs of opposing sides is extended, and the extended side is a long side and the other side is a short side. When the polygon is a hexagon, a pair of opposite sides is extended, and the extended pair of sides is a long side, and the other two opposite sides are short sides. In addition, in order to clarify the positional relationship of the active region 13, the active region 13 is shown as a one-dot chain line in the figure.

従来は、図２に示すようなＮ型コラム領域２とＰ型コラム領域３とが半導体基板上に交互に短冊状に並ぶ構造において、Ｐ型コラム領域の長辺に対向する領域のＡ−Ａ'断面構造に相当する構造が知られている。 Conventionally, in a structure in which N-type column regions 2 and P-type column regions 3 are alternately arranged in a strip shape on a semiconductor substrate as shown in FIG. 2, AA of a region facing the long side of the P-type column region. 'A structure corresponding to a cross-sectional structure is known.

しかしながら、前述のＰ型コラム領域３の短辺に対向する領域の構造、図２に示すＢ−Ｂ'断面構造に相当する構造については、これまで有効な構造が明らかにされていなかった。基板表面においては、アクティブ領域１３の最外周部分からコラム領域４の終端部分までの距離は、長くされるほど耐圧に有利なことは自明であるが、半導体装置は一般に微細化が要求され、小型の素子で高耐圧、低オン抵抗を満足できる条件が切望されていた。 However, an effective structure has not been clarified so far for the structure of the region facing the short side of the P-type column region 3 and the structure corresponding to the BB ′ cross-sectional structure shown in FIG. On the substrate surface, it is obvious that the longer the distance from the outermost peripheral portion of the active region 13 to the end portion of the column region 4 is, the more advantageous the breakdown voltage is. The conditions that can satisfy the high withstand voltage and the low on-resistance with these elements have been desired.

本発明は上記点に鑑み、Ｎ型コラム領域とＰ型コラム領域とが半導体基板上に交互に並ぶ高耐圧半導体装置において、小型で且つ充分な耐圧とオン抵抗特性を達成できる構造を提供することを目的とする。 SUMMARY OF THE INVENTION In view of the above, the present invention provides a structure capable of achieving a small size and sufficient breakdown voltage and on-resistance characteristics in a high breakdown voltage semiconductor device in which N-type column regions and P-type column regions are alternately arranged on a semiconductor substrate. With the goal.

上記目的を達成するため、本発明者が、ボディコンタクト領域の終端で決まるアクティブ領域１３の終端１７と、コラム領域４におけるＰ型コラム領域３の短辺側の終端１６との距離を終端領域長Ｌとして検討したところ、この終端領域長Ｌは、完全空乏化時に前記コラム領域の基板深さ方向に広がる空乏層の深さと同等の距離になるよう離間しなければならないという知見を得た。 In order to achieve the above object, the present inventor determines the distance between the termination 17 of the active region 13 determined by the termination of the body contact region and the termination 16 on the short side of the P-type column region 3 in the column region 4 as the termination region length. As a result of studying as L, it was found that the termination region length L must be separated so as to have a distance equivalent to the depth of the depletion layer extending in the substrate depth direction of the column region at the time of complete depletion.

この知見の概略を簡単な図によって説明する。図３はコラム領域４、即ちＮ型コラム領域２とＰ型コラム領域３が交互に配列される構造の断面の一部を示している。この図に示すように、コラム領域４を完全空乏化させるために、Ｎ型コラム領域２とＰ型コラム領域３からなる領域は、基板面に水平な方向においては各々のコラム領域幅（Ｗ_N、Ｗ_P）の１／２ずつが互いに空乏化し、基板面に垂直な方向においてはコラム領域の深さ（ｄ）が空乏化するように設計されている。半導体素子の耐圧をコラム構造で設定するためには、基板面に水平な方向に延びる空乏層幅も、基板面に垂直な方向に延びる空乏層幅と同等にする必要がある。このため、ボディコンタクト領域８の終端で定義されるアクティブ領域１３の終端１７からコラム領域４の終端１６までの距離を以下のように設定しなければならない。 The outline of this knowledge will be explained with a simple diagram. FIG. 3 shows a part of a cross section of a structure in which the column regions 4, that is, the N-type column regions 2 and the P-type column regions 3 are alternately arranged. As shown in this figure, in order to completely deplete the column region 4, the region composed of the N-type column region 2 and the P-type column region 3 has a column region width (W _{N) in the} direction horizontal to the substrate surface. , W _P ) are depleted each other, and the depth (d) of the column region is depleted in the direction perpendicular to the substrate surface. In order to set the breakdown voltage of the semiconductor element with a column structure, the width of the depletion layer extending in the direction horizontal to the substrate surface needs to be equal to the width of the depletion layer extending in the direction perpendicular to the substrate surface. For this reason, the distance from the end 17 of the active region 13 defined at the end of the body contact region 8 to the end 16 of the column region 4 must be set as follows.

コラム構造を有する半導体素子の斜視断面図を示す図４を使って説明する。耐圧時において、基板と水平な方向にアクティブ領域１３の終端から広がる空乏層の最外周部、即ち空乏層の終端部は、前述のようにコラム領域終端１６よりもＮ型コラム領域幅（Ｗ_N）の１／２の長さだけ外側に位置する。従って、アクティブ領域終端部１７からコラム領域の深さ（ｄ）に相当する距離よりもＮ型コラム領域幅（Ｗ_N）の１／２の長さ分だけ短い距離離間した位置にコラム領域終端部１６を配置すれば、Ｐ型コラム領域３の短辺に対向する領域に広がる空乏層は、基板面に垂直な方向に延びる空乏層と同等に広がるため、空乏層内部の特定部位に電界集中が発生することはない。 A description will be given with reference to FIG. 4 showing a perspective sectional view of a semiconductor element having a column structure. At the time of withstand voltage, the outermost peripheral portion of the depletion layer extending from the end of the active region 13 in the direction parallel to the substrate, that is, the end portion of the depletion layer, as described above, is wider than the N-type column region width (W _N ) Is located outside by a length of 1/2. Accordingly, the column region end portion is located at a position that is separated from the active region end portion 17 by a distance shorter than the distance corresponding to the depth (d) of the column region by a half of the N-type column region width (W _N ). 16 is disposed, the depletion layer extending in the region facing the short side of the P-type column region 3 extends in the same manner as the depletion layer extending in the direction perpendicular to the substrate surface. It does not occur.

そこで、アクティブ領域の短辺に対向するアクティブ領域の終端１７から、コラム領域の短辺に対向するコラム領域終端１６に存在するＰ／Ｎ接合部分までの距離を終端領域長Ｌと定義すると、数式１を満たせば、設計値よりも耐圧の低い部分が存在せず、充分な耐圧とオン抵抗特性を達成できる縦型半導体装置を最小寸法で設計・製造することが可能となる。 Therefore, if the distance from the end 17 of the active region facing the short side of the active region to the P / N junction existing at the column region end 16 facing the short side of the column region is defined as the termination region length L, If 1 is satisfied, there is no portion whose breakdown voltage is lower than the design value, and a vertical semiconductor device capable of achieving sufficient breakdown voltage and on-resistance characteristics can be designed and manufactured with the minimum dimensions.

（数１）
Ｌ＋Ｗ_N／２≧ｄ
Ｌ：終端領域長
Ｗ_N:Ｎ型コラム領域幅
ｄ：コラム構造深さ
そこで、請求項１ないし３に記載の発明では、コラム領域（４）を有する縦型半導体装置において、アクティブ領域の終端（１７）となるボディコンタクト領域（８）の終端と、コラム領域終端（１６）までの距離を終端領域長Ｌ、第１半導体領域幅をＷ₁、コラム領域深さをｄと定義して、Ｌ≧ｄ−Ｗ₁／２の式を満たすように構成されたことを特徴としている。 (Equation 1)
L + W _N / 2 ≧ d
L: termination region length W _N: N-type column region width d: column structure depth Therefore, in the invention according to any one of claims 1 to 3, in the vertical semiconductor device having the column region (4), the termination of the active region ( 17), the distance from the end of the body contact region (8) to the end of the column region (16) is defined as the termination region length L, the first semiconductor region width as W ₁ , and the column region depth as d. It is characterized by being configured to satisfy the formula of ≧ d−W _1/2 .

このように構成することにより、コラム領域（４）の内部から、コラム領域終端（１６）に向けて広がる空乏層の幅を、コラム領域の内部から基板深さ方向に広がる空乏層の幅と同等に広げることが可能となり、コラム構造の短辺に対向する領域中の特定部位での電界集中を回避できるため、縦型ＭＯＳＦＥＴの耐圧向上が可能となる。 With this configuration, the width of the depletion layer extending from the inside of the column region (4) toward the column region end (16) is equal to the width of the depletion layer extending from the inside of the column region in the substrate depth direction. Since it is possible to avoid electric field concentration at a specific portion in the region facing the short side of the column structure, the breakdown voltage of the vertical MOSFET can be improved.

請求項４または５に記載の発明では、第１導電型のＳｉ（１１０）基板上に形成され、第２導電型の半導体領域（３）の外形（枠）を構成する面が少なくとも１組のＳｉ（１１１）面を含む縦型半導体装置において、アクティブ領域終端１７となるボディコンタクト領域（８）の終端からコラム領域（４）における第２半導体領域（３）の短辺側の終端領域（１６）までの距離を終端領域長Ｌ、第１半導体領域幅をＷ₁、コラム構造深さをｄと定義して、Ｌ≧（ｄ−Ｗ₁／２）／sin35.27の式を満たすように構成されたことを特徴としている。 In the invention according to claim 4 or 5, at least one set of surfaces constituting the outer shape (frame) of the second conductivity type semiconductor region (3) formed on the first conductivity type Si (110) substrate. In the vertical semiconductor device including the Si (111) plane, the termination region (16) on the short side of the second semiconductor region (3) in the column region (4) from the termination of the body contact region (8) serving as the active region termination 17 ) Is defined as the termination region length L, the first semiconductor region width is W ₁ , and the column structure depth is d, so that L ≧ (d−W ₁ /2)/sin35.27 is satisfied. It is characterized by being composed.

また、請求項６に記載の発明では、第１導電型のＳｉ（１１０）基板上に形成され、第２導電型の半導体領域（３）の外形（枠）を構成する面が少なくとも１組のＳｉ（１１１）面を含む縦型半導体装置において、アクティブ領域終端（１７）となるボディコンタクト領域（８）の終端と、コラム領域（４）における第２半導体領域（３）の短辺側の終端（１６）までの距離を終端領域長Ｌ、第１半導体領域幅Ｗ₁、コラム構造深さをｄ、ボディ領域深さをｄ_Bと定義して、Ｌ≧｛（ｄ−Ｗ₁／２）／sin35.27｝＋（ｄ_B／tan35.27）の式を満たすように構成されたことを特徴としている。 According to a sixth aspect of the present invention, at least one set of surfaces forming the outer shape (frame) of the second conductive type semiconductor region (3) is formed on the first conductive type Si (110) substrate. In the vertical semiconductor device including the Si (111) plane, the end of the body contact region (8) serving as the active region termination (17) and the termination of the second semiconductor region (3) on the short side of the column region (4) (16) distance termination region length to L, the first semiconductor region width W _1, the column structure depth d, a body region depth is defined as _{d B, L ≧ {(d} -W 1/2) /Sin35.27}+(d _B /tan35.27).

これら請求項４ないし６に示す構成により、コラム領域（４）の内部から、コラム領域終端（１６）に向けて広がる空乏層を、コラム領域（４）の内部から基板深さ方向に広がる空乏層と同等に広げることが可能となり、コラム構造の短辺に対向する領域中における特定部位での電界集中が回避できるため、縦型ＭＯＳＦＥＴの耐圧向上が可能となる。 According to the structure shown in the fourth to sixth aspects, the depletion layer extending from the inside of the column region (4) toward the end of the column region (16) is depleted from the inside of the column region (4) in the substrate depth direction. Since it is possible to avoid electric field concentration at a specific portion in the region facing the short side of the column structure, the breakdown voltage of the vertical MOSFET can be improved.

なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものである。 In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

（第１実施形態）
図１（ａ）は本発明の第１実施形態における縦型ＭＯＳＦＥＴの断面図であり、図２に示すＰ型コラム領域３の短辺に対向する領域のＢ−Ｂ'断面構造に相当する構造である。なお、本実施形態の理解を容易にするために示した図１の（ｂ）は図２に示すＰ型コラム領域３の長辺に対向する領域のＡ−Ａ'断面構造に相当する構造であり、従来から知られている構造である。 (First embodiment)
FIG. 1A is a cross-sectional view of a vertical MOSFET according to the first embodiment of the present invention, and a structure corresponding to the BB ′ cross-sectional structure of the region facing the short side of the P-type column region 3 shown in FIG. It is. Note that FIG. 1B shown for ease of understanding of the present embodiment is a structure corresponding to the AA ′ cross-sectional structure of the region facing the long side of the P-type column region 3 shown in FIG. There is a conventionally known structure.

これらの図に示される縦型ＭＯＳＦＥＴ構造を説明する。縦型ＭＯＳＦＥＴはＮ⁺型の半導体基板上に形成されており、Ｎ⁺型ドレイン領域１、コラム領域４、Ｎ⁺型ソース領域７、Ｐ型ボディ領域６、Ｐ⁺型ボディコンタクト領域８、トレンチゲート１１、を備えている。 The vertical MOSFET structure shown in these drawings will be described. The vertical MOSFET is formed on an N ⁺ type semiconductor substrate, and includes an N ⁺ type drain region 1, a column region 4, an N ⁺ type source region 7, a P type body region 6, a P ⁺ type body contact region 8, and a trench. A gate 11 is provided.

Ｎ⁺型ドレイン領域１はＮ⁺型の半導体基板により構成され、半導体基板の裏面には、例えば、アルミニウムからなる電極部が取り付けられている。 The N ⁺ -type drain region 1 is composed of an N ⁺ -type semiconductor substrate, and an electrode portion made of, for example, aluminum is attached to the back surface of the semiconductor substrate.

Ｎ⁺型ドレイン領域１上には、コラム領域４が位置している。コラム領域４を構成する
コラム構造は、図１（ｂ）に示されるように、Ｐ型半導体単結晶からなるＰ型コラム領域３とＮ型半導体単結晶からなるＮ型コラム領域２とが交互に並んで構成されるものである。図１（ａ）ではコラム領域４のうち、Ｐ型コラム領域３のみの断面を図示しているが、実際にはコラム領域４には図面奥行き方向に隣接してＮ型シリコン単結晶で形成されるＮ型コラム領域２が存在する。Ｎ型コラム領域２は縦型ＭＯＳＦＥＴのドリフト領域と見なすことができ、ドレイン電流はこのＮ型コラム領域２を流れる。 A column region 4 is located on the N ⁺ -type drain region 1. As shown in FIG. 1B, the column structure constituting the column region 4 is such that a P-type column region 3 made of a P-type semiconductor single crystal and an N-type column region 2 made of an N-type semiconductor single crystal are alternately arranged. They are arranged side by side. FIG. 1A shows a cross section of only the P-type column region 3 in the column region 4, but the column region 4 is actually formed of N-type silicon single crystal adjacent to the depth direction of the drawing. N-type column region 2 exists. The N-type column region 2 can be regarded as a drift region of the vertical MOSFET, and a drain current flows through the N-type column region 2.

コラム領域４の外側には、Ｎ型半導体領域２１が位置している。このＮ型半導体領域２１と図１（ａ）中のＰ型コラム領域３との境界がコラム領域終端１６となる。コラム領域４上、またはコラム領域４及びコラム領域４の外側のＮ型半導体単結晶領域２１上には、Ｐ^-型半導体単結晶領域５が位置している。 An N-type semiconductor region 21 is located outside the column region 4. A boundary between the N-type semiconductor region 21 and the P-type column region 3 in FIG. A P ⁻ type semiconductor single crystal region 5 is located on the column region 4 or on the N type semiconductor single crystal region 21 outside the column region 4 and the column region 4.

Ｐ^-型半導体単結晶領域５の基板表層部には、図１（ｂ）で示すように、Ｐ型ボディ領域６が形成され、このＰ型ボディ領域６内にはＮ⁺ソース領域７、Ｐ⁺ボディコンタクト領域８、トレンチが形成されている。トレンチの側面と底面には例えばシリコン酸化膜等のゲート絶縁膜９が形成され、ポリシリコン等の電極材料１０が埋め込まれてトレンチゲート１１が形成されている。Ｎ⁺型ソース領域７は、トレンチゲート１１の周囲にあって、かつＰ型ボディ領域６の表面に位置している。このような構成ではトレンチゲート１１に電圧を印加すると、Ｐ型ボディ領域６のうち、トレンチゲート１１の側面に沿った領域、つまりソース領域７とバッファ領域１２に挟まれた領域にチャネルが形成されるようになっている。 As shown in FIG. 1B, a P-type body region 6 is formed in the substrate surface layer portion of the P ⁻ -type semiconductor single crystal region 5, and an N ⁺ source region 7, P ⁺ Body contact region 8 and a trench are formed. A gate insulating film 9 such as a silicon oxide film is formed on the side and bottom surfaces of the trench, and an electrode material 10 such as polysilicon is embedded to form a trench gate 11. N ⁺ -type source region 7 is located around trench gate 11 and on the surface of P-type body region 6. In such a configuration, when a voltage is applied to the trench gate 11, a channel is formed in a region of the P-type body region 6 along the side surface of the trench gate 11, that is, a region sandwiched between the source region 7 and the buffer region 12. It has become so.

Ｐ⁺型ボディコンタクト領域８もＰ型ボディ領域６の表面に位置している。このＰ⁺型ボディコンタクト領域８は、基本的には、各トレンチゲート１１の間に配置されたＰ型ボディ領域６のみに形成されていれば良いが、アクティブ領域１３の最外周に位置するＰ型ボディ領域６の表面についても形勢されている。このようにすれば、アクティブ領域１３の最外周に位置するＰ型ボディ領域６の電位固定を行うことができ、寄生動作が発生しないようにすることが可能となる。 The P ⁺ type body contact region 8 is also located on the surface of the P type body region 6. The P ⁺ -type body contact region 8 may basically be formed only in the P-type body region 6 disposed between the trench gates 11, but the P ⁺ -type body contact region 8 is located on the outermost periphery of the active region 13. The surface of the mold body region 6 is also tended. In this way, the potential of the P-type body region 6 located on the outermost periphery of the active region 13 can be fixed, and it is possible to prevent a parasitic operation from occurring.

また、Ｎバッファ領域１２は、ドリフト領域となるＮ型コラム領域２とトレンチゲート１１とＰ型ボディ領域６とに接するように設置され、トレンチゲート１１はＮバッファ領域１２に到達するように形成されている。このようなバッファ層１２をトレンチゲート１１の下方のみでなく、アクティブ領域１３全域に形成することも可能であるが、各トレンチゲート１１の間に配置されるＰ型ボディ領域６がＰ型コラム領域３から電気的に離れ、フローティング状態になってしまうため、トレンチゲート１１の下方のみに形成するのが好ましい。 The N buffer region 12 is disposed so as to be in contact with the N-type column region 2 serving as a drift region, the trench gate 11, and the P-type body region 6, and the trench gate 11 is formed so as to reach the N buffer region 12. ing. It is possible to form such a buffer layer 12 not only under the trench gate 11 but also in the entire active region 13, but the P-type body region 6 disposed between the trench gates 11 is formed in the P-type column region. Since it is electrically separated from 3 and becomes a floating state, it is preferably formed only under the trench gate 11.

以上のように構成された縦型ＭＯＳＦＥＴにおいて、Ｐ⁺型ボディコンタクト領域８の最外周部分によってきまるアクティブ領域終端部Ｌから、コラム領域終端部１６にあるＰ／Ｎ接合部分までの距離を終端領域長Ｌと定義し、数式２に示す関係を満たすように、終端領域長だけ離間してアクティブ領域１３とＮ型シリコン単結晶領域２１が形成されている。 In the vertical MOSFET configured as described above, the distance from the active region termination portion L determined by the outermost peripheral portion of the P ⁺ -type body contact region 8 to the P / N junction portion in the column region termination portion 16 is defined as the termination region. The active region 13 and the N-type silicon single crystal region 21 are formed so as to be separated from each other by the length of the terminal region so as to define the length L and satisfy the relationship shown in Formula 2.

なお、この数式は上記数式１の右辺におけるＷ_N／２を左辺に移項させたものに相当する。 This equation corresponds to a value obtained by shifting W _N / 2 on the right side of Equation 1 to the left side.

（数２）
Ｌ≧ｄ−Ｗ_N／２
Ｌ：終端領域長
Ｗ_N:Ｎ型コラム領域幅
ｄ：コラム構造深さ
更に、Ｎ型シリコン単結晶領域２１上部であって、Ｐ−型半導体単結晶領域５の外側にはＮ型の単結晶領域２２が表面から単結晶領域２１に接する形で形成される。この単結晶領域２２は、Ｐ型コラム領域３の終端位置と同じ位置から、もしくはそれよりも外側からアクティブ領域１３の外周側に向かって配置されるようになっている。そして、これら単結晶領域２１および２２によって素子の最外周が囲まれた構造となる。 (Equation 2)
L ≧ d−W _N / 2
L: termination region length W _N: N-type column region width d: column structure depth Furthermore, an N-type single crystal is located above the N-type silicon single crystal region 21 and outside the P-type semiconductor single crystal region 5. Region 22 is formed in contact with single crystal region 21 from the surface. The single crystal region 22 is arranged from the same position as the end position of the P-type column region 3 or from the outside to the outer peripheral side of the active region 13. The single crystal regions 21 and 22 have a structure in which the outermost periphery of the element is surrounded.

このような構成により、コラム領域４の内部からコラム領域終端１６に向けて広がる空乏層は、コラム領域４の内部から基板深さ方向に広がる空乏層と同等に広げられる。従ってコラム構造の短辺に対向する領域における電界集中が回避でき、縦型ＭＯＳＦＥＴの耐圧向上が可能となる。 With such a configuration, the depletion layer extending from the inside of the column region 4 toward the column region end 16 is expanded to the same extent as the depletion layer extending from the inside of the column region 4 in the substrate depth direction. Therefore, electric field concentration in the region facing the short side of the column structure can be avoided, and the breakdown voltage of the vertical MOSFET can be improved.

図５は本実施形態における耐圧設計値を約２２０Ｖにした縦型ＭＯＳＦＥＴの、耐圧の終端領域長Ｌ依存性を示したグラフである。グラフの縦軸は耐圧、横軸は終端領域長Ｌを示しており、終端領域長ＬがＬ＝ｄ−Ｗ_N／２を境界にして、Ｌ＜ｄ−Ｗ_N／２の領域では耐圧値が設計値を満足することができず、Ｌ＞ｄ−Ｗ_N／２の領域では耐圧値が設計値でほぼ飽和している。従って、このグラフによって終端領域長Ｌの最小寸法がＬ≧ｄ−Ｗ_N／２で表されることが確認できる。 FIG. 5 is a graph showing the dependency of the breakdown voltage on the termination region length L of a vertical MOSFET having a breakdown voltage design value of about 220V in the present embodiment. The vertical axis of the graph indicates the breakdown voltage, and the horizontal axis indicates the termination region length L. In the region where the termination region length L is L = d−W _N / 2 and L <d−W _N / 2, the breakdown voltage value is obtained. However, the withstand voltage value is almost saturated with the design value in the region of L> d−W _N / 2. Therefore, it can be confirmed from this graph that the minimum dimension of the termination region length L is expressed by L ≧ d−W _N / 2.

なお、上述したように、終端領域長Ｌは、コラム領域４におけるＰＮ接合の繰り返し構造にのみ着目して決定されている。そして、バッファ層１２が形成される深さに形成されるバッファ層１２とＰ^-型半導体単結晶領域５とによるＰＮ接合の繰り返し構造については考慮されていない。これは、本実施形態に示す縦型ＭＯＳＦＥＴの耐圧がコラム領域４の深さによって決定され、バッファ層１２があったとしても、それによって耐圧が決定される訳ではないためである。したがって、上記のように、コラム領域４におけるＰＮ接合の繰り返し構造にのみ着目して終端領域Ｌを決定すれば足りる。 As described above, the termination region length L is determined by paying attention only to the repeated structure of the PN junction in the column region 4. A repetitive structure of a PN junction formed by the buffer layer 12 formed at a depth where the buffer layer 12 is formed and the P ⁻ type semiconductor single crystal region 5 is not considered. This is because the withstand voltage of the vertical MOSFET shown in this embodiment is determined by the depth of the column region 4, and even if there is the buffer layer 12, the withstand voltage is not determined by that. Therefore, as described above, it is sufficient to determine the termination region L while paying attention only to the repeated structure of the PN junction in the column region 4.

また、ここでは、コラム構造として、図２−ａに示したストライプ構造のものを例に挙げたが、ストライプ構造以外にも、図２−ｂに示す四角形ドット構造、図２−ｃに示す六角形ドット構造、図２−ｄに示す円形ドット構造とすることも可能である。 In addition, here, the column structure having the stripe structure shown in FIG. 2A is taken as an example, but in addition to the stripe structure, a rectangular dot structure shown in FIG. A square dot structure or a circular dot structure shown in FIG.

これらの場合、図２−ｂ〜図２−ｄにおいて一点鎖線で示したアクティブ領域１３と点線で示したコラム領域４の終端部との距離、すなわち終端領域長Ｌの最小寸法は、ドット毎の間隔をＷＮとして定義して、上記関係を満たすようなものとされる。 In these cases, the distance between the active region 13 indicated by the alternate long and short dash line in FIG. 2B to FIG. 2D and the end portion of the column region 4 indicated by the dotted line, that is, the minimum dimension of the end region length L is The interval is defined as WN so that the above relationship is satisfied.

また、ゲート構造もコラム構造と同様にストライプ構造やドットの周期的構造をとることが可能であり、また、ストライプ構造とした場合であっても、表面からみてコラム構造と平行な構造に限定されるものではなく、直行もしくは斜めの位置関係となる配置も可能である。 In addition, the gate structure can have a stripe structure or a periodic structure of dots as well as the column structure, and even when it is a stripe structure, it is limited to a structure parallel to the column structure as viewed from the surface. However, it is possible to arrange them in a direct or oblique positional relationship.

（第２実施形態）
図６（ａ）は本発明の第２実施形態における縦型ＭＯＳＦＥＴの断面図である。本実施形態は第１実施形態に対して、図１（ａ）、（ｂ）で示した断面図のうち基板表面にあるＰ^-型半導体単結晶領域５及びＮバッファ領域１２が存在せず、コラム構造がＰボディ領域６の存在しない基板表面に到達している点が異なる。 (Second Embodiment)
FIG. 6A is a sectional view of a vertical MOSFET according to the second embodiment of the present invention. This embodiment is different from the first embodiment in that the P ⁻ type semiconductor single crystal region 5 and the N buffer region 12 on the substrate surface are not present in the cross-sectional views shown in FIGS. The difference is that the column structure reaches the substrate surface where the P body region 6 does not exist.

基板表面上のレイアウトは第１実施形態と同様、図２に示すＰ型コラム領域３の短辺に対向する領域のＢ−Ｂ'断面構造に相当する構造である。なお、本実施形態の理解を容易にするために示した図６（ｂ）は図２に示すＰ型コラム領域３の長辺に対向する領域のＡ−Ａ'断面構造に相当する構造であり、従来から知られている構造である。 Similar to the first embodiment, the layout on the substrate surface is a structure corresponding to the BB ′ cross-sectional structure of the region facing the short side of the P-type column region 3 shown in FIG. Note that FIG. 6B shown for easy understanding of the present embodiment is a structure corresponding to the AA ′ cross-sectional structure of the region facing the long side of the P-type column region 3 shown in FIG. This is a conventionally known structure.

第２実施形態においても第１実施形態と同一の数式２を満たすようにアクティブ領域１３とＮ型シリコン単結晶からなるＮ型半導体領域２１が形成されている。 Also in the second embodiment, an active region 13 and an N-type semiconductor region 21 made of an N-type silicon single crystal are formed so as to satisfy the same mathematical formula 2 as in the first embodiment.

このようにすることで、第２実施形態においても第１実施形態と同様に、コラム領域４の内部から、コラム領域終端１６に向けて広がる空乏層は、コラム領域４の基板深さ方向に広がる空乏層と同等に広げることが可能となり、コラム構造の短辺に対向する領域における電界集中を回避でき、縦型ＭＯＳＦＥＴの耐圧向上が可能となる。 By doing so, the depletion layer extending from the inside of the column region 4 toward the column region end 16 also extends in the substrate depth direction of the column region 4 in the second embodiment as in the first embodiment. It is possible to extend the same as the depletion layer, avoid electric field concentration in the region facing the short side of the column structure, and improve the breakdown voltage of the vertical MOSFET.

（第３実施形態）
図７（ａ）は本発明の第３実施形態における縦型ＭＯＳＦＥＴの断面図であり、図８に示すＰ型コラム領域３の短辺に対向する領域のＤ−Ｄ'断面構造に相当する構造である。なお、本実施形態の理解を容易にするために示した図７の（ｂ）は図８に示すＰ型コラム領域３の長辺に対向する領域のＣ−Ｃ'断面構造に相当する構造であり、従来から知られている構造である。 (Third embodiment)
FIG. 7A is a cross-sectional view of a vertical MOSFET according to the third embodiment of the present invention, and corresponds to a DD ′ cross-sectional structure in a region facing the short side of the P-type column region 3 shown in FIG. It is. Note that FIG. 7B shown for easy understanding of the present embodiment is a structure corresponding to the CC ′ cross-sectional structure of the region facing the long side of the P-type column region 3 shown in FIG. There is a conventionally known structure.

第３実施形態は第１実施形態と同様であるが、コラム構造を形成する際に、Ｓｉ（１１０）基板を利用し、エッチング速度の面方位依存性を利用したウエットエッチングによりコラム構造を形成するため、コラム形状が前述の実施形態とは異なっている。その他基本的な構成は第１実施形態とほぼ同様である。 The third embodiment is the same as the first embodiment, but when forming the column structure, the Si (110) substrate is used, and the column structure is formed by wet etching using the surface orientation dependence of the etching rate. Therefore, the column shape is different from that of the above-described embodiment. Other basic configurations are substantially the same as those of the first embodiment.

第１及び第２実施形態では、コラム領域終端部１６にあるＰ／Ｎ接合面は、基板面と水平な方向に対して垂直に位置していたが、第３実施形態では、図７（ａ）に示すように、コラム領域終端部１６にあるＰ／Ｎ接合面は基板面と水平な方向に対して３５．２７°の角度を持つ。空乏層の広がる距離は前述の実施形態と同一で、基板内部においては、アクティブ領域の終端１７から前記コラム領域４におけるＰ型コラム領域３の短辺側の終端１６までの距離にＮ型コラム領域幅Ｗ_Nの１／２の長さを加えた長さだけ空乏層は広がる。基板表面上での終端領域長Ｌは三角関数を用いて表現され、具体的には以下のように表される。 In the first and second embodiments, the P / N junction surface at the column region end portion 16 is positioned perpendicular to the substrate surface and in the horizontal direction, but in the third embodiment, FIG. ), The P / N junction surface at the column region end portion 16 has an angle of 35.27 ° with respect to the direction parallel to the substrate surface. The distance that the depletion layer spreads is the same as that of the above-described embodiment, and in the substrate, the distance between the end 17 of the active region and the end 16 on the short side of the P-type column region 3 in the column region 4 is N-type column region. The depletion layer expands by a length that is a half of the width W _N. The termination region length L on the substrate surface is expressed using a trigonometric function, and is specifically expressed as follows.

まず、コラム領域におけるアクティブ領域の終端１７から基板深さ方向に基板面に対する垂線引き、この垂線と、Ｐ^-型半導体領域５とＰ型コラム領域３との境界線との交点を起点１８とし、コラム深さからＮ型コラム領域幅Ｗ_Nの１／２の長さを減じた距離を示す円弧を描く。そして、この円弧が接するＳｉ（１１１）面、即ちコラム領域終端１６との接点からコラム領域４の終端に対する法線を引く。この法線と終端領域長Ｌとｓｉｎ３５．２７°の関係から、終端領域長Ｌは、コラム深さからＮ型コラム領域幅Ｗ_Nの１／２の長さを減じた距離の１／ｓｉｎ３５．２７°倍で表される。従って、終端領域長Ｌは数式３で示される距離になるよう設定される。 First, a vertical line is drawn from the terminal end 17 of the active region in the column region to the substrate surface in the depth direction of the substrate, and the intersection of this normal and the boundary line between the P ⁻ type semiconductor region 5 and the P type column region 3 is set as the starting point 18. An arc indicating a distance obtained by subtracting 1/2 the length of the N-type column region width W _N from the column depth is drawn. Then, a normal line to the end of the column region 4 is drawn from the Si (111) surface with which the arc contacts, that is, the contact with the column region end 16. From the relationship between this normal line, the termination region length L, and sin 35.27 °, the termination region length L is 1 / sin 35. which is a distance obtained by subtracting ½ of the N-type column region width W _N from the column depth. It is represented by 27 ° times. Accordingly, the termination region length L is set to be a distance represented by Equation 3.

（数３）
Ｌ≧（ｄ−Ｗ_N／２）／sin35.27
Ｌ：終端領域長
Ｗ_N:Ｎ型コラム領域幅
ｄ：コラム構造深さ
このため、Ｐ⁺型ボディコンタクト領域８の最外周部分によってきまるアクティブ領域の終端１７から、基板表面におけるコラム領域終端１６にあるＰ／Ｎ接合部分までの距離を終端領域長と定義し、数式３を満たす終端領域長Ｌだけ離間してアクティブ領域１３とＮ型シリコン単結晶からなるＮ型半導体領域２１を形成する。 (Equation 3)
L ≧ (d−W _N /2)/sin35.27
L: Termination region length W _N: N-type column region width d: Column structure depth Therefore, from the end 17 of the active region determined by the outermost peripheral portion of the P ⁺ -type body contact region 8 to the column region termination 16 on the substrate surface A distance to a certain P / N junction is defined as a termination region length, and an active region 13 and an N-type semiconductor region 21 made of an N-type silicon single crystal are formed separated by a termination region length L satisfying Equation 3.

このような構成により、コラム領域４の内部からコラム領域終端１６に向けて広がる空乏層は、コラム領域４から基板深さ方向に広がる空乏層と同等に広げられる。従ってコラム構造の短辺に対向する領域における電界集中を回避でき、縦型ＭＯＳＦＥＴの耐圧向上が可能となる。 With such a configuration, the depletion layer extending from the inside of the column region 4 toward the column region end 16 is expanded to the same extent as the depletion layer extending from the column region 4 in the substrate depth direction. Therefore, electric field concentration in the region facing the short side of the column structure can be avoided, and the breakdown voltage of the vertical MOSFET can be improved.

（第４実施形態）
図９（ａ）は本発明の第４実施形態における縦型ＭＯＳＦＥＴの断面図である。第３実施形態と異なる部分は、第３実施形態の図７（ａ）、（ｂ）で示した断面図のうち基板表面にあるＰ^-型半導体領域５及びＮバッファ領域１２が存在せず、Ｐボディ領域６がコラム領域４の内部に存在する点である。 (Fourth embodiment)
FIG. 9A is a sectional view of a vertical MOSFET in the fourth embodiment of the present invention. The difference from the third embodiment is that the P ⁻ type semiconductor region 5 and the N buffer region 12 on the substrate surface are not present in the cross-sectional views shown in FIGS. 7A and 7B of the third embodiment, The P body region 6 is present in the column region 4.

基板表面上のレイアウトは第３実施形態と同様、図８に示す第２導電型の第２半導体領域３の短辺に対向する領域のＤ−Ｄ'断面構造に相当する構造である。なお、本実施形態の理解を容易にするために示した図９（ｂ）は図２に示す第２導電型の第２半導体領域３の長辺に対向する領域のＣ−Ｃ'断面構造に相当する構造であり、従来から知られている構造である。 Similar to the third embodiment, the layout on the substrate surface is a structure corresponding to the DD ′ cross-sectional structure of the region facing the short side of the second conductivity type second semiconductor region 3 shown in FIG. Note that FIG. 9B shown in order to facilitate understanding of the present embodiment shows a CC ′ cross-sectional structure of a region facing the long side of the second conductivity type second semiconductor region 3 shown in FIG. This is a corresponding structure and is a conventionally known structure.

第４実施形態においては、第３実施形態におけるＰ^-型半導体領域５とＮバッファ領域１２が存在しないため、基板表面に現れる終端領域１４のＰ／Ｎ接合面が第３実施形態と比較して外周に位置することになる。即ち、数式３に対して、図９（ａ）に図示するＰ型ボディ領域の深さ（ｄ_B）を変数とする項（ｄ_B／tan35.27）を加えた数式４を満たすようにアクティブ領域１３とＮ型シリコン単結晶領域２１が形成されている。 In the fourth embodiment, since the P ⁻ type semiconductor region 5 and the N buffer region 12 in the third embodiment do not exist, the P / N junction surface of the termination region 14 that appears on the substrate surface is compared with the third embodiment. It will be located on the outer periphery. In other words, the expression 3 is active so as to satisfy the expression 4 in which the term (d _B /tan35.27) having the variable (D _B ) of the P-type body region shown in FIG. Region 13 and N-type silicon single crystal region 21 are formed.

（数４）
Ｌ≧｛（ｄ−Ｗ_N／２）／sin35.27｝＋（ｄ_B／tan35.27）
Ｌ：終端領域長
Ｗ_N:Ｎ型コラム領域幅
ｄ：コラム構造深さ
ｄ_B：Ｐ型ボディ領域深さ
このようにすることで、第４実施形態においても第３実施形態と同様に、コラム領域４の内部からコラム領域終端１６に向けて広がる空乏層は、基板深さ方向に広がる空乏層と同等に広げることが可能となり、コラム構造の短辺に対向する領域における電界集中を回避でき、縦型ＭＯＳＦＥＴの耐圧向上が可能となる。 (Equation 4)
L ≧ {(d−W _N /2)/sin35.27}+(d _B /tan35.27)
L: Termination region length W _N: N-type column region width d: Column structure depth d _B : P-type body region depth In this way, the column in the fourth embodiment is the same as that in the third embodiment. The depletion layer extending from the inside of the region 4 toward the column region end 16 can be expanded to the same extent as the depletion layer extending in the substrate depth direction, and electric field concentration in the region facing the short side of the column structure can be avoided. The breakdown voltage of the vertical MOSFET can be improved.

（第５実施形態）
本実施形態は前述の実施形態におけるコラム領域の角部について、コラム構造の短辺に対向する領域での電界集中を回避し、縦型ＭＯＳＦＥＴの耐圧向上を図るものである。即ち、図１０に示すように、基板上面方向から見てアクティブ領域終端１７からの終端領域長Ｌの範囲が曲率を持って示される部分においては、終端領域長Ｌの範囲よりもコラムの短辺が外側に位置する様にする。 (Fifth embodiment)
In the present embodiment, electric field concentration in a region facing the short side of the column structure is avoided at the corner of the column region in the above-described embodiment, and the breakdown voltage of the vertical MOSFET is improved. That is, as shown in FIG. 10, in the portion where the range of the termination region length L from the active region termination 17 is shown with a curvature when viewed from the top surface direction of the substrate, the shorter side of the column than the range of the termination region length L is shown. To be on the outside.

上記各実施形態で示した終端領域長Ｌの関係は、コラム領域４の角部についても同様である。つまり、終端領域長Ｌが数式２、３、４で示されるそれぞれの場合において、基板上面方向から見た耐圧時の空乏層の角部は、アクティブ領域の角部を起点にして円弧状に外周に向かって広がる。このとき、Ｐ型コラム領域終端１６１を終端領域長Ｌよりも外周部となるように配置すれば、前述の実施形態で示した終端領域長Ｌを表す数式２、３、４が各実施形態でのコラム領域４の角部において成り立つ。従って、本実施形態に示す構成とすることにより、半導体装置全体において局所的に耐圧の低い部分ができることを回避することができる。 The relationship of the termination region length L shown in the above embodiments is the same for the corners of the column region 4. That is, in each case where the termination region length L is expressed by Equations 2, 3, and 4, the corner portion of the depletion layer at the time of withstand voltage viewed from the substrate upper surface direction is an arcuate outer periphery starting from the corner portion of the active region Spread towards. At this time, if the P-type column region end 161 is arranged so as to be more peripheral than the end region length L, Formulas 2, 3, and 4 representing the end region length L shown in the above-described embodiment are expressed in each embodiment. This holds at the corners of the column region 4. Therefore, with the configuration shown in this embodiment, it is possible to avoid the formation of a locally low withstand voltage portion in the entire semiconductor device.

（他の実施形態）
これまではコラム領域４について、Ｐ型またはＮ型コラム領域の幅（Ｗ_N、Ｗ_P）、Ｐ型またはＮ型コラム領域の濃度については特に説明しなかったが、基板面内全体のＰ型またはＮ型コラム領域の幅（Ｗ_N、Ｗ_P）、Ｐ型またはＮ型コラム領域の濃度が一定であってもよい。 (Other embodiments)
Up to now, for the column region 4, the width (W _N , W _P ) of the P-type or N-type column region and the concentration of the P-type or N-type column region have not been particularly explained. Alternatively, the width of the N-type column region (W _N , W _P ) and the concentration of the P-type or N-type column region may be constant.

更に、縦型ＭＯＳＦＥＴに本発明を適用しているが、他の縦型半導体装置に本発明を適用することもできる。加えて、縦型ＭＯＳＦＥＴは、Ｎ型であるが、Ｐ型でもよい。 Furthermore, although the present invention is applied to the vertical MOSFET, the present invention can also be applied to other vertical semiconductor devices. In addition, the vertical MOSFET is an N type, but may be a P type.

本発明の第１実施形態における縦型ＭＯＳＦＥＴの断面を示す図である。It is a figure which shows the cross section of the vertical MOSFET in 1st Embodiment of this invention. 本発明の第１実施形態における縦型ＭＯＳＦＥＴのレイアウトを示す図である。It is a figure which shows the layout of the vertical MOSFET in 1st Embodiment of this invention. 第１実施形態の他の例における縦型ＭＯＳＦＥＴのレイアウトを示す図である。It is a figure which shows the layout of the vertical MOSFET in the other example of 1st Embodiment. 第１実施形態の他の例における縦型ＭＯＳＦＥＴのレイアウトを示す図である。It is a figure which shows the layout of the vertical MOSFET in the other example of 1st Embodiment. 第１実施形態の他の例における縦型ＭＯＳＦＥＴのレイアウトを示す図である。It is a figure which shows the layout of the vertical MOSFET in the other example of 1st Embodiment. 本発明のコラム領域における空乏層の広がり方を説明する図である。It is a figure explaining how the depletion layer spreads in the column area | region of this invention. 本発明のコラム領域終端の配置を説明する図である。It is a figure explaining arrangement | positioning of the column area | region terminal of this invention. 本発明の第１実施形態における縦型ＭＯＳＦＥＴの耐圧の終端領域長Ｌ依存性を示すグラフである。It is a graph which shows the termination region length L dependence of the proof pressure of the vertical MOSFET in 1st Embodiment of this invention. 本発明の第２実施形態における縦型ＭＯＳＦＥＴの断面を示す図である。It is a figure which shows the cross section of the vertical MOSFET in 2nd Embodiment of this invention. 本発明の第３実施形態における縦型ＭＯＳＦＥＴの断面を示す図である。It is a figure which shows the cross section of the vertical MOSFET in 3rd Embodiment of this invention. 本発明の第３実施形態における縦型ＭＯＳＦＥＴのレイアウトを示す図である。It is a figure which shows the layout of the vertical MOSFET in 3rd Embodiment of this invention. 本発明の第４実施形態における縦型ＭＯＳＦＥＴの断面を示す図である。It is a figure which shows the cross section of the vertical MOSFET in 4th Embodiment of this invention. 本発明のその他の実施形態における縦型ＭＯＳＦＥＴの断面を示す図である。It is a figure which shows the cross section of the vertical MOSFET in other embodiment of this invention. 従来構造を示す図である。It is a figure which shows a conventional structure.

Explanation of symbols

１…Ｎ⁺型ドレイン領域、２…Ｎ型コラム領域、３…Ｐ型コラム領域、４…コラム領域、５…Ｐ^-型半導体単結晶領域、６…Ｐ型ボディ領域、７…Ｎ⁺型ソース領域、８…Ｐ⁺型ボディコンタクト領域、９…ゲート絶縁膜、１０…電極材料、１１…トレンチゲート、１２…Ｎ型バッファ領域、１３…アクティブ領域、１４…終端領域、１４１…コラム領域の外周部分、１６…コラム領域終端、１７…アクティブ領域の終端、２１…Ｎ型半導体領域、１６１…Ｐ型コラム領域終端。

1 ... N ⁺ -type drain region, 2 ... N-type column regions, 3 ... P-type column regions, 4 ... column region, 5 ... P ^- -type semiconductor single crystal regions, 6 ... P-type body region, 7 ... N ⁺ -type source 8 ... P ⁺ type body contact region, 9 ... gate insulating film, 10 ... electrode material, 11 ... trench gate, 12 ... N-type buffer region, 13 ... active region, 14 ... termination region, 141 ... outer periphery of column region Part, 16 ... end of column area, 17 ... end of active area, 21 ... N-type semiconductor area, 161 ... end of P-type column area.

Claims

A semiconductor device comprising a vertical semiconductor element,
A first conductivity type semiconductor substrate (1);
On the semiconductor substrate, a first conductivity type first semiconductor region (2) and a second conductivity type second semiconductor region (3) having a constant depth with respect to the substrate depth direction of the semiconductor substrate are provided. The plurality of second semiconductor regions are polygons formed in a strip shape when viewed from the substrate surface side in the first semiconductor region, and a plurality of the second semiconductor regions are formed at a predetermined distance from each other. A column region (4) having a column structure in which the first semiconductor region and the second semiconductor region are alternately arranged on a substrate;
Wherein an outer column regions (4), the third semi-conductive region (21) overlying the first conductivity type semiconductor substrate (1),
The upper column region or located on the third upper half conductive area (21) located outside of the column region from over the column region, a fourth semiconductor region of the second conductivity type (5),
In further outside of the fourth semiconductor region, and the third extending from the semi-conductor region (21) surface at the top to the third semi-conductive region fifth semi conductor region (22),
A second conductivity type body region (6) formed on the substrate surface side of the column region ;
A first conductivity type source region (7), a second conductivity type body contact region (8), and a trench formed in the body region;
A gate insulating film (9) formed on the side and bottom of the trench;
A trench gate (11) formed by embedding an electrode material (10) through the gate insulating film inside the trench,
The source region is located around the trench gate and on the surface of the body region (6);
The body contact region is located on a surface of the body region;
The trench gate is formed to reach the first semiconductor region;
The semiconductor substrate and the first semiconductor region are electrically connected,
On the column region, when a region having the source region, the body region, the body contact region, and the trench gate region is an active region (13),
The distance from the end of the body contact region, which is the end (17) of the active region, to the end (16) on the short side of the second semiconductor region in the column region is the end region length L and the first semiconductor region width is W _1, the column structure depth is defined as d, configured vertical semiconductor device so as to satisfy the equation _{L ≧ d-W 1/2} .

A semiconductor device comprising a vertical semiconductor element,
A first conductivity type semiconductor substrate (1);
On the semiconductor substrate, a first conductivity type first semiconductor region (2) and a second conductivity type second semiconductor region (3) having a constant depth with respect to the substrate depth direction of the semiconductor substrate are provided. The plurality of second semiconductor regions are polygons formed in a strip shape when viewed from the substrate surface side in the first semiconductor region, and a plurality of the second semiconductor regions are formed at a predetermined distance from each other. A column region (4) having a column structure in which the first semiconductor region and the second semiconductor region are alternately arranged on a substrate;
Wherein an outer column regions (4), the third semi-conductive region (21) overlying the first conductivity type semiconductor substrate (1),
The upper column region or located on the third upper half conductive area (21) located outside of the column region from over the column region, a fourth semiconductor region of the second conductivity type (5),
In further outside of the fourth semiconductor region, and the third extending from the semi-conductor region (21) surface at the top to the third semi-conductive region fifth semi conductor region (22),
A second conductivity type body region (6) formed on the substrate surface side of the fourth semiconductor region on the column region;
A first conductivity type source region (7), a second conductivity type body contact region (8), and a trench formed in the body region;
A gate insulating film (9) formed on the side and bottom of the trench;
Inside the trench, a trench gate (11) formed by embedding an electrode material (10) through the gate insulating film;
A first conductivity type buffer region (12) disposed so that the trench gate, the body region, and the first semiconductor region are in contact with each other;
The source region is located around the trench gate and on the surface of the body region (6);
The body contact region is located on a surface of the body region;
The trench gate is formed to reach the buffer region;
The semiconductor substrate and the first semiconductor region are electrically connected,
On the column region, when a region having the source region, the body region, the body contact region, and the trench gate region is an active region (13),
The distance from the end of the body contact region, which is the end (17) of the active region, to the end (16) on the short side of the second semiconductor region in the column region is the end region length L and the first semiconductor region width is W _1, the column structure depth is defined as d, configured vertical semiconductor device so as to satisfy the equation _{L ≧ d-W 1/2} .

A semiconductor device comprising a vertical semiconductor element,
A first conductivity type semiconductor substrate (1);
On the semiconductor substrate, a first conductivity type first semiconductor region (2) and a second conductivity type second semiconductor region (3) having a constant depth with respect to the substrate depth direction of the semiconductor substrate are provided. The plurality of second semiconductor regions are polygons formed in a strip shape when viewed from the substrate surface side in the first semiconductor region, and a plurality of the second semiconductor regions are formed at a predetermined distance from each other. A column region (4) having a column structure in which the first semiconductor region and the second semiconductor region are alternately arranged on a substrate;
A second conductivity type body region (6) formed on the substrate surface side of the column region;
A first conductivity type source region (7), a second conductivity type body contact region (8), and a trench formed in the body region;
A gate insulating film (9) formed on the side and bottom of the trench;
A trench gate (11) formed by embedding an electrode material (10) through the insulating film inside the trench,
The source region is located around the trench gate and on the surface of the body region;
The body contact region is located on a surface of the body region;
The trench gate is formed to reach the first semiconductor region;
The semiconductor substrate and the first semiconductor region are electrically connected,
On the column region, when a region having the source region, the body region, the body contact region, and the trench gate region is an active region (13),
The distance from the end of the body contact region, which is the end (17) of the active region, to the end (16) on the short side of the second semiconductor region in the column region is the end region length L and the first semiconductor region width is W ₁ , column structure depth is defined as d,
L ≧ d-W _1/2
A vertical semiconductor device configured to satisfy the formula:

A semiconductor device comprising a vertical semiconductor element,
A first conductivity type Si (110) substrate;
On the semiconductor substrate, a first conductivity type first semiconductor region (2) and a second conductivity type second semiconductor region (3) having a constant depth with respect to the substrate depth direction of the semiconductor substrate are provided. The plurality of second semiconductor regions are polygons formed in a strip shape when viewed from the substrate surface side in the first semiconductor region, and a plurality of the second semiconductor regions are formed at a predetermined distance from each other. A column region (4) having a column structure in which the first semiconductor region and the second semiconductor region are alternately arranged on a substrate;
Wherein an outer column regions (4), the third semi-conductive region (21) overlying the first conductivity type semiconductor substrate (1),
Located on the third upper half conductive area (21) located outside of the column region from the column region or on the column region on a fourth semiconductor region of the second conductivity type (5),
In further outside of the fourth semiconductor region, and the third extending from the semi-conductor region (21) surface at the top to the third semi-conductive region fifth semi conductor region (22),
A second conductivity type body region (6) formed on the substrate surface side of the column region ;
A first conductivity type source region (7), a second conductivity type body contact region (8), and a trench formed in the body region;
A gate insulating film (9) formed on the side and bottom of the trench;
A trench gate (11) formed by embedding an electrode material (10) through the insulating film inside the trench,
The surface constituting the outer shape of the second semiconductor region includes at least one set of Si (111) surfaces,
The source region is located around the trench gate and on the surface of the body region;
The body contact region is located on a surface of the body region;
The trench gate is formed to reach the first semiconductor region;
The semiconductor substrate and the first semiconductor region are electrically connected,
On the column region, when a region having the source region, the body region, the body contact region, and the trench gate region is an active region (13),
The distance from the end of the body contact region, which is the end (17) of the active region, to the end (16) on the short side of the second semiconductor region in the column region is the end region length L and the first semiconductor region width is A vertical semiconductor device configured to satisfy the formula of L ≧ (d−W _{1/2) /} sin 35.27, where W ₁ and the column structure depth are defined as d.

A semiconductor device comprising a vertical semiconductor element,
A first conductivity type Si (110) substrate;
On the semiconductor substrate, a first conductivity type first semiconductor region (2) and a second conductivity type second semiconductor region (3) having a constant depth with respect to the substrate depth direction of the semiconductor substrate are provided. The plurality of second semiconductor regions are polygons formed in a strip shape when viewed from the substrate surface side in the first semiconductor region, and a plurality of the second semiconductor regions are formed at a predetermined distance from each other. A column region (4) having a column structure in which the first semiconductor region and the second semiconductor region are alternately arranged on a substrate;
Wherein an outer column regions (4), the third semi-conductive region (21) overlying the first conductivity type semiconductor substrate (1),
The upper column region or located on the third upper half conductive area (21) located outside of the column region from over the column region, a fourth semiconductor region of the second conductivity type (5), said fourth semiconductor in further outside the region, and the third extending from the semi-conductor region (21) surface at the top to the third semi-conductive region fifth semi conductor region (22),
A second conductivity type body region (6) formed on the substrate surface side of the fourth semiconductor region on the column region;
A first conductivity type source region (7), a second conductivity type body contact region (8), and a trench formed in the body region;
A gate insulating film (9) formed on the side and bottom of the trench;
Inside the trench, a trench gate (11) formed by embedding an electrode material (10) through the insulating film;
A first conductivity type buffer region (12) disposed so that the trench gate, the body region, and the first semiconductor region are in contact with each other;
The surface constituting the outer shape of the second semiconductor region includes at least one set of Si (111) surfaces,
The source region is located around the trench gate and on the surface of the body region;
The body contact region is located on a surface of the body region;
The trench gate is formed to reach the buffer region;
The semiconductor substrate and the first semiconductor region are electrically connected,
On the column region, when a region having the source region, the body region, the body contact region, and the trench gate region is an active region (13),
The distance from the end of the body contact region, which is the end (17) of the active region, to the end (16) on the short side of the second semiconductor region in the column region is the end region length L and the first semiconductor region width is A vertical semiconductor device configured to satisfy the formula of L ≧ (d−W _{1/2) /} sin 35.27, where W ₁ and the column structure depth are defined as d.

A semiconductor device comprising a vertical semiconductor element,
A first conductivity type Si (110) substrate;
On the semiconductor substrate, a first conductivity type first semiconductor region (2) and a second conductivity type second semiconductor region (3) having a constant depth with respect to the substrate depth direction of the semiconductor substrate are provided. Configured,
The second semiconductor region is a polygon formed in a strip shape when viewed from the substrate surface side in the first semiconductor region, and a plurality of the second semiconductor regions spaced apart from each other by a predetermined distance are formed on the semiconductor substrate. A column region (4) having a column structure in which one semiconductor region and the second semiconductor region are alternately arranged;
A second conductivity type body region (6) formed on the substrate surface side of the column region;
A first conductivity type source region (7), a second conductivity type body contact region (8), and a trench formed in the body region;
A gate insulating film (9) formed on the side and bottom of the trench;
A trench gate (11) formed by embedding an electrode material (10) through the insulating film inside the trench,
The surface constituting the outer shape of the second semiconductor region includes at least one set of Si (111) surfaces,
The source region is located around the trench gate and on the surface of the body region;
The body contact region is located on a surface of the body region;
The trench gate is formed to reach the first semiconductor region;
The semiconductor substrate and the first semiconductor region are electrically connected,
On the column region, when a region having the source region, the body region, the body contact region, and the trench gate region is an active region (13),
The distance from the end of the body contact region, which is the end (17) of the active region, to the end (16) on the short side of the second semiconductor region in the column region is the end region length L and the first semiconductor region width is W _1, the column structure depth d, a body region depth is defined as d _B,
L ≧ {(d−W ₁ /2)/sin35.27}+(d _B /tan35.27)
A vertical semiconductor device configured to satisfy the formula: