JP4631268B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4631268B2
JP4631268B2 JP2003369049A JP2003369049A JP4631268B2 JP 4631268 B2 JP4631268 B2 JP 4631268B2 JP 2003369049 A JP2003369049 A JP 2003369049A JP 2003369049 A JP2003369049 A JP 2003369049A JP 4631268 B2 JP4631268 B2 JP 4631268B2
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conductivity type
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semiconductor device
impurity concentration
inclined groove
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JP2005136064A (en
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学 武井
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Fuji Electric Co Ltd
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Fuji Electric Systems Co Ltd
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Description

本発明は電力変換装置などに主として使用されるパワー半導体装置に関する。さらに詳しくは、エピタキシャルウェハ型、拡散ウェハ型またはＦＺウェハ型のダイオード、ＢＪＴ、ＭＯＳＦＥＴ、ＩＧＢＴ等に関する。   The present invention relates to a power semiconductor device mainly used for a power conversion device or the like. More specifically, the present invention relates to an epitaxial wafer type, diffusion wafer type or FZ wafer type diode, BJT, MOSFET, IGBT and the like.

一枚の半導体ウェハ内に多数のデバイスを形成するダイオード、ＢＪＴ、ＭＯＳＦＥＴ、ＩＧＢＴ等では耐圧構造としてプレーナ型の接合終端構造が多く採用されている。プレーナ型の接合終端構造は、該構造内の接合面に曲率部分を有するために活性部内の平面状の接合に比べて電界集中による高電界部分ができ易く、何の対策もないと、通常は活性部より先にブレークダウンの臨界電界に到達し、低い耐圧となる。従って、従来においてもプレーナ型の接合終端構造として、図６のプレーナ型接合終端構造を示す断面図のように、フローティングガードリング構造、フィールドプレート構造、リサーフ構造等またはそれらを組み合わせた接合終端構造にすることにより改善が図られてきた。
ただし、前記プレーナ型の接合終端構造２１の表面は、平面的には活性部１０表面と同一表面にあって、活性部の周囲に形成されることが多いので、チップの全面積に占める接合終端構造の面積比率が大きくなると、有効電流の流れる活性部の面積比率は相対的に小さくなり、電気特性的にも、価格的にも不利となる。小面積のチップほど、この傾向は顕著になる。 In a diode, BJT, MOSFET, IGBT, etc. that form a large number of devices in one semiconductor wafer, a planar type junction termination structure is often used as a withstand voltage structure. A planar junction termination structure has a curved portion on the joint surface in the structure, and therefore, a higher electric field portion due to electric field concentration is more easily formed than a planar junction in the active portion. The critical electric field for breakdown is reached before the active portion, resulting in a low breakdown voltage. Accordingly, as a planar junction termination structure, a floating termination structure such as a floating guard ring structure, a field plate structure, a RESURF structure, or a combination thereof as shown in the sectional view of the planar junction termination structure in FIG. This has been improved.
However, since the surface of the planar junction termination structure 21 is planarly the same surface as the active portion 10 surface and is often formed around the active portion, the junction termination occupies the entire area of the chip. When the area ratio of the structure is increased, the area ratio of the active portion through which the effective current flows becomes relatively small, which is disadvantageous in terms of electrical characteristics and price. This tendency becomes more remarkable as the chip has a smaller area.

図２に、従来のトレンチを有する耐圧構造（接合終端構造）の半導体装置の要部断面図を示す。この半導体装置は高不純物濃度の半導体基板１１上に反対導電型で低不純物濃度のエピタキシャル層１２を形成することにより設けられるｐｎ主接合を有する半導体ウェハ５０の主表面から、前記ｐｎ主接合の深さを超える深さの傾斜溝１５をトレンチ技術またはエッチング技術などにより形成し、前記傾斜溝１５表面のドリフト層１２（前記エピタキシャル層）に、ドリフト層１２のドーズ量の１０倍以上のドーズ量を有する反対導電型の表面層１４を形成して、前記ドリフト層１２の両面の形成されている高濃度層１１、１３を繋ぐように形成することにより、ｐｎ主接合への逆バイアス印加により形成される空乏層を主表面の接合終端部に延ばして耐圧を確保することは知られている（特許文献１）。同様な発明の記載は他の特許文献にもある（特許文献２−図１５、図２４）。しかし、いずれの発明もチップ全面積に占める接合終端構造面積の比率を改善していない。
特開平２−２２８６９号公報 特開２００１−１８５７２７号公報 FIG. 2 is a cross-sectional view of a main part of a conventional semiconductor device having a breakdown voltage structure (junction termination structure) having a trench. This semiconductor device has a depth of the pn main junction from a main surface of a semiconductor wafer 50 having a pn main junction provided by forming an epitaxial layer 12 having a low impurity concentration of opposite conductivity type on a semiconductor substrate 11 having a high impurity concentration. An inclined groove 15 having a depth exceeding the depth is formed by a trench technique or an etching technique, and a dose amount of 10 times or more the dose amount of the drift layer 12 is applied to the drift layer 12 (the epitaxial layer) on the surface of the inclined groove 15. By forming the surface layer 14 of the opposite conductivity type and having the high-concentration layers 11 and 13 formed on both sides of the drift layer 12 connected to each other, it is formed by applying a reverse bias to the pn main junction. It is known that a depletion layer is extended to the junction termination portion on the main surface to ensure a breakdown voltage (Patent Document 1). Similar inventions are described in other patent documents (Patent Documents 2 to 15 and 24). However, none of the inventions improve the ratio of the junction termination structure area to the total chip area.
JP-A-2-22869 JP 2001-185727 A

本発明は、以上述べた点に鑑みてなされたものであり、接合終端構造内でブレークダウンを起こす電界に到達することなく活性部のｐｎ主接合による設計耐圧を確保すると共に、チップ全面積に占める接合終端構造面積の比率を小さくできる半導体装置の提供を目的とする。   The present invention has been made in view of the above points, and ensures the design breakdown voltage by the pn main junction of the active portion without reaching the electric field causing breakdown in the junction termination structure, and reduces the total chip area. An object of the present invention is to provide a semiconductor device capable of reducing the ratio of the area of the junction termination structure.

本発明によれば、第一導電型の高不純物濃度層と、該層に接する第一導電型の低不純物濃度層と、この第一導電型の低不純物濃度層の表面に形成される第二導電型の高不純物濃度層を少なくとも備え、前記第一導電型の低不純物層と第二導電型の高不純物層からなるｐｎ主接合の活性部を備え、前記第二導電型の高不純物濃度層の表面から前記第一導電型の高不純物濃度層に至る傾斜溝を前記活性部の周囲に環状に備える半導体装置において、前記傾斜溝の側壁の前記第一導電型の低不純物濃度層の表面に沿って、前記傾斜溝の側壁の単位表面積あたりの不純物の総ドーズ量をＤ、前記第一導電型の低不純物濃度層の、不純物濃度をＮ、厚さをｔとしたとき、前記総ドーズ量Ｄが０．１Ｎｔ＜Ｄ＜１０Ｎｔの範囲にある第二導電型の低不純物領域が前記第一導電型と第二導電型の両高不純物層間を繋ぐように形成され、前記傾斜溝内は酸化膜で充填され、前記第二導電型の高不純物層に接する電極が前記傾斜溝内の酸化膜に接しかつ該傾斜溝を跨いで形成されている半導体装置とすることにより、達成される。
本発明によれば、第一導電型の高不純物濃度層と、該層に接する第一導電型の低不純物濃度層とが、それぞれ第二導電型の高不純物濃度を有する半導体基板上にエピタキシャル成長させた第一導電型の不純物濃度層である特許請求の範囲の請求項１記載の半導体装置とすることが好ましい。 According to the present invention, the first conductivity type high impurity concentration layer, the first conductivity type low impurity concentration layer in contact with the layer, and the second conductivity type low impurity concentration layer formed on the surface of the first conductivity type low impurity concentration layer. A high impurity concentration layer of the second conductivity type , comprising at least an active portion of a pn main junction comprising the low impurity layer of the first conductivity type and the high impurity layer of the second conductivity type; In a semiconductor device having an inclined groove extending from the surface of the first conductive type to the high impurity concentration layer of the first conductivity type around the active portion, on the surface of the low impurity concentration layer of the first conductivity type on the side wall of the inclined groove Along with the above, when the total dose amount of impurities per unit surface area of the sidewall of the inclined groove is D, the impurity concentration of the low impurity concentration layer of the first conductivity type is N, and the thickness is t, the total dose amount Low impurity of the second conductivity type in which D is in the range of 0.1 Nt <D <10 Nt Pass is formed so as to connect both high impurity layers of the first conductivity type and the second conductivity type, the inclined groove is filled with an oxide film, the electrode is the slope in contact with the high impurity layer of the second conductivity type This is achieved by forming a semiconductor device in contact with the oxide film in the trench and straddling the inclined trench .
According to the present invention, the first conductivity type high impurity concentration layer and the first conductivity type low impurity concentration layer in contact with the layer are epitaxially grown on the semiconductor substrate having the second conductivity type high impurity concentration, respectively. Preferably, the semiconductor device according to claim 1 is an impurity concentration layer of the first conductivity type.

本発明によれば、傾斜溝の側壁がパシベーション処理されている特許請求の範囲の請求項1または２記載の半導体装置とすることが望ましい。
本発明によれば、パシベーション処理が気相成長酸化膜の形成を含む特許請求の範囲の請求項３記載の半導体装置とすることがより望ましい。
本発明によれば、半導体装置がダイオードである特許請求の範囲の請求項1乃至４のいずれか一項に記載の半導体装置とすることが好ましい。
本発明によれば、半導体装置がＩＧＢＴである特許請求の範囲の請求項1乃至４のいずれか一項に記載の半導体装置とすることが好適である。 According to the present invention, it is desirable to provide the semiconductor device according to claim 1 or 2 in which the side wall of the inclined groove is passivated .
According to the present invention, it is more desirable to make the semiconductor device according to claim 3 in which the passivation treatment includes formation of a vapor growth oxide film.
According to the present invention, the semiconductor device is preferably a semiconductor device according to any one of claims 1 to 4 wherein the semiconductor device is a diode.
According to the present invention, it is preferable that the semiconductor device is an IGBT according to any one of claims 1 to 4.

本発明によれば、前述の構成としたので、接合終端構造内でブレークダウンを起こす電界に到達することなく活性部のｐｎ主接合の設計耐圧を確保すると共に、チップ全面積に占める接合終端構造面積の比率を小さくした半導体装置を提供することができる。 According to the present invention, since the above-described configuration is adopted, the design withstand voltage of the pn main junction of the active portion is ensured without reaching the electric field causing breakdown in the junction termination structure, and the junction termination structure occupies the entire chip area. A semiconductor device with a reduced area ratio can be provided.

本発明にかかる実施例について、図面を用いて詳細に説明する。本発明は以下説明する実施例に限定されるものではない。図１は本発明にかかる接合終端構造における等電位線を示す断面図、図３乃至図５は本発明にかかる半導体装置の製造方法を示す接合終端構造部分の断面図である。
図３乃至図５を用いて本発明にかかる半導体装置として、耐圧６００Ｖのダイオードの製造方法について、その接合終端構造部分２０を中心に説明する。充分に高不純物濃度のｎ型Ｓｉ半導体基板１上に、比抵抗３０Ω・ｃｍで、厚み７０μｍのエピタキシャル成長層（ｎ−層２）を形成する。このエピタキシャル成長層を有するＳｉ基板をＳｉエピタキシャルウェハ１００とする。このウェハ１００の前記エピタキシャル成長層側にボロンをイオン注入し、１１５０℃でドライブ拡散することにより、深さ３μｍのＰ＋アノード層３を形成する。残りのｎ−層２はドリフト層となる。前記Ｐ＋アノード層３のドライブ拡散は酸化雰囲気中で行われるので、同時にこのアノード層３表面に厚さ１．６μｍの熱酸化膜４が形成される（図３（ａ））。次に前記Ｓｉエピタキシャルウェハ１００内に形成される複数ダイオードチップの各表面パターンの周辺に位置する耐圧構造部２０（接合終端構造）に相当する酸化膜４の部分に環状の窓開けを行い、さらに残る酸化膜４をマスクとして前記窓開け部から公知のＳｉエッチング技術、トレンチ形成技術などにより、テーパ角付きで、深さ８０μｍのトレンチ５を形成する（図３（ｂ））。前記テーパ角付きトレンチ５は底部の幅が入口の幅より狭い形状になるようにテーパ角を付けることが好ましい。続いて前記トレンチ５の側壁にドーズ量Ｄが１×１０１２ｃｍ−２のボロンをイオン注入し、ドライブ拡散して表面濃度５×１０１５ｃｍ−３のｐ−層６を、トレンチ５内に露出したＰ＋アノード層３とｎ＋層１の間のｎ−層２（ドリフト層）の側壁に沿って形成する。前記ドライブ拡散によるｐ−層６の形成と同時にその表面には、厚さ０．８μｍのＳｉ熱酸化膜４が成長する（図４（ａ））。ＣＶＤ酸化膜７を前記トレンチ５の溝内およびＳｉエピタキシャルウェハ１００の主表面上に堆積させる（図４（ｂ））。次にこのＣＶＤ酸化膜７をエッチバックする。前記ＣＶＤ酸化膜７と前記熱酸化膜４におけるエッチング速度差を利用して、前記Ｓｉエピタキシャルウェハ１００の主表面上のＣＶＤ酸化膜７を完全に除去すると共に、熱酸化膜４を残すようにエッチバックすることが好ましい（図５（ａ））。Ｓｉエピタキシャルウェハ１００の裏面から全厚さ３５０μｍとなるまでバックラップした後、裏面からライフタイムキラーである白金を９００℃で拡散する。活性部１０内の電極部に相当する酸化膜４をフォトエッチングにより除去して、アルミニウム電極８をスパッタおよびフォトエッチングにより形成する。主表面上にポリイミド膜を保護膜として形成した後、裏面側にカソード電極９を蒸着により形成すると、ダイオードが完成する（図５（ｂ））。前記比抵抗３０Ω・ｃｍで、厚さ７０μｍのｎ−層のドーズ量Ｎｔは１×１０１２ｃｍ−２であるので、本発明にかかる、ドーズ量Ｄが１×１０１２ｃｍ−２の前記ｐ−層６は、特許請求の範囲の請求項１記載の０．１Ｎｔ＜Ｄ＜１０Ｎｔを満足する。前記ｐ−層６は前記ｎ−層２と同程度のドーズ量とすることにより完全空乏層化されるので、前記ｐ−層６の内部に電界が発生するようになる。前記ｐ−層６に発生する電界はｐｎ主接合に印加された逆バイアス電圧を負担するが、前記ｐ−層６が空乏層化されていること、およびトレンチ５側壁とこの側壁に沿って形成されている前記ｐ−層６が共に傾斜していることかつそれらの沿面距離が共に垂直距離よりも長くなるので、図１の耐圧構造断面図に示す等電位線１０１で表した前記逆バイアス電界に示すように、等電位線１０１に大きい曲率を有する個所がなく全体的にほぼ平坦であると共に、活性部よりも前記ｐ−層６における等電位線１０１の密度が低く、前記ｐ−層６内の方が電界集中度が緩和されていることが分かる。さらに重要な点は、この半導体装置としてのダイオードチップの主表面上に延びる空乏層がないので、主表面に占めていた従来のような耐圧構造（接合終端構造）を無くすことができる。本発明にかかるダイオードの耐圧構造（接合終端構造）２０は実質的にはトレンチ幅と言うことができ、従来のトレンチを有するメサタイプの半導体装置と同程度の耐圧構造の占有面積にすることができる。ただし、前記ｐ−層６のドーズ量Ｄが前記ｎ−層２のドーズ量Ｎｔの１／１０以下になると、このｐ−層６は極めて空乏層化され易くなり、また、１０倍以上になると、ほとんど空乏層化されなくなり、いずれの場合もｐ−層６中の電界は不均一になって電界集中が発生し易くなり、ｐ−層６内またはその表面で、低い逆バイアス電圧でも局所的にブレークダウンを生じる臨界電界に達するので、活性部の接合により得られる耐圧以下の耐圧になってしまうので、好ましくなく、また、本発明にも含まれない。 Embodiments according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the examples described below. FIG. 1 is a sectional view showing equipotential lines in a junction termination structure according to the present invention, and FIGS. 3 to 5 are sectional views of a junction termination structure portion showing a method for manufacturing a semiconductor device according to the present invention.
A method for manufacturing a diode having a withstand voltage of 600 V as a semiconductor device according to the present invention will be described with reference to FIGS. An epitaxial growth layer (n − layer 2) having a specific resistance of 30 Ω · cm and a thickness of 70 μm is formed on a sufficiently high impurity concentration n-type Si semiconductor substrate 1. The Si substrate having this epitaxial growth layer is defined as an Si epitaxial wafer 100. Boron ions are implanted into the epitaxial growth layer side of the wafer 100 and drive diffusion is performed at 1150 ° C. to form a P + anode layer 3 having a depth of 3 μm. The remaining n − layer 2 becomes a drift layer. Since the drive diffusion of the P + anode layer 3 is performed in an oxidizing atmosphere, a 1.6 μm thick thermal oxide film 4 is simultaneously formed on the surface of the anode layer 3 (FIG. 3A). Next, an annular window is opened in a portion of the oxide film 4 corresponding to the breakdown voltage structure 20 (junction termination structure) located around each surface pattern of the plurality of diode chips formed in the Si epitaxial wafer 100, and Using the remaining oxide film 4 as a mask, a trench 5 having a taper angle and a depth of 80 μm is formed from the window opening portion by a known Si etching technique, trench forming technique, or the like (FIG. 3B). The taper angled trench 5 preferably has a taper angle so that the bottom width is narrower than the width of the inlet. Subsequently, boron having a dose D of 1 × 10 12 cm −2 is ion-implanted into the sidewall of the trench 5, and drive diffusion is performed to form a p − layer 6 having a surface concentration of 5 × 10 15 cm −3 in the trench 5. It is formed along the sidewall of the n − layer 2 (drift layer) between the exposed P + anode layer 3 and the n + layer 1. Simultaneously with the formation of the p − layer 6 by the drive diffusion, a Si thermal oxide film 4 having a thickness of 0.8 μm is grown on the surface (FIG. 4A). A CVD oxide film 7 is deposited in the trench 5 and on the main surface of the Si epitaxial wafer 100 (FIG. 4B). Next, the CVD oxide film 7 is etched back. Using the etching rate difference between the CVD oxide film 7 and the thermal oxide film 4, the CVD oxide film 7 on the main surface of the Si epitaxial wafer 100 is completely removed and etched so as to leave the thermal oxide film 4. It is preferable to back (FIG. 5A). After back-wrapping from the back surface of the Si epitaxial wafer 100 to a total thickness of 350 μm, platinum as a lifetime killer is diffused from the back surface at 900 ° C. The oxide film 4 corresponding to the electrode part in the active part 10 is removed by photoetching, and the aluminum electrode 8 is formed by sputtering and photoetching. After the polyimide film is formed on the main surface as a protective film, the cathode electrode 9 is formed on the back surface side by vapor deposition to complete the diode (FIG. 5B). Since the dose Nt of the n - layer having a specific resistance of 30 Ω · cm and a thickness of 70 μm is 1 × 10 12 cm −2 , the p of the dose D according to the present invention is 1 × 10 12 cm −2 . The layer 6 satisfies 0.1 Nt <D <10 Nt as claimed in claim 1. Since the p − layer 6 has a dose almost equal to that of the n − layer 2, an electric field is generated inside the p − layer 6. The electric field generated in the p − layer 6 bears the reverse bias voltage applied to the pn main junction, but the p − layer 6 is depleted and formed along the trench 5 side wall and this side wall. Since the p - layers 6 are inclined together and their creepage distances are both longer than the vertical distance, the reverse bias electric field represented by the equipotential line 101 shown in the sectional view of the breakdown voltage structure of FIG. as shown in, the location having a greater curvature to the equipotential lines 101 are generally substantially flat rather than active portion the p - low density of equipotential lines 101 in the layer 6, the p - layer 6 It can be seen that the electric field concentration is relaxed in the inside. More importantly, since there is no depletion layer extending on the main surface of the diode chip as the semiconductor device, the conventional breakdown voltage structure (junction termination structure) occupied on the main surface can be eliminated. The diode withstand voltage structure (junction termination structure) 20 according to the present invention can be said to be substantially a trench width, and can have an occupation area of a withstand voltage structure comparable to that of a conventional mesa type semiconductor device having a trench. . However, the p - becomes the following layers 2 dose Nt 1/10, the p - - dose D of the layer 6 is the n layer 6 becomes easy to be extremely depleted, also becomes more than 10 times In any case, the electric field in the p − layer 6 becomes non-uniform and electric field concentration is likely to occur. In either case or in the surface of the p − layer 6, even at a low reverse bias voltage, Since the critical electric field that causes breakdown is reached, the breakdown voltage is lower than the breakdown voltage obtained by the junction of the active part, which is not preferable and is not included in the present invention.

前述のダイオードで６００Ｖの耐圧クラスの場合、主平面における接合終端構造（耐圧構造）の幅（距離）は５００μｍ必要であったが、本発明によれば、５０μｍ幅に減少させることができた。たとえば、活性部面積が４ｍｍ角で、面積１６ｍｍ２の場合、耐圧構造を活性部の周囲に５００μｍの幅で設けると、チップ全面積は５．０ｍｍ角の面積２５．００ｍｍ２であるが、活性部が同面積（４ｍｍ角で、面積１６ｍｍ２）で、耐圧構造部を５０μｍ幅で同様に設けると、チップ全面積は４．１０ｍｍ角の面積約１６．８１ｍｍ２となり、元のチップ面積の約６７％に縮小できる。
またさらに、前記トレンチ５の底部が高不純物層に達していて空乏層の延びを抑えているため、空乏層がトレンチ５を越えて外側のスクライブ領域３０にまで拡がることは無く、耐圧の安定度および信頼性が高い。本発明にかかる半導体装置によれば、活性部の主接合下でブレークダウンが起きるようになっている限り、前記トレンチ５側壁のｐ−層６中の不純物濃度に多少のバラツキがあっても、半導体装置の主接合による設計耐圧を確保することができる。 In the case of the above-mentioned diode with a withstand voltage of 600 V, the width (distance) of the junction termination structure (withstand voltage structure) in the main plane needs to be 500 μm, but according to the present invention, the width could be reduced to 50 μm. For example, in the case where the active part area is 4 mm square and the area is 16 mm 2 , if the pressure-resistant structure is provided with a width of 500 μm around the active part, the total chip area is 5.0 mm square area 25.00 mm 2. If the part has the same area (4 mm square, area 16 mm 2 ) and the pressure-resistant structure part is similarly provided with a width of 50 μm, the total chip area is about 4.81 mm square, which is about 16.81 mm 2 . It can be reduced to 67%.
Furthermore, since the bottom of the trench 5 reaches the high impurity layer and the extension of the depletion layer is suppressed, the depletion layer does not extend beyond the trench 5 to the outer scribe region 30, and the stability of the breakdown voltage. And reliable. According to the semiconductor device of the present invention, as long as breakdown occurs under the main junction of the active part, even if there is some variation in the impurity concentration in the p − layer 6 on the side wall of the trench 5, The design breakdown voltage due to the main junction of the semiconductor device can be ensured.

また、以上、エピタキシャルウェハを用いたダイオードの場合について説明したが、高濃度のｐ＋半導体基板上にｎ＋層、とｎ−層の２段にエピタキシャル成長させた層を備えるＳｉウェハのｎ−層上に、トレンチを有するＭＯＳ構造を形成してなるＰＴ型の縦型ＩＧＢＴに、前述した本発明にかかる耐圧構造（接合終端構造）を適用することにより、ＩＧＢＴにも、全チップ面積に対する接合終端構造の面積比率を小さくした素子を同様にして作製することができる。同様にＭＯＳＦＥＴにも適用できる。その他、ＦＺウェハを用いたダイオード、ＢＪＴにも適用可能である。 In the above, the description has been given of the diode using the epitaxial wafer, a high concentration of the p + semiconductor substrate on the n + layer, the n - of the Si wafer comprising a layer epitaxially grown on the 2-stage layer n - layer Further, by applying the above-mentioned breakdown voltage structure (junction termination structure) according to the present invention to a PT type vertical IGBT formed by forming a MOS structure having a trench, the junction termination for the entire chip area is also applied to the IGBT. An element with a reduced area ratio of the structure can be similarly manufactured. Similarly, it can be applied to a MOSFET. In addition, the present invention can also be applied to a diode using an FZ wafer and BJT.

図１は本発明にかかる接合終端構造における等電位線を示す断面図、FIG. 1 is a sectional view showing equipotential lines in a junction termination structure according to the present invention, 従来のトレンチを有する半導体装置の接合終端構造の断面図、Sectional drawing of the junction termination structure of the semiconductor device which has the conventional trench, 本発明にかかるダイオードの製造方法を示す接合終端構造の断面図、Sectional drawing of the junction termination | terminus structure which shows the manufacturing method of the diode concerning this invention, 本発明にかかるダイオードの製造方法を示す接合終端構造の断面図、Sectional drawing of the junction termination | terminus structure which shows the manufacturing method of the diode concerning this invention, 本発明にかかるダイオードの製造方法を示す接合終端構造の断面図、Sectional drawing of the junction termination | terminus structure which shows the manufacturing method of the diode concerning this invention, 従来のプレーナ型半導体装置の接合終端構造の断面図である。It is sectional drawing of the junction termination structure of the conventional planar type semiconductor device.

符号の説明Explanation of symbols

１ ｎ＋半導体基板
２ ｎ−層（ドリフト層）
３ ｐ＋層（アノード層）
４ Ｓｉ酸化膜
５ トレンチ
６ ｐ−層
７ ＣＶＤ酸化膜
８ アルミニウム電極
９ 金属電極
１０ 活性層
２０ 耐圧構造（接合終端構造）
３０ スクライブ領域
１００ Ｓｉウェハ。

1 n + semiconductor substrate 2 n − layer (drift layer)
3 p + layer (anode layer)
4 Si oxide film 5 Trench 6 p - layer 7 CVD oxide film 8 Aluminum electrode 9 Metal electrode 10 Active layer 20 Withstand voltage structure (junction termination structure)
30 Scribe area 100 Si wafer.

Claims (6)

第一導電型の高不純物濃度層と、該層に接する第一導電型の低不純物濃度層と、この第一導電型の低不純物濃度層の表面に形成される第二導電型の高不純物濃度層を少なくとも備え、前記第一導電型の低不純物層と第二導電型の高不純物層からなるｐｎ主接合の活性部を備え、前記第二導電型の高不純物濃度層の表面から前記第一導電型の高不純物濃度層に至る傾斜溝を前記活性部の周囲に環状に備える半導体装置において、前記傾斜溝の側壁の前記第一導電型の低不純物濃度層の表面に沿って、前記傾斜溝の側壁の単位表面積あたりの不純物の総ドーズ量をＤ、前記第一導電型の低不純物濃度層の、不純物濃度をＮ、厚さをｔとしたとき、前記総ドーズ量Ｄが０．１Ｎｔ＜Ｄ＜１０Ｎｔの範囲にある第二導電型の低不純物領域が前記第一導電型と第二導電型の両高不純物層間を繋ぐように形成され、前記傾斜溝内は酸化膜で充填され、前記第二導電型の高不純物層に接する電極が前記傾斜溝内の酸化膜に接しかつ該傾斜溝を跨いで形成されていることを特徴とする半導体装置。 The first conductivity type high impurity concentration layer, the first conductivity type low impurity concentration layer in contact with the layer, and the second conductivity type high impurity concentration formed on the surface of the first conductivity type low impurity concentration layer An active portion of a pn main junction comprising at least a first conductivity type low impurity layer and a second conductivity type high impurity layer, and the first conductivity type high impurity concentration layer from the surface of the first conductivity type In the semiconductor device having an inclined groove reaching the high impurity concentration layer of the conductive type around the active portion , the inclined groove along the surface of the low impurity concentration layer of the first conductivity type on the side wall of the inclined groove. When the total dose of impurities per unit surface area of the side wall of the first conductivity type is D, the impurity concentration of the first conductivity type low impurity concentration layer is N, and the thickness is t, the total dose D is 0.1 Nt < A low impurity region of the second conductivity type in the range of D <10 Nt So as to connect the mold and both high impurity layers of the second conductivity type, the inclined groove is filled with an oxide film, the oxide film of the second conductivity type high impurity layer electrode the inclined groove in contact with the A semiconductor device characterized by being formed in contact with and straddling the inclined groove . 第一導電型の高不純物濃度層と、該層に接する第一導電型の低不純物濃度層とが、それぞれ第二導電型の高不純物濃度を有する半導体基板上にエピタキシャル成長させた第一導電型の不純物濃度層であることを特徴とする請求項１記載の半導体装置。 A first conductivity type high impurity concentration layer and a first conductivity type low impurity concentration layer in contact with the layer are epitaxially grown on a semiconductor substrate having a second impurity conductivity type high impurity concentration, respectively. 2. The semiconductor device according to claim 1, wherein the semiconductor device is an impurity concentration layer. 傾斜溝の側壁がパシベーション処理されていることを特徴とする請求項1または２記載の半導体装置。 3. The semiconductor device according to claim 1, wherein a side wall of the inclined groove is passivated. パシベーション処理が気相成長酸化膜の形成を含むことを特徴とする請求項３記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the passivation treatment includes formation of a vapor growth oxide film. 半導体装置がダイオードであることを特徴とする請求項1乃至４のいずれか一項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor device is a diode. 半導体装置がＩＧＢＴであることを特徴とする請求項1乃至４のいずれか一項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor device is an IGBT.
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