TWI692866B - Semiconductor element, semiconductor substrate and semiconductor element manufacturing method - Google Patents

Abstract

A semiconductor device includes: a substrate having a first surface and a second surface; a concave portion formed on the first surface; and a first doped region formed by the concave portion The first surface is formed in the substrate by thermal diffusion, wherein the shortest distance between the portion of the first doped region corresponding to the recess and the second surface is smaller than that of the first doped region corresponding to the first surface The shortest distance between the non-recessed portion and the second surface.

Description

Semiconductor element, semiconductor substrate and semiconductor element manufacturing method

The invention relates to a semiconductor element, a substrate for manufacturing the semiconductor element, and a method for manufacturing the semiconductor element, in particular to a semiconductor element with a recess, a substrate for manufacturing the semiconductor element with a recess, and the A method for manufacturing a semiconductor element in a recess.

A conventional PN diode structure is to drive P doping (such as boron or other group III A elements) and N doping (such as phosphorus or other group IV A elements) by thermal diffusion treatment on both sides of the substrate. In the drive-in substrate, this process requires a long time and high temperature, so the energy consumption is extremely high, which is the most energy-consuming stage in the entire manufacturing process of the diode element. In general, in the thermal diffusion process of doping drive, the temperature is usually higher than 1100 degrees Celsius, the time is often more than 150 hours, and the driving depth of P doping or N doping can only reach about 150 ~ 180 microns ( μm).

In order to maintain a certain mechanical strength of the wafer to avoid cracking or breaking during device manufacturing, the industry's actual process usually requires a 4-inch wafer to have a thickness of at least 350 to 400 microns to avoid fragmentation during the process Cause yield reduction.

In general, the maximum depth of thermal diffusion of phosphorus doping and boron doping is about 150 microns. If the thickness of the wafer is greater than 300 microns, the thermal diffusion of phosphorus doping and boron doping on both sides of the wafer will be Leaving a region that is not doped by secondary high temperature drive area. The thickness of the wafer minus the diffusion depth of phosphorus doping and boron doping is the thickness or width of the non-secondary doped region. This value is also called the base width.

According to Poisson's equation, the charge concentration and base width of the PN junction will affect the voltage performance of the diode element. On the other hand, the non-secondary doped region is the region with the highest impedance among the diode elements. In addition to supporting the voltage, it will also cause the impedance of current conduction. In other words, the larger the base width, the higher the conduction energy loss when the diode element works. Therefore, when designing the device structure, the base width must be strictly controlled to control the characteristics of the forward voltage (V _F ) and reverse voltage (V _R ) of the diode device. In the conventional technology, an epi wafer is generally used to form a lower doped epi layer on a thicker doped substrate to provide sufficient substrate thickness (mechanical strength) ), and set the base width (the thickness of the epitaxial semiconductor layer is the doping depth plus the base width that supports the set reverse bias) to support the voltage performance and the lowest impedance of the device.

In addition, for the design of diode devices with fast recovery characteristics, a common way is to dope the life cycle killer of the carrier into the device so that it is distributed near the PN junction In the region, when the diode element switches from forward bias mode to reverse bias mode, the life cycle killer of the carrier doped in the element can accelerate the recombination of the remaining charges (ie, electrons and holes) near the PN junction. This shortens the time required for the current to be completely cut off, that is, the reverse recovery time.

Carrier life cycle killer doping is generally doping platinum (Pt) or gold (Au) from the wafer surface (P-doped or N-doped surface) by thermal diffusion. Since the residual charge mainly exists near the PN junction, in order to effectively accelerate the recombination of the residual charge in the diode, platinum or gold doping must also be distributed near the PN junction. Therefore, with Diode components with deeper PN junctions require higher temperature thermal diffusion treatment, which is enough to move the higher concentration carrier life cycle killer to the deeper PN junction, so that it accelerates the electrons and holes. complex. On the contrary, if the carrier life cycle killer cannot be driven to a sufficient depth, the reverse recovery time of the diode element cannot be effectively shortened.

In summary, for the manufacture of diode devices, in order to maintain the mechanical strength and process yield, the wafer substrate must have a certain thickness. If you want to reduce the base width to reduce the resistance of the device, you must increase the heat. The temperature and/or time of the diffusion process enables the doping to be driven to a sufficient depth, which not only makes the process very energy-intensive, but also not conducive to further shortening the diode element with the killer of the doping carrier life cycle Reverse reply time. Therefore, in the past, when designing diode components, these limitations could not be overcome. They could only be compromised according to the situation, and they lacked the flexibility to control the parameters of the components.

In view of the problems existing in the prior art, the present invention proposes a diode element with a recessed structure. The manufacturing method is to form a recessed portion on a wafer substrate before performing a thermal diffusion process. Therefore, in the region corresponding to the recess, the distance between the P-doped region and the N-doped region is shortened, thereby equivalently reducing the base width of the entire device. In other words, only shallower P and N doped regions are needed to obtain voltage/current performance equivalent to conventional diode devices without recesses, which can greatly reduce the energy consumption required for thermal diffusion treatment.

An aspect of the present invention is to provide a semiconductor device including a substrate having a first surface and a second surface with a concave portion on the first surface; the semiconductor device also includes a first doped region, The first doped region is formed in the substrate by thermal diffusion treatment on the first surface having the recess, so that the The shortest distance between the portion of the first doped region corresponding to the recess and the second surface is less than the shortest distance between the portion of the first doped region corresponding to the non-recessed portion of the first surface and the second surface. In this semiconductor device, a second doped region may be further included, which is formed in the substrate by thermal diffusion treatment on the second surface. Furthermore, the recess can be, for example, a cylindrical space.

Another aspect of the present invention is to provide a semiconductor substrate for manufacturing a plurality of semiconductor devices, which includes a wafer having a first surface and a second surface; and includes a plurality of concave portions, which are processed by etching Formed on the first surface, the positions of the recesses correspond to the positions (or specific relative positions) of the diode elements to be manufactured. In this semiconductor substrate, the recesses may be, for example, cylindrical spaces.

Using the semiconductor substrate as described in the previous paragraph, another aspect of the present invention is to provide a method for manufacturing a semiconductor element, the steps of which include performing thermal diffusion treatment on the first surface of the semiconductor substrate to form a first in the semiconductor substrate A doped region, the shortest distance between the portion of the first doped region corresponding to the recesses and the second surface is less than the shortest distance between the portion of the first doped region corresponding to the non-recessed portion of the first surface and the second surface distance. In the manufacturing method of the semiconductor device described herein, before or after the formation of the first doped region, by performing thermal diffusion treatment on the second surface of the semiconductor substrate, a second A doped region, and further after forming the first doped region and the second doped region, by performing thermal diffusion treatment on the first or second surface of the semiconductor substrate, the carrier life cycle killer is Drive into the semiconductor substrate.

Therefore, according to the present invention, at least the following unexpected effects can be achieved: (1) By appropriately designing the geometry of the recess, such as shape, depth, width, etc., the diode can be controlled more effectively and more elastically The voltage/current characteristics of the device can also be used to adjust other steps or conditions in the manufacturing process more flexibly; (2) Adding a recess structure to the traditional diode device can reduce the forward voltage V _{F of the} diode device. It can reduce the energy transmission loss of the element; (3) The diode element with a concave structure can reach a voltage equivalent to the diode element without a concave structure when the P and N doping depths are relatively shallow / Current characteristics, so it can reduce the energy consumption of the device during thermal diffusion treatment and reduce the time required for thermal diffusion treatment, thereby improving production efficiency; (4) If the concave structure is applied to the rapid recovery diode, due to the PN junction The depth of the carrier is relatively shallow, and the driving depth required by the carrier life cycle killer is also reduced, which shortens the time and temperature of the thermal diffusion treatment of the carrier life cycle killer, and can shorten the reverse recovery time of the diode element; (5) Adding the concave structure still maintains sufficient mechanical strength of the wafer to avoid fragmentation during the manufacturing process. In other words, while achieving the above-mentioned effects, there is no need to sacrifice mechanical strength and process yield. In addition, when a PN diode device with a concave structure is subjected to a glass passivation process (GPP), the depth of the trench to be formed is relatively shallow, which can also relatively improve the mechanical strength of the wafer and the yield of the process.

1‧‧‧Semiconductor substrate

2‧‧‧ Wafer

10‧‧‧recess

11‧‧‧First doped region

12‧‧‧Second doped region

13‧‧‧First doped region

14‧‧‧Second doped region

15‧‧‧ Carrier life cycle killer drives deeper

16‧‧‧groove

20‧‧‧recess

101‧‧‧First recess

102‧‧‧Second recess

D1‧‧‧Distance

D2‧‧‧Distance

FIG. 1 is a schematic diagram of a partial structure of a conventional diode device; FIG. 2(a) is a schematic diagram of a semiconductor substrate with recesses of the present invention; FIG. 2(b) is a partial structure of a diode device of the present invention with recesses 2(c) is a partial structure diagram of a diode element with two recesses according to the present invention FIG. 3 is a schematic diagram of a wafer with a plurality of recesses of the present invention; FIG. 4(a) is a schematic diagram of a prior art diode device structure used for computer simulation; FIG. 4(b) is used for computer A schematic diagram of the structure of the diode element of the present invention simulated; FIG. 4(c) is a schematic diagram of another prior art diode element structure used for computer simulation; FIG. 5 is FIG. 4(a), (b) , (C) The computer simulation results of the forward voltage of the structure shown in Figure 6; Figure 6 is the computer simulation results of the reverse voltage of the structure shown in Figure 4 (a), (b), (c); Figure 7 is based on The schematic diagram of the invention's diode structure is driven by the killer of the carrier life cycle; Figure 8 is a schematic diagram of the invention's diode structure subjected to glass passivation treatment.

The specific embodiments of the present invention will be described in conjunction with the drawings as follows. The structure or geometric relationship presented in the drawings is for illustrative purposes only, and does not represent the structure or geometry of the actual device or element, nor is it used to limit all components of the device or element. For example, the doping concentration of the P and N doped regions formed in the semiconductor substrate by thermal diffusion treatment is not uniformly distributed, and in fact there is no obvious boundary with the undoped regions in the substrate. However, if a critical value of the doping concentration is set, the boundary of the doping area can be defined. Similarly, because the geometry or structure of the doped region is not easy to describe in words, when describing the doped region (such as in the patent application), it is more appropriate to define it by the manufacturing method (such as thermal diffusion treatment) , Because the distribution of doping will depend on the properties of the doping and substrate materials, diffusion temperature and time, etc., which is commonly known It can be understood that those with ordinary knowledge in the technical field of the present invention can also easily deduce the corresponding device structure or geometry formed from the materials and process conditions.

FIG. 1 is a partial schematic diagram of a conventional diode device, wherein the semiconductor substrate 1 may be, for example, a silicon (Si) wafer, and a doped or undoped silicon wafer may be used. One manufacturing method of the conventional diode device is to perform P and N doping on the two surfaces of the semiconductor substrate 1 by thermal diffusion treatment to form the first doped region 11 and the second doped as shown in FIG. 1 Region 12. As mentioned above, if the yield is to be maintained and the distance (base width) of the P and N doped regions is sufficiently small, the P and N doping must be driven to a sufficient depth, that is, a large diffusion is required Depth to form a deep junction diode element. In this regard, FIG. 2 is a schematic diagram of a diode element and a manufacturing method thereof proposed by the present invention. Unlike the conventional diode structure of FIG. 1, the present invention forms a recess 10 in the semiconductor substrate 1, as shown in FIG. 2(a). Then, P and N doped thermal diffusion processes are performed on both surfaces of the semiconductor substrate 1 to form the first doped region 13 and the second doped region 14, as shown in FIG. 2(b).

As shown in FIG. 3, in the actual manufacturing process, the substrate with the recessed portion 10 is to etch the wafer 2 to form a plurality of recessed portions 20, and then perform other subsequent processes. Therefore, these recesses 20 may correspond to the position of each die.

As can be seen from FIG. 2(b), the structural feature of the diode of the present invention is mainly the distribution of the first doped region 13. Since the recess 10 is formed first and then the thermal diffusion process is performed, the first doped region 13 and the second doped region 14 will have a closer distance D2 in the portion corresponding to the recess, and D2 is smaller than the first doped region 13 and the second doped region The impurity region 14 is at a distance D1 corresponding to the non-recessed portion. In other words, the geometry of the recess 10 can control a portion of the distance between the first doped region 13 and the second doped region 14. It should be noted that the cross section of the concave portion 10 shown in FIG. 2 is rectangular, and the corresponding three-dimensional The structure may be a cylindrical space or a rectangular parallelepiped space, and the rectangular cross-section is only one embodiment of the concave portion 10 of the present invention. The cross-sectional shape is not limited to a rectangle, for example, it may be an inverted triangle or an inverted semicircle. In addition to the shape, the geometric dimensions (such as depth and width) can also be appropriately selected according to requirements, and those with ordinary knowledge in the technical field to which the present invention belongs can design appropriately. In addition, although FIG. 2 discloses that only one concave portion 10 is formed on one surface of the semiconductor substrate 1, it is also possible to form more than two concave portions on one surface of one diode element (grain) or both surfaces. The recesses are formed, and then doped thermal diffusion treatment is performed. For example, in the case where the lateral dimension of the diode element (horizontal direction in FIG. 2(b)) is large, if a single concave portion cannot satisfy the desired voltage characteristics and mechanical strength at the same time, it can be placed on a single grain More than two concave parts are formed, and each concave part can have the same or different geometric structure, thereby adding more design flexibility, and realizing the voltage characteristics and mechanical strength that cannot be taken into account by a single concave part. Fig. 2(c) presents a schematic diagram of a structure with two recesses in a single diode element. According to the requirement of carrier conduction or recombination, the two recesses can be designed to be spatially symmetric or asymmetric, and the two recesses can be Have the same or different shapes and geometric structures (the cross-section shown in FIG. 2(c), the first concave portion 101 and the second concave portion 102 are rectangular cross-sections, but the width may be different, and the two concave portions are relative to FIG. 2(c) The center points of the lateral direction may be asymmetrically set; if viewed from above in FIG. 2(c), the first concave portion 101 and the second concave portion 102 may be a specific distribution of different sizes).

In the embodiments of the present invention, the formation of recesses and the thermal diffusion treatment of doping are conventional semiconductor manufacturing technologies. Even though the process details and parameters are not described in detail in this specification, the technical field of the present invention has general knowledge They should be implemented based on conventional technology. For example, for a PN diode, the recess can be formed on the P-doped surface or the N-doped surface according to the device and process characteristics.

The diode element provided with recesses in the present invention can change the distribution of at least one doped region by forming recesses on the substrate, so that the characteristics of the diode element can be changed. The following will take the performance of voltage/current as an example to present the effect of the present invention on improving the characteristics of diode elements by way of computer simulation. 4(a) to 4(c) are element structures used for computer simulation: FIG. 4(a) is a diode element structure of the conventional technology; FIG. 4(b) is a diode with a recess in the present invention. For the structure of the polar body, the temperature and time of the thermal diffusion treatment of the doping are the same as those in FIG. 4(a); FIG. 4(c) is also the structure of the diode body of the conventional technology, but it is compared with FIG. 4(a) A higher temperature and longer time doping thermal diffusion process is used, so the doping diffusion depth is deeper and the base width is smaller compared to FIG. 4(a). In FIGS. 4(a) to 4(c), the units of the horizontal axis and the vertical axis are both micrometers, and the doping polarity of each element is shown in the figure. According to the three structures of FIG. 4(a) to FIG. 4(c), FIG. 5 is the forward bias characteristics obtained by computer simulation. It can be seen from FIG. 5 that the device structure of the present invention (FIG. 4(b)) can greatly reduce the forward voltage compared to the conventional diode device using the same doping and diffusion conditions (FIG. 4(a)). V _F (on-voltage drop in forward bias). Even if the doping diffusion depth in the conventional diode device is greatly increased (FIG. 4(c)), the V _{F is} still higher than that of the present invention. In other words, the diode element of the present invention having a concave portion can obtain a lower V _F under the same doping and diffusion conditions (equivalent to the same energy dissipation degree); and the conventional technology even if the doping diffusion depth is deeper ( Equivalent to more energy consumption), its effect of reducing V _F is still not as good as the present invention. On the other hand, FIG. 6 shows that the voltage/current characteristics of the device structure of the present invention when reverse-biased are not significantly different from the conventional technology. Based on the same principle, for those with ordinary knowledge in the technical field to which the present invention belongs, it can be expected that a diode element including more than two recesses (such as the one shown in FIG. 2(c)) will also have similar voltage/current characteristics, and Multiple recesses can increase the design flexibility, such as but not limited to: control of forward current density (current density is closely related to on-resistance), or improve die specificity through smaller recess design (or partial absence of recesses) The mechanical strength of the part.

As can be seen from the foregoing description, the diode element of the present invention having a recess can indeed improve (or at least change) the characteristics of the element. Therefore, in the actual device design process, with the help of computer simulation technology, the concave structure of the present invention can be changed according to the application field, expected device characteristics, process capability, cost, etc., to obtain a device that effectively achieves the purpose Structure and process condition parameters. In other words, for those with ordinary knowledge in the technical field to which the present invention belongs, a simple trial can determine the best or most suitable device structure and process condition parameters. In the actual manufacturing process, since the techniques of etching, thermal diffusion treatment, measurement of device structure and characteristics are all very mature, those with ordinary knowledge in the technical field of the present invention only need to simply try to realize the structure of the present invention and verify Its effect.

In addition to the voltage/current characteristics, the following further describes other functions of the diode element with recesses of the present invention.

In order to make the diode device have the characteristics of fast recovery, a common practice is to dope the carrier life cycle killer (such as gold or platinum) near the PN junction of the device. If the diode element structure with recesses shown in FIG. 2(b) is doped by the life-cycle killer of the carrier through thermal diffusion treatment, the structure shown in FIG. 7 can be formed; Respectively show the driving depth 15 of diffusion from two surfaces. The beneficial effects of the diode element of the present invention on carrier life cycle killer doping have at least two aspects. First, the concave structure on the surface allows the carrier life cycle killer to be more easily driven to the desired depth; second, the diode element with the concave structure can use a shallower PN doped region, so the carrier life cycle killer Correspondingly, it only needs to be driven to a shallow depth. In addition, the concave structure can be formed in a specific area and depth of the grain range, which also helps to dope the life cycle killer of the carrier to a specific location, generating the desired Specific die reverse recovery time and waveform. Therefore, in accordance with the foregoing description, in the present invention, by forming recesses on the diode element, in addition to controlling the conditions for forming recesses as needed (such as but not limited to: formed on the surface of P or N doping, the number of recesses, each The geometry of the recess, etc.), and can further control the doping conditions of the carrier life cycle killer (such as but not limited to: diffusion from the surface with or without the recess, diffusion from the P or N-doped surface, diffusion temperature And time, etc.) to achieve the desired device characteristics.

In the conventional diode manufacturing process, a glass passivation process (GPP) can be added, which mainly includes forming a trench and filling the glass to form the device structure shown in FIG. 8. Among them, the depth of the trench 16 for filling the glass is affected by the depth of the second doped region 14. As mentioned above, the diode element with recesses proposed by the present invention can reduce the depth of the second doped region 14, thereby reducing the depth required for the trench 16. The formation of shallow trenches during glass passivation, in addition to relatively improving the yield of the process, when using wet etching to form trenches, the deeper trenches tend to form a bird's beak on the top of the trench, causing the glass to adhere or The coating effect is not good, and the shallower groove can avoid these problems.

The above is only an example of the embodiments and effects of the present invention, and it is not exhaustive to list all possible changes. According to the concept of the present invention, those with ordinary knowledge in the technical field to which the present invention pertains can easily make various specific changes covered by the concept of the present invention by changing themselves according to the contents disclosed in this specification. The scope of rights claimed by the applicant is set out in the scope of patent application mentioned later, in which the meaning and the equal scope of each claim are covered by the scope of rights of this patent.

1‧‧‧Semiconductor substrate

10‧‧‧recess

13‧‧‧First doped region

14‧‧‧Second doped region

D1‧‧‧Distance

D2‧‧‧Distance

Claims (10)

A semiconductor device includes: a substrate having a first surface and a second surface; a first recessed portion formed on the first surface; and a first doped region by having the The first surface of the first recess is thermally diffused and formed in the substrate, wherein the shortest distance between the portion of the first doped region corresponding to the first recess and the second surface is smaller than the first doped region The shortest distance between the portion of the first surface other than the first recess and the second surface. The semiconductor device according to claim 1, further comprising: a second doped region formed in the substrate by thermal diffusion treatment on the second surface. The semiconductor device according to claim 1, wherein the first doped region is a P-doped region or an N-doped region. The semiconductor device according to claim 1, further comprising a second concave portion having the same or different geometric structure as the first concave portion, the second concave portion is formed symmetrically or asymmetrically with the first concave portion On the first surface. A semiconductor substrate for manufacturing a plurality of semiconductor elements includes: a wafer having a first surface and a second surface; and a plurality of first recesses formed on the first surface by etching process, The positions of the first recesses correspond to the positions of the diode elements to be manufactured. The semiconductor substrate for manufacturing a plurality of semiconductor devices according to claim 5 further includes a plurality of second recesses, which are formed on the first surface simultaneously with the first recesses by etching, and the positions of the second recesses correspond In the position of the diode elements to be manufactured. The semiconductor substrate for manufacturing a plurality of semiconductor elements according to claim 5, wherein the first concave portions are cylindrical or rectangular parallelepiped spaces. A method for manufacturing a semiconductor element using the semiconductor substrate of claim 5 includes: performing thermal diffusion treatment on the first surface of the semiconductor substrate to form a first doped region in the semiconductor substrate, wherein the first doping The shortest distance between the portion of the impurity region corresponding to the first recesses and the second surface is less than the shortest distance between the portion of the first doped region corresponding to the first surface that is not the first recesses and the second surface. The method of manufacturing a semiconductor device according to claim 8, further comprising: before or after forming the first doped region, by performing thermal diffusion treatment on the second surface of the semiconductor substrate, forming a first Two doped regions. The method for manufacturing a semiconductor device according to claim 8 or 9, further comprising: after forming the first doped region and the second doped region, by thermally diffusing the first or second surface of the semiconductor substrate Processing, so that the carrier life cycle killer (lifetime killer) is driven into the semiconductor substrate.

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