JP2003197921A - High withstand voltage semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a highly reliable semiconductor device with a high withstand voltage and a low on-voltage. <P>SOLUTION: An interval between the main electrode and termination area of an SiC semiconductor device is formed largely, and an aerial discharging start voltage between the main electrode and a termination area is increased. In addition, insulating gas with SF<SB>6</SB>(hexafluorosulfur) gas or SF<SB>6</SB>gas as main components is sealed into the package of the semiconductor device. When the pressure of the insulating gas is made higher than an atmosphere, the aerial discharging start voltage is much more increased. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device for controlling a large current, and more particularly to a high breakdown voltage power semiconductor device.

[0002]

2. Description of the Related Art Silicon carbide (SiC), which is a wide-gap semiconductor material, has excellent characteristics such as a dielectric breakdown electric field strength which is about 10 times higher than that of silicon (Si) and has a high reverse voltage resistance. It has attracted attention as a suitable material for high withstand voltage power semiconductor devices that require characteristics. As a conventional wide gap high withstand voltage semiconductor device using SiC,
For example, a SiC pn diode having a withstand voltage of about 12 kV shown in the cross-sectional view of FIG.
It is shown on pages 27 to 30 of the proceedings of ium on Power Semicondumctor Devices & ICs. Figure 9 shows SiCp
The cross section of the right half of the n-diode is shown in an enlarged manner, and the left half is line-symmetrical to the right half, and therefore is not shown.
In this conventional example, n having a cathode electrode 107 on the lower surface is used.
N-type drift layer 102 is formed on the upper surface of cathode region 101 of n-type SiC, and p is formed in the central portion of n-type drift layer 102.
The mold layer 103 is formed. The p-type layer 103 is provided with an anode contact electrode 108 made of a thin metal film having a good conductor. The anode contact electrode 108 is provided with an anode electrode 109 made of a metal film thickened to reduce electric resistance. Anode contact electrode 10
Titanium or the like having excellent adhesion to SiC is used for 8, and gold or the like having corrosion resistance is used for the anode electrode 109. A termination region T is provided in the end region of the p-type layer 103. The “termination region” means a peripheral region having a special structure in order to suppress electric field concentration in the peripheral portion of the high breakdown voltage semiconductor element. A p-type region 104 is formed at the left end of the termination region T, and an n-type channel stopper region 105 for preventing the depletion layer from spreading to the end of the n-type drift layer 102 is formed at the right end. . On the surface of this high withstand voltage diode, a passivation film 106 of a silicon dioxide film having a thickness of about 2 μm is provided for the surface protection except for the anode electrode 109.

FIG. 10 is a sectional view of a conventional SiC MOS field effect transistor (MOSFET). This MO
The chip size of the SFET is 4 mm (4
mm × 4 mm). In the figure, the n-type drift layer 2 is formed on a substrate that has a drain electrode 53 on the lower surface and serves as the n-type drain layer 11 having a high impurity concentration.
An n-type source layer 7 is formed in a part of the p-type body layer 33 partially formed on the n-type drift layer 2, and a trench (groove) 60 is formed in the p-type body layer 33. A gate 54 is formed in the trench 60 through the gate insulating layer 8.
Are formed. A source contact electrode 155 is provided on the p-type body layer 33 and the n-type source layer 7, and all the source contact electrodes 155 are connected to the source electrode 161 at the portion where the trench 60 does not exist.

FIG. 11 is a sectional view of a conventional SiC gate turn-off thyristor (GTO). In the figure, a low impurity concentration n-type drift layer 2 is formed on a high impurity concentration p-type SiC substrate that has an anode electrode 51 and functions as the anode layer 21. A p-type layer 22 is formed on the n-type drift layer 2, and an n-type cathode region 23 is formed on the entire surface of the p-type layer 22. Etching a predetermined portion of the n-type cathode region 23 to a depth reaching the p-type layer 22,
A gate electrode 54 is formed on the etched portion so as to be in contact with the p-type layer 22. All gate electrodes 54, 54,
54 ... are commonly connected at a position that cannot be seen in the cross section of FIG. A cathode contact electrode 159 is formed on the remaining n-type cathode region 23. Each cathode contact electrode 1 over all cathode contact electrodes 159
A cathode electrode 150 that contacts 59 is formed.

[0005]

SiC is suitable for increasing the withstand voltage of a semiconductor device because of its high dielectric breakdown electric field strength. However, a SiC single crystal substrate has a diameter of several μm called a micropipe. There are many crystal defects.
Therefore, if a semiconductor device having a large area is to be manufactured, the yield will deteriorate. The maximum area of a practical SiC semiconductor device is about 0.7 cm ² . Therefore, it is necessary to ensure a high reverse withstand voltage in such a semiconductor device having a relatively small area. Since the semiconductor device using SiC has a high dielectric breakdown electric field, which is about 10 times higher than that of Si,
The termination region T having a width shorter than that of the semiconductor device using Si has a reverse withstand voltage similar to that of the semiconductor device of Si. The reverse withstand voltage in such a semiconductor device is called "internal withstand voltage". The internal withstand voltage is substantially equal to the breakdown voltage.

In the SiC semiconductor device, it is desirable to increase the areas of the anode contact electrode 108 and the anode electrode 109 and to reduce the area of the termination region T as much as possible in order to increase the conduction area thereof as much as possible. However, in a semiconductor device having a small area, if the termination region T is reduced and the area of the anode electrode 109 is increased, the distance between the end portion R1 of the semiconductor device and the end portion R2 of the anode electrode 109 becomes shorter. As a result, there is a problem that the "external withstand voltage", which is the withstand voltage of the space between the end portion R1 near the potential of the cathode electrode 107 and the end portion R2 at the anode potential, becomes low, causing air discharge. For example, in the case of the SiC high breakdown voltage diode shown in FIG. 9, since the width of the termination region T is 500 μm, the distance between the ends R1 and R2 is also about 500 μm. Si is used as a filling gas for the package of this diode.
If nitrogen, which is commonly used for semiconductor devices, is used,
The breakdown electric field of nitrogen is 3.8 kV / mm, so 5
1.9kV which is the discharge start voltage at a distance of 00 microns
At (= 3.8 kV / mm × 0.5 mm), air discharge occurs. The withstand voltage of a semiconductor device is determined by the lower of the internal withstand voltage and the external withstand voltage.

As a method of increasing the external withstand voltage between the ends R1 and R2, it may be possible to cover the right side portion of the anode electrode 109 including the end R2 with a passivation film 106A as shown by a dotted line. The SiC semiconductor element is often used at a high temperature of 300 to 700 ° C., and the passivation film 106A must be a film made of a heat resistant material such as silicon dioxide. It is difficult to form silicon dioxide on a wall surface having a high level difference such as the end portion R2, and even if it can be formed, it may be cracked or peeled off depending on the temperature cycle during use, resulting in poor long-term reliability. There's a problem. Each of the above problems is related to the conventional M shown in FIG.
The same applies to the OSFET and the conventional GTO shown in FIG. An object of the present invention is to provide a semiconductor device having a relatively small area and high external withstand voltage.

[0008]

A high breakdown voltage semiconductor device of the present invention is a substrate of a wide-gap semiconductor having a high impurity concentration and having a first electrode on one surface, and a low-voltage semiconductor device formed on the other surface of the substrate. A drift layer of a wide-gap semiconductor having an impurity concentration, an active region generation layer of a wide-gap semiconductor formed on the drift layer, and at least one of the same conductivity type as the drift layer formed in an end region of the drift layer.
A termination region having two high impurity concentration regions, a second electrode formed on the active region generating layer, electrically connected to the second electrode, and provided with a predetermined distance from the termination region. And a surface protection film formed so as to cover the termination region and the second electrode. Since the third electrode is separated from the high-potential outer edge of the termination region, the air discharge start voltage between the third electrode and the outer edge becomes high.

According to another aspect of the present invention, there is provided a high withstand voltage semiconductor device having a substrate of a first conductivity type wide gap semiconductor having a high impurity concentration and having a first electrode on one surface, and the other surface of the substrate. Formed on the drift layer of the first conductivity type wide-gap semiconductor having a low impurity concentration, formed on the drift layer, the impurity concentration of a portion close to the drift layer, the portion far from the drift layer An active region generation layer of a second conductivity type wide-gap semiconductor having a high impurity concentration, and at least one high impurity concentration region of the same conductivity type as the drift layer formed in an end region of the drift layer. A termination region, a second electrode formed on the active region generating layer, electrically connected to the second electrode, and provided with a predetermined distance from the termination region. It was a third electrode, and the termination region and forming the surface protective film to cover the second electrode. The active region is widened by increasing the impurity concentration of the part of the active region generating layer far from the drift layer with respect to the impurity concentration of the part close to the drift layer.

According to another aspect of the present invention, there is provided a high withstand voltage semiconductor device having a first conductive type wide gap semiconductor substrate having a high impurity concentration and having a first electrode on one surface, and the other surface of the substrate. A low-concentration first-conductivity-type wide-gap semiconductor drift layer, a high-impurity-concentration second-conductivity-wide-gap semiconductor layer, and a drift layer formed on the drift layer. A termination region having at least one high impurity concentration region of the same conductivity type as the drift layer formed in the end region, a second electrode provided as a gate electrode on the drift layer via an insulating film, A region of high impurity concentration of the first conductivity type formed in the layer of the wide gap semiconductor of the second conductivity type in the vicinity of the second electrode, a layer of the wide gap semiconductor of the second conductivity type, and A contact electrode provided on the first conductivity type region near the second electrode and thickened to have high conductivity; contacting the contact electrode and maintaining a predetermined distance from the termination region. A surface protection film formed so as to cover the provided third electrode, the termination region, and the contact electrode. By thickening the contact electrode of the MOS field effect type semiconductor device and separating the third electrode from the termination region by a predetermined distance, the active region becomes wider and the withstand voltage becomes higher.

A high withstand voltage semiconductor device according to another aspect of the present invention is a substrate of a second conductivity type wide gap semiconductor having a high impurity concentration and having a first electrode on one surface, and the other surface of the substrate. A low-concentration first-conductivity-type wide-gap semiconductor drift layer having a low impurity concentration, a second-conductivity-type wide-gap semiconductor layer formed on the drift layer, and an end region of the drift layer. A formed termination region having at least one high impurity concentration region of the same conductivity type as the drift layer, a second electrode provided on the drift layer via an insulating film, and serving as a gate electrode, the second electrode A region of high impurity concentration of the first conductivity type formed in the layer of the second conductivity type wide gap semiconductor, the layer of the second conductivity type wide gap semiconductor, and the second electrode. A contact electrode that is provided on a region of the first conductivity type in the vicinity and is thickened so as to have high conductivity, and a third contact electrode that is in contact with the contact electrode and maintains a predetermined distance from the termination region. Electrode, and the surface protection film formed so as to cover the termination region and the contact electrode. By thickening the contact electrode of the insulated gate bipolar type semiconductor device and separating the third electrode from the termination region by a predetermined distance, the active region is expanded and the withstand voltage is increased.

According to another aspect of the present invention, there is provided a high withstand voltage semiconductor device having a second conductivity type wide gap semiconductor substrate having a high impurity concentration and having an anode electrode of the first electrode on one surface thereof. A drift layer of the first conductivity type wide gap semiconductor having a low impurity concentration formed on the other surface, a layer of the second conductivity type wide gap semiconductor formed on the drift layer, and an end of the drift layer. Termination region having at least one high impurity concentration region of the same conductivity type as the drift layer, the first conductivity type formed on the second conductivity type wide gap semiconductor layer. Is provided on the cathode region, the gate electrode of the second electrode formed on the layer of the second conductivity type wide gap semiconductor, and the cathode region, and is thickened to have high conductivity. Cathode contact electrode,
A cathode electrode of a third electrode that is in contact with the cathode contact electrode and is provided at a predetermined distance from the termination region, and a surface protective film formed to cover the termination region and the contact electrode. By thickening the contact electrode of the semiconductor device of the gate turn-off thyristor and keeping the third electrode at a predetermined distance from the termination region, the active region is expanded and the withstand voltage is increased.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to FIGS. << First Embodiment >> FIG. 1 is a top view of a high withstand voltage semiconductor device using a semiconductor material of silicon carbide (SiC) according to a first embodiment of the present invention. The semiconductor device of the first embodiment is a SiCpn diode having a designed withstand voltage of 12 kV, and the vertical and horizontal dimensions of the specific example are both 8 mm (8 mm × 8 mm).
2 is a sectional view taken along the line II-II of FIG. 1 and shows a right half section of FIG. In FIG. 2, on a substrate serving as the drain layer 1 of n-type SiC having a high impurity concentration and having a thickness of about 350 μm, which has the cathode electrode 50 of the first electrode on the lower surface,
A low impurity concentration n-type SiC drift layer 2 having a thickness of about 100 μm is formed. The cathode electrode 50 has a terminal 50
A may be provided. A low impurity concentration of about 2 μm, for example, 1 × 10 ¹⁷ is formed on the left side portion of the drift layer 2.
The p-type layer 3, which is the active region generating layer, of atm / cm ³ is formed by the epitaxial growth method. The active region generation layer injects charges into the drift layer 2 when energized to turn on the semiconductor device. In the process of forming the p-type layer 3, the impurity concentration is controlled to increase the impurity concentration of the upper layer portion 3A of the p-type layer 3 to about 1 × 10 ¹⁹ atm / cm ³ . p-type layer 3
The vertical and horizontal dimensions are 7 with a metal film such as titanium on the top.
mm (7 mm × 7 mm) of the second electrode anode contact electrode 52 is formed, and the anode contact electrode 52
In the figure, the anode electrode 51 of the third electrode made of gold or the like is provided at the left end portion. As shown in the top view of FIG.
The anode contact electrode 52 and the anode electrode 51 are
Each of them has a substantially rectangular shape and is formed concentrically in the central region of the diode. The anode 51 has a terminal 51 for connection.
A may be provided.

In FIG. 2, the drift layer 2 is shallowly etched by a kind of reactive ion etching method, which is a mesa etching method, to form a termination region T. Ions of boron or aluminum or the like are implanted from the upper surface of the termination region T to form the p-type region 4. Its width (length in the left-right direction in the figure) is about 200 μm.
The impurity concentration of the p-type region 4 is 10 ¹⁶ to 10 ¹⁹ atm
It is preferably in the range of / cm ³ . An n-type channel stopper region 5 having a width of about 200 μm is formed in the end region of the drift layer 2, that is, the right end portion (outer peripheral portion in FIG. 1) of the termination region T. The distance between the p-type region 4 and the channel stopper region 5 is about 100 μm.
On the surface of the termination region T, the slope of the p-type layer 3 adjacent to the termination region T, and the surface of the anode contact electrode 52, a passivation film 16 of a surface protective film made of a thin film of silicon dioxide or silicon nitride is formed. The film thickness of the passivation film 16 is in the range of 0.4 μm to 5 μm. In the SiC diode having the vertical and horizontal dimensions of 8 mm (8 mm × 8 mm) shown in the top view of FIG. 1, the end R3 of the anode electrode 51 is separated from the left end R4 of the termination region T by about 1 mm at the maximum. And is about 1.5 mm away from the right end R1.

In this embodiment, the electric conductivity at the boundary between the anode contact electrode 52 and the p-type layer 3 is increased by increasing the impurity concentration in the upper layer portion 3A of the p-type layer 3 near the anode contact electrode 52. Therefore, although the anode electrode 51 is provided only in the central portion (see FIG. 1) of the anode contact electrode 52,
All regions of the anode contact electrode 52 are active regions in which current flows. That is, the vertical and horizontal dimensions are both about 7
An active area of mm (7 mm × 7 mm) can be secured. The on-voltage of the pn diode of this example was 3.5V.
In FIG. 2, when a voltage is applied in the reverse direction to the pn diode of this embodiment (hereinafter, referred to as reverse bias), from the junction 34 of the p-type layer 3 and the n-type drift layer 2 to the cathode electrode 50 and the anode electrode. The depletion layer spreads toward 51. When the reverse bias voltage becomes higher, the depletion layer spreading in the drift layer 2 spreads toward the channel stopper region 5 at the right end of the figure by the action of the p-type region 4. The depletion layer relaxes the electric field, and a high reverse withstand voltage (internal withstand voltage) of 12 kV or more, which is the designed withstand voltage, is obtained. The internal withstand voltage is substantially equal to the breakdown voltage.

The diode of the present embodiment having an internal withstand voltage of 12.3 kV was manufactured by using Fluorinert (trademark) which is an insulating liquid.
The device was housed in a package filled with and was subjected to a reverse voltage application test. As a result, a reverse withstand voltage of 12.3 kV, which was almost the theoretical value, was obtained. The breakdown electric field of Fluorinert (trademark) is 16k.
Since it is V / mm, the reverse withstand voltage of 12.3 kV is due to the internal withstand voltage of this diode, and the external withstand voltage is found to be 12.3 kV or more. But S
Since the iC semiconductor device is used at a high temperature of several hundreds of degrees, it is not possible to use Fluorinert, which easily evaporates at high temperatures. The external withstand voltage is mainly equal to the air discharge starting voltage that depends on the distance between the end R1 of the channel stopper region 5 and the end R3 of the anode electrode 51. If an insulating gas is enclosed in the package, the air discharge start voltage becomes high. For example, a dielectric breakdown electric field of 9 kV /
Sulfur hexafluoride gas (SF ₆ ) which is a highly insulating gas of mm
, A reverse withstand voltage of about 12 kV was obtained. A mixed gas of SF ₆ and nitrogen is also used as the insulating gas. It was found that when the pressure of SF ₆ gas is higher than atmospheric pressure, the reverse withstand voltage further increases. On the other hand, the conventional S of FIG.
The iCpn diode had a reverse withstand voltage of 7 kV in Fluorinert (trademark), but had a low reverse withstand voltage of 4 kV in SF ₆ gas.

In the conventional SiC pn diode shown in FIG. 9, for example, the width of the termination region T is 1.5 mm.
The reverse withstand voltage in SF ₆ gas was increased to 12 kV or more, but the active region was reduced to 5 mm × 5 mm, which is about 50% less than that of this example. As a result, the on-voltage of the diode increased from 3.5V to 5V. In the SiC pn diode of the present embodiment, it is possible to obtain an external withstand voltage higher than the high internal withstand voltage originally possessed by the SiC diode, while maintaining a wide active region having both vertical and horizontal dimensions of about 7 mm. When the SiC diode is used at a relatively low temperature of 150 ° C. or less, the termination region T is coated with a resin end protection material, or the entire diode is covered with a solid insulator such as silicon rubber to prevent external withstand voltage. Can be higher. The SiC pn diode according to the present embodiment does not allow the use of edge protectants or solid insulators at 300 ° C.
It is effective for those used at the above-mentioned high temperature and those using a pressure contact type package in which application of the edge protecting agent is difficult. Since no edge protectant is applied, the manufacturing process can be simplified. Since no resin is used, ions such as sodium do not adhere to the interface between the resin and the semiconductor, and the reliability of the semiconductor device is improved. Also, the manufacturing process is simplified.

<Second Embodiment> FIG. 3 is a sectional view of a SiC (silicon carbide) pn diode having a designed withstand voltage of 12 kV and having a planar structure according to a second embodiment of the present invention. S of the first embodiment
Although the termination region T of the iCpn diode is a mesa type, this embodiment differs from the first example in that the termination region T is a planar type. The chip size of the pn diode of this embodiment is 6 mm (6 mm × 6 mm) in both the vertical and horizontal dimensions. The end portion R3 of the anode electrode 51 is connected to the end portion R4 of the termination region T.
About 1 mm away from. The impurity concentration of the upper layer portion 13A of the p-type layer 13, which is the active region generation layer, is higher than that of the p-type layer 3. Other configurations and operations are the same as those of the first embodiment. The reverse breakdown voltage of the pn diode of this example was 2.8 kV in nitrogen. Further, it was 12.1 kV in a highly insulating gas such as SF ₆ gas. Since the anode contact electrode 52 is formed from the central portion to the vicinity of the end portion R4 of the termination region T, the active region is 5 mm ×
A maximum area of 5 mm (25 mm ² ) can be secured, and the on-voltage is as low as 3.5V.

For example, a pn diode having the configuration shown in FIG.
In order to obtain a reverse withstand voltage of 12 kV with the same chip size of 6 mm × 6 mm as in this example, the width of the termination region T needs to be 1.5 mm, and as a result, the active region is 3 mm × 3 mm ( 9 mm ² ). The area 9 mm ² 3 of the area 25 mm ² according to the present example
6%, which is quite narrow. The on-voltage was 6 V, which was 70% higher than the on-voltage of 3.5 V of the present example. Since the pn diode of the present embodiment does not have the mesa structure in the termination region T, the reverse withstand voltage is slightly lower than that of the mesa structure, but there is no mesa formation process and the manufacturing process is simplified. Although the pn diode having the p-type region 13 is described in this embodiment,
Also in the Schottky diode in which a metal such as Ni having a rectifying property is formed on the n-type drift layer 2 without forming the p-type region 13, a high withstand voltage and a low on-voltage can be realized at the same time as in this embodiment. .

<Third Embodiment> FIG. 4 is a cross-sectional view of a SiC MOS field effect transistor (MOSFET) having a designed withstand voltage of 5 kV according to a third embodiment of the present invention. This MOSF
The chip size of ET is 4 mm in both vertical and horizontal (4 mm
× 4 mm). In the figure, the thickness of the substrate serving as the high impurity concentration n-type drain layer 11 having the drain electrode 53 of the first electrode on the lower surface is about 200 μm. The thickness of the n-type drift layer 2 formed on the drain layer 11 is about 50 μm. The p-type body layer 33 partially formed on the n-type drift layer 2 has a thickness of about 4 μm, and the n-type source layer 7 formed on a part of the p-type body layer 33 has a thickness of about 0.5 μm.
μm. These become the active region generating layer. The function of the active region generating layer is the same as that of the first embodiment. A trench 60 is formed in the p-type body layer 33. The trench 60 has a depth of about 6 μm and a width of about 3 μm. The thickness of the gate insulating layer 8 formed in the trench 60 is about 1 μm at the bottom of the trench 60 and about 0.1 μm at the side.
m. The gate electrode 54 of the second electrode is provided in the trench 60 via the gate insulator layer 8. A source contact electrode 55 is provided on the p-type body layer 33 and the n-type source layer 7. Source contact electrode 55
Is about twice as thick as the source contact electrode 155 of the conventional MOSFET shown in FIG. 10 so as to have high conductivity. All the source contact electrodes 55 are commonly connected at the portion where the trench 60 is not present, and are also connected to the source electrode 61 of the third electrode. The trench 60 and the gate electrode 54 may have a stripe shape extending in a direction perpendicular to the paper surface of the drawing, and may have, for example, a circular shape or a square shape.

The manufacturing method of the MOSFET of this embodiment is as follows.
It is as follows. In FIG. 4, the drain layer 11 is used as a device.
Effective, impurity concentration is 10¹⁸From 10²⁰atm / c
m^ThreeN-type SiC substrate of
Is 10¹⁵From 10¹⁶atm / cm^ThreeSiCn type
The lift layer 2 is formed by the epitaxial growth method. n
The impurity concentration is 10 on the drift layer 2.¹⁶atm /
cm^ThreeEpitaxial SiCp type body layer 33
It is formed by a growth method or the like. Only the left part of the figure is a p-type body
The p-type body layer 33 of the other portion is left with the layer 33 remaining.
Forming a termination region T by etching
It By implanting ions into the termination area T,
Impurity concentration is 10¹⁶From 10¹⁸atm / cm^ThreeP
The mold region 4 is formed. On the right edge of the termination area T
An n-type channel stopper region 5 is formed. Remaining right
The impurity concentration of the p-type body layer 33 on the side is 10¹⁹atm /
cm ^ThreeThe n-type source region 7 of about 10
It is formed by implantation. Impurity of n-type source region 7
The concentration is 10 in the conventional MOSFET shown in FIG.^{1 8}
atm / cm^ThreeIn this example, the impurity concentration
Is 10¹⁹atm / cm^ThreeAnd about 10 times more than the conventional one
Has been done.

Next, a trench 60 penetrating the p-type body layer 33 and reaching the n-type drift layer 2 at the bottom is formed by anisotropic etching. After forming the gate insulating film 8 of SiO _{2 on} the inner wall of the trench 60, polysilicon containing a high concentration of phosphorus is deposited to fill the trench 60. Other polysilicon is removed while leaving the polysilicon film attached to the gate insulating film 8 on the inner wall of the trench 60. A conductive material is filled in the recesses from which the polysilicon has been removed to form a gate electrode 54 containing a polysilicon film. A source contact electrode 55 is formed on the surfaces of the n-type region 7 and the p-type body layer 33 with aluminum, nickel or the like, and the source electrode 61 in the central portion is formed.
Connect to. The drain electrode 53 is formed on the drain layer 11. Finally, the thickness excluding the source electrode 61 is 0.5 μm
The passivation film 16 is formed to form M of this embodiment.
OSFET is completed. The width of the termination region T in the left-right direction in the figure is 0.5 mm. In this embodiment, the source electrode 61 is 1 m from the termination region T.
Since the distance is more than m, the distance from the end R1 is about 1.5 mm. The withstand voltage was measured by setting the voltage between the source electrode 61 and the gate electrode 54 of the MOSFET thus configured to zero and applying a forward voltage between the source electrode and the drain electrode 53. 4kV when MOSFET is placed in nitrogen gas
The above withstand voltage was obtained. When placed in SF ₆ gas, the withstand voltage was 5.1 kV, and a withstand voltage almost at the design value was obtained.
The on-resistance was 55 mΩcm ² . M of this embodiment
In the OSFET, the drift layer 2 may be partially raised without forming the trench as shown in FIG. The gate electrode 54 is provided on the elevated drift layer 2A via the insulating film 8A. With this structure, the on-resistance was slightly higher than that of FIG. 4, but the withstand voltage was unchanged.

In the MOSFET of this embodiment, the impurity concentration of the n-type source region 7 is about 10 times that of the conventional one, and the source contact electrode 55 having twice the thickness of the conventional one is provided between the termination region T and the source electrode 61. When formed, these regions become active regions. MOSF in Figure 4
In ET, the vertical and horizontal dimensions of the active region are both 3 mm (3 mm
× 3 mm) and its area is 9 mm ² .

The conventional MOSFET shown in FIG.
To obtain a withstand voltage of kV, the termination region T
Width of 1.5 mm is required. Chip size is 4
When a termination area having a width of 1.5 mm is provided in a MOSFET having a size of 4 mm, the vertical and horizontal dimensions of the active region are both 1 mm (1 mm × 1 mm) and the area is 1 mm ² . That is, the area of the active region of this example is 9 m.
Since it is m ^2, it is 9 times that of the conventional example. The on-resistance of the conventional MOSFET having an active area of 1 mm × 1 mm is 470 mΩcm ² , which is about 8.5 times that of the present embodiment, which is inferior to that of the present embodiment.

<Fourth Embodiment> FIG. 6 shows a fourth embodiment of the present invention, which is an insulated SiC of a design withstand voltage of 5 kV.
It is sectional drawing of a gate bipolar transistor (IGBT). The IGBT of this embodiment is the MOS of the third embodiment.
The n-type drain layer 11 of the FET is changed to the p-type drain layer 12. The other structure is the MO of the third embodiment.
It is substantially the same as the SFET. The chip size is 8 mm (8 mm × 8 mm) in both vertical and horizontal dimensions. In this embodiment, since the emitter electrode 57 of the third electrode and the termination region T are separated by 1 mm or more,
A distance of 1.5 mm or more can be secured between the emitter electrode 57 and the end R1. The voltage of the gate electrode 65 of the second electrode of the IGBT was set to zero, a forward voltage was applied between the emitter electrode 57 and the collector electrode 56 of the first electrode, and the withstand voltage was measured. As a result, a withstand voltage of 4 kV or more was obtained even in a nitrogen atmosphere. Since the active region is also formed between the end R4 of the termination region T and the emitter electrode 57, the active region is as large as 76.5% (= 7 × 7 ÷ 8 ÷ 8) of the chip area, and the emitter electrode 57 is Although it was provided only in the central part of the chip, the on-resistance did not rise. In this embodiment, since the collector layer 12 is p-type,
Holes are injected from the p-type collector layer 12 into the n-type drift layer 2 to cause conductivity modulation. This lowers the resistance of the n-type drift layer 2 and lowers the on-voltage. In the IGBT of this embodiment, the drift layer 2 may be partially raised without forming the trench as shown in FIG. 7. The gate electrode 65 is formed on the raised drift layer 2A through the insulating film 8A.
To provide. With this configuration, the on-resistance was slightly higher than that of FIG. 6, but the withstand voltage was unchanged.

In the conventional IGBT (not shown), since the width of the termination region T needs to be 1.5 mm, the area of the active region is 39% of the chip area (= 5 × 5).
÷ 8 ÷ 8) The on-voltage of the IGBT of this embodiment is 4
Although it was V, the ON voltage of the conventional device is 6V. That is, in this example, the ON voltage could be reduced by 33% as compared with the conventional one. If the chip area is smaller, the effect obtained by the present embodiment is even greater.

<Fifth Embodiment> FIG. 8 shows a fifth embodiment of the present invention, which is a gate turn-off gate of SiC having a design withstand voltage of 20 kV.
It is a sectional view of a thyristor (GTO). In the figure, 10 ¹⁴ to 10 10 are formed on a p-type SiC substrate having a high impurity concentration of 10 ¹⁸ to 10 ²⁰ atm / cm ³ functioning as the anode layer 21 having the anode electrode 21 of the first electrode.
N-type drift layer 2 with a low impurity concentration of ¹⁶ atm / cm ³
Are formed by a vapor phase growth method or the like. A p-type layer 22 is formed on the n-type drift layer 2. An n-type cathode region 23 is formed on the entire surface of the p-type layer 22. In the GTO of this embodiment, the impurity concentration of the n-type cathode region 23 is shown in FIG.
The n-type cathode region 23 is about 10 times higher.
A predetermined portion of the n-type cathode region 23 is etched to a depth reaching the p-type layer 22, and the p-type layer 2 is formed in the etched portion.
The gate electrode 54 of the second electrode is formed so as to be in contact with 2. The p-type layer 22 and the n-type cathode region 23 form an active region generating layer. The function of the active region generating layer is the same as that of the first embodiment. All gate electrodes 54, 54, 54
Are commonly connected at a position that cannot be seen in the cross section of FIG. A cathode contact electrode 59 is formed on the remaining n-type cathode region 23. In this embodiment, the thickness of the cathode contact electrode 59 is about twice as thick as the thickness of the conventional cathode contact electrode 159 shown in FIG. All the cathode electrodes 59, 59, 59 ...
Are commonly connected at positions not visible in the cross section of FIG. A thickness of 10 μm that contacts the cathode contact electrode 59 on the cathode contact electrode 59 at the center of the GTO
The cathode electrode 50 of the third electrode is formed of the gold film of. The cathode electrode 50 may be provided with the terminal 50A. The method of forming the termination region T is the same as that of the first embodiment.

In the GTO of this embodiment, the termination
The width of the area T is 1 mm, and the termination area T and the casing are
The distance from the electrode 50 is 0.5 mm. G of this embodiment
The voltage of the TO gate electrode 54 is set to zero, and the cathode electrode 5
A forward voltage is applied between 0 and the anode electrode 51 to measure the withstand voltage.
Decided SF of GTO 1 atm₆When placed in gas,
Withstand voltage is 11.5kV, and the design withstand voltage is 20kV
There wasn't. So SF ₆Make the gas pressure 2.5 atm
And the withstand voltage is 21.5kV, which is a withstand voltage exceeding the design value.
I was able to Also in the GTO of this embodiment, the term
Almost all areas except the nation area T are active areas
Therefore, a GTO with low on-resistance can be obtained.

The present invention described in each of the above embodiments includes more applicable scopes and derived structures. In the first to fifth embodiments, the case where the drift layer 2 is an n-type semiconductor device has been described. However, when the drift layer 2 is p-type, the n-type region of another element is a p-type region, The structure of the present invention can be applied by replacing the p-type region with the n-type region. In each of the embodiments, the case where SiC is used as the wide gap semiconductor material has been described as an example, but the present invention is a semiconductor device using another wide gap semiconductor material such as diamond or gallium nitride having a high critical electric field. Can be effectively applied to.

[0030]

As is clear from the detailed description of each embodiment above, the semiconductor device of the present invention has a main electrode formed in the central portion of the semiconductor device apart from the termination region. The distance between the ends of the semiconductor device can be made sufficiently large as long as it does not exceed the dielectric breakdown voltage of the gas enclosed in the package of the semiconductor device. As a result, the withstand voltage of the semiconductor device can be improved. In the region between the main electrode and the termination region, by increasing the impurity limit of the upper layer of the p-type body layer or thickening the contact electrode, a wide active region can be secured and the on-resistance of the semiconductor device can be kept low. it can. Furthermore, the semiconductor device of the present invention has a high reverse withstand voltage even at a high temperature exceeding 200 ° C. by enclosing the insulating gas containing SF ₆ gas as a main component in the package.

[Brief description of drawings]

FIG. 1 is a top view of a SiC pn diode according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a SiC pn diode according to a first embodiment of the present invention.

FIG. 3 is a sectional view of a SiC pn diode according to a second embodiment of the present invention.

FIG. 4 is a schematic diagram of an S having a trench structure according to a third embodiment of the present invention.
Cross section of iC MOSFET

FIG. 5 is a sectional view of another SiC MOSFET of the third embodiment.

FIG. 6 is a diagram illustrating an S having a trench structure according to a fourth embodiment of the present invention.
Cross section of iC IGBT

FIG. 7 is a sectional view of another SiC IGBT of the fourth embodiment.

FIG. 8 is a sectional view of a SiC GTO according to a fifth embodiment of the present invention.

FIG. 9 is a sectional view of a conventional SiC pn diode.

FIG. 10 is a sectional view of a conventional SiC MOSFET.

FIG. 11 is a sectional view of a conventional SiC GTO.

[Explanation of symbols]

1 drain layer 2 Drift layer 3 p-type layer 3A Upper part 4 p-type region 5 channel stopper area 11 drain layer 12 Collector layer 16 passivation film 21 Anode layer 22 P-type layer 23 Cathode area 33 body layer 50 cathode electrode 51 Anode electrode 52 Anode contact electrode 53 drain electrode 54 Gate electrode 55 Source contact electrode 56 Collector electrode 57 Emitter electrode 58 Emitter contact electrode 59 Cathode contact electrode 60 trench 61 Source electrode 65 Gate electrode 101 cathode region 102 drift layer 103 p-type layer 104 p-type region 105 Channel stopper area 106 passivation film 107 cathode electrode 108 Anode contact electrode 109 Anode electrode T termination area R1, R2, R3, R4 ends

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 653 H01L 29/74 C 655 B

Claims (18)

[Claims] 1. A high-impurity-concentration wide-gap semiconductor substrate having a first electrode on one surface, a low-impurity-concentration wide-gap semiconductor drift layer formed on the other surface of the substrate, and the drift layer. A wide-gap semiconductor active region generation layer formed on the top surface of the drift layer, a termination region having at least one high impurity concentration region of the same conductivity type as the drift layer formed in an end region of the drift layer, the active region A second electrode formed on the generation layer, a third electrode electrically connected to the second electrode and provided with a predetermined distance from the termination region, and the termination region and the third electrode. A high withstand voltage semiconductor device having a surface protective film formed so as to cover the second electrode. 2. The high withstand voltage according to claim 1, wherein the active region generation layer has a higher impurity concentration in a portion far from the drift layer than an impurity concentration in a portion near the drift layer. Semiconductor device. 3. A high-concentration first conductivity type wide-gap semiconductor substrate having a first electrode on one surface, and a low-impurity concentration first conductivity formed on the other surface of the substrate. Type wide-gap semiconductor drift layer, a second conductivity type drift layer formed on the drift layer and having a higher impurity concentration in a portion far from the drift layer than an impurity concentration in a portion near the drift layer. A wide-gap semiconductor active region generation layer, a termination region formed in an end region of the drift layer, the termination region having at least one high impurity concentration region of the same conductivity type as the drift layer, formed on the active region generation layer A second electrode, a third electrode electrically connected to the second electrode and provided with a predetermined distance from the termination region, and the terminator. Deployment region and the high withstand voltage semiconductor device having a forming surface protective film to cover the second electrode. 4. The predetermined separation distance between the termination region and the third electrode is set such that an air discharge start voltage at the separation distance is a breakdown voltage between the first electrode and the second electrode. The high withstand voltage semiconductor device according to claim 1, wherein the high withstand voltage semiconductor device is selected to have a higher voltage. 5. A substrate of a high-conductivity first-conductivity wide-gap semiconductor having a first electrode on one surface, and a low-impurity-concentration first conductivity formed on the other surface of the substrate. -Type wide-gap semiconductor drift layer, a high-concentration second-conductivity-type wide-gap semiconductor layer formed on the drift layer, the same as the drift layer formed in an end region of the drift layer A termination region having at least one high conductivity type region of conductivity type, a second electrode provided on the drift layer via an insulating film and serving as a gate electrode, the second electrode in the vicinity of the second electrode, First formed on a conductive wide-gap semiconductor layer
A high-conductivity-type region of a conductivity type, a wide-gap semiconductor layer of the second conductivity type, and a first conductivity-type region in the vicinity of the second electrode,
A contact electrode thickened to have high conductivity, a third electrode that is in contact with the contact electrode and is provided at a predetermined distance from the termination region, and covers the termination region and the contact electrode. A MOS field effect type high withstand voltage semiconductor device having a formed surface protective film. 6. The high withstand voltage semiconductor device of the MOS field effect type according to claim 5, wherein the first electrode is a drain electrode and the third electrode is a source electrode. 7. The predetermined separation distance between the termination region and the third electrode is set such that an air discharge start voltage at the separation distance is a breakdown voltage between the first electrode and the third electrode. 6. The MOS field effect type high withstand voltage semiconductor device according to claim 5, wherein the device is selected to have a higher voltage. 8. A substrate of a second conductivity type wide gap semiconductor having a high impurity concentration and having a first electrode on one surface, and a first conductivity having a low impurity concentration formed on the other surface of the substrate. Type wide gap semiconductor drift layer, a second conductivity type wide gap semiconductor layer formed on the drift layer, and at least the same conductivity type as the drift layer formed in an end region of the drift layer. A termination region having one region of high impurity concentration, a second electrode provided on the drift layer via an insulating film and acting as a gate electrode, a wide region of the second conductivity type in the vicinity of the second electrode First formed on gap semiconductor layer
A high-conductivity-type region of a conductivity type, a wide-gap semiconductor layer of the second conductivity type, and a first conductivity-type region in the vicinity of the second electrode,
A contact electrode thickened to have high conductivity, a third electrode that is in contact with the contact electrode and is provided at a predetermined distance from the termination region, and covers the termination region and the contact electrode. An insulated gate bipolar high withstand voltage semiconductor device having a formed surface protective film. 9. The first electrode is a collector electrode,
The high withstand voltage semiconductor device according to claim 8, wherein the third electrode is an emitter electrode. 10. The predetermined separation distance between the termination region and the emitter electrode is selected so that an air discharge start voltage at the separation distance is higher than a breakdown voltage between the emitter and the collector. The high withstand voltage semiconductor device according to claim 8. 11. The high breakdown voltage semiconductor device according to claim 5, wherein the second electrode is provided in a trench. 12. A substrate of a second conductivity type wide-gap semiconductor having a high impurity concentration, which has an anode electrode of a first electrode on one surface, and a low impurity concentration first substrate formed on the other surface of the substrate. No. 1 conductivity type wide gap semiconductor drift layer, second conductivity type wide gap semiconductor layer formed on the drift layer, and the same conductivity as the drift layer formed in an end region of the drift layer Termination region having at least one high impurity concentration region of a first conductivity type, a first conductivity type cathode region formed on the layer of the second conductivity type wide gap semiconductor, and a second conductivity type wide region. A gate electrode of a second electrode formed on the layer of the gap semiconductor, a cathode contact electrode provided on the cathode region and thickened so as to have high conductivity, A cathode electrode of a third electrode which is in contact with the cathode contact electrode and is kept at a predetermined distance from the termination region, and a surface protection film formed so as to cover the termination region and the contact electrode. Voltage semiconductor device. 13. The predetermined distance between the outer edge of the termination region and the cathode electrode is set so that the air discharge start voltage at the distance is higher than the breakdown voltage between the cathode electrode and the anode electrode. 13. The high withstand voltage semiconductor device according to claim 12, wherein the high withstand voltage semiconductor device is selected. 14. The in-air discharge starting voltage is a discharge starting voltage in an atmosphere of any one of sulfur hexafluoride gas and a mixed gas of sulfur hexafluoride gas and nitrogen gas.
The high withstand voltage semiconductor device according to any one of 7, 10, and 13. 15. The semiconductor device is a sulfur hexafluoride gas,
And a mixed gas of sulfur hexafluoride gas and nitrogen gas, which is housed in a package sealed at a pressure exceeding atmospheric pressure.
13. The high withstand voltage semiconductor device according to any one of 8 and 12. 16. The high withstand voltage semiconductor device according to claim 1, wherein the termination region is a mesa type. 17. The termination region is a planar type, and the termination region is a planar type.
The high withstand voltage semiconductor device according to any one of 1. 18. The termination region and the third region
4. The distance between the electrode and the electrode is 0.3 times or more the width of the termination region.
The high withstand voltage semiconductor device according to any one of 5, 8, and 12.