WO2014132689A1 - Silicon carbide semiconductor device - Google Patents

Silicon carbide semiconductor device Download PDF

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Publication number
WO2014132689A1
WO2014132689A1 PCT/JP2014/050625 JP2014050625W WO2014132689A1 WO 2014132689 A1 WO2014132689 A1 WO 2014132689A1 JP 2014050625 W JP2014050625 W JP 2014050625W WO 2014132689 A1 WO2014132689 A1 WO 2014132689A1
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Prior art keywords
silicon carbide
region
semiconductor device
interface
main surface
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PCT/JP2014/050625
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French (fr)
Japanese (ja)
Inventor
増田　健良
和田　圭司
健二 平塚
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住友電気工業株式会社
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Publication of WO2014132689A1 publication Critical patent/WO2014132689A1/en

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Definitions

  • the present invention relates to a silicon carbide semiconductor device, and more particularly to a silicon carbide semiconductor device provided with a transistor element and a Schottky barrier diode element.
  • the main determinant of the withstand voltage is the upper limit of the electric field strength that the drift layer forming the withstand voltage holding region can withstand.
  • a drift layer made of Si can be broken at a place where an electric field of about 0.3 MV / cm or more is applied. For this reason, it is necessary to suppress the electric field strength to less than a predetermined value in the entire drift layer of the MOSFET.
  • the simplest method is to reduce the impurity concentration of the drift layer.
  • this method has a disadvantage that the on-resistance of the MOSFET is increased. That is, there is a trade-off relationship between on-resistance and breakdown voltage.
  • a trade-off relationship between on-resistance and breakdown voltage is described for a typical Si MOSFET in consideration of theoretical limits obtained from Si physical property values.
  • a lower p-type buried layer and an upper p-type buried layer may be added in the n-type base layer on the n-type substrate on the drain electrode. It is disclosed.
  • the lower p-type buried layer and the upper buried layer divide the n-type base layer into a lower stage, an intermediate stage, and an upper stage each having the same thickness. According to this publication, an equal voltage is shared by each of the three stages, and the maximum electric field of each stage is kept below the limit electric field strength.
  • a termination structure having a guard ring also referred to as “Field Limiting Ring”.
  • a guard ring is provided at a depth position corresponding to each of the three steps described above. More specifically, a buried guard ring is provided at each of two different depth positions in the n-type base layer at the terminal portion, and a guard ring is also provided on the surface of the n-type base layer. With these three types of guard rings, the maximum electric field at each stage is kept below the limit strength even in the termination structure.
  • SiC is a material that can sufficiently withstand an electric field strength of 0.4 MV / cm or more. That is, under such electric field strength, the Si layer is easily destroyed, but the SiC layer is not destroyed.
  • a high electric field can be applied in this way, breakdown due to electric field concentration at a specific position in the MOSFET structure becomes a problem.
  • the breakdown phenomenon of the gate insulating film due to the electric field concentration in the gate insulating film, not in the SiC layer is the main determinant of the breakdown voltage.
  • the determination factor of the breakdown voltage differs between the Si semiconductor device and the SiC semiconductor device. For this reason, it is not the best measure to simply apply the technique of the above publication, which is considered to be based on the use of Si, in order to improve the breakdown voltage of the SiC semiconductor device. Therefore, it is preferable to use an optimum structure for the SiC semiconductor device for the structure for maintaining the breakdown voltage.
  • the area of the termination structure in the planar layout directly increases the area of the semiconductor device.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a silicon carbide semiconductor device having a high breakdown voltage and a small size.
  • the silicon carbide semiconductor device of the present invention includes an electrode layer, a silicon carbide film, a first semiconductor element, and a second semiconductor element.
  • the silicon carbide film has a first main surface facing the electrode layer and a second main surface opposite to the first main surface.
  • the silicon carbide film includes a drift layer that forms the first main surface and has the first conductivity type.
  • the drift layer has a first region forming a first main surface and a second region provided on the first region via an interface.
  • the interface has a central surface and an outer edge surface surrounding the central surface on the interface.
  • the silicon carbide film includes a buried region partially provided at the interface and having the second conductivity type.
  • the buried region has an electric field relaxation region partially provided on the central surface and a guard ring region provided on the outer edge surface so as to surround the central surface at the interface.
  • the first semiconductor element is disposed on the center plane of the interface.
  • the second semiconductor element is at least partially disposed on the outer edge surface of the interface.
  • One of the first and second semiconductor elements is a transistor element, and the other of the first and second semiconductor elements is a Schottky barrier diode element.
  • the Schottky barrier diode element has a Schottky electrode provided on the second main surface and at least partially in contact with the drift layer.
  • both the guard ring region for increasing the breakdown voltage and the semiconductor element for the original function of the semiconductor device are arranged on the outer edge surface.
  • region on an outer edge surface is utilized more effectively. That is, the size of the silicon carbide semiconductor device can be reduced while increasing the breakdown voltage of the silicon carbide semiconductor device.
  • the first semiconductor element may be a transistor element.
  • the second semiconductor element may be a Schottky barrier diode element.
  • the transistor element having a high degree of difficulty in suppressing the variation in characteristics is arranged on the central surface where the guard ring region is not provided. Thereby, the influence of the guard ring region on the characteristics of the transistor element can be suppressed. Therefore, it becomes easy to suppress the characteristic variation of the transistor elements.
  • the portion where the Schottky electrode is in contact with the drift layer on the second main surface may be parallel to the first main surface.
  • the portion where the Schottky electrode is in contact with the drift layer on the second main surface may have a portion inclined from the first main surface.
  • the direction of the portion where the Schottky electrode is in contact with the drift layer can be adjusted so that the physical properties of the interface between the Schottky electrode and the drift layer are optimized. Therefore, the characteristics of the Schottky barrier diode can be further improved.
  • a recess may be provided on the second main surface of the silicon carbide film.
  • the recess may have a sidewall made of a drift layer and in contact with the Schottky electrode.
  • the plane orientation of the side wall may be inclined from 50 degrees to 80 degrees from the (000-1) plane.
  • the plane orientation of the side wall in contact with the Schottky electrode is inclined by 50 degrees or more from the (000-1) plane, that is, the carbon plane of silicon carbide.
  • the forward voltage of the Schottky barrier diode can be reduced.
  • the inclination is 80 degrees or less, a highly flat side wall can be easily formed.
  • the portion of the interface that faces the contact surface between the Schottky electrode and the drift layer in the thickness direction may be a buried region.
  • the leakage current path along the thickness direction of the Schottky barrier diode can be blocked by the buried region. Therefore, the leakage current of the Schottky barrier diode can be further reduced.
  • the silicon carbide film may partially have a junction region having the second conductivity type on the second main surface.
  • the junction region may be in contact with the Schottky electrode.
  • the Schottky barrier diode can have a junction barrier Schottky (JBS) structure. Therefore, the breakdown voltage of the Schottky barrier diode can be increased.
  • JBS junction barrier Schottky
  • the portion of the interface that faces the junction region in the thickness direction may be at least partially composed of a buried region.
  • the leakage current path of the Schottky barrier diode can be narrowed by the depletion layer extending in the thickness direction from the junction region toward the buried region. Therefore, the leakage current of the Schottky barrier diode can be further reduced.
  • the Schottky electrode may be made of a metal having a work function smaller than 4.33 eV.
  • the forward voltage of the Schottky barrier diode can be further reduced as compared with the case where a general Ti electrode is used as the Schottky electrode.
  • the metal may contain at least one atom of Hf, Zr, Ta, Mn, Nb and V.
  • the Schottky electrode includes metal atoms having electronegativity smaller than that of each of silicon carbide atoms Si and C. Therefore, the forward voltage of the Schottky barrier diode can be further reduced.
  • the silicon carbide semiconductor device can be reduced in size while increasing the breakdown voltage of the silicon carbide semiconductor device.
  • FIG. 3 is a partial cross sectional view along a line II in FIG. 2 schematically showing a configuration of the silicon carbide semiconductor device in the first embodiment of the present invention.
  • FIG. 2 is a schematic plan view of the silicon carbide semiconductor device of FIG. 1.
  • FIG. 3 is a schematic partial cross-sectional perspective view of a silicon carbide film included in the silicon carbide semiconductor device in part III of FIG. 2.
  • FIG. 3 is a partial cross sectional view schematically showing a leakage current path of a Schottky barrier diode element in the silicon carbide semiconductor device of FIG. 2.
  • FIG. 8 is a partial cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 1 is a schematic plan view of the silicon carbide semiconductor device of FIG. 1.
  • FIG. 3 is a schematic partial cross-sectional perspective view of a silicon carbide film included in the silicon carbide semiconductor device in part III of FIG. 2.
  • FIG. 3 is a partial cross sectional
  • FIG. 8 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 8 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 8 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 8 is a partial cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. It is a fragmentary sectional view which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 2 of this invention.
  • FIG. 11 is a partial cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device of FIG. 10.
  • FIG. 11 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device of FIG. 10.
  • It is a fragmentary sectional view which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 3 of this invention. It is a fragmentary sectional view showing roughly the example of the fine structure of the side wall provided in the silicon carbide film which a silicon carbide semiconductor device has.
  • FIG. 3 is a diagram showing a crystal structure of a (000-1) plane in polytype 4H hexagonal crystal.
  • FIG. 16 is a diagram showing a crystal structure of a (11-20) plane along line XVI-XVI in FIG.
  • FIG. 21 is a diagram showing a crystal structure in the vicinity of the surface of the composite surface in FIG. 14 in the (11-20) plane.
  • FIG. 15 is a diagram when the composite surface of FIG. 14 is viewed from the (01-10) plane. It is a figure which shows the modification of FIG.
  • a semiconductor device 201 (silicon carbide semiconductor device) of the present embodiment includes a single crystal substrate 80, a gate oxide film 91 (gate insulating film), a gate electrode 92, an interlayer insulating film 93, The source electrode 94, the wiring layer 97, the drain electrode layer 98 (electrode layer), the epitaxial film 90 (silicon carbide film), the transistor element ET as the first semiconductor element, and the second semiconductor element And a Schottky barrier diode element ED1.
  • the Schottky barrier diode element ED1 can have a function as a free-wheeling diode electrically connected to the transistor element ET.
  • Single crystal substrate 80 is made of n-type (first conductivity type) silicon carbide.
  • Single crystal substrate 80 preferably has a hexagonal crystal structure, and more preferably has polytype 4H.
  • Epitaxial film 90 (FIGS. 1 and 3) is a silicon carbide film formed epitaxially on single crystal substrate 80.
  • Epitaxial film 90 has lower surface P1 (first main surface) facing drain electrode layer 98 and upper surface P2 (second main surface) opposite to lower surface P1.
  • lower surface P ⁇ b> 1 is arranged on drain electrode layer 98 with single crystal substrate 80 interposed therebetween.
  • Epitaxial film 90 includes drift layer 81 having lower surface P1 and having n-type.
  • Drift layer 81 has lower drift region 81A (first region) forming lower surface P1, and upper drift region 81B (second region) provided on lower drift region 81A via interface IF.
  • Lower drift region 81A preferably has an impurity concentration lower than that of single crystal substrate 80.
  • the impurity concentration of lower drift region 81A is preferably 1 ⁇ 10 15 cm ⁇ 3 or more and 5 ⁇ 10 16 cm ⁇ 3 or less, for example, 8 ⁇ 10 15 cm ⁇ 3 .
  • the impurity concentration of upper drift region 81B may be the same as the impurity concentration of lower drift region 81A.
  • the interface IF has a center surface FC and an outer edge surface FT surrounding the center surface FC on the interface IF.
  • a portion of the interface IF located on the inner side of the guard ring 73J (described in detail later) is the center plane FC, and a portion located on the guard ring 73J and on the outer side thereof is the outer edge surface FT. It is.
  • Epitaxial film 90 may be divided into a lower range RA and an upper range RB that are separated from each other by an interface IF.
  • Upper range RB includes upper drift region 81B, base layer 82, source region 83, and contact region 84.
  • Base layer 82 is provided on upper drift region 81B.
  • Base layer 82 has a p-type.
  • the impurity concentration of base layer 82 is, for example, 1 ⁇ 10 18 cm ⁇ 3 .
  • the source region 83 is provided on the base layer 82 and is separated from the upper drift region 81B by the base layer 82.
  • Source region 83 has n-type.
  • Contact region 84 is connected to base layer 82.
  • Contact region 84 has a p-type.
  • a trench TR is provided on the upper surface P2 of the upper side range RB of the epitaxial film 90 on the center surface FC.
  • Trench TR has side wall surface SW and bottom surface BT.
  • Sidewall surface SW passes through source region 83 and base layer 82 and reaches upper drift region 81B. Therefore, the side wall surface SW includes a portion constituted by the base layer 82.
  • the gate oxide film 91 covers each of the sidewall surface SW and the bottom surface BT of the trench TR.
  • Gate oxide film 91 has a portion that connects upper drift region 81 ⁇ / b> B and source region 83 on base layer 82.
  • the gate electrode 92 is provided on the gate oxide film 91.
  • Gate electrode 92 is arranged on sidewall surface SW via gate oxide film 91.
  • the source electrode 94 is in contact with each of the source region 83 and the contact region 84.
  • the source electrode 94 is an ohmic electrode and is made of, for example, silicide.
  • the interlayer insulating film 93 insulates between the gate electrode 92 and the wiring layer 97.
  • the epitaxial film 90 includes a buried region that is partially provided at the interface IF and has p-type (second conductivity type).
  • the buried region has an electric field relaxation region 71 partially provided on the center surface FC and a guard ring region 73 provided on the outer edge surface FT so as to surround the center surface FC at the interface IF.
  • the portion of the interface IF that faces the contact surface between the Schottky electrode 95 and the drift layer 81 in the thickness direction is preferably formed of an embedded region as shown in FIG.
  • the electric field relaxation region 71 has an electric field relaxation region 71T in which the transistor element ET is disposed above and an electric field relaxation region 71D in which the Schottky barrier diode element ED1 is disposed above.
  • the electric field relaxation region 71 preferably has an impurity concentration of about 2.5 ⁇ 10 13 cm ⁇ 3 or more.
  • the guard ring region 73 has a guard ring 73J located on the innermost periphery.
  • Guard ring 73J is preferably in contact with electric field relaxation region 71, and in FIG. 1, is in contact with electric field relaxation region 71D.
  • the guard ring region 73 may further include a guard ring 73I arranged so as to surround the guard ring 73J on the interface IF.
  • Guard ring 73J preferably has an impurity concentration lower than that of electric field relaxation region 71.
  • the epitaxial film 90 may have a field stop region 69 surrounding the guard ring region 73 on the interface IF.
  • Field stop region 69 has n type and has an impurity concentration higher than that of drift layer 81.
  • the transistor element ET as the first semiconductor element is disposed on the center plane FC of the interface IF.
  • the Schottky barrier diode element ED1 as the second semiconductor element is at least partially disposed on the outer edge surface FT of the interface IF. It is preferable that a plurality of semiconductor elements are arranged on the central plane FC, and it is more preferable that the plurality of semiconductor elements do not include the Schottky barrier diode element ED1. A plurality of semiconductor elements may be arranged on the outer edge surface FT. In this case, it is more preferable that the plurality of semiconductor elements do not include the transistor element ET.
  • Schottky barrier diode element ED1 includes Schottky electrode 95 and junction region 85 having a p-type.
  • the Schottky electrode 95 is provided on the upper surface P ⁇ b> 2 and at least partially in contact with the drift layer 81.
  • the Schottky electrode 95 is preferably made of a metal having a work function smaller than 4.33 eV which is the work function of Ti. Schottky electrode 95 is preferably made of a metal having a work function larger than 3.7 eV corresponding to the electric affinity of silicon carbide.
  • the Schottky electrode 95 preferably has a melting point of 1000 ° C. or higher from the viewpoint of stability at high temperatures.
  • the electronegativity of atoms contained in Schottky electrode 95 is preferably smaller than the electronegativity of atoms contained in silicon carbide, that is, the electronegativity of each of Si and C. Examples of the metal that satisfies the above conditions include Hf, Zr, Ta, Mn, Nb, and V.
  • Schottky electrode 95 may be made of any one of these metal elements, or may be made of an alloy containing two or more of these metal elements.
  • junction region 85 is included in the epitaxial film 90 and is partially provided on the upper surface P2. Junction region 85 is in contact with Schottky electrode 95. In the present embodiment, the portion where Schottky electrode 95 is in contact with drift layer 81 on upper surface P2 is parallel to lower surface P1. The portion of the interface IF that faces the junction region 85 in the thickness direction is preferably at least partially made of a buried region.
  • the wiring layer 97 is provided in contact with each of the source electrode 94 and the Schottky electrode 95.
  • the wiring layer 97 is made of a conductor. Thereby, the source electrode 94 and the Schottky electrode 95 are electrically connected.
  • the wiring layer 97 is made of, for example, aluminum or an aluminum alloy. Note that in the case where electrical connection between the source electrode 94 and the Schottky electrode 95 is unnecessary, the wiring layer 97 may be formed so as to be in contact with the source electrode 94 and not in contact with the Schottky electrode 95.
  • the maximum electric field strength in RB is preferably configured to be less than 2/3 of the maximum electric field strength in lower range RA, and more preferably configured to be less than half. Such a configuration can be obtained if the impurity concentration of the electric field relaxation region 71 and the guard ring region 73 is sufficiently increased.
  • the plane orientation of the upper surface P2 where the trench TR is not provided preferably has an off angle of 8 degrees or less from the ⁇ 0001 ⁇ plane, more preferably an off angle of 8 degrees or less from the (000-1) plane.
  • Bottom surface BT of trench TR is separated from lower range RA by upper range RB.
  • bottom surface BT has a flat shape substantially parallel to upper surface P2 of epitaxial film 90. Note that the bottom surface BT does not have to be a flat surface, and may be substantially point-like in the cross-sectional view of FIG. 1. In this case, the trench TR has a V-shape.
  • the side wall surface SW is inclined with respect to the upper surface P2 of the epitaxial film 90, so that the trench TR extends in a tapered shape toward the opening.
  • the plane orientation of the side wall surface SW is preferably inclined at 50 ° or more and 80 ° or less with respect to the ⁇ 000-1 ⁇ plane, and is inclined at 50 ° or more and 80 ° or less with respect to the (000-1) plane. It is more preferable.
  • Side wall surface SW has one of the plane orientations ⁇ 0-33-8 ⁇ , ⁇ 0-11-2 ⁇ , ⁇ 0-11-4 ⁇ and ⁇ 0-11-1 ⁇ when viewed macroscopically. May be.
  • the plane orientation ⁇ 0-33-8 ⁇ has an off angle of 54.7 degrees from the ⁇ 000-1 ⁇ plane.
  • the plane orientation ⁇ 0-11-1 ⁇ has an off angle of 75.1 degrees from the ⁇ 000-1 ⁇ plane. Accordingly, the plane orientations ⁇ 0-33-8 ⁇ , ⁇ 0-11-2 ⁇ , ⁇ 0-11-4 ⁇ and ⁇ 0-11-1 ⁇ correspond to off-angles of 54.7 to 75.1 degrees. Considering that a manufacturing error of about 5 degrees is assumed for the off angle, the sidewall surface SW is processed by inclining about 50 degrees or more and 80 degrees or less with respect to the ⁇ 000-1 ⁇ plane. The macroscopic plane orientation of SW is easily set to any one of ⁇ 0-33-8 ⁇ , ⁇ 0-11-2 ⁇ , ⁇ 0-11-4 ⁇ , and ⁇ 0-11-1 ⁇ . In order to increase the channel mobility of the transistor element ET, it is preferable that the side wall surface SW has a predetermined crystal plane (also referred to as a special plane) particularly in a portion on the base layer 82. Details of the special surface will be described later.
  • a predetermined crystal plane also referred to as a special plane
  • both guard ring region 73 for increasing the breakdown voltage and Schottky barrier diode element ED1 which is one of the semiconductor elements for the original function of semiconductor device 201 are provided on outer edge surface FT. Is placed. Thereby, the area
  • the first semiconductor element is the transistor element ET
  • the second semiconductor element is the Schottky barrier diode element ED1.
  • the transistor element ET having a high degree of difficulty in suppressing the variation in characteristics is arranged on the central plane FC where the guard ring region 73 is not provided.
  • the influence of the guard ring region 73 on the characteristics of the transistor element ET can be suppressed. Therefore, it becomes easy to suppress variation in characteristics of the transistor element ET.
  • the portion where Schottky electrode 95 is in contact with drift layer 81 on upper surface P2 is parallel to lower surface P1. Thereby, it is not necessary to incline the direction where the Schottky electrode 95 is in contact with the drift layer 81 from the direction parallel to the lower surface P1. Therefore, the manufacturing method of the Schottky barrier diode element ED1 can be simplified.
  • the portion of the interface IF that faces the contact surface between the Schottky electrode 95 and the drift layer 81 in the thickness direction is preferably composed of a buried region (electric field relaxation region 71, guard ring region 73).
  • a buried region electrical field relaxation region 71, guard ring region 73.
  • the Schottky barrier diode element ED1 can have a junction barrier Schottky (JBS) structure. Therefore, the breakdown voltage of the Schottky barrier diode element ED1 can be increased.
  • JBS junction barrier Schottky
  • the depletion layer extending from the junction region 85 obstructs the leakage current path (solid arrow in FIG. 4) of the Schottky barrier diode, thereby reducing the leakage current.
  • the portion of the interface IF that faces the junction region 85 in the thickness direction is at least partially formed of a buried region (electric field relaxation region 71, guard ring region 73).
  • the leakage current path of the Schottky barrier diode can be narrowed by the depletion layer extending in the thickness direction from the junction region 85 toward the buried region. Therefore, the leakage current of the Schottky barrier diode can be further reduced.
  • the Schottky electrode 95 is preferably made of a metal having a work function smaller than 4.33 eV. Thereby, the forward voltage of the Schottky barrier diode can be further reduced as compared with the case where a general Ti electrode is used as the Schottky electrode 95.
  • the metal preferably contains at least one atom of Hf, Zr, Ta, Mn, Nb and V.
  • Schottky electrode 95 contains metal atoms having electronegativity smaller than that of each of silicon carbide atoms Si and C. Therefore, the forward voltage of the Schottky barrier diode can be further reduced.
  • the semiconductor device 201 can handle such a high voltage that a maximum electric field of 0.4 MV / cm or more is applied in the drift layer 81. Further, by providing the electric field relaxation region 71 and the guard ring region 73, the maximum electric field strength in the upper range RB is less than 2/3 of the maximum electric field strength in the lower range RA under the voltage application as described above.
  • the semiconductor device 201 can be configured to be less than half. Thereby, the electric field strength in the upper range RB in the vicinity of the transistor element ET, which is a determining factor of the breakdown voltage, is further reduced.
  • the electric field strength applied to gate oxide film 91 at the corner formed by sidewall surface SW and bottom surface BT of trench TR is further reduced.
  • the maximum electric field strength in the lower range RA is 1.5 times the maximum electric field strength in the upper range RB in the central portion PC, more preferably more than twice.
  • the maximum electric field strength in the side range RA is made higher. Thereby, a higher voltage can be applied to the semiconductor device 201. That is, the breakdown voltage can be increased.
  • lower drift region 81 ⁇ / b> A is formed by epitaxial growth of silicon carbide on single crystal substrate 80.
  • the plane on which epitaxial growth is performed preferably has an off angle of 8 degrees or less from the ⁇ 000-1 ⁇ plane, and more preferably has an off angle of 8 degrees or less from the (000-1) plane.
  • Epitaxial growth can be performed by a CVD method.
  • the source gas for example, a mixed gas of silane (SiH 4 ) and propane (C 3 H 8 ) can be used. At this time, it is preferable to introduce, for example, nitrogen (N) or phosphorus (P) as impurities.
  • the buried region exposed at this time is formed by impurity ion implantation on the interface IF exposed at this time. That is, the electric field relaxation region 71 and the guard ring region 73 are formed. Further, a field stop region 69 may be formed.
  • the order of forming the impurity regions is arbitrary.
  • the acceptor impurity for example, aluminum can be used.
  • phosphorus may be used as the donor impurity.
  • upper drift region 81B is formed by the same method as lower drift region 81A. Thereby, an epitaxial film 90 having a lower range RA and an upper range RB is obtained.
  • an impurity region is formed by implanting impurity ions onto the upper surface P2 of the epitaxial film 90.
  • base layer 82 is formed on upper drift region 81B.
  • a source region 83 separated from upper drift region 81B by base layer 82 is formed on base layer 82.
  • a contact region 84 extending from the upper surface P2 to the base layer 82 is formed.
  • a junction region 85 is also formed. The order of forming the impurity regions is arbitrary.
  • the temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C.
  • the heat treatment time is, for example, about 30 minutes.
  • the atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an argon atmosphere.
  • mask layer 61 having an opening is formed on upper surface P ⁇ b> 2 of epitaxial film 90.
  • the opening is formed corresponding to the position of trench TR (FIG. 1).
  • Mask layer 61 is preferably made of silicon dioxide, and more preferably formed by thermal oxidation.
  • thermal etching using the mask layer 61 is performed. Details of the thermal etching will be described later.
  • a trench TR is formed in the upper surface P2 of the epitaxial film 90 by this thermal etching. At this time, a special surface is self-formed on the side wall surface SW of the trench TR, particularly on the base layer 82.
  • the mask layer 61 is removed by an arbitrary method such as etching.
  • gate oxide film 91 is formed on sidewall surface SW and bottom surface BT of trench TR.
  • Gate oxide film 91 has a portion that connects upper drift region 81 ⁇ / b> B and source region 83 on base layer 82.
  • the gate oxide film 91 is preferably formed by thermal oxidation.
  • NO annealing using nitrogen monoxide (NO) gas as the atmospheric gas may be performed.
  • the temperature profile has, for example, conditions of a temperature of 1100 ° C. to 1300 ° C. and a holding time of about 1 hour.
  • nitrogen atoms are introduced into the interface region between gate oxide film 91 and base layer 82.
  • a gas other than NO gas may be used as the atmospheric gas.
  • Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing.
  • the heating temperature for Ar annealing is preferably higher than the heating temperature for NO annealing and lower than the melting point of the gate oxide film 91.
  • the time during which this heating temperature is maintained is, for example, about 1 hour. Thereby, the formation of interface states in the interface region between gate oxide film 91 and base layer 82 is further suppressed.
  • other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.
  • a gate electrode 92 is formed on the gate oxide film 91.
  • gate electrode 92 is formed on gate oxide film 91 so as to fill the region inside trench TR with gate oxide film 91 interposed therebetween.
  • the gate electrode 92 can be formed, for example, by film formation of conductor or doped polysilicon and CMP (Chemical Mechanical Polishing).
  • interlayer insulating film 93 is formed on gate electrode 92 and gate oxide film 91 so as to cover the exposed surface of gate electrode 92. Etching is performed so that openings are formed in the interlayer insulating film 93 and the gate oxide film 91. Through this opening, each of source region 83 and contact region 84 is exposed on upper surface P2. Next, source electrode 94 in contact with each of source region 83 and n contact region 84 is formed on upper surface P2.
  • drain electrode layer 98 is formed on lower drift region 81A via single crystal substrate 80. Further, Schottky electrode 95 is formed so as to be in contact with each of drift layer 81 and junction region 85 on upper surface P2 after interlayer insulating film 93 and gate oxide film 91 are partially removed as necessary. . Next, the wiring layer 97 is formed. Thereby, the semiconductor device 201 is obtained.
  • terrace portion HX (concave portion) in which Schottky barrier diode element ED2 is formed is provided on upper surface P2 of epitaxial film 90. It has been. Specifically, as shown in the upper right part in FIG. 10, a terrace portion HX having a terrace shape is provided at the edge of the upper surface P2.
  • the terrace portion HX has a side wall SX and a bottom surface BX. At least a part of the side wall SX is composed of the drift layer 81, and the Schottky electrode 95 is in contact with the part.
  • the part where Schottky electrode 95 is in contact with drift layer 81 on upper surface P2 includes sidewall SX.
  • the portion where Schottky electrode 95 is in contact with drift layer 81 on upper surface P2 has a portion inclined from lower surface P1.
  • the plane orientation of the side wall SX is preferably inclined from 50 ° to 80 ° from the ⁇ 000-1 ⁇ plane, and more preferably from 50 ° to 80 ° from the (000-1) plane.
  • the side wall SX has one of the plane orientations ⁇ 0-33-8 ⁇ , ⁇ 0-11-2 ⁇ , ⁇ 0-11-4 ⁇ , and ⁇ 0-11-1 ⁇ when viewed macroscopically. Also good.
  • the plane orientation ⁇ 0-33-8 ⁇ has an off angle of 54.7 degrees from the ⁇ 000-1 ⁇ plane.
  • the plane orientation ⁇ 0-11-1 ⁇ has an off angle of 75.1 degrees from the ⁇ 000-1 ⁇ plane.
  • the plane orientations ⁇ 0-33-8 ⁇ , ⁇ 0-11-2 ⁇ , ⁇ 0-11-4 ⁇ and ⁇ 0-11-1 ⁇ correspond to off-angles of 54.7 to 75.1 degrees.
  • the side wall SX is processed by inclining about 50 degrees or more and 80 degrees or less with respect to the ⁇ 000-1 ⁇ plane.
  • the macroscopic plane orientation is likely to be any one of ⁇ 0-33-8 ⁇ , ⁇ 0-11-2 ⁇ , ⁇ 0-11-4 ⁇ , and ⁇ 0-11-1 ⁇ .
  • Such a side wall SX is likely to have a “special surface”. When the side wall SX has a special surface, the flatness of the side wall SX can be improved. Details of the special surface will be described later.
  • the direction of the portion where the Schottky electrode 95 is in contact with the drift layer 81 is optimized so that the physical properties of the interface between the Schottky electrode 95 and the drift layer 81 are optimized. Can be adjusted. Therefore, the characteristics of the Schottky barrier diode can be further improved.
  • the plane orientation of the side wall SX is inclined by 50 degrees or more and 80 degrees or less from the (000-1) plane
  • the plane orientation of the side wall in contact with the Schottky electrode 95 is from the (000-1) plane, that is, the silicon carbide carbon plane. , Tilt more than 50 degrees.
  • the forward voltage of the Schottky barrier diode can be reduced.
  • the inclination is 80 degrees or less, a highly flat side wall can be easily formed.
  • the configuration shown in FIG. 11 is obtained by a method substantially similar to that of the first embodiment.
  • the trench TR is formed by etching in the first embodiment
  • the terrace portion HX is further formed in the present embodiment.
  • the formation of the terrace portion HX may be performed simultaneously with the formation of the trench TR, or may be performed separately.
  • gate oxide film 91, gate electrode 92, interlayer insulating film 93, source electrode 94, and drain electrode layer 98 are formed in substantially the same manner as in the first embodiment.
  • Schottky electrode 95 is formed after interlayer insulating film 93 and gate oxide film 91 are partially removed as necessary.
  • the wiring layer 97 is formed. Thereby, the semiconductor device 202 is obtained.
  • diode element ED3 is arranged on center surface FC in addition to transistor element ET.
  • the Schottky barrier diode element ED2 (FIG. 10: Embodiment 2) is provided in the terrace portion HX as a recess, but the diode element ED3 is provided in the trench portion HY as a recess.
  • the trench part HY has side walls SX that face each other and a bottom face BY that connects the side walls SX.
  • the bottom surface BY has a flat shape substantially parallel to the top surface P2 of the epitaxial film 90 in the present embodiment.
  • the bottom surface BY may not be a flat surface, and may be substantially point-like in the cross-sectional view of FIG. 13.
  • the trench portion HY has a V shape.
  • Trench portion HY may have the same shape as trench TR or may have a different shape. When a similar shape is used, the manufacturing method can be further simplified.
  • a Schottky diode element can be formed on the center plane FC.
  • a Schottky barrier diode element ED1 (FIG. 1) or ED2 (FIG. 10) may be arranged instead of the diode element ED3 (FIG. 13). Further, a Schottky barrier diode element may be disposed on the center surface FC, and a transistor element may be disposed on the outer edge surface FT (not shown in FIG. 13).
  • the first semiconductor element disposed on the central plane FC is any one of the Schottky barrier diode elements ED1 to ED3, and the second semiconductor element disposed on the outer edge surface FT is It may be a transistor element ET.
  • Thermal etching is performed by exposing an object to be etched to a reactive gas at a high temperature, and has substantially no physical etching action.
  • the reactive gas is capable of reacting with silicon carbide under heating.
  • the reactive film is supplied to the epitaxial film 90 under heating, whereby the epitaxial film 90 is etched.
  • the reactive gas preferably contains a halogen element.
  • the halogen element preferably contains chlorine or fluorine.
  • a process gas containing at least one of Cl 2 , BCl 3, CF 4 , and SF 6 can be used as the reactive gas.
  • Particularly preferred reactive gas is Cl 2.
  • the process gas may further contain oxygen gas.
  • the process gas preferably contains a carrier gas.
  • the carrier gas for example, nitrogen gas, argon gas or helium gas can be used.
  • the lower limit of the heating temperature of the epitaxial film 90 for thermal etching is preferably about 700 ° C., more preferably about 800 ° C., and further preferably about 900 ° C. from the viewpoint of securing the etching rate.
  • the upper limit of the heating temperature is preferably about 1200 ° C., more preferably about 1100 ° C., and further preferably about 1000 ° C. from the viewpoint of suppressing etching damage.
  • the etching rate of silicon carbide in the thermal etching is, for example, about 70 ⁇ m / hour. Compared to this, the etching rate of silicon dioxide is extremely low, and therefore, if the mask layer 61 (FIG. 7) is made of silicon dioxide, its consumption can be remarkably suppressed.
  • the side wall SX provided with the Schottky barrier diode element ED2 or ED3 preferably has a special surface.
  • the side wall SX having a special surface includes a surface S1 (first surface) having a surface orientation ⁇ 0-33-8 ⁇ .
  • the plane S1 preferably has a plane orientation (0-33-8). More preferably, the sidewall SX microscopically includes the surface S1, and the sidewall SX further microscopically includes a surface S2 (second surface) having a surface orientation ⁇ 0-11-1 ⁇ .
  • “microscopic” means that the dimensions are as detailed as at least a dimension of about twice the atomic spacing. As a microscopic structure observation method, for example, a TEM (Transmission Electron Microscope) can be used.
  • the plane S2 preferably has a plane orientation (0-11-1).
  • the surface S1 and the surface S2 of the side wall SX constitute a composite surface SR having a surface orientation ⁇ 0-11-2 ⁇ . That is, the composite surface SR is configured by periodically repeating the surfaces S1 and S2. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy).
  • the composite surface SR has an off angle of 62 degrees macroscopically with respect to the ⁇ 000-1 ⁇ plane.
  • “macroscopic” means ignoring a fine structure having a dimension on the order of atomic spacing. As such a macroscopic off-angle measurement, for example, a general method using X-ray diffraction can be used.
  • composite surface SR has a plane orientation (0-11-2).
  • the composite surface SR has an off angle of 62 degrees macroscopically with respect to the (000-1) plane.
  • the direction CD is along the direction in which the above-described periodic repetition is performed.
  • the direction CD roughly corresponds to the direction in which the thickness direction of the epitaxial film 90 (the vertical direction in FIG. 10 or FIG. 13) is projected onto the side wall SX.
  • Si atoms are atoms of the A layer (solid line in the figure), B layer atoms (broken line in the figure) located below, C layer atoms (dotted line in the figure) located below, and B layer atoms (not shown) located below this It is provided repeatedly. That is, a periodic laminated structure such as ABCBABCBABCB... Is provided with four layers ABCB as one period.
  • the atoms in each of the four layers ABCB constituting one period described above are (0-11-2) It is not arranged to be completely along the plane.
  • the (0-11-2) plane is shown so as to pass through the position of atoms in the B layer.
  • the atoms in the A layer and the C layer are separated from the (0-11-2) plane. You can see that it is shifted. For this reason, even if the macroscopic plane orientation of the surface of the silicon carbide single crystal, that is, the plane orientation when ignoring the atomic level structure is limited to (0-11-2), the surface is microscopic. Can take various structures.
  • a surface S1 having a surface orientation (0-33-8) and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternately provided. It is configured by being.
  • the length of each of the surface S1 and the surface S2 is twice the atomic spacing of Si atoms (or C atoms). Note that the surface obtained by averaging the surfaces S1 and S2 corresponds to the (0-11-2) surface (FIG. 16).
  • the single crystal structure when the composite surface SR is viewed from the (01-10) plane periodically includes a structure (part of the surface S1) equivalent to a cubic crystal when viewed partially.
  • a surface S1 having a surface orientation (001) in a structure equivalent to the above-described cubic crystal and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternated. It is comprised by being provided in.
  • polytypes other than 4H may constitute the surface according to S2).
  • the polytype may be 6H or 15R, for example.
  • the side wall SX may further include a surface S3 (third surface) in addition to the composite surface SR. More specifically, the side wall SX may include a composite surface SQ that is configured by periodically repeating the composite surface SR (shown in a simplified manner as a straight line in FIG. 19) and the surface S3. The periodic structure can be observed, for example, by TEM or AFM.
  • the off angle of the side wall SX with respect to the ⁇ 000-1 ⁇ plane deviates from 62 degrees that is the ideal off angle of the composite surface SR. This deviation is preferably small, and preferably within a range of ⁇ 10 degrees.
  • a surface included in such an angle range for example, there is a surface whose macroscopic plane orientation is a ⁇ 0-33-8 ⁇ plane.
  • the off angle of the side wall SX with respect to the (000-1) plane deviates from the ideal off angle of the composite surface SR of 62 degrees. This deviation is preferably small, and preferably within a range of ⁇ 10 degrees.
  • a surface included in such an angle range for example, there is a surface whose macroscopic plane orientation is a (0-33-8) plane.
  • the structure of the gate electrode is not limited to the trench type, but may be a planar type. That is, the trench TR (FIG. 1) may not be provided on the upper surface P2 of the epitaxial film 90, and the gate electrode may be provided on the flat upper surface P2.
  • the transistor element may be a MISFET (Metal Insulator Semiconductor Field Effect Transistor) other than the MOSFET.
  • the transistor element may be an IGBT (Insulated Gate Bipolar Transistor) element.
  • each of the source electrode and the drain electrode corresponds to an emitter electrode and a collector electrode.
  • the channel type of the transistor is not limited to the n-channel type, and may be a p-channel type. In this case, a configuration in which the p-type and the n-type are interchanged in the above-described embodiment can be used. Further, the junction region of the Schottky barrier diode may be omitted when the effect is not necessary. Further, when the single crystal substrate is removed during the manufacture of the semiconductor device, a structure in which the epitaxial film and the drain electrode layer are in direct contact with each other can also be obtained.

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Abstract

A silicon carbide film (90) includes a drift layer (81) that forms a first main surface (P1) and is of a first conductivity type. The drift layer (81) has a first region (81A) that forms the first main surface (P1), and a second region (81B) that is provided on the first region (81A) with an interface (IF) therebetween. The interface (IF) has a center surface (FC), and an outer peripheral surface (FT) that surrounds the center surface (FC). The silicon carbide film (90) includes an embedded region that is partially provided in the interface (IF) and is of a second conductivity type. The embedded region has an electric field attenuated region (71) that is provided to the center surface (FC), and a guard ring region (73) that is provided to the outer peripheral surface (FT). A transistor element and a Schottky barrier diode element are arranged on the center surface (FC) and the outer peripheral surface.

Description

炭化珪素半導体装置Silicon carbide semiconductor device
　この発明は、炭化珪素半導体装置に関し、特にトランジスタ素子およびショットキーバリアダイオード素子が設けられた炭化珪素半導体装置に関するものである。 The present invention relates to a silicon carbide semiconductor device, and more particularly to a silicon carbide semiconductor device provided with a transistor element and a Schottky barrier diode element.
　広く用いられている電力用半導体装置であるＳｉ（シリコン）ＭＯＳＦＥＴ（Metal　Oxide　Semiconductor　Field　Effect　Transistor）に関して、耐圧の主な決定要因は、耐圧保持領域をなすドリフト層が耐え得る電界強度の上限である。Ｓｉから作られたドリフト層は、０．３ＭＶ／ｃｍ程度以上の電界が印加された箇所で破壊し得る。このためＭＯＳＦＥＴのドリフト層全体において電界強度を所定の値未満に抑えることが必要である。最も単純な方法はドリフト層の不純物濃度を低くすることである。しかしながらこの方法ではＭＯＳＦＥＴのオン抵抗が大きくなるという短所がある。すなわちオン抵抗と耐圧との間にトレードオフ関係が存在する。 Regarding Si (silicon) MOSFET (Metal Oxide Semiconductor Field Effect Transistor), which is a widely used power semiconductor device, the main determinant of the withstand voltage is the upper limit of the electric field strength that the drift layer forming the withstand voltage holding region can withstand. . A drift layer made of Si can be broken at a place where an electric field of about 0.3 MV / cm or more is applied. For this reason, it is necessary to suppress the electric field strength to less than a predetermined value in the entire drift layer of the MOSFET. The simplest method is to reduce the impurity concentration of the drift layer. However, this method has a disadvantage that the on-resistance of the MOSFET is increased. That is, there is a trade-off relationship between on-resistance and breakdown voltage.
　特開平９－１９１１０９号公報において、典型的なＳｉ　ＭＯＳＦＥＴについて、Ｓｉの物性値から得られる理論限界を考慮しつつ、オン抵抗と耐圧との間のトレードオフ関係の説明がなされている。そしてこのトレードオフを解消するために、ドレイン電極上のｎ型基板の上のｎ型ベース層中において、下側のｐ型埋込層と、上側のｐ型埋込層とを付加することが開示されている。下側のｐ型埋込層および上側の埋込層によってｎ型ベース層は、各々等しい厚さを有する下段と中段と上段とに区分される。この公報によれば、３つの段の各々によって等しい電圧が分担され、各段の最大電界が限界電界強度以下に保たれる。 In Japanese Patent Laid-Open No. 9-191109, a trade-off relationship between on-resistance and breakdown voltage is described for a typical Si MOSFET in consideration of theoretical limits obtained from Si physical property values. In order to eliminate this trade-off, a lower p-type buried layer and an upper p-type buried layer may be added in the n-type base layer on the n-type substrate on the drain electrode. It is disclosed. The lower p-type buried layer and the upper buried layer divide the n-type base layer into a lower stage, an intermediate stage, and an upper stage each having the same thickness. According to this publication, an equal voltage is shared by each of the three stages, and the maximum electric field of each stage is kept below the limit electric field strength.
　また上記公報は、ガードリング（"Field　Limiting　Ring"とも称される）を有する終端構造を設けることを開示している。具体的には、終端構造において、上述した３つの段の各々に対応する深さ位置にガードリングが設けられる。より具体的には終端部において、ｎ型ベース層中において２つの互いに異なる深さ位置のそれぞれに埋込みガードリングが設けられ、さらにｎ型ベース層の表面上にもガードリングが設けられる。これら３種類のガードリングによって、終端構造においても、各段の最大電界が限界強度以下に保たれる。 In addition, the above publication discloses providing a termination structure having a guard ring (also referred to as “Field Limiting Ring”). Specifically, in the termination structure, a guard ring is provided at a depth position corresponding to each of the three steps described above. More specifically, a buried guard ring is provided at each of two different depth positions in the n-type base layer at the terminal portion, and a guard ring is also provided on the surface of the n-type base layer. With these three types of guard rings, the maximum electric field at each stage is kept below the limit strength even in the termination structure.
特開平９－１９１１０９号公報JP-A-9-191109
　オン抵抗と耐圧との間のトレードオフをより大きく改善するための方法として、近年、Ｓｉに代わりＳｉＣを用いることが活発に検討されている。ＳｉＣはＳｉと異なり０．４ＭＶ／ｃｍ以上の電界強度にも十分に耐え得る材料である。すなわち、そのような電界強度下において、Ｓｉ層は破壊されやすいが、ＳｉＣ層は破壊されない。このように高い電界が印加され得る場合は、ＭＯＳＦＥＴ構造における特定位置での電界集中に起因した破壊が問題となる。たとえばトレンチ型ＭＯＳＦＥＴの場合、ＳｉＣ層中ではなくゲート絶縁膜中での電界集中に起因したゲート絶縁膜の破壊現象が、耐圧の主な決定要因である。このように耐圧の決定要因がＳｉ半導体装置とＳｉＣ半導体装置との間で異なる。このため、Ｓｉの使用を前提としていると考えられる上記公報の技術をＳｉＣ半導体装置の耐圧を向上させるために単純に適用することは最善の策ではない。よって、耐圧を維持するための構造についても、ＳｉＣ半導体装置に最適なものを用いることが好ましい。 In recent years, it has been actively studied to use SiC instead of Si as a method for greatly improving the trade-off between on-resistance and breakdown voltage. Unlike Si, SiC is a material that can sufficiently withstand an electric field strength of 0.4 MV / cm or more. That is, under such electric field strength, the Si layer is easily destroyed, but the SiC layer is not destroyed. When a high electric field can be applied in this way, breakdown due to electric field concentration at a specific position in the MOSFET structure becomes a problem. For example, in the case of a trench MOSFET, the breakdown phenomenon of the gate insulating film due to the electric field concentration in the gate insulating film, not in the SiC layer, is the main determinant of the breakdown voltage. As described above, the determination factor of the breakdown voltage differs between the Si semiconductor device and the SiC semiconductor device. For this reason, it is not the best measure to simply apply the technique of the above publication, which is considered to be based on the use of Si, in order to improve the breakdown voltage of the SiC semiconductor device. Therefore, it is preferable to use an optimum structure for the SiC semiconductor device for the structure for maintaining the breakdown voltage.
　上記公報に記載の技術によれば、平面レイアウトにおける終端構造の面積がそのまま半導体装置の面積の増大につながっていた。しかしながら、半導体装置の大きさは、より小さくされることが望ましい。 According to the technique described in the above publication, the area of the termination structure in the planar layout directly increases the area of the semiconductor device. However, it is desirable that the size of the semiconductor device be made smaller.
　本発明は、上記のような課題を解決するために成されたものであり、この発明の目的は、高い耐圧と小さな大きさとを有する炭化珪素半導体装置を提供することである。 The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a silicon carbide semiconductor device having a high breakdown voltage and a small size.
　本発明の炭化珪素半導体装置は、電極層と、炭化珪素膜と、第１の半導体素子と、第２の半導体素子とを有する。炭化珪素膜は、電極層に面する第１の主面と、第１の主面と反対の第２の主面とを有する。炭化珪素膜は、第１の主面をなし第１の導電型を有するドリフト層を含む。ドリフト層は、第１の主面をなす第１の領域と、第１の領域上に界面を介して設けられた第２の領域とを有する。界面は、中央面と、界面上において中央面を取り囲む外縁面とを有する。炭化珪素膜は、界面に部分的に設けられ第２の導電型を有する埋込領域を含む。埋込領域は、中央面に部分的に設けられた電界緩和領域と、界面において中央面を取り囲むように外縁面に設けられたガードリング領域とを有する。第１の半導体素子は界面の中央面上に配置されている。第２の半導体素子は界面の外縁面上に少なくとも部分的に配置されている。第１および第２の半導体素子の一方はトランジスタ素子であり、第１および第２の半導体素子の他方はショットキーバリアダイオード素子である。ショットキーバリアダイオード素子は、第２の主面上に設けられ少なくとも部分的にドリフト層に接するショットキー電極を有する。 The silicon carbide semiconductor device of the present invention includes an electrode layer, a silicon carbide film, a first semiconductor element, and a second semiconductor element. The silicon carbide film has a first main surface facing the electrode layer and a second main surface opposite to the first main surface. The silicon carbide film includes a drift layer that forms the first main surface and has the first conductivity type. The drift layer has a first region forming a first main surface and a second region provided on the first region via an interface. The interface has a central surface and an outer edge surface surrounding the central surface on the interface. The silicon carbide film includes a buried region partially provided at the interface and having the second conductivity type. The buried region has an electric field relaxation region partially provided on the central surface and a guard ring region provided on the outer edge surface so as to surround the central surface at the interface. The first semiconductor element is disposed on the center plane of the interface. The second semiconductor element is at least partially disposed on the outer edge surface of the interface. One of the first and second semiconductor elements is a transistor element, and the other of the first and second semiconductor elements is a Schottky barrier diode element. The Schottky barrier diode element has a Schottky electrode provided on the second main surface and at least partially in contact with the drift layer.
　この炭化珪素半導体装置によれば、外縁面上に、耐圧を高めるためのガードリング領域と、半導体装置の本来の機能のための半導体素子との両方が配置される。これにより、外縁面上の領域がより有効に利用される。すなわち、炭化珪素半導体装置の耐圧を高めつつ炭化珪素半導体装置の大きさを小さくすることができる。 According to this silicon carbide semiconductor device, both the guard ring region for increasing the breakdown voltage and the semiconductor element for the original function of the semiconductor device are arranged on the outer edge surface. Thereby, the area | region on an outer edge surface is utilized more effectively. That is, the size of the silicon carbide semiconductor device can be reduced while increasing the breakdown voltage of the silicon carbide semiconductor device.
　第１の半導体素子がトランジスタ素子であってもよい。第２の半導体素子がショットキーバリアダイオード素子であってもよい。 The first semiconductor element may be a transistor element. The second semiconductor element may be a Schottky barrier diode element.
　これにより、その特性ばらつきを抑制することの難易度が高いトランジスタ素子が、ガードリング領域の設けられていない中央面上に配置される。これにより、トランジスタ素子の特性へのガードリング領域の影響を抑えることができる。よってトランジスタ素子の特性ばらつきを抑制しやすくなる。 Thereby, the transistor element having a high degree of difficulty in suppressing the variation in characteristics is arranged on the central surface where the guard ring region is not provided. Thereby, the influence of the guard ring region on the characteristics of the transistor element can be suppressed. Therefore, it becomes easy to suppress the characteristic variation of the transistor elements.
　第２の主面上においてショットキー電極がドリフト層に接する部分は、第１の主面と平行であってもよい。 The portion where the Schottky electrode is in contact with the drift layer on the second main surface may be parallel to the first main surface.
　これにより、ショットキー電極がドリフト層に接する部分の向きを、第１の主面と平行な向きから傾ける必要がない。よってショットキーバリアダイオード素子の製造方法を簡素化することができる。 Thereby, it is not necessary to incline the direction of the portion where the Schottky electrode is in contact with the drift layer from the direction parallel to the first main surface. Therefore, the manufacturing method of the Schottky barrier diode element can be simplified.
　第２の主面上においてショットキー電極がドリフト層に接する部分は、第１の主面から傾いている部分を有してもよい。 The portion where the Schottky electrode is in contact with the drift layer on the second main surface may have a portion inclined from the first main surface.
　これにより、ショットキー電極がドリフト層に接する部分の向きを、ショットキー電極とドリフト層との界面の物性が最適化されるように調整し得る。よってショットキーバリアダイオードの特性をより高めることができる。 Thereby, the direction of the portion where the Schottky electrode is in contact with the drift layer can be adjusted so that the physical properties of the interface between the Schottky electrode and the drift layer are optimized. Therefore, the characteristics of the Schottky barrier diode can be further improved.
　炭化珪素膜の第２の主面には凹部が設けられていてもよい。凹部は、ドリフト層からなりショットキー電極が接する側壁を有してもよい。側壁の面方位は（０００－１）面から５０度以上８０度以下傾いていてもよい。 A recess may be provided on the second main surface of the silicon carbide film. The recess may have a sidewall made of a drift layer and in contact with the Schottky electrode. The plane orientation of the side wall may be inclined from 50 degrees to 80 degrees from the (000-1) plane.
　これにより、ショットキー電極が接する側壁の面方位が、（０００－１）面、すなわち炭化珪素のカーボン面から、５０度以上傾く。これによりショットキーバリアダイオードの順方向電圧を小さくすることができる。またこの傾きが８０度以下とされることで、平坦性の高い側壁を容易に形成し得る。 Thereby, the plane orientation of the side wall in contact with the Schottky electrode is inclined by 50 degrees or more from the (000-1) plane, that is, the carbon plane of silicon carbide. As a result, the forward voltage of the Schottky barrier diode can be reduced. Further, when the inclination is 80 degrees or less, a highly flat side wall can be easily formed.
　界面のうち厚さ方向においてショットキー電極とドリフト層との接触面に対向する部分は、埋込領域からなってもよい。 The portion of the interface that faces the contact surface between the Schottky electrode and the drift layer in the thickness direction may be a buried region.
　これにより、ショットキーバリアダイオードの、厚さ方向に沿ったリーク電流経路を、埋込領域によって遮断することができる。よってショットキーバリアダイオードのリーク電流をより小さくすることができる。 Thereby, the leakage current path along the thickness direction of the Schottky barrier diode can be blocked by the buried region. Therefore, the leakage current of the Schottky barrier diode can be further reduced.
　炭化珪素膜は第２の主面上に部分的に、第２の導電型を有するジャンクション領域を有してもよい。ジャンクション領域はショットキー電極に接していてもよい。 The silicon carbide film may partially have a junction region having the second conductivity type on the second main surface. The junction region may be in contact with the Schottky electrode.
　これにより、ショットキーバリアダイオードを、ジャンクション・バリア・ショットキー（ＪＢＳ）構造を有するものとすることができる。よってショットキーバリアダイオードの耐圧を高めることができる。 Thereby, the Schottky barrier diode can have a junction barrier Schottky (JBS) structure. Therefore, the breakdown voltage of the Schottky barrier diode can be increased.
　界面のうち厚さ方向においてジャンクション領域に対向する部分は、少なくとも部分的に埋込領域からなってもよい。 The portion of the interface that faces the junction region in the thickness direction may be at least partially composed of a buried region.
　これにより、ショットキーバリアダイオードのリーク電流経路を、ジャンクション領域から埋込領域に向かって厚さ方向に延びる空乏層によって狭窄することができる。よってショットキーバリアダイオードのリーク電流をより小さくすることができる。 Thereby, the leakage current path of the Schottky barrier diode can be narrowed by the depletion layer extending in the thickness direction from the junction region toward the buried region. Therefore, the leakage current of the Schottky barrier diode can be further reduced.
　ショットキー電極は、４．３３ｅＶより小さい仕事関数を有する金属から作られていてもよい。 The Schottky electrode may be made of a metal having a work function smaller than 4.33 eV.
　これにより、ショットキー電極として一般的なＴｉ電極が用いられる場合に比して、ショットキーバリアダイオードの順方向電圧をより小さくすることができる。 Thereby, the forward voltage of the Schottky barrier diode can be further reduced as compared with the case where a general Ti electrode is used as the Schottky electrode.
　金属は、Ｈｆ、Ｚｒ、Ｔａ、Ｍｎ、ＮｂおよびＶの少なくともいずれかの原子を含んでもよい。 The metal may contain at least one atom of Hf, Zr, Ta, Mn, Nb and V.
　これにより、ショットキー電極に、炭化珪素の原子ＳｉおよびＣの各々の電気陰性度に比して小さい電気陰性度を有する金属原子が含まれる。よってショットキーバリアダイオードの順方向電圧をより小さくすることができる。 Thereby, the Schottky electrode includes metal atoms having electronegativity smaller than that of each of silicon carbide atoms Si and C. Therefore, the forward voltage of the Schottky barrier diode can be further reduced.
　本発明によれば上述したように、炭化珪素半導体装置の耐圧を高めつつ、炭化珪素半導体装置の大きさを小さくすることができる。 According to the present invention, as described above, the silicon carbide semiconductor device can be reduced in size while increasing the breakdown voltage of the silicon carbide semiconductor device.
本発明の実施の形態１における炭化珪素半導体装置の構成を概略的に示す、図２の線Ｉ－Ｉに沿う部分断面図である。FIG. 3 is a partial cross sectional view along a line II in FIG. 2 schematically showing a configuration of the silicon carbide semiconductor device in the first embodiment of the present invention. 図１の炭化珪素半導体装置の概略的な平面図である。FIG. 2 is a schematic plan view of the silicon carbide semiconductor device of FIG. 1. 図２の部分ＩＩＩにおける、炭化珪素半導体装置が有する炭化珪素膜の概略的な部分断面斜視図である。FIG. 3 is a schematic partial cross-sectional perspective view of a silicon carbide film included in the silicon carbide semiconductor device in part III of FIG. 2. 図２の炭化珪素半導体装置におけるショットキーバリアダイオード素子のリーク電流経路を概略的に示す部分断面図である。FIG. 3 is a partial cross sectional view schematically showing a leakage current path of a Schottky barrier diode element in the silicon carbide semiconductor device of FIG. 2. 図１の炭化珪素半導体装置の製造方法の第１工程を概略的に示す部分断面図である。FIG. 8 is a partial cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. 図１の炭化珪素半導体装置の製造方法の第２工程を概略的に示す部分断面図である。FIG. 8 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. 図１の炭化珪素半導体装置の製造方法の第３工程を概略的に示す部分断面図である。FIG. 8 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. 図１の炭化珪素半導体装置の製造方法の第４工程を概略的に示す部分断面図である。FIG. 8 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. 図１の炭化珪素半導体装置の製造方法の第５工程を概略的に示す部分断面図である。FIG. 8 is a partial cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. 本発明の実施の形態２における炭化珪素半導体装置の構成を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 2 of this invention. 図１０の炭化珪素半導体装置の製造方法の第１工程を概略的に示す部分断面図である。FIG. 11 is a partial cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device of FIG. 10. 図１０の炭化珪素半導体装置の製造方法の第２工程を概略的に示す部分断面図である。FIG. 11 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device of FIG. 10. 本発明の実施の形態３における炭化珪素半導体装置の構成を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 3 of this invention. 炭化珪素半導体装置が有する炭化珪素膜に設けられた側壁の微細構造の例を概略的に示す部分断面図である。It is a fragmentary sectional view showing roughly the example of the fine structure of the side wall provided in the silicon carbide film which a silicon carbide semiconductor device has. ポリタイプ４Ｈの六方晶における（０００－１）面の結晶構造を示す図である。FIG. 3 is a diagram showing a crystal structure of a (000-1) plane in polytype 4H hexagonal crystal. 図１５の線ＸＶＩ－ＸＶＩに沿う（１１－２０）面の結晶構造を示す図である。FIG. 16 is a diagram showing a crystal structure of a (11-20) plane along line XVI-XVI in FIG. 図１４の複合面の表面近傍における結晶構造を（１１－２０）面内において示す図である。FIG. 21 is a diagram showing a crystal structure in the vicinity of the surface of the composite surface in FIG. 14 in the (11-20) plane. 図１４の複合面を（０１－１０）面から見た図である。FIG. 15 is a diagram when the composite surface of FIG. 14 is viewed from the (01-10) plane. 図１４の変形例を示す図である。It is a figure which shows the modification of FIG.
　以下、本発明の実施の形態について図に基づいて説明する。なお、以下の図面において、同一または相当する部分には同一の参照番号を付し、その説明は繰り返さない。また、本明細書中の結晶学的記載においては、個別方位を［］、集合方位を＜＞、個別面を（）、集合面を｛｝でそれぞれ示している。また結晶学上の指数が負であることは、通常、”－”（バー）を数字の上に付すことによって表現されるが、本明細書中では数字の前に負の符号を付している。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding “-” (bar) above a number. In this specification, a negative sign is added before the number. Yes.
　（実施の形態１）
　図１に示すように、本実施の形態の半導体装置２０１（炭化珪素半導体装置）は、単結晶基板８０と、ゲート酸化膜９１（ゲート絶縁膜）と、ゲート電極９２と、層間絶縁膜９３と、ソース電極９４と、配線層９７と、ドレイン電極層９８（電極層）と、エピタキシャル膜９０（炭化珪素膜）と、第１の半導体素子としてのトランジスタ素子ＥＴと、第２の半導体素子としてのショットキーバリアダイオード素子ＥＤ１とを有する。ショットキーバリアダイオード素子ＥＤ１は、トランジスタ素子ＥＴに電気的に接続された還流ダイオードとしての機能を有し得る。 (Embodiment 1)
As shown in FIG. 1, a semiconductor device 201 (silicon carbide semiconductor device) of the present embodiment includes a single crystal substrate 80, a gate oxide film 91 (gate insulating film), a gate electrode 92, an interlayer insulating film 93, The source electrode 94, the wiring layer 97, the drain electrode layer 98 (electrode layer), the epitaxial film 90 (silicon carbide film), the transistor element ET as the first semiconductor element, and the second semiconductor element And a Schottky barrier diode element ED1. The Schottky barrier diode element ED1 can have a function as a free-wheeling diode electrically connected to the transistor element ET.
　単結晶基板８０はｎ型（第１の導電型）の炭化珪素から作られている。単結晶基板８０は、好ましくは六方晶系の結晶構造を有し、より好ましくはポリタイプ４Ｈを有する。 Single crystal substrate 80 is made of n-type (first conductivity type) silicon carbide. Single crystal substrate 80 preferably has a hexagonal crystal structure, and more preferably has polytype 4H.
　エピタキシャル膜９０（図１および図３）は、単結晶基板８０上にエピタキシャルに形成された炭化珪素膜である。エピタキシャル膜９０は、ドレイン電極層９８に面する下面Ｐ１（第１の主面）と、下面Ｐ１と反対の上面Ｐ２（第２の主面）とを有する。本実施の形態においては、下面Ｐ１は、単結晶基板８０を介してドレイン電極層９８上に配置されている。 Epitaxial film 90 (FIGS. 1 and 3) is a silicon carbide film formed epitaxially on single crystal substrate 80. Epitaxial film 90 has lower surface P1 (first main surface) facing drain electrode layer 98 and upper surface P2 (second main surface) opposite to lower surface P1. In the present embodiment, lower surface P <b> 1 is arranged on drain electrode layer 98 with single crystal substrate 80 interposed therebetween.
　エピタキシャル膜９０は、下面Ｐ１をなしｎ型を有するドリフト層８１を含む。ドリフト層８１は、下面Ｐ１をなす下側ドリフト領域８１Ａ（第１の領域）と、下側ドリフト領域８１Ａ上に界面ＩＦを介して設けられた上側ドリフト領域８１Ｂ（第２の領域）とを有する。下側ドリフト領域８１Ａは単結晶基板８０の不純物濃度に比して低い不純物濃度を有することが好ましい。下側ドリフト領域８１Ａの不純物濃度は、好ましくは１×１０15ｃｍ-3以上５×１０16ｃｍ-3以下であり、たとえば８×１０15ｃｍ-3である。上側ドリフト領域８１Ｂの不純物濃度は、下側ドリフト領域８１Ａの不純物濃度と同じであってもよい。 Epitaxial film 90 includes drift layer 81 having lower surface P1 and having n-type. Drift layer 81 has lower drift region 81A (first region) forming lower surface P1, and upper drift region 81B (second region) provided on lower drift region 81A via interface IF. . Lower drift region 81A preferably has an impurity concentration lower than that of single crystal substrate 80. The impurity concentration of lower drift region 81A is preferably 1 × 10 15 cm −3 or more and 5 × 10 16 cm −3 or less, for example, 8 × 10 15 cm −3 . The impurity concentration of upper drift region 81B may be the same as the impurity concentration of lower drift region 81A.
　界面ＩＦは、図２に示すように、中央面ＦＣと、界面ＩＦ上において中央面ＦＣを取り囲む外縁面ＦＴとを有する。図１においては、界面ＩＦのうち、ガードリング７３Ｊ（詳しくは後述する）よりも内側に位置する部分が中央面ＦＣであり、ガードリング７３Ｊ上およびそれよりも外側に位置する部分が外縁面ＦＴである。 2, the interface IF has a center surface FC and an outer edge surface FT surrounding the center surface FC on the interface IF. In FIG. 1, a portion of the interface IF located on the inner side of the guard ring 73J (described in detail later) is the center plane FC, and a portion located on the guard ring 73J and on the outer side thereof is the outer edge surface FT. It is.
　エピタキシャル膜９０は、界面ＩＦによって互いに隔てられた下側範囲ＲＡおよび上側範囲ＲＢに区分され得る。上側範囲ＲＢは、上側ドリフト領域８１Ｂと、ベース層８２と、ソース領域８３と、コンタクト領域８４とを有する。ベース層８２は上側ドリフト領域８１Ｂ上に設けられている。ベース層８２はｐ型を有する。ベース層８２の不純物濃度は、たとえば１×１０18ｃｍ-3である。ソース領域８３は、ベース層８２上に設けられており、ベース層８２によって上側ドリフト領域８１Ｂから隔てられている。ソース領域８３はｎ型を有する。コンタクト領域８４はベース層８２につながっている。コンタクト領域８４はｐ型を有する。 Epitaxial film 90 may be divided into a lower range RA and an upper range RB that are separated from each other by an interface IF. Upper range RB includes upper drift region 81B, base layer 82, source region 83, and contact region 84. Base layer 82 is provided on upper drift region 81B. Base layer 82 has a p-type. The impurity concentration of base layer 82 is, for example, 1 × 10 18 cm −3 . The source region 83 is provided on the base layer 82 and is separated from the upper drift region 81B by the base layer 82. Source region 83 has n-type. Contact region 84 is connected to base layer 82. Contact region 84 has a p-type.
　中央面ＦＣ上においてエピタキシャル膜９０の上側範囲ＲＢの上面Ｐ２上にトレンチＴＲが設けられている。トレンチＴＲは側壁面ＳＷおよび底面ＢＴを有する。側壁面ＳＷは、ソース領域８３およびベース層８２を貫通して上側ドリフト領域８１Ｂに至っている。よって側壁面ＳＷは、ベース層８２によって構成された部分を含む。 A trench TR is provided on the upper surface P2 of the upper side range RB of the epitaxial film 90 on the center surface FC. Trench TR has side wall surface SW and bottom surface BT. Sidewall surface SW passes through source region 83 and base layer 82 and reaches upper drift region 81B. Therefore, the side wall surface SW includes a portion constituted by the base layer 82.
　ゲート酸化膜９１はトレンチＴＲの側壁面ＳＷおよび底面ＢＴの各々を覆っている。ゲート酸化膜９１は、ベース層８２上において上側ドリフト領域８１Ｂとソース領域８３とを互いにつなぐ部分を有する。ゲート電極９２はゲート酸化膜９１上に設けられている。ゲート電極９２はゲート酸化膜９１を介して側壁面ＳＷ上に配置されている。このようなゲート構造がドリフト層８１上に設けられることで、ＭＯＳ構造を有するトランジスタ素子ＥＴが形成されている。トランジスタ素子ＥＴは、ゲート電極９２に印加されるゲート電位によって、ソース電極９４からドレイン電極層９８への、キャリアとしての電子の流れを制御することができる。言い換えれば、トランジスタ素子ＥＴは、ゲート電位によって、上面Ｐ２および界面ＩＦの一方から他方への電流を制御することができる。 The gate oxide film 91 covers each of the sidewall surface SW and the bottom surface BT of the trench TR. Gate oxide film 91 has a portion that connects upper drift region 81 </ b> B and source region 83 on base layer 82. The gate electrode 92 is provided on the gate oxide film 91. Gate electrode 92 is arranged on sidewall surface SW via gate oxide film 91. By providing such a gate structure on the drift layer 81, a transistor element ET having a MOS structure is formed. The transistor element ET can control the flow of electrons as carriers from the source electrode 94 to the drain electrode layer 98 by the gate potential applied to the gate electrode 92. In other words, the transistor element ET can control a current from one of the upper surface P2 and the interface IF to the other by the gate potential.
　ソース電極９４はソース領域８３およびコンタクト領域８４の各々に接している。ソース電極９４はオーミック電極であり、たとえばシリサイドから作られている。層間絶縁膜９３はゲート電極９２と配線層９７との間を絶縁している。 The source electrode 94 is in contact with each of the source region 83 and the contact region 84. The source electrode 94 is an ohmic electrode and is made of, for example, silicide. The interlayer insulating film 93 insulates between the gate electrode 92 and the wiring layer 97.
　またエピタキシャル膜９０は、界面ＩＦに部分的に設けられｐ型（第２の導電型）を有する埋込領域を含む。埋込領域は、中央面ＦＣに部分的に設けられた電界緩和領域７１と、界面ＩＦにおいて中央面ＦＣを取り囲むように外縁面ＦＴに設けられたガードリング領域７３とを有する。界面ＩＦのうち、厚さ方向においてショットキー電極９５とドリフト層８１との接触面に対向する部分は、図１に示すように、埋込領域からなっていることが好ましい。 The epitaxial film 90 includes a buried region that is partially provided at the interface IF and has p-type (second conductivity type). The buried region has an electric field relaxation region 71 partially provided on the center surface FC and a guard ring region 73 provided on the outer edge surface FT so as to surround the center surface FC at the interface IF. The portion of the interface IF that faces the contact surface between the Schottky electrode 95 and the drift layer 81 in the thickness direction is preferably formed of an embedded region as shown in FIG.
　電界緩和領域７１は、その上方にトランジスタ素子ＥＴが配置されている電界緩和領域７１Ｔと、その上方にショットキーバリアダイオード素子ＥＤ１が配置されている電界緩和領域７１Ｄとを有する。電界緩和領域７１は２．５×１０13ｃｍ-3程度以上の不純物濃度を有することが好ましい。 The electric field relaxation region 71 has an electric field relaxation region 71T in which the transistor element ET is disposed above and an electric field relaxation region 71D in which the Schottky barrier diode element ED1 is disposed above. The electric field relaxation region 71 preferably has an impurity concentration of about 2.5 × 10 13 cm −3 or more.
　ガードリング領域７３は、最も内周に位置するガードリング７３Ｊを有する。ガードリング７３Ｊは、電界緩和領域７１に接していることが好ましく、図１においては電界緩和領域７１Ｄに接している。またガードリング領域７３はさらに、界面ＩＦ上においてガードリング７３Ｊを囲むように配置されたガードリング７３Ｉをさらに有してもよい。ガードリング７３Ｊは、電界緩和領域７１の不純物濃度よりも低い不純物濃度を有することが好ましい。 The guard ring region 73 has a guard ring 73J located on the innermost periphery. Guard ring 73J is preferably in contact with electric field relaxation region 71, and in FIG. 1, is in contact with electric field relaxation region 71D. The guard ring region 73 may further include a guard ring 73I arranged so as to surround the guard ring 73J on the interface IF. Guard ring 73J preferably has an impurity concentration lower than that of electric field relaxation region 71.
　またエピタキシャル膜９０は、界面ＩＦ上においてガードリング領域７３を囲むフィールドストップ領域６９を有してもよい。フィールドストップ領域６９は、ｎ型を有し、かつドリフト層８１の不純物濃度よりも高い不純物濃度を有する。 Further, the epitaxial film 90 may have a field stop region 69 surrounding the guard ring region 73 on the interface IF. Field stop region 69 has n type and has an impurity concentration higher than that of drift layer 81.
　第１の半導体素子としてのトランジスタ素子ＥＴは、界面ＩＦの中央面ＦＣ上に配置されている。第２の半導体素子としてのショットキーバリアダイオード素子ＥＤ１は、界面ＩＦの外縁面ＦＴ上に少なくとも部分的に配置されている。中央面ＦＣ上には複数の半導体素子が配置されていることが好ましく、この複数の半導体素子にはショットキーバリアダイオード素子ＥＤ１が含まれないことがより好ましい。また外縁面ＦＴには複数の半導体素子が配置されていてもよく、この場合、複数の半導体素子にはトランジスタ素子ＥＴが含まれないことがより好ましい。 The transistor element ET as the first semiconductor element is disposed on the center plane FC of the interface IF. The Schottky barrier diode element ED1 as the second semiconductor element is at least partially disposed on the outer edge surface FT of the interface IF. It is preferable that a plurality of semiconductor elements are arranged on the central plane FC, and it is more preferable that the plurality of semiconductor elements do not include the Schottky barrier diode element ED1. A plurality of semiconductor elements may be arranged on the outer edge surface FT. In this case, it is more preferable that the plurality of semiconductor elements do not include the transistor element ET.
　ショットキーバリアダイオード素子ＥＤ１は、ショットキー電極９５と、ｐ型を有するジャンクション領域８５とを含む。ショットキー電極９５は、上面Ｐ２上に設けられており、少なくとも部分的にドリフト層８１に接している。 Schottky barrier diode element ED1 includes Schottky electrode 95 and junction region 85 having a p-type. The Schottky electrode 95 is provided on the upper surface P <b> 2 and at least partially in contact with the drift layer 81.
　ショットキー電極９５は、Ｔｉの仕事関数である４．３３ｅＶより小さい仕事関数を有する金属から作られていることが好ましい。またショットキー電極９５は、炭化珪素の電気親和力に相当する３．７ｅＶよりも大きな仕事関数を有する金属から作られていることが好ましい。またショットキー電極９５は、高温での安定性の観点で、１０００℃以上の融点を有することが好ましい。またショットキー電極９５に含まれる原子の電気陰性度は、炭化珪素に含まれる原子の電気陰性度、すなわちＳｉおよびＣの各々の電気陰性度よりも小さい電気陰性度を有することが好ましい。上記のような条件を満たす金属としては、たとえば、Ｈｆ、Ｚｒ、Ｔａ、Ｍｎ、ＮｂおよびＶがある。ショットキー電極９５は、これらの金属元素のいずれかの単体から作られていてもよく、あるいはこれらの金属元素のうち２つ以上を含む合金から作られていてもよい。 The Schottky electrode 95 is preferably made of a metal having a work function smaller than 4.33 eV which is the work function of Ti. Schottky electrode 95 is preferably made of a metal having a work function larger than 3.7 eV corresponding to the electric affinity of silicon carbide. The Schottky electrode 95 preferably has a melting point of 1000 ° C. or higher from the viewpoint of stability at high temperatures. The electronegativity of atoms contained in Schottky electrode 95 is preferably smaller than the electronegativity of atoms contained in silicon carbide, that is, the electronegativity of each of Si and C. Examples of the metal that satisfies the above conditions include Hf, Zr, Ta, Mn, Nb, and V. Schottky electrode 95 may be made of any one of these metal elements, or may be made of an alloy containing two or more of these metal elements.
　ジャンクション領域８５は、エピタキシャル膜９０に含まれ、上面Ｐ２上に部分的に設けられている。ジャンクション領域８５はショットキー電極９５に接している。本実施の形態においては、上面Ｐ２上においてショットキー電極９５がドリフト層８１に接する部分は、下面Ｐ１と平行である。界面ＩＦのうち厚さ方向においてジャンクション領域８５に対向する部分は、少なくとも部分的に埋込領域からなっていることが好ましい。 The junction region 85 is included in the epitaxial film 90 and is partially provided on the upper surface P2. Junction region 85 is in contact with Schottky electrode 95. In the present embodiment, the portion where Schottky electrode 95 is in contact with drift layer 81 on upper surface P2 is parallel to lower surface P1. The portion of the interface IF that faces the junction region 85 in the thickness direction is preferably at least partially made of a buried region.
　配線層９７は、ソース電極９４およびショットキー電極９５の各々に接するように設けられている。配線層９７は導体から作られている。これによりソース電極９４とショットキー電極９５とが電気的に接続されている。配線層９７は、たとえば、アルミニウム、またはアルミニウム合金から作られている。なおソース電極９４とショットキー電極９５との間の電気的接続が不要の場合は、ソース電極９４に接しかつショットキー電極９５に接しないように配線層９７が形成されてもよい。 The wiring layer 97 is provided in contact with each of the source electrode 94 and the Schottky electrode 95. The wiring layer 97 is made of a conductor. Thereby, the source electrode 94 and the Schottky electrode 95 are electrically connected. The wiring layer 97 is made of, for example, aluminum or an aluminum alloy. Note that in the case where electrical connection between the source electrode 94 and the Schottky electrode 95 is unnecessary, the wiring layer 97 may be formed so as to be in contact with the source electrode 94 and not in contact with the Schottky electrode 95.
　なお半導体装置２０１はオフ状態において、ドリフト層８１中の最大電界強度が０．４ＭＶ／ｃｍ以上となるようにソース電極９４とドレイン電極層９８との間に電圧が印加された場合に、上側範囲ＲＢにおける最大電界強度が下側範囲ＲＡにおける最大電界強度の２／３未満となるように構成されていることが好ましく、半分未満となるように構成されていることがより好ましい。このような構成は、電界緩和領域７１およびガードリング領域７３の不純物濃度を十分に高くすれば、得ることができる。 Note that when the semiconductor device 201 is in the off state and a voltage is applied between the source electrode 94 and the drain electrode layer 98 so that the maximum electric field strength in the drift layer 81 is 0.4 MV / cm or more, the upper range. The maximum electric field strength in RB is preferably configured to be less than 2/3 of the maximum electric field strength in lower range RA, and more preferably configured to be less than half. Such a configuration can be obtained if the impurity concentration of the electric field relaxation region 71 and the guard ring region 73 is sufficiently increased.
　上面Ｐ２のうちトレンチＴＲが設けられていない部分の面方位は、好ましくは｛０００１｝面から８度以内のオフ角を有し、より好ましくは（０００－１）面から８度以内のオフ角を有する。トレンチＴＲの底面ＢＴは上側範囲ＲＢによって下側範囲ＲＡから離れている。底面ＢＴは、本実施の形態においてはエピタキシャル膜９０の上面Ｐ２とほぼ平行な平坦な形状を有する。なお底面ＢＴは平坦面でなくてもよく、図１の断面視においてほぼ点状であってもよく、この場合、トレンチＴＲはＶ字形状を有する。 The plane orientation of the upper surface P2 where the trench TR is not provided preferably has an off angle of 8 degrees or less from the {0001} plane, more preferably an off angle of 8 degrees or less from the (000-1) plane. Have Bottom surface BT of trench TR is separated from lower range RA by upper range RB. In this embodiment, bottom surface BT has a flat shape substantially parallel to upper surface P2 of epitaxial film 90. Note that the bottom surface BT does not have to be a flat surface, and may be substantially point-like in the cross-sectional view of FIG. 1. In this case, the trench TR has a V-shape.
　側壁面ＳＷはエピタキシャル膜９０の上面Ｐ２に対して傾斜しており、これによりトレンチＴＲは開口に向かってテーパ状に拡がっている。側壁面ＳＷの面方位は、｛０００－１｝面に対して５０°以上８０°以下傾斜していることが好ましく、（０００－１）面に対して５０°以上８０°以下傾斜していることがより好ましい。側壁面ＳＷは、巨視的に見て、面方位｛０－３３－８｝、｛０－１１－２｝、｛０－１１－４｝および｛０－１１－１｝のいずれかを有してもよい。なお面方位｛０－３３－８｝は｛０００－１｝面から５４．７度のオフ角を有する。面方位｛０－１１－１｝は｛０００－１｝面から７５．１度のオフ角を有する。よって面方位｛０－３３－８｝、｛０－１１－２｝、｛０－１１－４｝および｛０－１１－１｝は、オフ角５４．７～７５．１度に対応する。オフ角について５度程度の製造誤差が想定されることを考慮すると、側壁面ＳＷが｛０００－１｝面に対して５０度以上８０度以下程度傾斜するような加工を行うことで、側壁面ＳＷの巨視的な面方位を、｛０－３３－８｝、｛０－１１－２｝、｛０－１１－４｝および｛０－１１－１｝のいずれかとしやすくなる。トランジスタ素子ＥＴのチャネル移動度を高めるためには、側壁面ＳＷが、特にベース層８２上の部分において、所定の結晶面（特殊面とも称する）を有することが好ましい。特殊面の詳細については後述する。 The side wall surface SW is inclined with respect to the upper surface P2 of the epitaxial film 90, so that the trench TR extends in a tapered shape toward the opening. The plane orientation of the side wall surface SW is preferably inclined at 50 ° or more and 80 ° or less with respect to the {000-1} plane, and is inclined at 50 ° or more and 80 ° or less with respect to the (000-1) plane. It is more preferable. Side wall surface SW has one of the plane orientations {0-33-8}, {0-11-2}, {0-11-4} and {0-11-1} when viewed macroscopically. May be. The plane orientation {0-33-8} has an off angle of 54.7 degrees from the {000-1} plane. The plane orientation {0-11-1} has an off angle of 75.1 degrees from the {000-1} plane. Accordingly, the plane orientations {0-33-8}, {0-11-2}, {0-11-4} and {0-11-1} correspond to off-angles of 54.7 to 75.1 degrees. Considering that a manufacturing error of about 5 degrees is assumed for the off angle, the sidewall surface SW is processed by inclining about 50 degrees or more and 80 degrees or less with respect to the {000-1} plane. The macroscopic plane orientation of SW is easily set to any one of {0-33-8}, {0-11-2}, {0-11-4}, and {0-11-1}. In order to increase the channel mobility of the transistor element ET, it is preferable that the side wall surface SW has a predetermined crystal plane (also referred to as a special plane) particularly in a portion on the base layer 82. Details of the special surface will be described later.
　本実施の形態によれば、外縁面ＦＴ上に、耐圧を高めるためのガードリング領域７３と、半導体装置２０１の本来の機能のための半導体素子のひとつであるショットキーバリアダイオード素子ＥＤ１との両方が配置される。これにより、外縁面ＦＴ上の領域がより有効に利用される。すなわち、半導体装置２０１の耐圧を高めつつ半導体装置２０１の大きさを小さくすることができる。 According to the present embodiment, both guard ring region 73 for increasing the breakdown voltage and Schottky barrier diode element ED1 which is one of the semiconductor elements for the original function of semiconductor device 201 are provided on outer edge surface FT. Is placed. Thereby, the area | region on the outer edge surface FT is utilized more effectively. That is, the semiconductor device 201 can be reduced in size while increasing the breakdown voltage of the semiconductor device 201.
　また第１の半導体素子がトランジスタ素子ＥＴであり、第２の半導体素子がショットキーバリアダイオード素子ＥＤ１である。これにより、その特性ばらつきを抑制することの難易度が高いトランジスタ素子ＥＴが、ガードリング領域７３の設けられていない中央面ＦＣ上に配置される。これにより、トランジスタ素子ＥＴの特性へのガードリング領域７３の影響を抑えることができる。よってトランジスタ素子ＥＴの特性ばらつきを抑制しやすくなる。 The first semiconductor element is the transistor element ET, and the second semiconductor element is the Schottky barrier diode element ED1. Thereby, the transistor element ET having a high degree of difficulty in suppressing the variation in characteristics is arranged on the central plane FC where the guard ring region 73 is not provided. Thereby, the influence of the guard ring region 73 on the characteristics of the transistor element ET can be suppressed. Therefore, it becomes easy to suppress variation in characteristics of the transistor element ET.
　上面Ｐ２上においてショットキー電極９５がドリフト層８１に接する部分は、下面Ｐ１と平行である。これにより、ショットキー電極９５がドリフト層８１に接する部分の向きを、下面Ｐ１と平行な向きから傾ける必要がない。よってショットキーバリアダイオード素子ＥＤ１の製造方法を簡素化することができる。 The portion where Schottky electrode 95 is in contact with drift layer 81 on upper surface P2 is parallel to lower surface P1. Thereby, it is not necessary to incline the direction where the Schottky electrode 95 is in contact with the drift layer 81 from the direction parallel to the lower surface P1. Therefore, the manufacturing method of the Schottky barrier diode element ED1 can be simplified.
　界面ＩＦのうち厚さ方向においてショットキー電極９５とドリフト層８１との接触面に対向する部分は、埋込領域（電界緩和領域７１、ガードリング領域７３）からなっていることが好ましい。この場合、ショットキーバリアダイオード素子ＥＤ１の、厚さ方向に沿ったリーク電流経路を、埋込領域によって遮断することができる。よってショットキーバリアダイオード素子ＥＤ１のリーク電流をより小さくすることができる。 The portion of the interface IF that faces the contact surface between the Schottky electrode 95 and the drift layer 81 in the thickness direction is preferably composed of a buried region (electric field relaxation region 71, guard ring region 73). In this case, the leakage current path along the thickness direction of the Schottky barrier diode element ED1 can be blocked by the buried region. Therefore, the leakage current of the Schottky barrier diode element ED1 can be further reduced.
　またジャンクション領域８５が設けられる場合、ショットキーバリアダイオード素子ＥＤ１を、ジャンクション・バリア・ショットキー（ＪＢＳ）構造を有するものとすることができる。よってショットキーバリアダイオード素子ＥＤ１の耐圧を高めることができる。 Further, when the junction region 85 is provided, the Schottky barrier diode element ED1 can have a junction barrier Schottky (JBS) structure. Therefore, the breakdown voltage of the Schottky barrier diode element ED1 can be increased.
　またジャンクション領域８５から延びる空乏層（図４において白抜き矢印で示すように延びる破線部）が、ショットキーバリアダイオードのリーク電流経路（図４の実線矢印）を妨げることで、リーク電流を小さくすることができる。この目的では、界面ＩＦのうち厚さ方向においてジャンクション領域８５に対向する部分は、少なくとも部分的に埋込領域（電界緩和領域７１、ガードリング領域７３）からなっていることが好ましい。この場合、ショットキーバリアダイオードのリーク電流経路を、ジャンクション領域８５から埋込領域に向かって厚さ方向に延びる空乏層によって狭窄することができる。よってショットキーバリアダイオードのリーク電流をより小さくすることができる。 Also, the depletion layer extending from the junction region 85 (broken line portion extending as shown by the white arrow in FIG. 4) obstructs the leakage current path (solid arrow in FIG. 4) of the Schottky barrier diode, thereby reducing the leakage current. be able to. For this purpose, it is preferable that the portion of the interface IF that faces the junction region 85 in the thickness direction is at least partially formed of a buried region (electric field relaxation region 71, guard ring region 73). In this case, the leakage current path of the Schottky barrier diode can be narrowed by the depletion layer extending in the thickness direction from the junction region 85 toward the buried region. Therefore, the leakage current of the Schottky barrier diode can be further reduced.
　ショットキー電極９５は、４．３３ｅＶより小さい仕事関数を有する金属から作られていることが好ましい。これにより、ショットキー電極９５として一般的なＴｉ電極が用いられる場合に比して、ショットキーバリアダイオードの順方向電圧をより小さくすることができる。 The Schottky electrode 95 is preferably made of a metal having a work function smaller than 4.33 eV. Thereby, the forward voltage of the Schottky barrier diode can be further reduced as compared with the case where a general Ti electrode is used as the Schottky electrode 95.
　金属は、Ｈｆ、Ｚｒ、Ｔａ、Ｍｎ、ＮｂおよびＶの少なくともいずれかの原子を含むことが好ましい。これにより、ショットキー電極９５に、炭化珪素の原子ＳｉおよびＣの各々の電気陰性度に比して小さい電気陰性度を有する金属原子が含まれる。よってショットキーバリアダイオードの順方向電圧をより小さくすることができる。 The metal preferably contains at least one atom of Hf, Zr, Ta, Mn, Nb and V. Thereby, Schottky electrode 95 contains metal atoms having electronegativity smaller than that of each of silicon carbide atoms Si and C. Therefore, the forward voltage of the Schottky barrier diode can be further reduced.
　またエピタキシャル膜９０の材料が炭化珪素であることにより、半導体装置２０１は、ドリフト層８１中に０．４ＭＶ／ｃｍ以上の最大電界が印加されるような高い電圧を扱うことができる。また電界緩和領域７１およびガードリング領域７３が設けられることで、上記のような電圧印加の下で、上側範囲ＲＢにおける最大電界強度が、下側範囲ＲＡにおける最大電界強度の２／３未満、さらには半分未満となるように、半導体装置２０１を構成し得る。これにより、耐圧の決定要因となる、トランジスタ素子ＥＴ近傍での上側範囲ＲＢにおける電界強度が、より低くされる。具体的には、トレンチＴＲの側壁面ＳＷと底面ＢＴとがなす角部においてゲート酸化膜９１に加わる電界強度が、より低くされる。逆に言えば、下側範囲ＲＡにおける最大電界強度が、中央部ＰＣ内の上側範囲ＲＢにおける最大電界強度の１．５倍、より好ましくは２倍を超えることにより、耐圧の決定要因とならない下側範囲ＲＡにおける最大電界強度が、より高くされる。これにより半導体装置２０１に、より高い電圧を印加することができる。すなわち耐圧を高めることができる。 In addition, since the material of the epitaxial film 90 is silicon carbide, the semiconductor device 201 can handle such a high voltage that a maximum electric field of 0.4 MV / cm or more is applied in the drift layer 81. Further, by providing the electric field relaxation region 71 and the guard ring region 73, the maximum electric field strength in the upper range RB is less than 2/3 of the maximum electric field strength in the lower range RA under the voltage application as described above. The semiconductor device 201 can be configured to be less than half. Thereby, the electric field strength in the upper range RB in the vicinity of the transistor element ET, which is a determining factor of the breakdown voltage, is further reduced. Specifically, the electric field strength applied to gate oxide film 91 at the corner formed by sidewall surface SW and bottom surface BT of trench TR is further reduced. In other words, the maximum electric field strength in the lower range RA is 1.5 times the maximum electric field strength in the upper range RB in the central portion PC, more preferably more than twice. The maximum electric field strength in the side range RA is made higher. Thereby, a higher voltage can be applied to the semiconductor device 201. That is, the breakdown voltage can be increased.
　なお上記のように上側範囲ＲＢに比して下側範囲ＲＡによる電圧負担を高める構造を、仮にＳｉＣ半導体装置でなくＳｉ半導体装置に適用したとすると、耐圧に対して悪影響が生じ得る。なぜならば、下側範囲ＲＡにおいてＳｉ層の破壊現象が生じやすくなるためである。 If the structure for increasing the voltage burden due to the lower range RA as compared with the upper range RB as described above is applied to the Si semiconductor device instead of the SiC semiconductor device, an adverse effect on the breakdown voltage may occur. This is because the breakdown phenomenon of the Si layer is likely to occur in the lower range RA.
　次に半導体装置２０１の製造方法について説明する。
　図５を参照して、単結晶基板８０上における炭化珪素のエピタキシャル成長によって下側ドリフト領域８１Ａが形成される。エピタキシャル成長が行われる面は、｛０００－１｝面から８度以内のオフ角を有することが好ましく、（０００－１）面から８度以内のオフ角を有することがより好ましい。エピタキシャル成長はＣＶＤ法により行われ得る。原料ガスとしては、たとえば、シラン（ＳｉＨ4）とプロパン（Ｃ3Ｈ8）との混合ガスを用い得る。この際、不純物として、たとえば窒素（Ｎ）やリン（Ｐ）を導入することが好ましい。 Next, a method for manufacturing the semiconductor device 201 will be described.
Referring to FIG. 5, lower drift region 81 </ b> A is formed by epitaxial growth of silicon carbide on single crystal substrate 80. The plane on which epitaxial growth is performed preferably has an off angle of 8 degrees or less from the {000-1} plane, and more preferably has an off angle of 8 degrees or less from the (000-1) plane. Epitaxial growth can be performed by a CVD method. As the source gas, for example, a mixed gas of silane (SiH 4 ) and propane (C 3 H 8 ) can be used. At this time, it is preferable to introduce, for example, nitrogen (N) or phosphorus (P) as impurities.
　次に、この時点では露出されている界面ＩＦ上への不純物イオン注入によって、この時点では露出されている埋込領域が形成される。すなわち電界緩和領域７１およびガードリング領域７３が形成される。またさらにフィールドストップ領域６９が形成されてもよい。各不純物領域の形成の順番は任意である。アクセプタ不純物としては、たとえばアルミニウムを用い得る。ドナー不純物としては、たとえばリンを用い得る。 Next, the buried region exposed at this time is formed by impurity ion implantation on the interface IF exposed at this time. That is, the electric field relaxation region 71 and the guard ring region 73 are formed. Further, a field stop region 69 may be formed. The order of forming the impurity regions is arbitrary. As the acceptor impurity, for example, aluminum can be used. For example, phosphorus may be used as the donor impurity.
　図６を参照して、下側ドリフト領域８１Ａと同様の方法によって、上側ドリフト領域８１Ｂが形成される。これにより下側範囲ＲＡおよび上側範囲ＲＢを有するエピタキシャル膜９０が得られる。 Referring to FIG. 6, upper drift region 81B is formed by the same method as lower drift region 81A. Thereby, an epitaxial film 90 having a lower range RA and an upper range RB is obtained.
　次に、エピタキシャル膜９０の上面Ｐ２上への不純物イオン注入によって不純物領域が形成される。具体的には上側ドリフト領域８１Ｂ上にベース層８２が形成される。またベース層８２によって上側ドリフト領域８１Ｂから隔てられたソース領域８３が、ベース層８２上に形成される。また上面Ｐ２からベース層８２まで延びるコンタクト領域８４が形成される。またジャンクション領域８５が形成される。各不純物領域の形成の順番は任意である。 Next, an impurity region is formed by implanting impurity ions onto the upper surface P2 of the epitaxial film 90. Specifically, base layer 82 is formed on upper drift region 81B. A source region 83 separated from upper drift region 81B by base layer 82 is formed on base layer 82. A contact region 84 extending from the upper surface P2 to the base layer 82 is formed. A junction region 85 is also formed. The order of forming the impurity regions is arbitrary.
　次に、不純物を活性化するための熱処理が行われる。この熱処理の温度は、好ましくは１５００℃以上１９００℃以下であり、たとえば１７００℃程度である。熱処理の時間は、たとえば３０分程度である。熱処理の雰囲気は、好ましくは不活性ガス雰囲気であり、たとえばアルゴン雰囲気である。 Next, a heat treatment for activating the impurities is performed. The temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The heat treatment time is, for example, about 30 minutes. The atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an argon atmosphere.
　図７を参照して、エピタキシャル膜９０の上面Ｐ２上に、開口部を有するマスク層６１が形成される。開口部はトレンチＴＲ（図１）の位置に対応して形成される。マスク層６１は、二酸化珪素から作られることが好ましく、熱酸化によって形成されることがより好ましい。次に、マスク層６１を用いた熱エッチングが行われる。熱エッチングの詳細については後述する。この熱エッチングによりエピタキシャル膜９０の上面Ｐ２にトレンチＴＲが形成される。この時に、トレンチＴＲの側壁面ＳＷ上、特にベース層８２上において、特殊面が自己形成される。次にマスク層６１がエッチングなど任意の方法により除去される。 Referring to FIG. 7, mask layer 61 having an opening is formed on upper surface P <b> 2 of epitaxial film 90. The opening is formed corresponding to the position of trench TR (FIG. 1). Mask layer 61 is preferably made of silicon dioxide, and more preferably formed by thermal oxidation. Next, thermal etching using the mask layer 61 is performed. Details of the thermal etching will be described later. A trench TR is formed in the upper surface P2 of the epitaxial film 90 by this thermal etching. At this time, a special surface is self-formed on the side wall surface SW of the trench TR, particularly on the base layer 82. Next, the mask layer 61 is removed by an arbitrary method such as etching.
　図８を参照して、トレンチＴＲの側壁面ＳＷおよび底面ＢＴの上にゲート酸化膜９１が形成される。ゲート酸化膜９１は、ベース層８２上において上側ドリフト領域８１Ｂとソース領域８３とを互いにつなぐ部分を有する。ゲート酸化膜９１は、熱酸化により形成されることが好ましい。 Referring to FIG. 8, gate oxide film 91 is formed on sidewall surface SW and bottom surface BT of trench TR. Gate oxide film 91 has a portion that connects upper drift region 81 </ b> B and source region 83 on base layer 82. The gate oxide film 91 is preferably formed by thermal oxidation.
　ゲート酸化膜９１の形成後に、雰囲気ガスとして一酸化窒素（ＮＯ）ガスを用いるＮＯアニールが行われてもよい。温度プロファイルは、たとえば、温度１１００℃以上１３００℃以下、保持時間１時間程度の条件を有する。これにより、ゲート酸化膜９１とベース層８２との界面領域に窒素原子が導入される。その結果、界面領域における界面準位の形成が抑制されることで、チャネル移動度を向上させることができる。なお、このような窒素原子の導入が可能であれば、ＮＯガス以外のガスが雰囲気ガスとして用いられてもよい。このＮＯアニールの後にさらに、雰囲気ガスとしてアルゴン（Ａｒ）を用いるＡｒアニールが行われてもよい。Ａｒアニールの加熱温度は、上記ＮＯアニールの加熱温度よりも高く、ゲート酸化膜９１の融点よりも低いことが好ましい。この加熱温度が保持される時間は、たとえば１時間程度である。これにより、ゲート酸化膜９１とベース層８２との界面領域における界面準位の形成がさらに抑制される。なお、雰囲気ガスとして、Ａｒガスに代えて窒素ガスなどの他の不活性ガスが用いられてもよい。 After the formation of the gate oxide film 91, NO annealing using nitrogen monoxide (NO) gas as the atmospheric gas may be performed. The temperature profile has, for example, conditions of a temperature of 1100 ° C. to 1300 ° C. and a holding time of about 1 hour. Thereby, nitrogen atoms are introduced into the interface region between gate oxide film 91 and base layer 82. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved. As long as such nitrogen atoms can be introduced, a gas other than NO gas may be used as the atmospheric gas. Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing. The heating temperature for Ar annealing is preferably higher than the heating temperature for NO annealing and lower than the melting point of the gate oxide film 91. The time during which this heating temperature is maintained is, for example, about 1 hour. Thereby, the formation of interface states in the interface region between gate oxide film 91 and base layer 82 is further suppressed. Note that other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.
　次に、ゲート酸化膜９１上にゲート電極９２が形成される。具体的には、トレンチＴＲの内部の領域をゲート酸化膜９１を介して埋めるように、ゲート酸化膜９１上にゲート電極９２が形成される。ゲート電極９２の形成方法は、たとえば、導体またはドープトポリシリコンの成膜とＣＭＰ（Chemical　Mechanical　Polishing）とによって行い得る。 Next, a gate electrode 92 is formed on the gate oxide film 91. Specifically, gate electrode 92 is formed on gate oxide film 91 so as to fill the region inside trench TR with gate oxide film 91 interposed therebetween. The gate electrode 92 can be formed, for example, by film formation of conductor or doped polysilicon and CMP (Chemical Mechanical Polishing).
　図９を参照して、ゲート電極９２の露出面を覆うように、ゲート電極９２およびゲート酸化膜９１上に層間絶縁膜９３が形成される。層間絶縁膜９３およびゲート酸化膜９１に開口部が形成されるようにエッチングが行われる。この開口部により上面Ｐ２上においてソース領域８３およびコンタクト領域８４の各々が露出される。次に上面Ｐ２上においてソース領域８３およびｎコンタクト領域８４の各々に接するソース電極９４が形成される。 Referring to FIG. 9, interlayer insulating film 93 is formed on gate electrode 92 and gate oxide film 91 so as to cover the exposed surface of gate electrode 92. Etching is performed so that openings are formed in the interlayer insulating film 93 and the gate oxide film 91. Through this opening, each of source region 83 and contact region 84 is exposed on upper surface P2. Next, source electrode 94 in contact with each of source region 83 and n contact region 84 is formed on upper surface P2.
　再び図１を参照して、下側ドリフト領域８１Ａ上に単結晶基板８０を介してドレイン電極層９８が形成される。また、必要に応じて層間絶縁膜９３およびゲート酸化膜９１が部分的に除去された後に、上面Ｐ２上においてドリフト層８１およびジャンクション領域８５の各々に接するように、ショットキー電極９５が形成される。次に、配線層９７が形成される。これにより、半導体装置２０１が得られる。 Referring again to FIG. 1, drain electrode layer 98 is formed on lower drift region 81A via single crystal substrate 80. Further, Schottky electrode 95 is formed so as to be in contact with each of drift layer 81 and junction region 85 on upper surface P2 after interlayer insulating film 93 and gate oxide film 91 are partially removed as necessary. . Next, the wiring layer 97 is formed. Thereby, the semiconductor device 201 is obtained.
　（実施の形態２）
　図１０に示すように、本実施の形態の半導体装置２０２（炭化珪素半導体装置）においては、エピタキシャル膜９０の上面Ｐ２に、ショットキーバリアダイオード素子ＥＤ２が形成されたテラス部ＨＸ（凹部）が設けられている。具体的には、図１０における右上部分に示すように、上面Ｐ２の縁部においてテラス状の形状を有するテラス部ＨＸが設けられている。テラス部ＨＸは側壁ＳＸおよび底面ＢＸを有する。側壁ＳＸの少なくとも一部はドリフト層８１からなり、その部分にショットキー電極９５が接している。このようにショットキーバリアダイオード素子ＥＤ２では、上面Ｐ２上においてショットキー電極９５がドリフト層８１に接する部分は、側壁ＳＸを含む。この結果、上面Ｐ２上においてショットキー電極９５がドリフト層８１に接する部分は、下面Ｐ１から傾いている部分を有する。 (Embodiment 2)
As shown in FIG. 10, in semiconductor device 202 (silicon carbide semiconductor device) of the present embodiment, terrace portion HX (concave portion) in which Schottky barrier diode element ED2 is formed is provided on upper surface P2 of epitaxial film 90. It has been. Specifically, as shown in the upper right part in FIG. 10, a terrace portion HX having a terrace shape is provided at the edge of the upper surface P2. The terrace portion HX has a side wall SX and a bottom surface BX. At least a part of the side wall SX is composed of the drift layer 81, and the Schottky electrode 95 is in contact with the part. Thus, in Schottky barrier diode element ED2, the part where Schottky electrode 95 is in contact with drift layer 81 on upper surface P2 includes sidewall SX. As a result, the portion where Schottky electrode 95 is in contact with drift layer 81 on upper surface P2 has a portion inclined from lower surface P1.
　側壁ＳＸの面方位は、｛０００－１｝面から５０度以上８０度以下傾いていることが好ましく、（０００－１）面から５０度以上８０度以下傾いていることがより好ましい。側壁ＳＸは、巨視的に見て、面方位｛０－３３－８｝、｛０－１１－２｝、｛０－１１－４｝および｛０－１１－１｝のいずれかを有してもよい。面方位｛０－３３－８｝は｛０００－１｝面から５４．７度のオフ角を有する。面方位｛０－１１－１｝は｛０００－１｝面から７５．１度のオフ角を有する。よって面方位｛０－３３－８｝、｛０－１１－２｝、｛０－１１－４｝および｛０－１１－１｝は、オフ角５４．７～７５．１度に対応する。オフ角について５度程度の製造誤差が想定されることを考慮すると、側壁ＳＸが｛０００－１｝面に対して５０度以上８０度以下程度傾斜するような加工を行うことで、側壁ＳＸの巨視的な面方位を、｛０－３３－８｝、｛０－１１－２｝、｛０－１１－４｝および｛０－１１－１｝のいずれかとしやすくなる。このような側壁ＳＸは「特殊面」を有するものとしやすい。側壁ＳＸが特殊面を有する場合、側壁ＳＸの平坦性を向上させることができる。特殊面の詳細については後述する。 The plane orientation of the side wall SX is preferably inclined from 50 ° to 80 ° from the {000-1} plane, and more preferably from 50 ° to 80 ° from the (000-1) plane. The side wall SX has one of the plane orientations {0-33-8}, {0-11-2}, {0-11-4}, and {0-11-1} when viewed macroscopically. Also good. The plane orientation {0-33-8} has an off angle of 54.7 degrees from the {000-1} plane. The plane orientation {0-11-1} has an off angle of 75.1 degrees from the {000-1} plane. Accordingly, the plane orientations {0-33-8}, {0-11-2}, {0-11-4} and {0-11-1} correspond to off-angles of 54.7 to 75.1 degrees. Considering that a manufacturing error of about 5 degrees is assumed for the off angle, the side wall SX is processed by inclining about 50 degrees or more and 80 degrees or less with respect to the {000-1} plane. The macroscopic plane orientation is likely to be any one of {0-33-8}, {0-11-2}, {0-11-4}, and {0-11-1}. Such a side wall SX is likely to have a “special surface”. When the side wall SX has a special surface, the flatness of the side wall SX can be improved. Details of the special surface will be described later.
　本実施の形態によれば、ショットキー電極９５がドリフト層８１に接する部分の向き、言い換えれば側壁ＳＸの向きを、ショットキー電極９５とドリフト層８１との界面の物性が最適化されるように調整し得る。よってショットキーバリアダイオードの特性をより高めることができる。側壁ＳＸの面方位が（０００－１）面から５０度以上８０度以下傾いている場合、ショットキー電極９５が接する側壁の面方位が、（０００－１）面、すなわち炭化珪素のカーボン面から、５０度以上傾く。これによりショットキーバリアダイオードの順方向電圧を小さくすることができる。またこの傾きが８０度以下とされることで、平坦性の高い側壁を容易に形成し得る。 According to the present embodiment, the direction of the portion where the Schottky electrode 95 is in contact with the drift layer 81, in other words, the direction of the side wall SX, is optimized so that the physical properties of the interface between the Schottky electrode 95 and the drift layer 81 are optimized. Can be adjusted. Therefore, the characteristics of the Schottky barrier diode can be further improved. When the plane orientation of the side wall SX is inclined by 50 degrees or more and 80 degrees or less from the (000-1) plane, the plane orientation of the side wall in contact with the Schottky electrode 95 is from the (000-1) plane, that is, the silicon carbide carbon plane. , Tilt more than 50 degrees. As a result, the forward voltage of the Schottky barrier diode can be reduced. Further, when the inclination is 80 degrees or less, a highly flat side wall can be easily formed.
　次に半導体装置２０２の製造方法について説明する。まず、実施の形態１とほぼ同様の方法によって、図１１に示す構成を得る。実施の形態１においてはエッチングによってトレンチＴＲが形成されるが、本実施の形態においてはさらにテラス部ＨＸが形成される。テラス部ＨＸの形成は、トレンチＴＲの形成と同時に行なわれてもよく、また別個に行なわれてもよい。次に図１２に示すように、ゲート酸化膜９１、ゲート電極９２、層間絶縁膜９３、ソース電極９４およびドレイン電極層９８が、実施の形態１とほぼ同様に形成される。再び図１０を参照して、必要に応じて層間絶縁膜９３およびゲート酸化膜９１が部分的に除去された後に、ショットキー電極９５が形成される。次に、配線層９７が形成される。これにより、半導体装置２０２が得られる。 Next, a method for manufacturing the semiconductor device 202 will be described. First, the configuration shown in FIG. 11 is obtained by a method substantially similar to that of the first embodiment. Although the trench TR is formed by etching in the first embodiment, the terrace portion HX is further formed in the present embodiment. The formation of the terrace portion HX may be performed simultaneously with the formation of the trench TR, or may be performed separately. Next, as shown in FIG. 12, gate oxide film 91, gate electrode 92, interlayer insulating film 93, source electrode 94, and drain electrode layer 98 are formed in substantially the same manner as in the first embodiment. Referring to FIG. 10 again, Schottky electrode 95 is formed after interlayer insulating film 93 and gate oxide film 91 are partially removed as necessary. Next, the wiring layer 97 is formed. Thereby, the semiconductor device 202 is obtained.
　なお、上記以外の構成については、上述した実施の形態１の構成とほぼ同じであるため、同一または対応する要素について同一の符号を付し、その説明を繰り返さない。 Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.
　（実施の形態３）
　図１３に示すように、本実施の形態の半導体装置２０３（炭化珪素半導体装置）においては、中央面ＦＣ上に、トランジスタ素子ＥＴに加えダイオード素子ＥＤ３が配置されている。ショットキーバリアダイオード素子ＥＤ２（図１０：実施の形態２）は凹部としてのテラス部ＨＸに設けられているが、ダイオード素子ＥＤ３は凹部としてのトレンチ部ＨＹに設けられている。 (Embodiment 3)
As shown in FIG. 13, in semiconductor device 203 (silicon carbide semiconductor device) of the present embodiment, diode element ED3 is arranged on center surface FC in addition to transistor element ET. The Schottky barrier diode element ED2 (FIG. 10: Embodiment 2) is provided in the terrace portion HX as a recess, but the diode element ED3 is provided in the trench portion HY as a recess.
　トレンチ部ＨＹは、互いに対向する側壁ＳＸと、その間をつなぐ底面ＢＹとを有する。底面ＢＹは、本実施の形態においてはエピタキシャル膜９０の上面Ｐ２とほぼ平行な平坦な形状を有する。なお底面ＢＹは平坦面でなくてもよく、図１３の断面視においてほぼ点状であってもよく、この場合、トレンチ部ＨＹはＶ字形状を有する。トレンチ部ＨＹは、トレンチＴＲと同様の形状であってもよく、異なる形状であってもよい。同様の形状が用いられる場合、その製造方法がより簡素化され得る。本実施の形態によれば、中央面ＦＣ上にショットキーダイオード素子を形成することができる。 The trench part HY has side walls SX that face each other and a bottom face BY that connects the side walls SX. The bottom surface BY has a flat shape substantially parallel to the top surface P2 of the epitaxial film 90 in the present embodiment. Note that the bottom surface BY may not be a flat surface, and may be substantially point-like in the cross-sectional view of FIG. 13. In this case, the trench portion HY has a V shape. Trench portion HY may have the same shape as trench TR or may have a different shape. When a similar shape is used, the manufacturing method can be further simplified. According to the present embodiment, a Schottky diode element can be formed on the center plane FC.
　ダイオード素子ＥＤ３（図１３）の代わりにショットキーバリアダイオード素子ＥＤ１（図１）またはＥＤ２（図１０）が配置されてもよい。また中央面ＦＣ上にショットキーバリアダイオード素子が配置され、外縁面ＦＴ（図１３において図示せず）上にトランジスタ素子が配置されてもよい。 A Schottky barrier diode element ED1 (FIG. 1) or ED2 (FIG. 10) may be arranged instead of the diode element ED3 (FIG. 13). Further, a Schottky barrier diode element may be disposed on the center surface FC, and a transistor element may be disposed on the outer edge surface FT (not shown in FIG. 13).
　上記以外の構成については、上述した実施の形態１または２の構成とほぼ同じであるため、同一または対応する要素について同一の符号を付し、その説明を繰り返さない。 Since the configuration other than the above is substantially the same as the configuration of the first or second embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.
　なお上記各実施の形態において、中央面ＦＣ上に配置される第１の半導体素子がショットキーバリアダイオード素子ＥＤ１～ＥＤ３のいずれかであり、外縁面ＦＴ上に配置される第２の半導体素子がトランジスタ素子ＥＴであってもよい。 In each of the above embodiments, the first semiconductor element disposed on the central plane FC is any one of the Schottky barrier diode elements ED1 to ED3, and the second semiconductor element disposed on the outer edge surface FT is It may be a transistor element ET.
　（熱エッチング）
　熱エッチングとは、エッチングされる対象を高温下で反応性ガスにさらすことによって行われるものであり、物理的エッチング作用を実質的に有しないものである。反応性ガスは、加熱下において炭化珪素と反応し得るものである。反応性ガスが加熱下でエピタキシャル膜９０へ供給されることで、エピタキシャル膜９０がエッチングされる。 (Thermal etching)
Thermal etching is performed by exposing an object to be etched to a reactive gas at a high temperature, and has substantially no physical etching action. The reactive gas is capable of reacting with silicon carbide under heating. The reactive film is supplied to the epitaxial film 90 under heating, whereby the epitaxial film 90 is etched.
　反応性ガスはハロゲン元素を含有することが好ましい。ハロゲン元素は塩素またはフッ素を含むことが好ましい。たとえば、反応性ガスとしてＣｌ2、ＢＣｌ3、ＣＦ4、およびＳＦ6の少なくともいずれかを含有するプロセスガスを用いることができる。特に好適な反応性ガスはＣｌ2である。プロセスガスはさらに酸素ガスを含んでもよい。プロセスガスはキャリアガスを含むことが好ましい。キャリアガスとしては、たとえば窒素ガス、アルゴンガスまたはヘリウムガスを用いることができる。 The reactive gas preferably contains a halogen element. The halogen element preferably contains chlorine or fluorine. For example, a process gas containing at least one of Cl 2 , BCl 3, CF 4 , and SF 6 can be used as the reactive gas. Particularly preferred reactive gas is Cl 2. The process gas may further contain oxygen gas. The process gas preferably contains a carrier gas. As the carrier gas, for example, nitrogen gas, argon gas or helium gas can be used.
　熱エッチングのためのエピタキシャル膜９０の加熱温度の下限は、エッチング速度を確保する観点で、７００℃程度が好ましく、８００℃程度がより好ましく、９００℃程度がさらに好ましい。また加熱温度の上限は、エッチングダメージを抑制する観点で、１２００℃程度が好ましく、１１００℃程度がより好ましく、１０００℃程度がさらに好ましい。 The lower limit of the heating temperature of the epitaxial film 90 for thermal etching is preferably about 700 ° C., more preferably about 800 ° C., and further preferably about 900 ° C. from the viewpoint of securing the etching rate. The upper limit of the heating temperature is preferably about 1200 ° C., more preferably about 1100 ° C., and further preferably about 1000 ° C. from the viewpoint of suppressing etching damage.
　熱エッチングにおける炭化珪素のエッチング速度はたとえば約７０μｍ／時になる。これに比して二酸化珪素のエッチング速度は極めて小さいので、マスク層６１（図７）が二酸化珪素から作られていれば、その消耗を顕著に抑制することができる。 The etching rate of silicon carbide in the thermal etching is, for example, about 70 μm / hour. Compared to this, the etching rate of silicon dioxide is extremely low, and therefore, if the mask layer 61 (FIG. 7) is made of silicon dioxide, its consumption can be remarkably suppressed.
　（特殊面）
　ショットキーバリアダイオード素子ＥＤ２またはＥＤ３が設けられる側壁ＳＸは、特殊面を有することが好ましい。特殊面を有する側壁ＳＸは、図１４に示すように、面方位｛０－３３－８｝を有する面Ｓ１（第１の面）を含む。面Ｓ１は好ましくは面方位（０－３３－８）を有する。より好ましくは、側壁ＳＸは面Ｓ１を微視的に含み、側壁ＳＸはさらに、面方位｛０－１１－１｝を有する面Ｓ２（第２の面）を微視的に含む。ここで「微視的」とは、原子間隔の２倍程度の寸法を少なくとも考慮する程度に詳細に、ということを意味する。このように微視的な構造の観察方法としては、たとえばＴＥＭ（Transmission　Electron　Microscope）を用いることができる。面Ｓ２は好ましくは面方位（０－１１－１）を有する。 (Special surface)
The side wall SX provided with the Schottky barrier diode element ED2 or ED3 preferably has a special surface. As shown in FIG. 14, the side wall SX having a special surface includes a surface S1 (first surface) having a surface orientation {0-33-8}. The plane S1 preferably has a plane orientation (0-33-8). More preferably, the sidewall SX microscopically includes the surface S1, and the sidewall SX further microscopically includes a surface S2 (second surface) having a surface orientation {0-11-1}. Here, “microscopic” means that the dimensions are as detailed as at least a dimension of about twice the atomic spacing. As a microscopic structure observation method, for example, a TEM (Transmission Electron Microscope) can be used. The plane S2 preferably has a plane orientation (0-11-1).
　好ましくは、側壁ＳＸの面Ｓ１および面Ｓ２は、面方位｛０－１１－２｝を有する複合面ＳＲを構成している。すなわち複合面ＳＲは、面Ｓ１およびＳ２が周期的に繰り返されることによって構成されている。このような周期的構造は、たとえば、ＴＥＭまたはＡＦＭ（Atomic　Force　Microscopy）により観察し得る。この場合、複合面ＳＲは｛０００－１｝面に対して巨視的に６２度のオフ角を有する。ここで「巨視的」とは、原子間隔程度の寸法を有する微細構造を無視することを意味する。このように巨視的なオフ角の測定としては、たとえば、一般的なＸ線回折を用いた方法を用い得る。 Preferably, the surface S1 and the surface S2 of the side wall SX constitute a composite surface SR having a surface orientation {0-11-2}. That is, the composite surface SR is configured by periodically repeating the surfaces S1 and S2. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy). In this case, the composite surface SR has an off angle of 62 degrees macroscopically with respect to the {000-1} plane. Here, “macroscopic” means ignoring a fine structure having a dimension on the order of atomic spacing. As such a macroscopic off-angle measurement, for example, a general method using X-ray diffraction can be used.
　好ましくは複合面ＳＲは面方位（０－１１－２）を有する。この場合、複合面ＳＲは（０００－１）面に対して巨視的に６２度のオフ角を有する。図中、方向ＣＤは、上述した周期的繰り返しが行われる方向に沿っている。方向ＣＤは、おおよそ、エピタキシャル膜９０の厚さ方向（図１０または図１３における縦方向）を側壁ＳＸへ射影した方向に対応する。 Preferably, composite surface SR has a plane orientation (0-11-2). In this case, the composite surface SR has an off angle of 62 degrees macroscopically with respect to the (000-1) plane. In the figure, the direction CD is along the direction in which the above-described periodic repetition is performed. The direction CD roughly corresponds to the direction in which the thickness direction of the epitaxial film 90 (the vertical direction in FIG. 10 or FIG. 13) is projected onto the side wall SX.
　次に、複合面ＳＲの詳細な構造について説明する。
　一般に、ポリタイプ４Ｈの炭化珪素単結晶を（０００－１）面から見ると、図１５に示すように、Ｓｉ原子（またはＣ原子）は、Ａ層の原子（図中の実線）と、この下に位置するＢ層の原子（図中の破線）と、この下に位置するＣ層の原子（図中の一点鎖線）と、この下に位置するＢ層の原子（図示せず）とが繰り返し設けられている。つまり４つの層ＡＢＣＢを１周期としてＡＢＣＢＡＢＣＢＡＢＣＢ・・・のような周期的な積層構造が設けられている。 Next, the detailed structure of the composite surface SR will be described.
In general, when a silicon carbide single crystal of polytype 4H is viewed from the (000-1) plane, as shown in FIG. 15, Si atoms (or C atoms) are atoms of the A layer (solid line in the figure), B layer atoms (broken line in the figure) located below, C layer atoms (dotted line in the figure) located below, and B layer atoms (not shown) located below this It is provided repeatedly. That is, a periodic laminated structure such as ABCBABCBABCB... Is provided with four layers ABCB as one period.
　図１６に示すように、（１１－２０）面（図１５の線ＸＶＩ－ＸＶＩの断面）において、上述した１周期を構成する４つの層ＡＢＣＢの各層の原子は、（０－１１－２）面に完全に沿うようには配列されていない。図１６においてはＢ層の原子の位置を通るように（０－１１－２）面が示されており、この場合、Ａ層およびＣ層の各々の原子は（０－１１－２）面からずれていることがわかる。このため、炭化珪素単結晶の表面の巨視的な面方位、すなわち原子レベルの構造を無視した場合の面方位が（０－１１－２）に限定されたとしても、この表面は、微視的には様々な構造をとり得る。 As shown in FIG. 16, in the (11-20) plane (cross section taken along line XVI-XVI in FIG. 15), the atoms in each of the four layers ABCB constituting one period described above are (0-11-2) It is not arranged to be completely along the plane. In FIG. 16, the (0-11-2) plane is shown so as to pass through the position of atoms in the B layer. In this case, the atoms in the A layer and the C layer are separated from the (0-11-2) plane. You can see that it is shifted. For this reason, even if the macroscopic plane orientation of the surface of the silicon carbide single crystal, that is, the plane orientation when ignoring the atomic level structure is limited to (0-11-2), the surface is microscopic. Can take various structures.
　図１７に示すように、複合面ＳＲは、面方位（０－３３－８）を有する面Ｓ１と、面Ｓ１につながりかつ面Ｓ１の面方位と異なる面方位を有する面Ｓ２とが交互に設けられることによって構成されている。面Ｓ１および面Ｓ２の各々の長さは、Ｓｉ原子（またはＣ原子）の原子間隔の２倍である。なお面Ｓ１および面Ｓ２が平均化された面は、（０－１１－２）面（図１６）に対応する。 As shown in FIG. 17, in the composite surface SR, a surface S1 having a surface orientation (0-33-8) and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternately provided. It is configured by being. The length of each of the surface S1 and the surface S2 is twice the atomic spacing of Si atoms (or C atoms). Note that the surface obtained by averaging the surfaces S1 and S2 corresponds to the (0-11-2) surface (FIG. 16).
　図１８に示すように、複合面ＳＲを（０１－１０）面から見て単結晶構造は、部分的に見て立方晶と等価な構造（面Ｓ１の部分）を周期的に含んでいる。具体的には複合面ＳＲは、上述した立方晶と等価な構造における面方位（００１）を有する面Ｓ１と、面Ｓ１につながりかつ面Ｓ１の面方位と異なる面方位を有する面Ｓ２とが交互に設けられることによって構成されている。このように、立方晶と等価な構造における面方位（００１）を有する面（図１８においては面Ｓ１）と、この面につながりかつこの面方位と異なる面方位を有する面（図１８においては面Ｓ２）とによって表面を構成することは４Ｈ以外のポリタイプにおいても可能である。ポリタイプは、たとえば６Ｈまたは１５Ｒであってもよい。 As shown in FIG. 18, the single crystal structure when the composite surface SR is viewed from the (01-10) plane periodically includes a structure (part of the surface S1) equivalent to a cubic crystal when viewed partially. Specifically, in the composite surface SR, a surface S1 having a surface orientation (001) in a structure equivalent to the above-described cubic crystal and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternated. It is comprised by being provided in. Thus, a plane having a plane orientation (001) in the structure equivalent to a cubic crystal (plane S1 in FIG. 18) and a plane connected to this plane and having a plane orientation different from this plane orientation (plane in FIG. 18). It is also possible for polytypes other than 4H to constitute the surface according to S2). The polytype may be 6H or 15R, for example.
　図１９に示すように、側壁ＳＸは複合面ＳＲに加えてさらに面Ｓ３（第３の面）を含んでもよい。より具体的には、複合面ＳＲ（図１９においては直線で単純化して示されている）および面Ｓ３が周期的に繰り返されることによって構成された複合面ＳＱを側壁ＳＸが含んでもよい。周期的構造は、たとえば、ＴＥＭまたはＡＦＭにより観察し得る。この場合、側壁ＳＸの｛０００－１｝面に対するオフ角は、理想的な複合面ＳＲのオフ角である６２度からずれる。このずれは小さいことが好ましく、±１０度の範囲内であることが好ましい。このような角度範囲に含まれる表面としては、たとえば、巨視的な面方位が{０－３３－８}面となる表面がある。 As shown in FIG. 19, the side wall SX may further include a surface S3 (third surface) in addition to the composite surface SR. More specifically, the side wall SX may include a composite surface SQ that is configured by periodically repeating the composite surface SR (shown in a simplified manner as a straight line in FIG. 19) and the surface S3. The periodic structure can be observed, for example, by TEM or AFM. In this case, the off angle of the side wall SX with respect to the {000-1} plane deviates from 62 degrees that is the ideal off angle of the composite surface SR. This deviation is preferably small, and preferably within a range of ± 10 degrees. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a {0-33-8} plane.
　より好ましくは、側壁ＳＸの（０００－１）面に対するオフ角は、理想的な複合面ＳＲのオフ角である６２度からずれる。このずれは小さいことが好ましく、±１０度の範囲内であることが好ましい。このような角度範囲に含まれる表面としては、たとえば、巨視的な面方位が（０－３３－８）面となる表面がある。 More preferably, the off angle of the side wall SX with respect to the (000-1) plane deviates from the ideal off angle of the composite surface SR of 62 degrees. This deviation is preferably small, and preferably within a range of ± 10 degrees. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a (0-33-8) plane.
　今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の請求の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　たとえば、ゲート電極の構造はトレンチ型に限定されず、プレーナ型であってもよい。すなわち、エピタキシャル膜９０の上面Ｐ２上にトレンチＴＲ（図１）が設けられておらず、平坦な上面Ｐ２上にゲート電極が設けられてもよい。またトランジスタ素子はＭＯＳＦＥＴ以外のＭＩＳＦＥＴ（Metal　Insulator　Semiconductor　Field　Effect　Transistor）であってもよい。またドレイン電極の一部の上にｐ型のコレクタ領域が付加されることで、トランジスタ素子がＩＧＢＴ（Insulated　Gate　Bipolar　Transistor）素子とされてもよい。この場合、ソース電極およびドレイン電極のそれぞれはエミッタ電極およびコレクタ電極に対応する。またトランジスタのチャネル型はｎチャネル型に限定されず、ｐチャネル型であってもよい。この場合、上述した実施の形態においてｐ型とｎ型とが入れ替えられた構成を用いることができる。またショットキーバリアダイオードのジャンクション領域は、その効果が必要でない場合、省略されてもよい。また半導体装置の製造中に単結晶基板が除去される場合、エピタキシャル膜とドレイン電極層とが直接接する構成も得られる。 For example, the structure of the gate electrode is not limited to the trench type, but may be a planar type. That is, the trench TR (FIG. 1) may not be provided on the upper surface P2 of the epitaxial film 90, and the gate electrode may be provided on the flat upper surface P2. The transistor element may be a MISFET (Metal Insulator Semiconductor Field Effect Transistor) other than the MOSFET. Further, by adding a p-type collector region on a part of the drain electrode, the transistor element may be an IGBT (Insulated Gate Bipolar Transistor) element. In this case, each of the source electrode and the drain electrode corresponds to an emitter electrode and a collector electrode. The channel type of the transistor is not limited to the n-channel type, and may be a p-channel type. In this case, a configuration in which the p-type and the n-type are interchanged in the above-described embodiment can be used. Further, the junction region of the Schottky barrier diode may be omitted when the effect is not necessary. Further, when the single crystal substrate is removed during the manufacture of the semiconductor device, a structure in which the epitaxial film and the drain electrode layer are in direct contact with each other can also be obtained.
　６１　マスク層、６９　フィールドストップ領域、７１，７１Ｄ，７１Ｔ　電界緩和領域、７３　ガードリング領域、７３Ｉ，７３Ｊ　ガードリング、８０　単結晶基板、８１　ドリフト層、８１Ａ　下側ドリフト領域（第１の領域）、８１Ｂ　上側ドリフト領域（第２の領域）、８２　ベース層、８３　ソース領域、８４　コンタクト領域、９０　エピタキシャル膜（炭化珪素膜）、９１　ゲート酸化膜（ゲート絶縁膜）、９２　ゲート電極、９３　層間絶縁膜、９４　ソース電極、９５　ショットキー電極、９７　配線層、９８　ドレイン電極層（電極層）、２０１～２０３　半導体装置（炭化珪素半導体装置）、ＥＤ１～ＥＤ３　ショットキーバリアダイオード素子、ＥＴ　トランジスタ素子、ＦＣ　中央面、ＦＴ　外縁面、ＨＸ　テラス部（凹部）、ＨＹ　トレンチ部（凹部）、ＩＦ　界面、Ｐ１　下面（第１の主面）、Ｐ２　上面（第２の主面）、ＲＡ　下側範囲、ＲＢ　上側範囲、ＳＷ　側壁面、ＳＸ　側壁、ＴＲ　トレンチ。 61 mask layer, 69 field stop region, 71, 71D, 71T electric field relaxation region, 73 guard ring region, 73I, 73J guard ring, 80 single crystal substrate, 81 drift layer, 81A lower drift region (first region), 81B Upper drift region (second region), 82 base layer, 83 source region, 84 contact region, 90 epitaxial film (silicon carbide film), 91 gate oxide film (gate insulating film), 92 gate electrode, 93 interlayer insulating film , 94 source electrode, 95 Schottky electrode, 97 wiring layer, 98 drain electrode layer (electrode layer), 201-203 semiconductor device (silicon carbide semiconductor device), ED1-ED3 Schottky barrier diode element, ET transistor element, FC center Surface, FT outer edge surface, HX Lath (recess), HY trench (recess), IF interface, P1 lower surface (first main surface), P2 upper surface (second main surface), RA lower range, RB upper range, SW side wall surface, SX Side wall, TR trench.

Claims (10)

  1. 　炭化珪素半導体装置であって、
    　電極層と、
    　前記電極層に面する第１の主面と、前記第１の主面と反対の第２の主面とを有する炭化珪素膜とを備え、前記炭化珪素膜は、前記第１の主面をなし第１の導電型を有するドリフト層を含み、前記ドリフト層は、前記第１の主面をなす第１の領域と、前記第１の領域上に界面を介して設けられた第２の領域とを有し、前記界面は、中央面と、前記界面上において前記中央面を取り囲む外縁面とを有し、前記炭化珪素膜は、前記界面に部分的に設けられ第２の導電型を有する埋込領域を含み、前記埋込領域は、前記中央面に部分的に設けられた電界緩和領域と、前記界面において前記中央面を取り囲むように前記外縁面に設けられたガードリング領域とを有し、前記炭化珪素半導体装置はさらに
    　前記界面の前記中央面上に配置された第１の半導体素子と、
    　前記界面の前記外縁面上に少なくとも部分的に配置された第２の半導体素子とを備え、前記第１および第２の半導体素子の一方はトランジスタ素子であり、前記第１および第２の半導体素子の他方は、前記第２の主面上に設けられ少なくとも部分的に前記ドリフト層に接するショットキー電極を有するショットキーバリアダイオード素子である、炭化珪素半導体装置。     A silicon carbide semiconductor device,
    An electrode layer;
    A silicon carbide film having a first main surface facing the electrode layer and a second main surface opposite to the first main surface, the silicon carbide film including the first main surface; None, including a drift layer having a first conductivity type, wherein the drift layer includes a first region forming the first main surface, and a second region provided on the first region via an interface And the interface has a center surface and an outer edge surface surrounding the center surface on the interface, and the silicon carbide film is partially provided on the interface and has a second conductivity type. The buried region includes an electric field relaxation region partially provided on the central surface and a guard ring region provided on the outer edge surface so as to surround the central surface at the interface. The silicon carbide semiconductor device further includes a first semiconductor disposed on the central surface of the interface. Elements,
    A second semiconductor element disposed at least partially on the outer edge surface of the interface, wherein one of the first and second semiconductor elements is a transistor element, and the first and second semiconductor elements The other of the silicon carbide semiconductor devices is a Schottky barrier diode element having a Schottky electrode provided on the second main surface and at least partially in contact with the drift layer.
  2. 　前記第１の半導体素子がトランジスタ素子であり、前記第２の半導体素子がショットキーバリアダイオード素子である、請求項１に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 1, wherein the first semiconductor element is a transistor element, and the second semiconductor element is a Schottky barrier diode element.
  3. 　前記第２の主面上において前記ショットキー電極が前記ドリフト層に接する部分は、前記第１の主面と平行である、請求項１または請求項２に記載の炭化珪素半導体装置。 3. The silicon carbide semiconductor device according to claim 1, wherein a portion of the second main surface where the Schottky electrode is in contact with the drift layer is parallel to the first main surface.
  4. 　前記第２の主面上において前記ショットキー電極が前記ドリフト層に接する部分は、前記第１の主面から傾いている部分を有する、請求項１または請求項２に記載の炭化珪素半導体装置。 3. The silicon carbide semiconductor device according to claim 1, wherein a portion of the second main surface where the Schottky electrode is in contact with the drift layer has a portion inclined from the first main surface.
  5. 　前記炭化珪素膜の前記第２の主面には凹部が設けられており、前記凹部は、前記ドリフト層からなり前記ショットキー電極が接する側壁を有し、前記側壁の面方位は（０００－１）面から５０度以上８０度以下傾いている、請求項４に記載の炭化珪素半導体装置。 A recess is provided in the second main surface of the silicon carbide film, and the recess has a sidewall made of the drift layer and in contact with the Schottky electrode, and the plane orientation of the sidewall is (000-1). The silicon carbide semiconductor device according to claim 4, wherein the silicon carbide semiconductor device is tilted from 50 degrees to 80 degrees from the surface.
  6. 　前記界面のうち厚さ方向において前記ショットキー電極と前記ドリフト層との接触面に対向する部分は前記埋込領域からなる、請求項１から請求項５のいずれか１項に記載の炭化珪素半導体装置。 6. The silicon carbide semiconductor according to claim 1, wherein a portion of the interface facing the contact surface between the Schottky electrode and the drift layer in the thickness direction is formed of the buried region. apparatus.
  7. 　前記炭化珪素膜は前記第２の主面上に部分的に、前記第２の導電型を有するジャンクション領域を有し、前記ジャンクション領域は前記ショットキー電極に接している、請求項１から請求項６のいずれか１項に記載の炭化珪素半導体装置。 The silicon carbide film has a junction region having the second conductivity type partially on the second main surface, and the junction region is in contact with the Schottky electrode. 6. The silicon carbide semiconductor device according to any one of 6.
  8. 　前記界面のうち厚さ方向において前記ジャンクション領域に対向する部分は、少なくとも部分的に前記埋込領域からなる、請求項７に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 7, wherein a portion of the interface that faces the junction region in the thickness direction is at least partially made of the buried region.
  9. 　前記ショットキー電極は、４．３３ｅＶより小さい仕事関数を有する金属から作られている、請求項１から請求項８のいずれか１項に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to any one of claims 1 to 8, wherein the Schottky electrode is made of a metal having a work function smaller than 4.33 eV.
  10. 　前記金属は、Ｈｆ、Ｚｒ、Ｔａ、Ｍｎ、ＮｂおよびＶの少なくともいずれかの原子を含む、請求項９に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 9, wherein the metal includes at least one of Hf, Zr, Ta, Mn, Nb, and V atoms.
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